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Merge branch 'feature/spi_master_support_edma_on_s3_v5.5' into 'release/v5.5'

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feat(driver_spi): master driver psram edma support (v5.5)

See merge request espressif/esp-idf!44473
This commit is contained in:
morris
2026-01-14 10:46:15 +08:00
parent e0409f0175 6be402c177
commit 003eaf0896
29 changed files with 463 additions and 223 deletions
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docs/en/api-reference/peripherals/spi_master.rst
+9 -1
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@@ -353,6 +353,14 @@ Driver Usage
The example code for the SPI Master driver can be found in the :example:`peripherals/spi_master` directory of ESP-IDF examples.
.. only:: SOC_PSRAM_DMA_CAPABLE
Transactions with Data on PSRAM
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
{IDF_TARGET_NAME} supports GPSPI Master with DMA transferring data from/to PSRAM directly without extra internal copy process, which saves memory, by adding :c:macro:`SPI_TRANS_DMA_USE_PSRAM` flag to the transaction.
Note that this feature shares bandwidth (bus frequency * bus bits width) with MSPI bus, so GPSPI transfer bandwidth should be less than PSRAM bandwidth, **otherwise transmission data may be lost**. You can check the return value or :c:macro:`SPI_TRANS_DMA_RX_FAIL` and :c:macro:`SPI_TRANS_DMA_TX_FAIL` flags after the transaction is finished to check if error occurs during the transmission. If the transaction returns :c:macro:`ESP_ERR_INVALID_STATE` error, the transaction fails.
Transactions with Data Not Exceeding 32 Bits
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -490,7 +498,7 @@ GPIO Matrix and IO_MUX
Most of the chip's peripheral signals have a direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
When an SPI Host is set to 80 MHz or lower frequencies, routing SPI pins via the GPIO matrix will behave the same compared to routing them via IOMUX.
When an SPI Host is set to 40 MHz or lower frequencies, routing SPI pins via the GPIO matrix will behave the same compared to routing them via IOMUX.
The IO_MUX pins for SPI buses are given below.