diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c
index c3dfa34947..b2bf766c51 100644
--- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c
+++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c
@@ -76,10 +76,9 @@ static bool esp_clk_tree_initialized = false;
 void esp_clk_tree_initialize(void)
 {
     soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
-    if (((rst_reason == RESET_REASON_CPU0_MWDT0) || (rst_reason == RESET_REASON_CPU0_MWDT1)         \
+    if ((rst_reason == RESET_REASON_CPU0_MWDT0) || (rst_reason == RESET_REASON_CPU0_MWDT1)          \
             || (rst_reason == RESET_REASON_CPU0_SW) || (rst_reason == RESET_REASON_CPU0_RTC_WDT)    \
-            || (rst_reason == RESET_REASON_CPU0_JTAG) || (rst_reason == RESET_REASON_CPU0_LOCKUP))  \
-            && (REG_READ(RTC_CLK_SRC_REF_CNT_ARRAY_REG) == (uint32_t)s_pll_src_cg_ref_cnt)) {
+            || (rst_reason == RESET_REASON_CPU0_JTAG) || (rst_reason == RESET_REASON_CPU0_LOCKUP)) {
         esp_clk_tree_initialized = true;
         return;
     }
diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
index b0faf36052..3c5d3750b8 100644
--- a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
+++ b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h
@@ -58,7 +58,6 @@ extern "C" {
 #define RTC_SLOW_CLK_CAL_REG                LP_AON_STORE1_REG
 #define RTC_BOOT_TIME_LOW_REG               LP_AON_STORE2_REG
 #define RTC_BOOT_TIME_HIGH_REG              LP_AON_STORE3_REG
-#define RTC_CLK_SRC_REF_CNT_ARRAY_REG       LP_AON_STORE4_REG
 #define RTC_ENTRY_LENGTH_REG                LP_AON_STORE5_REG
 #define RTC_ENTRY_ADDR_REG                  LP_AON_STORE6_REG
 #define RTC_RESET_CAUSE_REG                 LP_AON_STORE6_REG