feat(esp_tee): Support for ESP32-C5 - the esp_tee component

components/esp_tee/src/esp_secure_service_wrapper.c

@@ -20,6 +20,7 @@
 #include "esp_flash.h"
 
 #include "soc/soc_caps.h"
+#include "sdkconfig.h"
 
 #include "esp_tee.h"
 #include "secure_service_num.h"
@@ -31,6 +32,13 @@ void IRAM_ATTR __wrap_esp_rom_route_intr_matrix(int cpu_no, uint32_t model_num,
     esp_tee_service_call(4, SS_ESP_ROM_ROUTE_INTR_MATRIX, cpu_no, model_num, intr_num);
 }
 
+#if SOC_INT_CLIC_SUPPORTED
+void IRAM_ATTR __wrap_esprv_int_set_vectored(int rv_int_num, bool vectored)
+{
+    esp_tee_service_call(3, SS_ESPRV_INT_SET_VECTORED, rv_int_num, vectored);
+}
+#endif
+
 /* ---------------------------------------------- RTC_WDT ------------------------------------------------- */
 
 void __wrap_wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr)
@@ -222,6 +230,13 @@ void __wrap_esp_crypto_sha_enable_periph_clk(bool enable)
     esp_tee_service_call(2, SS_ESP_CRYPTO_SHA_ENABLE_PERIPH_CLK, enable);
 }
 
+#if SOC_SHA_SUPPORT_SHA512_T
+int __wrap_esp_sha_512_t_init_hash(uint16_t t)
+{
+    return esp_tee_service_call(2, SS_ESP_SHA_512_T_INIT_HASH, t);
+}
+#endif
+
 /* ---------------------------------------------- HMAC ------------------------------------------------- */
 
 esp_err_t __wrap_esp_hmac_calculate(hmac_key_id_t key_id, const void *message, size_t message_len, uint8_t *hmac)
@@ -365,6 +380,25 @@ bool IRAM_ATTR __wrap_mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mm
     return esp_tee_service_call(6, SS_MMU_HAL_PADDR_TO_VADDR, mmu_id, paddr, target, type, out_vaddr);
 }
 
+/**
+ * NOTE: This ROM-provided API is intended to configure the Cache MMU size for
+ * instruction (irom) and rodata (drom) sections in flash.
+ *
+ * On ESP32-C5, it also sets the start pages for flash irom and drom sections,
+ * which involves accessing MMU registers directly.
+ *
+ * However, these MMU registers are protected by the APM and direct access
+ * from the REE results in a fault.
+ *
+ * To prevent this, we wrap this function to be routed as a TEE service call.
+ */
+#if CONFIG_IDF_TARGET_ESP32C5
+void IRAM_ATTR __wrap_Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size)
+{
+    esp_tee_service_call(3, SS_CACHE_SET_IDROM_MMU_SIZE, irom_size, drom_size);
+}
+#endif
+
 #if CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1
 /* ---------------------------------------------- SPI Flash HAL ------------------------------------------------- */
 

components/esp_tee/src/esp_tee_u2m_switch.S

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,6 @@
     .global _u2m_switch
     .type   _u2m_switch, @function
 _u2m_switch:
-     ecall
-     fence
-     ret
+    ecall
+    fence
+    ret