feat(esp_tee): Support for ESP32-C5 - the esp_tee component

components/esp_tee/subproject/main/core/esp_secure_services.c

@@ -203,6 +203,13 @@ void _ss_esp_crypto_sha_enable_periph_clk(bool enable)
     esp_crypto_sha_enable_periph_clk(enable);
 }
 
+#if SOC_SHA_SUPPORT_SHA512_T
+int _ss_esp_sha_512_t_init_hash(uint16_t t)
+{
+    return esp_sha_512_t_init_hash(t);
+}
+#endif
+
 /* ---------------------------------------------- HMAC ------------------------------------------------- */
 
 esp_err_t _ss_esp_hmac_calculate(hmac_key_id_t key_id, const void *message, size_t message_len, uint8_t *hmac)

components/esp_tee/subproject/main/core/esp_secure_services_iram.c

@@ -12,12 +12,14 @@
 #include "hal/mmu_types.h"
 #include "hal/mmu_hal.h"
 #include "hal/wdt_hal.h"
+#include "rom/cache.h"
 
 #include "hal/spi_flash_hal.h"
 #include "hal/spi_flash_types.h"
 #include "spi_flash_chip_generic.h"
 #include "memspi_host_driver.h"
 #include "esp_flash.h"
+#include "riscv/rv_utils.h"
 
 #include "esp_tee.h"
 #include "esp_tee_memory_utils.h"
@@ -63,7 +65,7 @@ void _ss_rv_utils_intr_set_threshold(int priority_threshold)
 
 void _ss_rv_utils_intr_edge_ack(uint32_t intr_num)
 {
-    rv_utils_tee_intr_edge_ack(intr_num);
+    rv_utils_intr_edge_ack(intr_num);
 }
 
 void _ss_rv_utils_intr_global_enable(void)
@@ -71,6 +73,42 @@ void _ss_rv_utils_intr_global_enable(void)
     rv_utils_tee_intr_global_enable();
 }
 
+uint32_t _ss_rv_utils_intr_get_enabled_mask(void)
+{
+    return rv_utils_intr_get_enabled_mask();
+}
+
+void _ss_rv_utils_set_cycle_count(uint32_t ccount)
+{
+    rv_utils_set_cycle_count(ccount);
+}
+
+#if SOC_BRANCH_PREDICTOR_SUPPORTED
+void _ss_rv_utils_en_branch_predictor(void)
+{
+    rv_utils_en_branch_predictor();
+}
+
+void _ss_rv_utils_dis_branch_predictor(void)
+{
+    rv_utils_dis_branch_predictor();
+}
+#endif
+
+#if SOC_CPU_SUPPORT_WFE
+void _ss_rv_utils_wfe_mode_enable(bool en)
+{
+    rv_utils_wfe_mode_enable(en);
+}
+#endif
+
+#if SOC_INT_CLIC_SUPPORTED
+void _ss_esprv_int_set_vectored(int rv_int_num, bool vectored)
+{
+    esprv_int_set_vectored(rv_int_num, vectored);
+}
+#endif
+
 /* ---------------------------------------------- RTC_WDT ------------------------------------------------- */
 
 void _ss_wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr)
@@ -164,6 +202,7 @@ void _ss_mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vad
     bool vaddr_chk = esp_tee_flash_check_vaddr_in_tee_region(vaddr);
     bool paddr_chk = esp_tee_flash_check_paddr_in_tee_region(paddr);
     if (vaddr_chk || paddr_chk) {
+        ESP_LOGD(TAG, "[%s] Illegal flash access at 0x%08x | 0x%08x", __func__, vaddr, paddr);
         return;
     }
     ESP_FAULT_ASSERT(!vaddr_chk && !paddr_chk);
@@ -175,6 +214,7 @@ void _ss_mmu_hal_unmap_region(uint32_t mmu_id, uint32_t vaddr, uint32_t len)
 {
     bool vaddr_chk = esp_tee_flash_check_vaddr_in_tee_region(vaddr);
     if (vaddr_chk) {
+        ESP_LOGD(TAG, "[%s] Illegal flash access at 0x%08x", __func__, vaddr);
         return;
     }
     ESP_FAULT_ASSERT(!vaddr_chk);
@@ -202,6 +242,13 @@ bool _ss_mmu_hal_paddr_to_vaddr(uint32_t mmu_id, uint32_t paddr, mmu_target_t ta
     return mmu_hal_paddr_to_vaddr(mmu_id, paddr, target, type, out_vaddr);
 }
 
+#if CONFIG_IDF_TARGET_ESP32C5
+void _ss_Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size)
+{
+    Cache_Set_IDROM_MMU_Size(irom_size, drom_size);
+}
+#endif
+
 #if CONFIG_SECURE_TEE_EXT_FLASH_MEMPROT_SPI1
 /* ---------------------------------------------- SPI Flash HAL ------------------------------------------------- */
 

components/esp_tee/subproject/main/core/esp_tee_intr.c

@@ -60,8 +60,23 @@ void esp_tee_route_intr_matrix(int cpu_no, uint32_t model_num, uint32_t intr_num
     if (esp_tee_is_intr_src_protected(model_num) || intr_num == TEE_SECURE_INUM) {
         return;
     }
+#if SOC_INT_CLIC_SUPPORTED
+    if (intr_num == TEE_PASS_INUM) {
+        return;
+    }
+#endif
 
     esp_rom_route_intr_matrix(cpu_no, model_num, intr_num);
+    ESP_LOGV(TAG, "Connected src %d to int %d (cpu %d)", model_num, intr_num, cpu_no);
+
+#if SOC_INT_CLIC_SUPPORTED
+    if (intr_num != ETS_T1_WDT_INUM && intr_num != ETS_CACHEERR_INUM) {
+        /* Configure interrupts to be visible in the TEE (M-mode) */
+        REG_SET_BIT(DR_REG_INTMTX_BASE + 4 * model_num, BIT(8));
+        /* Configure interrupts to be serviced in the REE (U-mode) */
+        rv_utils_tee_intr_set_mode(intr_num, PRV_U);
+    }
+#endif
 }
 
 /**
@@ -73,7 +88,7 @@ void esp_tee_route_intr_matrix(int cpu_no, uint32_t model_num, uint32_t intr_num
 static intr_handler_t tee_set_interrupt_handler(void *arg)
 {
     tee_handler_table_entry *entry;
-    intr_handler_t           old;
+    intr_handler_t old;
     vector_desc_t *vd = (vector_desc_t *)arg;
     int source = vd->source;
 
@@ -119,7 +134,7 @@ int esp_tee_intr_deregister(void *arg)
     tee_set_interrupt_handler(vd);
 
     // Setting back the default value for interrupt pin.
-    esp_rom_route_intr_matrix(cpu, vd->source, 0);
+    esp_rom_route_intr_matrix(cpu, vd->source, ETS_INVALID_INUM);
 
     return 0;
 }