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fix(mspi): collect mspi iomux pin macro from iomux_reg.h to spi_pins.h

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This commit is contained in:
wanckl
2024-08-30 15:51:17 +08:00
parent 473f39c31f
commit 19c6e77a31
33 changed files with 339 additions and 359 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
+17 -17
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -28,12 +28,12 @@
#include "bootloader_flash_priv.h"
#include "bootloader_init.h"
#define FLASH_CLK_IO SPI_CLK_GPIO_NUM
#define FLASH_CS_IO SPI_CS0_GPIO_NUM
#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM
#define FLASH_SPID_IO SPI_D_GPIO_NUM
#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM
#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM
#define FLASH_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
#define FLASH_CS_IO MSPI_IOMUX_PIN_NUM_CS0
#define FLASH_SPIQ_IO MSPI_IOMUX_PIN_NUM_MISO
#define FLASH_SPID_IO MSPI_IOMUX_PIN_NUM_MOSI
#define FLASH_SPIWP_IO MSPI_IOMUX_PIN_NUM_WP
#define FLASH_SPIHD_IO MSPI_IOMUX_PIN_NUM_HD
void bootloader_flash_update_id(void)
{
@@ -98,15 +98,15 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
} else {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MOSI, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_WP, SPIWP_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_HD, SPIHD_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
//select pin function gpio
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
@@ -190,7 +190,7 @@ int bootloader_flash_get_wp_pin(void)
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
return ESP32_PICO_V3_GPIO;
default:
return SPI_WP_GPIO_NUM;
return MSPI_IOMUX_PIN_NUM_WP;
}
#endif
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
+6 -6
View File
@@ -88,12 +88,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
// IDF-4066
const uint32_t spiconfig = 0;
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
if (spiconfig == 0) {
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
+6 -6
View File
@@ -92,12 +92,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
if (spiconfig == 0) {
} else {
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+6 -6
View File
@@ -74,12 +74,12 @@ static const char *TAG = "boot.esp32c5";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
+6 -6
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@@ -69,12 +69,12 @@ static const char *TAG = "boot.esp32c6";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+6 -6
View File
@@ -70,12 +70,12 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
+6 -6
View File
@@ -70,12 +70,12 @@ static const char *TAG = "boot.esp32h2";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+6 -6
View File
@@ -66,12 +66,12 @@ static const char *TAG = "boot.esp32p4";
void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
+7 -7
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -94,12 +94,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
if (spiconfig == 0) {
} else {
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
+6 -6
View File
@@ -105,12 +105,12 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
{
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
uint8_t hd_gpio_num = SPI_HD_GPIO_NUM;
uint8_t wp_gpio_num = SPI_WP_GPIO_NUM;
uint8_t clk_gpio_num = MSPI_IOMUX_PIN_NUM_CLK;
uint8_t q_gpio_num = MSPI_IOMUX_PIN_NUM_MISO;
uint8_t d_gpio_num = MSPI_IOMUX_PIN_NUM_MOSI;
uint8_t cs0_gpio_num = MSPI_IOMUX_PIN_NUM_CS0;
uint8_t hd_gpio_num = MSPI_IOMUX_PIN_NUM_HD;
uint8_t wp_gpio_num = MSPI_IOMUX_PIN_NUM_WP;
if (spiconfig == 0) {
} else {