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fix(ulp): enable astyle linter and format ULP component

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This commit is contained in:
Marius Vikhammer
2024-01-22 11:43:38 +08:00
parent 01f1434fdd
commit 1bcfde4e7f
51 changed files with 525 additions and 589 deletions
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components/ulp/test_apps/lp_core/main/lp_core/test_main.c
+43 -45
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,8 +10,6 @@
#include "test_shared.h"
#include "ulp_lp_core_utils.h"
volatile lp_core_test_commands_t main_cpu_command = LP_CORE_NO_COMMAND;
volatile lp_core_test_command_reply_t main_cpu_reply = LP_CORE_COMMAND_INVALID;
volatile lp_core_test_commands_t command_resp = LP_CORE_NO_COMMAND;
@@ -24,69 +22,69 @@ void handle_commands(lp_core_test_commands_t cmd)
{
switch (cmd) {
case LP_CORE_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_READ_WRITE_TEST;
case LP_CORE_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_READ_WRITE_TEST;
/* Process test data */
test_data_out = test_data_in ^ XOR_MASK;
/* Process test data */
test_data_out = test_data_in ^ XOR_MASK;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
break;
break;
case LP_CORE_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DELAY_TEST;
case LP_CORE_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DELAY_TEST;
ulp_lp_core_delay_us(test_data_in);
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
break;
ulp_lp_core_delay_us(test_data_in);
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
break;
case LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
case LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
ulp_lp_core_delay_us(1000*1000);
ulp_lp_core_wakeup_main_processor();
ulp_lp_core_delay_us(1000 * 1000);
ulp_lp_core_wakeup_main_processor();
break;
break;
case LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
case LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = LP_CORE_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
/* Set the command reply status */
main_cpu_reply = LP_CORE_COMMAND_OK;
main_cpu_command = LP_CORE_NO_COMMAND;
ulp_lp_core_delay_us(10000*1000);
ulp_lp_core_wakeup_main_processor();
ulp_lp_core_delay_us(10000 * 1000);
ulp_lp_core_wakeup_main_processor();
break;
break;
case LP_CORE_NO_COMMAND:
main_cpu_reply = LP_CORE_COMMAND_NOK;
break;
case LP_CORE_NO_COMMAND:
main_cpu_reply = LP_CORE_COMMAND_NOK;
break;
default:
main_cpu_reply = LP_CORE_COMMAND_NOK;
break;
default:
main_cpu_reply = LP_CORE_COMMAND_NOK;
break;
}
}
int main (void)
int main(void)
{
while (1) {
handle_commands(main_cpu_command);
}
}
return 0;
}
components/ulp/test_apps/lp_core/main/lp_core/test_main_counter.c
+1 -1
View File
@@ -10,7 +10,7 @@
volatile uint32_t counter;
volatile uint32_t counter_wakeup_limit;
int main (void)
int main(void)
{
counter++;
components/ulp/test_apps/lp_core/main/lp_core/test_main_gpio.c
+1 -2
View File
@@ -12,8 +12,7 @@
volatile uint32_t gpio_test_finished;
volatile uint32_t gpio_test_succeeded;
int main (void)
int main(void)
{
ulp_lp_core_gpio_init(LP_IO_NUM_0);
components/ulp/test_apps/lp_core/main/lp_core/test_main_i2c.c
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,19 +17,19 @@ volatile lp_core_test_command_reply_t write_test_cmd = LP_CORE_COMMAND_INVALID;
uint8_t data_rd[DATA_LENGTH] = {};
uint8_t data_wr[DATA_LENGTH] = {};
int main (void)
int main(void)
{
lp_core_i2c_master_read_from_device(LP_I2C_NUM_0, I2C_SLAVE_ADDRESS, data_rd, RW_TEST_LENGTH, LP_I2C_TRANS_WAIT_FOREVER);
read_test_reply = LP_CORE_COMMAND_OK;
/* Wait for write command from main CPU */
while(write_test_cmd != LP_CORE_COMMAND_OK) {
while (write_test_cmd != LP_CORE_COMMAND_OK) {
}
lp_core_i2c_master_write_to_device(LP_I2C_NUM_0, I2C_SLAVE_ADDRESS, data_wr, RW_TEST_LENGTH, LP_I2C_TRANS_WAIT_FOREVER);
write_test_cmd = LP_CORE_COMMAND_NOK;
while(1) {
while (1) {
}
}
components/ulp/test_apps/lp_core/main/lp_core/test_main_set_timer_wakeup.c
+2 -2
View File
@@ -11,13 +11,13 @@
volatile uint32_t set_timer_wakeup_counter;
volatile uint32_t WAKEUP_PERIOD_BASE_US = 100000;
int main (void)
int main(void)
{
set_timer_wakeup_counter++;
/* Alternate between WAKEUP_PERIOD_BASE_US and 2*WAKEUP_PERIOD_BASE_US to let the main CPU see that
the wake-up time can be reconfigured */
ulp_lp_core_lp_timer_set_wakeup_time( ((set_timer_wakeup_counter % 2) + 1)*WAKEUP_PERIOD_BASE_US);
ulp_lp_core_lp_timer_set_wakeup_time(((set_timer_wakeup_counter % 2) + 1)*WAKEUP_PERIOD_BASE_US);
return 0;
}
components/ulp/test_apps/lp_core/main/lp_core/test_shared.h
+1 -1
View File
@@ -12,7 +12,7 @@
#define DATA_LENGTH 200
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
typedef enum{
typedef enum {
LP_CORE_READ_WRITE_TEST = 1,
LP_CORE_DELAY_TEST,
LP_CORE_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST,
components/ulp/test_apps/lp_core/main/test_lp_core.c
+16 -20
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,7 +35,7 @@ extern const uint8_t lp_core_main_gpio_bin_end[] asm("_binary_lp_core_test_app
static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end)
{
TEST_ASSERT(ulp_lp_core_load_binary(firmware_start,
(firmware_end - firmware_start)) == ESP_OK);
(firmware_end - firmware_start)) == ESP_OK);
TEST_ASSERT(ulp_lp_core_run(cfg) == ESP_OK);
@@ -137,7 +137,6 @@ static void do_ulp_wakeup_deepsleep(lp_core_test_commands_t ulp_cmd)
UNITY_TEST_FAIL(__LINE__, "Should not get here!");
}
static void check_reset_reason_ulp_wakeup(void)
{
TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause());
@@ -154,13 +153,13 @@ static void do_ulp_wakeup_after_long_delay_deepsleep(void)
}
TEST_CASE_MULTIPLE_STAGES("LP-core is able to wakeup main CPU from deep sleep after a short delay", "[ulp]",
do_ulp_wakeup_after_short_delay_deepsleep,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_short_delay_deepsleep,
check_reset_reason_ulp_wakeup);
/* Certain erroneous wake-up triggers happen only after sleeping for a few seconds */
TEST_CASE_MULTIPLE_STAGES("LP-core is able to wakeup main CPU from deep sleep after a long delay", "[ulp]",
do_ulp_wakeup_after_long_delay_deepsleep,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_long_delay_deepsleep,
check_reset_reason_ulp_wakeup);
RTC_FAST_ATTR static struct timeval tv_start;
@@ -195,9 +194,8 @@ static void check_reset_reason_and_sleep_duration(void)
TEST_ASSERT_EQUAL(ESP_SLEEP_WAKEUP_ULP, esp_sleep_get_wakeup_cause());
int64_t sleep_duration = (tv_stop.tv_sec - tv_start.tv_sec)*1000 + (tv_stop.tv_usec - tv_start.tv_usec)/1000;
int64_t expected_sleep_duration_ms = ulp_counter_wakeup_limit * LP_TIMER_TEST_SLEEP_DURATION_US/1000;
int64_t sleep_duration = (tv_stop.tv_sec - tv_start.tv_sec) * 1000 + (tv_stop.tv_usec - tv_start.tv_usec) / 1000;
int64_t expected_sleep_duration_ms = ulp_counter_wakeup_limit * LP_TIMER_TEST_SLEEP_DURATION_US / 1000;
printf("CPU slept for %"PRIi64" ms, expected it to sleep approx %"PRIi64" ms\n", sleep_duration, expected_sleep_duration_ms);
/* Rough estimate, as CPU spends quite some time waking up, but will test if lp core is waking up way too often etc */
@@ -205,12 +203,11 @@ static void check_reset_reason_and_sleep_duration(void)
}
TEST_CASE_MULTIPLE_STAGES("LP Timer can wakeup lp core periodically during deep sleep", "[ulp]",
do_ulp_wakeup_with_lp_timer_deepsleep,
check_reset_reason_and_sleep_duration);
do_ulp_wakeup_with_lp_timer_deepsleep,
check_reset_reason_and_sleep_duration);
#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32P4)
TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
{
int64_t start, test_duration;
@@ -223,16 +220,15 @@ TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
load_and_start_lp_core_firmware(&cfg, lp_core_main_counter_bin_start, lp_core_main_counter_bin_end);
start = esp_timer_get_time();
vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S*1000));
vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S * 1000));
test_duration = esp_timer_get_time() - start;
uint32_t expected_run_count = test_duration / LP_TIMER_TEST_SLEEP_DURATION_US;
printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_counter, test_duration/1000, expected_run_count);
printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_counter, test_duration / 1000, expected_run_count);
TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_counter, "LP Core did not wake up the expected number of times");
}
static bool ulp_is_running(uint32_t *counter_variable)
{
uint32_t start_cnt = *counter_variable;
@@ -282,13 +278,13 @@ TEST_CASE("LP core can schedule next wake-up time by itself", "[ulp]")
load_and_start_lp_core_firmware(&cfg, lp_core_main_set_timer_wakeup_bin_start, lp_core_main_set_timer_wakeup_bin_end);
start = esp_timer_get_time();
vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S*1000));
vTaskDelay(pdMS_TO_TICKS(LP_TIMER_TEST_DURATION_S * 1000));
test_duration = esp_timer_get_time() - start;
/* ULP will alternative between setting WAKEUP_PERIOD_BASE_US and 2*WAKEUP_PERIOD_BASE_US
as a wakeup period which should give an average wakeup time of 1.5*WAKEUP_PERIOD_BASE_US */
uint32_t expected_run_count = test_duration / (1.5*ulp_WAKEUP_PERIOD_BASE_US);
printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_set_timer_wakeup_counter, test_duration/1000, expected_run_count);
uint32_t expected_run_count = test_duration / (1.5 * ulp_WAKEUP_PERIOD_BASE_US);
printf("LP core ran %"PRIu32" times in %"PRIi64" ms, expected it to run approx %"PRIu32" times\n", ulp_set_timer_wakeup_counter, test_duration / 1000, expected_run_count);
TEST_ASSERT_INT_WITHIN_MESSAGE(5, expected_run_count, ulp_set_timer_wakeup_counter, "LP Core did not wake up the expected number of times");
}
@@ -303,7 +299,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
load_and_start_lp_core_firmware(&cfg, lp_core_main_gpio_bin_start, lp_core_main_gpio_bin_end);
while(!ulp_gpio_test_finished) {
while (!ulp_gpio_test_finished) {
}
TEST_ASSERT_TRUE(ulp_gpio_test_succeeded);
components/ulp/test_apps/lp_core/main/test_lp_core_i2c.c
+8 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -25,20 +25,18 @@ static const char* TAG = "lp_core_i2c_test";
static void load_and_start_lp_core_firmware(ulp_lp_core_cfg_t* cfg, const uint8_t* firmware_start, const uint8_t* firmware_end)
{
TEST_ASSERT(ulp_lp_core_load_binary(firmware_start,
(firmware_end - firmware_start)) == ESP_OK);
(firmware_end - firmware_start)) == ESP_OK);
TEST_ASSERT(ulp_lp_core_run(cfg) == ESP_OK);
}
#define I2C_SCL_IO 7 /*!<gpio number for i2c clock, for C6 only GPIO7 is valid */
#define I2C_SDA_IO 6 /*!<gpio number for i2c data, for C6 only GPIO6 is valid */
#define I2C_SLAVE_NUM I2C_NUM_0 /*!<I2C port number for slave dev */
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
static uint8_t expected_master_write_data[DATA_LENGTH];
static uint8_t expected_master_read_data[DATA_LENGTH];
@@ -50,7 +48,7 @@ static void init_test_data(size_t len)
}
for (int i = 0; i < len; i++) {
expected_master_read_data[i] = i/2;
expected_master_read_data[i] = i / 2;
}
}
@@ -73,7 +71,7 @@ static void i2c_master_write_read_test(void)
load_and_start_lp_core_firmware(&cfg, lp_core_main_i2c_bin_start, lp_core_main_i2c_bin_end);
/* Wait for ULP to finish reading */
while(ulp_read_test_reply == LP_CORE_COMMAND_INVALID) {
while (ulp_read_test_reply == LP_CORE_COMMAND_INVALID) {
}
uint8_t *read_data = (uint8_t*)&ulp_data_rd;
@@ -82,7 +80,7 @@ static void i2c_master_write_read_test(void)
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_master_read_data, read_data, RW_TEST_LENGTH);
uint8_t *wr_data = (uint8_t*)&ulp_data_wr;
for(int i = 0; i < RW_TEST_LENGTH; i++) {
for (int i = 0; i < RW_TEST_LENGTH; i++) {
wr_data[i] = expected_master_write_data[i];
}
@@ -93,12 +91,10 @@ static void i2c_master_write_read_test(void)
unity_send_signal("slave read");
/* Wait for ULP to finish writing */
while( *write_test_cmd != LP_CORE_COMMAND_NOK) {
while (*write_test_cmd != LP_CORE_COMMAND_NOK) {
}
}
static i2c_config_t i2c_slave_init(void)
{
i2c_config_t conf_slave = {
@@ -122,7 +118,7 @@ static void i2c_slave_read_write_test(void)
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_param_config(I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
@@ -135,7 +131,7 @@ static void i2c_slave_read_write_test(void)
unity_send_signal("master write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 10000 / portTICK_PERIOD_MS);
size_rd = i2c_slave_read_buffer(I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 10000 / portTICK_PERIOD_MS);
ESP_LOGI(TAG, "Slave read data:");
ESP_LOG_BUFFER_HEX(TAG, data_rd, size_rd);
TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_master_write_data, data_rd, RW_TEST_LENGTH);
components/ulp/test_apps/ulp_fsm/main/test_ulp.c
+45 -47
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -34,7 +34,8 @@ extern const uint8_t ulp_test_app_bin_end[] asm("_binary_ulp_test_app_bin_end"
#define HEX_DUMP_DEBUG 0
static void hexdump(const uint32_t* src, size_t count) {
static void hexdump(const uint32_t* src, size_t count)
{
#if HEX_DUMP_DEBUG
for (size_t i = 0; i < count; ++i) {
printf("%08x ", *src);
@@ -68,7 +69,7 @@ TEST_CASE("ULP FSM addition test", "[ulp]")
RTC_SLOW_MEM[17] = 11;
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
@@ -107,7 +108,7 @@ TEST_CASE("ULP FSM subtraction and branch test", "[ulp]")
RTC_SLOW_MEM[33] = 18;
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
printf("\n\n");
@@ -131,7 +132,7 @@ TEST_CASE("ULP FSM JUMPS instruction test", "[ulp]")
* This ULP program is written in assembly. Please refer associated .S file.
*/
esp_err_t err = ulp_load_binary(0, ulp_test_app_bin_start,
(ulp_test_app_bin_end - ulp_test_app_bin_start) / sizeof(uint32_t));
(ulp_test_app_bin_end - ulp_test_app_bin_start) / sizeof(uint32_t));
TEST_ESP_OK(err);
/* Clear ULP FSM raw interrupt */
@@ -178,7 +179,7 @@ TEST_CASE("ULP FSM light-sleep wakeup test", "[ulp]")
};
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
@@ -223,7 +224,7 @@ static void ulp_fsm_deepsleep_wakeup_test(void)
};
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
@@ -246,7 +247,6 @@ TEST_CASE_MULTIPLE_STAGES("ULP FSM deep-sleep wakeup test", "[deepsleep][reset=D
ulp_fsm_deepsleep_wakeup_test,
check_sleep_reset)
TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
{
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -261,36 +261,36 @@ TEST_CASE("ULP FSM can write and read peripheral registers", "[ulp]")
/* ULP co-processor program to read from and write to peripheral registers */
const ulp_insn_t program[] = {
I_MOVI(R1, 64), // r1 = 64
I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15), // r0 = REG_READ(RTC_CNTL_STORE1_REG[15:0])
I_ST(R0, R1, 0), // mem[r1 + 0] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11), // r0 = REG_READ(RTC_CNTL_STORE1_REG[11:4])
I_ST(R0, R1, 1), // mem[r1 + 1] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31), // r0 = REG_READ(RTC_CNTL_STORE1_REG[31:16])
I_ST(R0, R1, 2), // mem[r1 + 2] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27), // r0 = REG_READ(RTC_CNTL_STORE1_REG[27:20])
I_ST(R0, R1, 3), // mem[r1 + 3] = r0
I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89), // REG_WRITE(RTC_CNTL_STORE0_REG[7:0], 0x89)
I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab), // REG_WRITE(RTC_CNTL_STORE0_REG[15:8], 0xab)
I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd), // REG_WRITE(RTC_CNTL_STORE0_REG[23:16], 0xcd)
I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef), // REG_WRITE(RTC_CNTL_STORE0_REG[31:24], 0xef)
I_LD(R0, R1, 4), // r0 = mem[r1 + 4]
I_ADDI(R0, R0, 1), // r0 = r0 + 1
I_ST(R0, R1, 4), // mem[r1 + 4] = r0
I_END(), // stop ULP timer
I_HALT() // halt
I_MOVI(R1, 64), // r1 = 64
I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15), // r0 = REG_READ(RTC_CNTL_STORE1_REG[15:0])
I_ST(R0, R1, 0), // mem[r1 + 0] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11), // r0 = REG_READ(RTC_CNTL_STORE1_REG[11:4])
I_ST(R0, R1, 1), // mem[r1 + 1] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31), // r0 = REG_READ(RTC_CNTL_STORE1_REG[31:16])
I_ST(R0, R1, 2), // mem[r1 + 2] = r0
I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27), // r0 = REG_READ(RTC_CNTL_STORE1_REG[27:20])
I_ST(R0, R1, 3), // mem[r1 + 3] = r0
I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89), // REG_WRITE(RTC_CNTL_STORE0_REG[7:0], 0x89)
I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab), // REG_WRITE(RTC_CNTL_STORE0_REG[15:8], 0xab)
I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd), // REG_WRITE(RTC_CNTL_STORE0_REG[23:16], 0xcd)
I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef), // REG_WRITE(RTC_CNTL_STORE0_REG[31:24], 0xef)
I_LD(R0, R1, 4), // r0 = mem[r1 + 4]
I_ADDI(R0, R0, 1), // r0 = r0 + 1
I_ST(R0, R1, 4), // mem[r1 + 4] = r0
I_END(), // stop ULP timer
I_HALT() // halt
};
/* Set data in the peripheral register to be read by the ULP co-processor */
REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
TEST_ESP_OK(ulp_run(0));
/* Wait for the ULP co-processor to finish up */
vTaskDelay(100/portTICK_PERIOD_MS);
vTaskDelay(100 / portTICK_PERIOD_MS);
/* Verify the test results */
TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG));
@@ -328,13 +328,13 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
};
const size_t test_items_count =
sizeof(test_items)/sizeof(test_items[0]);
sizeof(test_items) / sizeof(test_items[0]);
for (size_t i = 0; i < test_items_count; ++i) {
const uint32_t mask = (uint32_t) (((1ULL << test_items[i].width) - 1) << test_items[i].low);
const uint32_t mask = (uint32_t)(((1ULL << test_items[i].width) - 1) << test_items[i].low);
const uint32_t not_mask = ~mask;
printf("#%2d: low: %2d width: %2d mask: %08" PRIx32 " expected: %08" PRIx32 " ", i,
test_items[i].low, test_items[i].width,
mask, not_mask);
test_items[i].low, test_items[i].width,
mask, not_mask);
/* Set all bits in RTC_CNTL_STORE0_REG and reset all bits in RTC_CNTL_STORE1_REG */
uint32_t rtc_store0 = REG_READ(RTC_CNTL_STORE0_REG);
@@ -345,24 +345,24 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
/* ULP co-processor program to write to peripheral registers */
const ulp_insn_t program[] = {
I_WR_REG(RTC_CNTL_STORE0_REG,
test_items[i].low,
test_items[i].low + test_items[i].width - 1,
0),
test_items[i].low,
test_items[i].low + test_items[i].width - 1,
0),
I_WR_REG(RTC_CNTL_STORE1_REG,
test_items[i].low,
test_items[i].low + test_items[i].width - 1,
0xff & ((1 << test_items[i].width) - 1)),
test_items[i].low,
test_items[i].low + test_items[i].width - 1,
0xff & ((1 << test_items[i].width) - 1)),
I_END(),
I_HALT()
};
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
TEST_ESP_OK(ulp_run(0));
/* Wait for the ULP co-processor to finish up */
vTaskDelay(10/portTICK_PERIOD_MS);
vTaskDelay(10 / portTICK_PERIOD_MS);
/* Verify the test results */
uint32_t clear = REG_READ(RTC_CNTL_STORE0_REG);
@@ -378,9 +378,6 @@ TEST_CASE("ULP FSM I_WR_REG instruction test", "[ulp]")
}
}
TEST_CASE("ULP FSM timer setting", "[ulp]")
{
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -403,7 +400,7 @@ TEST_CASE("ULP FSM timer setting", "[ulp]")
};
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
assert(offset >= size && "data offset needs to be greater or equal to program size");
TEST_ESP_OK(ulp_run(0));
@@ -418,7 +415,8 @@ TEST_CASE("ULP FSM timer setting", "[ulp]")
100000, // 100 ms
200000, // 200 ms
500000, // 500 ms
1000000 }; // 1 sec
1000000
}; // 1 sec
const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
for (size_t i = 0; i < tests_count; ++i) {
@@ -474,7 +472,7 @@ TEST_CASE("ULP FSM interrupt signal can be handled via ISRs on the main core", "
TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_register(ulp_isr, (void *)ulp_isr_sem));
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ASSERT_EQUAL(ESP_OK, ulp_process_macros_and_load(0, program, &size));
TEST_ASSERT_EQUAL(ESP_OK, ulp_run(0));
@@ -482,7 +480,7 @@ TEST_CASE("ULP FSM interrupt signal can be handled via ISRs on the main core", "
TEST_ASSERT_EQUAL(pdTRUE, xSemaphoreTake(ulp_isr_sem, portMAX_DELAY));
/* Deregister the ISR */
TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_deregister(ulp_isr, (void *)ulp_isr_sem ));
TEST_ASSERT_EQUAL(ESP_OK, ulp_isr_deregister(ulp_isr, (void *)ulp_isr_sem));
/* Delete test semaphore */
vSemaphoreDelete(ulp_isr_sem);
components/ulp/test_apps/ulp_fsm/main/test_ulp_manual.c
+42 -44
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,29 +43,29 @@ void ulp_fsm_controls_rtc_io(void)
I_MOVI(R0, 0), // r0 is LED state
I_MOVI(R2, 16), // loop r2 from 16 down to 0
M_LABEL(4), // define label 4
I_SUBI(R2, R2, 1), // r2 = r2 - 1
M_BXZ(6), // branch to label 6 if r2 = 0
I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2
I_ANDI(R0, R0, 0x1),
M_BL(0, 1), // if r0 < 1 goto 0
M_LABEL(1), // define label 1
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
M_BX(2), // goto 2
M_LABEL(0), // define label 0
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
M_LABEL(2), // define label 2
I_MOVI(R1, 100), // loop R1 from 100 down to 0
M_LABEL(3), // define label 3
I_SUBI(R1, R1, 1), // r1 = r1 - 1
M_BXZ(5), // branch to label 5 if r1 = 0
I_DELAY(32000), // delay for a while
M_BX(3), // goto 3
M_LABEL(5), // define label 5
M_BX(4), // loop back to label 4
I_SUBI(R2, R2, 1), // r2 = r2 - 1
M_BXZ(6), // branch to label 6 if r2 = 0
I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2
I_ANDI(R0, R0, 0x1),
M_BL(0, 1), // if r0 < 1 goto 0
M_LABEL(1), // define label 1
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
M_BX(2), // goto 2
M_LABEL(0), // define label 0
I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
M_LABEL(2), // define label 2
I_MOVI(R1, 100), // loop R1 from 100 down to 0
M_LABEL(3), // define label 3
I_SUBI(R1, R1, 1), // r1 = r1 - 1
M_BXZ(5), // branch to label 5 if r1 = 0
I_DELAY(32000), // delay for a while
M_BX(3), // goto 3
M_LABEL(5), // define label 5
M_BX(4), // loop back to label 4
M_LABEL(6), // define label 6
I_WAKE(), // wake up the SoC
I_END(), // stop ULP program timer
I_HALT()
I_WAKE(), // wake up the SoC
I_END(), // stop ULP program timer
I_HALT()
};
/* Configure LED GPIOs */
@@ -74,14 +74,14 @@ void ulp_fsm_controls_rtc_io(void)
GPIO_NUM_0,
GPIO_NUM_4
};
for (size_t i = 0; i < sizeof(led_gpios)/sizeof(led_gpios[0]); ++i) {
for (size_t i = 0; i < sizeof(led_gpios) / sizeof(led_gpios[0]); ++i) {
rtc_gpio_init(led_gpios[i]);
rtc_gpio_set_direction(led_gpios[i], RTC_GPIO_MODE_OUTPUT_ONLY);
rtc_gpio_set_level(led_gpios[i], 0);
}
/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
TEST_ESP_OK(ulp_run(0));
@@ -155,18 +155,18 @@ void ulp_fsm_temp_sens(void)
I_SUBI(R3, R3, 1), // end = length - 1
I_SUBR(R3, R3, R2), // r3 = length - counter
M_BXF(1), // if overflow goto 1:
I_TSENS(R0, 16383), // r0 <- tsens
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0
I_ADDI(R2, R2, 1), // counter += 1
I_ST(R2, R1, 1), // save counter
I_HALT(), // enter sleep
I_TSENS(R0, 16383), // r0 <- tsens
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0
I_ADDI(R2, R2, 1), // counter += 1
I_ST(R2, R1, 1), // save counter
I_HALT(), // enter sleep
M_LABEL(1), // done with measurements
I_END(), // stop ULP timer
I_WAKE(), // initiate wakeup
I_HALT()
I_END(), // stop ULP timer
I_WAKE(), // initiate wakeup
I_HALT()
};
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
assert(offset >= size);
@@ -183,8 +183,6 @@ void ulp_fsm_temp_sens(void)
}
#endif //#if !DISABLED_FOR_TARGETS(ESP32)
void ulp_fsm_adc(void)
{
assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
@@ -258,17 +256,17 @@ void ulp_fsm_adc(void)
I_SUBI(R3, R3, 1), // end = length - 1
I_SUBR(R3, R3, R2), // r3 = length - counter
M_BXF(1), // if overflow goto 1:
I_ADC(R0, adc, channel), // r0 <- ADC
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0
I_ADDI(R2, R2, 1), // counter += 1
I_ST(R2, R1, 1), // save counter
I_HALT(), // enter sleep
I_ADC(R0, adc, channel), // r0 <- ADC
I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0
I_ADDI(R2, R2, 1), // counter += 1
I_ST(R2, R1, 1), // save counter
I_HALT(), // enter sleep
M_LABEL(1), // done with measurements
I_END(), // stop ULP program timer
I_HALT()
I_END(), // stop ULP program timer
I_HALT()
};
size_t size = sizeof(program)/sizeof(ulp_insn_t);
size_t size = sizeof(program) / sizeof(ulp_insn_t);
TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
assert(offset >= size);
components/ulp/test_apps/ulp_riscv/main/test_ulp_riscv.c
+13 -19
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -261,8 +261,6 @@ TEST_CASE("ULP-RISC-V can stop itself and be resumed from the main CPU", "[ulp]"
TEST_ASSERT(ulp_riscv_is_running(&ulp_riscv_counter));
}
TEST_CASE("ULP-RISC-V mutex", "[ulp]")
{
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
@@ -281,17 +279,16 @@ TEST_CASE("ULP-RISC-V mutex", "[ulp]")
ulp_riscv_lock_release(lock);
}
while(ulp_main_cpu_reply != RISCV_COMMAND_OK) {
while (ulp_main_cpu_reply != RISCV_COMMAND_OK) {
// Wait for ULP to finish
}
/* If the variable is protected there should be no race conditions
results should be the sum of increments made by ULP and by main CPU
*/
TEST_ASSERT_EQUAL(2*MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer);
TEST_ASSERT_EQUAL(2 * MUTEX_TEST_ITERATIONS, ulp_riscv_incrementer);
}
static void do_ulp_wakeup_deepsleep(riscv_test_commands_t ulp_cmd, bool rtc_periph_pd)
{
if (!rtc_periph_pd) {
@@ -325,9 +322,8 @@ static void do_ulp_wakeup_after_long_delay_deepsleep(void)
/* Certain erroneous wake-up triggers happen only after sleeping for a few seconds */
TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay", "[ulp]",
do_ulp_wakeup_after_long_delay_deepsleep,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_long_delay_deepsleep,
check_reset_reason_ulp_wakeup);
static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void)
{
@@ -335,8 +331,8 @@ static void do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on(void)
}
TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a long delay, RTC periph powerup", "[ulp]",
do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_long_delay_deepsleep_rtc_perip_on,
check_reset_reason_ulp_wakeup);
static void do_ulp_wakeup_after_short_delay_deepsleep(void)
{
@@ -344,9 +340,8 @@ static void do_ulp_wakeup_after_short_delay_deepsleep(void)
}
TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay", "[ulp]",
do_ulp_wakeup_after_short_delay_deepsleep,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_short_delay_deepsleep,
check_reset_reason_ulp_wakeup);
static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void)
{
@@ -354,8 +349,8 @@ static void do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on(void)
}
TEST_CASE_MULTIPLE_STAGES("ULP-RISC-V is able to wakeup main CPU from deep sleep after a short delay, RTC periph powerup", "[ulp]",
do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on,
check_reset_reason_ulp_wakeup);
do_ulp_wakeup_after_short_delay_deepsleep_rtc_perip_on,
check_reset_reason_ulp_wakeup);
typedef struct {
SemaphoreHandle_t ulp_isr_sw_sem;
@@ -393,7 +388,7 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core
/* Register ULP RISC-V signal ISR */
TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_register(ulp_riscv_isr, (void *)&test_sem_cfg,
(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
/* Load ULP RISC-V firmware and start the ULP RISC-V Coprocessor */
printf("Loading good ULP firmware\n");
@@ -425,7 +420,7 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core
/* Deregister the ISR */
TEST_ASSERT_EQUAL(ESP_OK, ulp_riscv_isr_deregister(ulp_riscv_isr, (void *)&test_sem_cfg,
(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
(ULP_RISCV_SW_INT | ULP_RISCV_TRAP_INT)));
/* Delete test semaphores */
vSemaphoreDelete(test_sem_cfg.ulp_isr_sw_sem);
@@ -445,7 +440,6 @@ TEST_CASE("ULP-RISC-V interrupt signals can be handled via ISRs on the main core
TEST_CASE("ULP ADC can init-deinit-init", "[ulp]")
{
ulp_adc_cfg_t riscv_adc_cfg = {
.adc_n = ADC_UNIT,
.channel = CHANNEL,
components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c
+65 -66
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,7 +12,6 @@
#include "ulp_riscv_lock_ulp_core.h"
#include "ulp_test_shared.h"
volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND;
@@ -28,96 +27,96 @@ void handle_commands(riscv_test_commands_t cmd)
riscv_counter++;
switch (cmd) {
case RISCV_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_READ_WRITE_TEST;
case RISCV_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_READ_WRITE_TEST;
/* Process test data */
riscv_test_data_out = riscv_test_data_in ^ XOR_MASK;
/* Process test data */
riscv_test_data_out = riscv_test_data_in ^ XOR_MASK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS);
ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS);
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_STOP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_STOP_TEST;
case RISCV_STOP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_STOP_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Will never return from here */
ulp_riscv_timer_stop();
ulp_riscv_halt();
/* Will never return from here */
ulp_riscv_timer_stop();
ulp_riscv_halt();
break;
break;
case RISCV_MUTEX_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_MUTEX_TEST;
case RISCV_MUTEX_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_MUTEX_TEST;
for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) {
ulp_riscv_lock_acquire(&lock);
riscv_incrementer++;
ulp_riscv_lock_release(&lock);
}
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
main_cpu_command = RISCV_NO_COMMAND;
for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) {
ulp_riscv_lock_acquire(&lock);
riscv_incrementer++;
ulp_riscv_lock_release(&lock);
}
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
main_cpu_command = RISCV_NO_COMMAND;
break;
break;
case RISCV_NO_COMMAND:
main_cpu_reply = RISCV_COMMAND_OK;
break;
case RISCV_NO_COMMAND:
main_cpu_reply = RISCV_COMMAND_OK;
break;
default:
main_cpu_reply = RISCV_COMMAND_NOK;
break;
default:
main_cpu_reply = RISCV_COMMAND_NOK;
break;
}
}
int main (void)
int main(void)
{
while (1) {
components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "ulp_riscv_utils.h"
int main (void)
int main(void)
{
// Wait for the main core in the test case to enter lightsleep
ulp_riscv_delay_cycles(100 * ULP_RISCV_CYCLES_PER_MS);
components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c
+1 -1
View File
@@ -8,7 +8,7 @@
volatile uint32_t riscv_counter2 = 0;
int main (void)
int main(void)
{
riscv_counter2++;
components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h
+1 -1
View File
@@ -8,7 +8,7 @@
#define MUTEX_TEST_ITERATIONS 100000
#define XOR_MASK 0xDEADBEEF
typedef enum{
typedef enum {
RISCV_READ_WRITE_TEST = 1,
RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST,
RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST,