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fix(ulp): enable astyle linter and format ULP component

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This commit is contained in:
Marius Vikhammer
2024-01-22 11:43:38 +08:00
parent 01f1434fdd
commit 1bcfde4e7f
51 changed files with 525 additions and 589 deletions
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components/ulp/test_apps/ulp_riscv/main/ulp/test_main.c
+65 -66
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,7 +12,6 @@
#include "ulp_riscv_lock_ulp_core.h"
#include "ulp_test_shared.h"
volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
volatile riscv_test_commands_t command_resp = RISCV_NO_COMMAND;
@@ -28,96 +27,96 @@ void handle_commands(riscv_test_commands_t cmd)
riscv_counter++;
switch (cmd) {
case RISCV_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_READ_WRITE_TEST;
case RISCV_READ_WRITE_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_READ_WRITE_TEST;
/* Process test data */
riscv_test_data_out = riscv_test_data_in ^ XOR_MASK;
/* Process test data */
riscv_test_data_out = riscv_test_data_in ^ XOR_MASK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS);
ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS);
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_LIGHT_SLEEP_WAKEUP_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
/* Wakeup the main CPU */
ulp_riscv_wakeup_main_processor();
break;
case RISCV_STOP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_STOP_TEST;
case RISCV_STOP_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_STOP_TEST;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
/* Will never return from here */
ulp_riscv_timer_stop();
ulp_riscv_halt();
/* Will never return from here */
ulp_riscv_timer_stop();
ulp_riscv_halt();
break;
break;
case RISCV_MUTEX_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_MUTEX_TEST;
case RISCV_MUTEX_TEST:
/* Echo the command ID back to the main CPU */
command_resp = RISCV_MUTEX_TEST;
for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) {
ulp_riscv_lock_acquire(&lock);
riscv_incrementer++;
ulp_riscv_lock_release(&lock);
}
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
main_cpu_command = RISCV_NO_COMMAND;
for (int i = 0; i < MUTEX_TEST_ITERATIONS; i++) {
ulp_riscv_lock_acquire(&lock);
riscv_incrementer++;
ulp_riscv_lock_release(&lock);
}
/* Set the command reply status */
main_cpu_reply = RISCV_COMMAND_OK;
main_cpu_command = RISCV_NO_COMMAND;
break;
break;
case RISCV_NO_COMMAND:
main_cpu_reply = RISCV_COMMAND_OK;
break;
case RISCV_NO_COMMAND:
main_cpu_reply = RISCV_COMMAND_OK;
break;
default:
main_cpu_reply = RISCV_COMMAND_NOK;
break;
default:
main_cpu_reply = RISCV_COMMAND_NOK;
break;
}
}
int main (void)
int main(void)
{
while (1) {
components/ulp/test_apps/ulp_riscv/main/ulp/test_main_cocpu_crash.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdint.h>
#include "ulp_riscv_utils.h"
int main (void)
int main(void)
{
// Wait for the main core in the test case to enter lightsleep
ulp_riscv_delay_cycles(100 * ULP_RISCV_CYCLES_PER_MS);
components/ulp/test_apps/ulp_riscv/main/ulp/test_main_second_cocpu_firmware.c
+1 -1
View File
@@ -8,7 +8,7 @@
volatile uint32_t riscv_counter2 = 0;
int main (void)
int main(void)
{
riscv_counter2++;
components/ulp/test_apps/ulp_riscv/main/ulp/ulp_test_shared.h
+1 -1
View File
@@ -8,7 +8,7 @@
#define MUTEX_TEST_ITERATIONS 100000
#define XOR_MASK 0xDEADBEEF
typedef enum{
typedef enum {
RISCV_READ_WRITE_TEST = 1,
RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST,
RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST,