global: bring up esp32s2(not beta)
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@@ -16,15 +16,26 @@
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#include "soc/rtc.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#ifdef CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/uart.h"
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#include "esp32/rom/rtc.h"
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#else
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/uart.h"
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#include "esp32s2beta/rom/rtc.h"
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#endif
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#if CONFIG_IDF_ENV_FPGA
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void bootloader_clock_configure(void)
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{
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uart_tx_wait_idle(0);
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REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
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rtc_cpu_freq_t cpu_freq = ets_get_apb_freq();
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ets_update_cpu_frequency(cpu_freq / 1000000);
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REG_WRITE(RTC_CNTL_STORE5_REG, (cpu_freq >> 12) | ((cpu_freq >> 12) << 16));
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}
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#else // CONFIG_IDF_ENV_FPGA
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void bootloader_clock_configure(void)
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{
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// ROM bootloader may have put a lot of text into UART0 FIFO.
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@@ -72,6 +83,7 @@ void bootloader_clock_configure(void)
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}
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#endif
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}
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#endif // CONFIG_IDF_ENV_FPGA
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#ifdef BOOTLOADER_BUILD
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