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esp32c6: add bootloader support

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This commit is contained in:
wuzhenghui
2022-07-08 16:46:11 +08:00
committed by Song Ruo Jing
parent a9f15d1556
commit 1c820b0a6d
22 changed files with 922 additions and 28 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+9 -11
View File
@@ -128,9 +128,9 @@ static const char *TAG = "bootloader_flash";
50th block for bootloader_flash_read
*/
#define MMU_BLOCK0_VADDR SOC_DROM_LOW
#define MMU_SIZE (0x320000)
#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
#define MMAP_MMU_SIZE (0x320000)
#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
#else // !CONFIG_IDF_TARGET_ESP32
@@ -139,15 +139,15 @@ static const char *TAG = "bootloader_flash";
*/
#define MMU_BLOCK0_VADDR SOC_DROM_LOW
#ifdef SOC_MMU_PAGE_SIZE_CONFIGURABLE
#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH(SPI_FLASH_MMU_PAGE_SIZE) - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
#else
#define MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
#define MMAP_MMU_SIZE (DRAM0_CACHE_ADDRESS_HIGH - DRAM0_CACHE_ADDRESS_LOW - SPI_FLASH_MMU_PAGE_SIZE) // This mmu size means that the mmu size to be mapped
#endif
#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMAP_MMU_SIZE)
#define FLASH_READ_VADDR MMU_BLOCK63_VADDR
#endif
#define MMU_FREE_PAGES (MMU_SIZE / FLASH_BLOCK_SIZE)
#define MMU_FREE_PAGES (MMAP_MMU_SIZE / CONFIG_MMU_PAGE_SIZE)
static bool mapped;
@@ -169,7 +169,7 @@ const void *bootloader_mmap(uint32_t src_paddr, uint32_t size)
ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice");
return NULL; /* can't map twice */
}
if (size > MMU_SIZE) {
if (size > MMAP_MMU_SIZE) {
ESP_EARLY_LOGE(TAG, "bootloader_mmap excess size %x", size);
return NULL;
}
@@ -769,10 +769,8 @@ esp_err_t IRAM_ATTR bootloader_flash_reset_chip(void)
bootloader_execute_flash_command(0x05, 0, 0, 0);
#if CONFIG_IDF_TARGET_ESP32
if (SPI1.ext2.st != 0)
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
if (SPIMEM1.fsm.st != 0)
#else
if (SPIMEM1.fsm.spi0_mst_st != 0)
if (!spimem_flash_ll_host_idle(&SPIMEM1))
#endif
{
return ESP_FAIL;
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c
+69
View File
@@ -0,0 +1,69 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include <assert.h>
#include "string.h"
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#include "esp32c6/rom/gpio.h"
#include "esp32c6/rom/spi_flash.h"
#include "esp32c6/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
#include "soc/soc_caps.h"
#include "flash_qio_mode.h"
#include "bootloader_flash_config.h"
#include "bootloader_common.h"
void bootloader_flash_update_id()
{
esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
chip->device_id = bootloader_read_flash_id();
}
void IRAM_ATTR bootloader_flash_cs_timing_config()
{
SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
spi_clk_div = 1;
break;
case ESP_IMAGE_SPI_SPEED_DIV_2:
spi_clk_div = 2;
break;
case ESP_IMAGE_SPI_SPEED_DIV_3:
spi_clk_div = 3;
break;
case ESP_IMAGE_SPI_SPEED_DIV_4:
spi_clk_div = 4;
break;
default:
break;
}
esp_rom_spiflash_config_clk(spi_clk_div, 0);
}
void IRAM_ATTR bootloader_flash_set_dummy_out(void)
{
REG_SET_BIT(SPI_MEM_CTRL_REG(0), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: IDF-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
REG_SET_BIT(SPI_MEM_CTRL_REG(1), /*SPI_MEM_FDUMMY_OUT |*/ SPI_MEM_D_POL | SPI_MEM_Q_POL); // TODO: idf-5631 ESP32C6 not have SPI_MEM_FDUMMY_OUT
}
void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
{
bootloader_configure_spi_pins(1);
bootloader_flash_set_dummy_out();
}
components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
+2 -2
View File
@@ -106,8 +106,8 @@ static void s_flash_set_qio_pins(void)
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
int wp_pin = bootloader_flash_get_wp_pin();
esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
#elif CONFIG_IDF_TARGET_ESP32C2
// ESP32C2 doesn't support configure mspi pins. So the second
#elif CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 // TODO: IDF-5649 Add a soc_caps
// ESP32C2/ESP32C6 doesn't support configure mspi pins. So the second
// parameter is set to 0, means that chip uses default SPI pins
// and wp_gpio_num parameter(the first parameter) is ignored.
esp_rom_spiflash_select_qio_pins(0, 0);