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esp_ipc: Update documentation and API descriptions

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This commit updates the documentation and API descriptions of
the esp_ipc and esp_ipc_isr features.
This commit is contained in:
KonstantinKondrashov
2021-10-26 21:12:26 +08:00
committed by Darian Leung
parent 460f3ad7b6
commit 209702d055
12 changed files with 182 additions and 144 deletions
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components/esp_system/Kconfig
+11 -17
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@@ -512,33 +512,27 @@ menu "IPC (Inter-Processor Call)"
default 2048 if APPTRACE_ENABLE
default 1024
help
Configure the IPC tasks stack size. One IPC task runs on each core
(in dual core mode), and allows for cross-core function calls.
See IPC documentation for more details.
The default stack size should be enough for most common use cases.
It can be shrunk if you are sure that you do not use any custom
IPC functionality.
Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for
cross-core function calls. See IPC documentation for more details. The default IPC stack size should be
enough for most common simple use cases. However, users can increase/decrease the stack size to their
needs.
config ESP_IPC_USES_CALLERS_PRIORITY
bool "IPC runs at caller's priority"
default y
depends on !FREERTOS_UNICORE
help
If this option is not enabled then the IPC task will keep behavior
same as prior to that of ESP-IDF v4.0, and hence IPC task will run
at (configMAX_PRIORITIES - 1) priority.
If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0,
hence IPC task will run at (configMAX_PRIORITIES - 1) priority.
config ESP_IPC_ISR_ENABLE
bool
default y if !FREERTOS_UNICORE
help
This feature serves a similar purpose to the IPC except that the callback function is run
in the context of a level 4 interrupt (i.e., high priority/level interrupt). The IPC ISR
feature is intended for low latency execution of simple functions written in assembly on
another CPU. Due to being run in higher level interrupt context, the assembly functions
should be written in a particular way (see esp_test_ipc_isr_asm() and the "High-Level Interrupts"
chapter in hlinterrupts.rst for more details).
The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the
context of a High Priority Interrupt. The IPC ISR feature is itended for low latency execution of simple
callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly
callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more
details).
endmenu # "IPC (Inter-Processor Call)