feat(wdt): add multicore support for WDTs on RISCV

components/riscv/include/esp_private/panic_reason.h

@@ -5,14 +5,16 @@
  */
 #pragma once
 
-/* Since riscv does not replace mcause with "pseudo_reason" as it xtensa does
- * PANIC_RSN_* defined with original interrupt numbers to make it work in
- * common code
+#include "soc/soc_caps.h"
+
+/* Need a way to signal which core caused the INT WDT like we do with EXCAUSE on xtensa.
+   Choosing a large number that is unlikely to conflict with any actual riscv mcauses
+   bit 12 and above are always zero on the CPU used by P4
  */
 #define PANIC_RSN_INTWDT_CPU0 ETS_INT_WDT_INUM
-
-//TODO: IDF-7511
 #if SOC_CPU_CORES_NUM > 1
-#define PANIC_RSN_INTWDT_CPU1 ETS_INT_WDT_INUM
+#define PANIC_RSN_INTWDT_CPU1_FLAG (1 << 12)
+#define PANIC_RSN_INTWDT_CPU1 (PANIC_RSN_INTWDT_CPU1_FLAG | ETS_INT_WDT_INUM)
 #endif
+
 #define PANIC_RSN_CACHEERR    3