pioduino/esp-idf
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

refactor(regi2c): ana i2c master clock is enabled per request

Browse Source
This commit is contained in:
Song Ruo Jing
2024-08-07 21:04:36 +08:00
parent 92ed77933b
commit 2cb35a2955
55 changed files with 334 additions and 175 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/src/bootloader_random_esp32c5.c
+6
View File
@@ -46,6 +46,9 @@ void bootloader_random_enable(void)
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C (HOST ID 0X69) and choose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_PERIF_ADDR, 1);
@@ -94,6 +97,9 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_EN_TOUT_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_EN_TOUT_ADDR, 0);
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
components/bootloader_support/src/bootloader_random_esp32c6.c
+7 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -40,6 +40,9 @@ void bootloader_random_enable(void)
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
@@ -88,6 +91,9 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
components/bootloader_support/src/bootloader_random_esp32c61.c
+7 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -45,6 +45,9 @@ void bootloader_random_enable(void)
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
@@ -93,6 +96,9 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
components/bootloader_support/src/bootloader_random_esp32h2.c
+7 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -35,6 +35,9 @@ void bootloader_random_enable(void)
// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_DTEST, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 1);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 1);
@@ -80,6 +83,9 @@ void bootloader_random_disable(void)
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_ENT_SAR, 0);
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SARADC_EN_TOUT_SAR1_BUS, 0);
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// disable ADC_CTRL_CLK (SAR ADC function clock)
REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
components/bootloader_support/src/bootloader_random_esp32p4.c
+6
View File
@@ -62,6 +62,9 @@ void bootloader_random_enable(void)
SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
// enable analog i2c master clock for RNG runtime
ANALOG_CLOCK_ENABLE();
adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
// cfg pattern table
@@ -94,6 +97,9 @@ void bootloader_random_enable(void)
void bootloader_random_disable(void)
{
// disable analog i2c master clock
ANALOG_CLOCK_DISABLE();
// No-op for now TODO IDF-6497
// ADC should be set to defaults here, once ADC API is implemented
// OR just keep this empty and let application continue to use RNG initialized by the bootloader
components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+1 -1
View File
@@ -85,7 +85,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
regi2c_ctrl_ll_master_enable_clock(true);
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-8667 Remove this?
regi2c_ctrl_ll_master_configure_clock();
}
components/bootloader_support/src/esp32c6/bootloader_esp32c6.c
+1 -1
View File
@@ -96,7 +96,7 @@ static inline void bootloader_hardware_init(void)
esp_rom_spiflash_fix_dummylen(1, 1);
#endif
regi2c_ctrl_ll_master_enable_clock(true);
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_configure_clock();
}
components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+1 -1
View File
@@ -86,7 +86,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
regi2c_ctrl_ll_master_enable_clock(true);
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-9274 Remove this?
regi2c_ctrl_ll_master_configure_clock();
}
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
+1 -1
View File
@@ -90,7 +90,7 @@ static inline void bootloader_hardware_init(void)
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_RFPLL);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_FORCE_RFPLL);
regi2c_ctrl_ll_master_enable_clock(true);
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_configure_clock();
}
components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
+1 -2
View File
@@ -95,8 +95,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_hardware_init(void)
{
int __DECLARE_RCC_RC_ATOMIC_ENV __attribute__ ((unused)); // To avoid build errors/warnings about __DECLARE_RCC_RC_ATOMIC_ENV
regi2c_ctrl_ll_master_enable_clock(true);
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
regi2c_ctrl_ll_master_configure_clock();
unsigned chip_version = efuse_hal_chip_revision();