Merge branch 'feat/spi_p4_eco5_support_v5.5' into 'release/v5.5'

feat(driver_spi): update p4 eco5 spi and twai support (v5.5)

See merge request espressif/esp-idf!42805

components/hal/esp32p4/include/hal/spi_ll.h

@@ -16,6 +16,7 @@
 
 #include <stdlib.h> //for abs()
 #include <string.h>
+#include "hal/config.h"
 #include "esp_types.h"
 #include "soc/spi_periph.h"
 #include "soc/spi_struct.h"
@@ -246,6 +247,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw)
     hw->slave.val = 0;
     hw->user.val = 0;
 
+    //Disable unused error_end condition
+    hw->user1.mst_wfull_err_end_en = 0;
+    hw->user2.mst_rempty_err_end_en = 0;
+
     hw->dma_conf.val = 0;
     hw->dma_conf.slv_tx_seg_trans_clr_en = 1;
     hw->dma_conf.slv_rx_seg_trans_clr_en = 1;
@@ -747,13 +752,16 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active)
  *----------------------------------------------------------------------------*/
 /**
  * Set the standard clock mode for master.
+ * This config take effect only when SPI_CLK (pre-div before periph) div >=2
  *
  * @param hw  Beginning address of the peripheral registers.
  * @param enable_std True for std timing, False for half cycle delay sampling.
  */
 static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point)
 {
-    //This is not supported
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1);
+#endif
 }
 
 /**
@@ -761,7 +769,11 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_
  */
 static inline bool spi_ll_master_is_rx_std_sample_supported(void)
 {
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+    return true;
+#else
     return false;
+#endif
 }
 
 /**