diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index f1d582651d..7a87e70b91 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -3,7 +3,7 @@ comment "Read the help text of the option below for explanation" config ESP32P4_SELECTS_REV_LESS_V3 bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)" - default y + default n help Select this option to support ESP32-P4 revisions 0.x and 1.x. Revisions higher than 3.0 (included) and revisions less than 3.0 diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h index e7b75d50a4..6545f51a1f 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_i2c_reg.h @@ -11,1183 +11,1183 @@ extern "C" { #endif -/** I2C_SCL_LOW_PERIOD_REG register +/** LP_I2C_SCL_LOW_PERIOD_REG register * Configures the low level width of the SCL * Clock */ -#define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) -/** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_LOW_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x0) +/** LP_I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL remains low in master mode, in * I2C module clock cycles. */ -#define I2C_SCL_LOW_PERIOD 0x000001FFU -#define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) -#define I2C_SCL_LOW_PERIOD_V 0x000001FFU -#define I2C_SCL_LOW_PERIOD_S 0 +#define LP_I2C_SCL_LOW_PERIOD 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_M (LP_I2C_SCL_LOW_PERIOD_V << LP_I2C_SCL_LOW_PERIOD_S) +#define LP_I2C_SCL_LOW_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_LOW_PERIOD_S 0 -/** I2C_CTR_REG register +/** LP_I2C_CTR_REG register * Transmission setting */ -#define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) -/** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; +#define LP_I2C_CTR_REG (DR_REG_LP_I2C_BASE + 0x4) +/** LP_I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; * This register is used to select the sample mode.1: sample SDA data on the SCL low * level.0: sample SDA data on the SCL high level. */ -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) -#define I2C_SAMPLE_SCL_LEVEL_V 0x00000001U -#define I2C_SAMPLE_SCL_LEVEL_S 2 -/** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; +#define LP_I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define LP_I2C_SAMPLE_SCL_LEVEL_M (LP_I2C_SAMPLE_SCL_LEVEL_V << LP_I2C_SAMPLE_SCL_LEVEL_S) +#define LP_I2C_SAMPLE_SCL_LEVEL_V 0x00000001U +#define LP_I2C_SAMPLE_SCL_LEVEL_S 2 +/** LP_I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * This register is used to configure the ACK value that need to sent by master when * the rx_fifo_cnt has reached the threshold. */ -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) -#define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U -#define I2C_RX_FULL_ACK_LEVEL_S 3 -/** I2C_TRANS_START : WT; bitpos: [5]; default: 0; +#define LP_I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define LP_I2C_RX_FULL_ACK_LEVEL_M (LP_I2C_RX_FULL_ACK_LEVEL_V << LP_I2C_RX_FULL_ACK_LEVEL_S) +#define LP_I2C_RX_FULL_ACK_LEVEL_V 0x00000001U +#define LP_I2C_RX_FULL_ACK_LEVEL_S 3 +/** LP_I2C_TRANS_START : WT; bitpos: [5]; default: 0; * Set this bit to start sending the data in txfifo. */ -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (I2C_TRANS_START_V << I2C_TRANS_START_S) -#define I2C_TRANS_START_V 0x00000001U -#define I2C_TRANS_START_S 5 -/** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; +#define LP_I2C_TRANS_START (BIT(5)) +#define LP_I2C_TRANS_START_M (LP_I2C_TRANS_START_V << LP_I2C_TRANS_START_S) +#define LP_I2C_TRANS_START_V 0x00000001U +#define LP_I2C_TRANS_START_S 5 +/** LP_I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; * This bit is used to control the sending mode for data needing to be sent. 1: send * data from the least significant bit,0: send data from the most significant bit. */ -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) -#define I2C_TX_LSB_FIRST_V 0x00000001U -#define I2C_TX_LSB_FIRST_S 6 -/** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; +#define LP_I2C_TX_LSB_FIRST (BIT(6)) +#define LP_I2C_TX_LSB_FIRST_M (LP_I2C_TX_LSB_FIRST_V << LP_I2C_TX_LSB_FIRST_S) +#define LP_I2C_TX_LSB_FIRST_V 0x00000001U +#define LP_I2C_TX_LSB_FIRST_S 6 +/** LP_I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; * This bit is used to control the storage mode for received data.1: receive data from * the least significant bit,0: receive data from the most significant bit. */ -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) -#define I2C_RX_LSB_FIRST_V 0x00000001U -#define I2C_RX_LSB_FIRST_S 7 -/** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; +#define LP_I2C_RX_LSB_FIRST (BIT(7)) +#define LP_I2C_RX_LSB_FIRST_M (LP_I2C_RX_LSB_FIRST_V << LP_I2C_RX_LSB_FIRST_S) +#define LP_I2C_RX_LSB_FIRST_V 0x00000001U +#define LP_I2C_RX_LSB_FIRST_S 7 +/** LP_I2C_CLK_EN : R/W; bitpos: [8]; default: 0; * Reserved */ -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) -#define I2C_CLK_EN_V 0x00000001U -#define I2C_CLK_EN_S 8 -/** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_CLK_EN (BIT(8)) +#define LP_I2C_CLK_EN_M (LP_I2C_CLK_EN_V << LP_I2C_CLK_EN_S) +#define LP_I2C_CLK_EN_V 0x00000001U +#define LP_I2C_CLK_EN_S 8 +/** LP_I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; * This is the enable bit for arbitration_lost. */ -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) -#define I2C_ARBITRATION_EN_V 0x00000001U -#define I2C_ARBITRATION_EN_S 9 -/** I2C_FSM_RST : WT; bitpos: [10]; default: 0; +#define LP_I2C_ARBITRATION_EN (BIT(9)) +#define LP_I2C_ARBITRATION_EN_M (LP_I2C_ARBITRATION_EN_V << LP_I2C_ARBITRATION_EN_S) +#define LP_I2C_ARBITRATION_EN_V 0x00000001U +#define LP_I2C_ARBITRATION_EN_S 9 +/** LP_I2C_FSM_RST : WT; bitpos: [10]; default: 0; * This register is used to reset the scl FMS. */ -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (I2C_FSM_RST_V << I2C_FSM_RST_S) -#define I2C_FSM_RST_V 0x00000001U -#define I2C_FSM_RST_S 10 -/** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; +#define LP_I2C_FSM_RST (BIT(10)) +#define LP_I2C_FSM_RST_M (LP_I2C_FSM_RST_V << LP_I2C_FSM_RST_S) +#define LP_I2C_FSM_RST_V 0x00000001U +#define LP_I2C_FSM_RST_S 10 +/** LP_I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; * synchronization bit */ -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (I2C_CONF_UPGATE_V << I2C_CONF_UPGATE_S) -#define I2C_CONF_UPGATE_V 0x00000001U -#define I2C_CONF_UPGATE_S 11 +#define LP_I2C_CONF_UPGATE (BIT(11)) +#define LP_I2C_CONF_UPGATE_M (LP_I2C_CONF_UPGATE_V << LP_I2C_CONF_UPGATE_S) +#define LP_I2C_CONF_UPGATE_V 0x00000001U +#define LP_I2C_CONF_UPGATE_S 11 -/** I2C_SR_REG register +/** LP_I2C_SR_REG register * Describe I2C work status. */ -#define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) -/** I2C_RESP_REC : RO; bitpos: [0]; default: 0; +#define LP_I2C_SR_REG (DR_REG_LP_I2C_BASE + 0x8) +/** LP_I2C_RESP_REC : RO; bitpos: [0]; default: 0; * The received ACK value in master mode or slave mode. 0: ACK, 1: NACK. */ -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (I2C_RESP_REC_V << I2C_RESP_REC_S) -#define I2C_RESP_REC_V 0x00000001U -#define I2C_RESP_REC_S 0 -/** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; +#define LP_I2C_RESP_REC (BIT(0)) +#define LP_I2C_RESP_REC_M (LP_I2C_RESP_REC_V << LP_I2C_RESP_REC_S) +#define LP_I2C_RESP_REC_V 0x00000001U +#define LP_I2C_RESP_REC_S 0 +/** LP_I2C_ARB_LOST : RO; bitpos: [3]; default: 0; * When the I2C controller loses control of SCL line, this register changes to 1. */ -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) -#define I2C_ARB_LOST_V 0x00000001U -#define I2C_ARB_LOST_S 3 -/** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; +#define LP_I2C_ARB_LOST (BIT(3)) +#define LP_I2C_ARB_LOST_M (LP_I2C_ARB_LOST_V << LP_I2C_ARB_LOST_S) +#define LP_I2C_ARB_LOST_V 0x00000001U +#define LP_I2C_ARB_LOST_S 3 +/** LP_I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; * 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state. */ -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) -#define I2C_BUS_BUSY_V 0x00000001U -#define I2C_BUS_BUSY_S 4 -/** I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; +#define LP_I2C_BUS_BUSY (BIT(4)) +#define LP_I2C_BUS_BUSY_M (LP_I2C_BUS_BUSY_V << LP_I2C_BUS_BUSY_S) +#define LP_I2C_BUS_BUSY_V 0x00000001U +#define LP_I2C_BUS_BUSY_S 4 +/** LP_I2C_RXFIFO_CNT : RO; bitpos: [12:8]; default: 0; * This field represents the amount of data needed to be sent. */ -#define I2C_RXFIFO_CNT 0x0000001FU -#define I2C_RXFIFO_CNT_M (I2C_RXFIFO_CNT_V << I2C_RXFIFO_CNT_S) -#define I2C_RXFIFO_CNT_V 0x0000001FU -#define I2C_RXFIFO_CNT_S 8 -/** I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; +#define LP_I2C_RXFIFO_CNT 0x0000001FU +#define LP_I2C_RXFIFO_CNT_M (LP_I2C_RXFIFO_CNT_V << LP_I2C_RXFIFO_CNT_S) +#define LP_I2C_RXFIFO_CNT_V 0x0000001FU +#define LP_I2C_RXFIFO_CNT_S 8 +/** LP_I2C_TXFIFO_CNT : RO; bitpos: [22:18]; default: 0; * This field stores the amount of received data in RAM. */ -#define I2C_TXFIFO_CNT 0x0000001FU -#define I2C_TXFIFO_CNT_M (I2C_TXFIFO_CNT_V << I2C_TXFIFO_CNT_S) -#define I2C_TXFIFO_CNT_V 0x0000001FU -#define I2C_TXFIFO_CNT_S 18 -/** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; +#define LP_I2C_TXFIFO_CNT 0x0000001FU +#define LP_I2C_TXFIFO_CNT_M (LP_I2C_TXFIFO_CNT_V << LP_I2C_TXFIFO_CNT_S) +#define LP_I2C_TXFIFO_CNT_V 0x0000001FU +#define LP_I2C_TXFIFO_CNT_S 18 +/** LP_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; * This field indicates the states of the I2C module state machine. 0: Idle, 1: * Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK */ -#define I2C_SCL_MAIN_STATE_LAST 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_M (I2C_SCL_MAIN_STATE_LAST_V << I2C_SCL_MAIN_STATE_LAST_S) -#define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U -#define I2C_SCL_MAIN_STATE_LAST_S 24 -/** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; +#define LP_I2C_SCL_MAIN_STATE_LAST 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_M (LP_I2C_SCL_MAIN_STATE_LAST_V << LP_I2C_SCL_MAIN_STATE_LAST_S) +#define LP_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_MAIN_STATE_LAST_S 24 +/** LP_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; * This field indicates the states of the state machine used to produce SCL.0: Idle, * 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop */ -#define I2C_SCL_STATE_LAST 0x00000007U -#define I2C_SCL_STATE_LAST_M (I2C_SCL_STATE_LAST_V << I2C_SCL_STATE_LAST_S) -#define I2C_SCL_STATE_LAST_V 0x00000007U -#define I2C_SCL_STATE_LAST_S 28 +#define LP_I2C_SCL_STATE_LAST 0x00000007U +#define LP_I2C_SCL_STATE_LAST_M (LP_I2C_SCL_STATE_LAST_V << LP_I2C_SCL_STATE_LAST_S) +#define LP_I2C_SCL_STATE_LAST_V 0x00000007U +#define LP_I2C_SCL_STATE_LAST_S 28 -/** I2C_TO_REG register +/** LP_I2C_TO_REG register * Setting time out control for receiving data. */ -#define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) -/** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_TO_REG (DR_REG_LP_I2C_BASE + 0xc) +/** LP_I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * This register is used to configure the timeout for receiving a data bit in APBclock * cycles. */ -#define I2C_TIME_OUT_VALUE 0x0000001FU -#define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) -#define I2C_TIME_OUT_VALUE_V 0x0000001FU -#define I2C_TIME_OUT_VALUE_S 0 -/** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; +#define LP_I2C_TIME_OUT_VALUE 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_M (LP_I2C_TIME_OUT_VALUE_V << LP_I2C_TIME_OUT_VALUE_S) +#define LP_I2C_TIME_OUT_VALUE_V 0x0000001FU +#define LP_I2C_TIME_OUT_VALUE_S 0 +/** LP_I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; * This is the enable bit for time out control. */ -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) -#define I2C_TIME_OUT_EN_V 0x00000001U -#define I2C_TIME_OUT_EN_S 5 +#define LP_I2C_TIME_OUT_EN (BIT(5)) +#define LP_I2C_TIME_OUT_EN_M (LP_I2C_TIME_OUT_EN_V << LP_I2C_TIME_OUT_EN_S) +#define LP_I2C_TIME_OUT_EN_V 0x00000001U +#define LP_I2C_TIME_OUT_EN_S 5 -/** I2C_FIFO_ST_REG register +/** LP_I2C_FIFO_ST_REG register * FIFO status register. */ -#define I2C_FIFO_ST_REG (DR_REG_I2C_BASE + 0x14) -/** I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; +#define LP_I2C_FIFO_ST_REG (DR_REG_LP_I2C_BASE + 0x14) +/** LP_I2C_RXFIFO_RADDR : RO; bitpos: [3:0]; default: 0; * This is the offset address of the APB reading from rxfifo */ -#define I2C_RXFIFO_RADDR 0x0000000FU -#define I2C_RXFIFO_RADDR_M (I2C_RXFIFO_RADDR_V << I2C_RXFIFO_RADDR_S) -#define I2C_RXFIFO_RADDR_V 0x0000000FU -#define I2C_RXFIFO_RADDR_S 0 -/** I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; +#define LP_I2C_RXFIFO_RADDR 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_M (LP_I2C_RXFIFO_RADDR_V << LP_I2C_RXFIFO_RADDR_S) +#define LP_I2C_RXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_RADDR_S 0 +/** LP_I2C_RXFIFO_WADDR : RO; bitpos: [8:5]; default: 0; * This is the offset address of i2c module receiving data and writing to rxfifo. */ -#define I2C_RXFIFO_WADDR 0x0000000FU -#define I2C_RXFIFO_WADDR_M (I2C_RXFIFO_WADDR_V << I2C_RXFIFO_WADDR_S) -#define I2C_RXFIFO_WADDR_V 0x0000000FU -#define I2C_RXFIFO_WADDR_S 5 -/** I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; +#define LP_I2C_RXFIFO_WADDR 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_M (LP_I2C_RXFIFO_WADDR_V << LP_I2C_RXFIFO_WADDR_S) +#define LP_I2C_RXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_RXFIFO_WADDR_S 5 +/** LP_I2C_TXFIFO_RADDR : RO; bitpos: [13:10]; default: 0; * This is the offset address of i2c module reading from txfifo. */ -#define I2C_TXFIFO_RADDR 0x0000000FU -#define I2C_TXFIFO_RADDR_M (I2C_TXFIFO_RADDR_V << I2C_TXFIFO_RADDR_S) -#define I2C_TXFIFO_RADDR_V 0x0000000FU -#define I2C_TXFIFO_RADDR_S 10 -/** I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; +#define LP_I2C_TXFIFO_RADDR 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_M (LP_I2C_TXFIFO_RADDR_V << LP_I2C_TXFIFO_RADDR_S) +#define LP_I2C_TXFIFO_RADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_RADDR_S 10 +/** LP_I2C_TXFIFO_WADDR : RO; bitpos: [18:15]; default: 0; * This is the offset address of APB bus writing to txfifo. */ -#define I2C_TXFIFO_WADDR 0x0000000FU -#define I2C_TXFIFO_WADDR_M (I2C_TXFIFO_WADDR_V << I2C_TXFIFO_WADDR_S) -#define I2C_TXFIFO_WADDR_V 0x0000000FU -#define I2C_TXFIFO_WADDR_S 15 +#define LP_I2C_TXFIFO_WADDR 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_M (LP_I2C_TXFIFO_WADDR_V << LP_I2C_TXFIFO_WADDR_S) +#define LP_I2C_TXFIFO_WADDR_V 0x0000000FU +#define LP_I2C_TXFIFO_WADDR_S 15 -/** I2C_FIFO_CONF_REG register +/** LP_I2C_FIFO_CONF_REG register * FIFO configuration register. */ -#define I2C_FIFO_CONF_REG (DR_REG_I2C_BASE + 0x18) -/** I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; +#define LP_I2C_FIFO_CONF_REG (DR_REG_LP_I2C_BASE + 0x18) +/** LP_I2C_RXFIFO_WM_THRHD : R/W; bitpos: [3:0]; default: 6; * The water mark threshold of rx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than * reg_rxfifo_wm_thrhd[3:0], reg_rxfifo_wm_int_raw bit will be valid. */ -#define I2C_RXFIFO_WM_THRHD 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_M (I2C_RXFIFO_WM_THRHD_V << I2C_RXFIFO_WM_THRHD_S) -#define I2C_RXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_RXFIFO_WM_THRHD_S 0 -/** I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; +#define LP_I2C_RXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_M (LP_I2C_RXFIFO_WM_THRHD_V << LP_I2C_RXFIFO_WM_THRHD_S) +#define LP_I2C_RXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_RXFIFO_WM_THRHD_S 0 +/** LP_I2C_TXFIFO_WM_THRHD : R/W; bitpos: [8:5]; default: 2; * The water mark threshold of tx FIFO in nonfifo access mode. When * reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than * reg_txfifo_wm_thrhd[3:0], reg_txfifo_wm_int_raw bit will be valid. */ -#define I2C_TXFIFO_WM_THRHD 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_M (I2C_TXFIFO_WM_THRHD_V << I2C_TXFIFO_WM_THRHD_S) -#define I2C_TXFIFO_WM_THRHD_V 0x0000000FU -#define I2C_TXFIFO_WM_THRHD_S 5 -/** I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; +#define LP_I2C_TXFIFO_WM_THRHD 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_M (LP_I2C_TXFIFO_WM_THRHD_V << LP_I2C_TXFIFO_WM_THRHD_S) +#define LP_I2C_TXFIFO_WM_THRHD_V 0x0000000FU +#define LP_I2C_TXFIFO_WM_THRHD_S 5 +/** LP_I2C_NONFIFO_EN : R/W; bitpos: [10]; default: 0; * Set this bit to enable APB nonfifo access. */ -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (I2C_NONFIFO_EN_V << I2C_NONFIFO_EN_S) -#define I2C_NONFIFO_EN_V 0x00000001U -#define I2C_NONFIFO_EN_S 10 -/** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; +#define LP_I2C_NONFIFO_EN (BIT(10)) +#define LP_I2C_NONFIFO_EN_M (LP_I2C_NONFIFO_EN_V << LP_I2C_NONFIFO_EN_S) +#define LP_I2C_NONFIFO_EN_V 0x00000001U +#define LP_I2C_NONFIFO_EN_S 10 +/** LP_I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; * Set this bit to reset rx-fifo. */ -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (I2C_RX_FIFO_RST_V << I2C_RX_FIFO_RST_S) -#define I2C_RX_FIFO_RST_V 0x00000001U -#define I2C_RX_FIFO_RST_S 12 -/** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; +#define LP_I2C_RX_FIFO_RST (BIT(12)) +#define LP_I2C_RX_FIFO_RST_M (LP_I2C_RX_FIFO_RST_V << LP_I2C_RX_FIFO_RST_S) +#define LP_I2C_RX_FIFO_RST_V 0x00000001U +#define LP_I2C_RX_FIFO_RST_S 12 +/** LP_I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; * Set this bit to reset tx-fifo. */ -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (I2C_TX_FIFO_RST_V << I2C_TX_FIFO_RST_S) -#define I2C_TX_FIFO_RST_V 0x00000001U -#define I2C_TX_FIFO_RST_S 13 -/** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; +#define LP_I2C_TX_FIFO_RST (BIT(13)) +#define LP_I2C_TX_FIFO_RST_M (LP_I2C_TX_FIFO_RST_V << LP_I2C_TX_FIFO_RST_S) +#define LP_I2C_TX_FIFO_RST_V 0x00000001U +#define LP_I2C_TX_FIFO_RST_S 13 +/** LP_I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * The control enable bit of FIFO pointer in non-fifo access mode. This bit controls * the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty. */ -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) -#define I2C_FIFO_PRT_EN_V 0x00000001U -#define I2C_FIFO_PRT_EN_S 14 +#define LP_I2C_FIFO_PRT_EN (BIT(14)) +#define LP_I2C_FIFO_PRT_EN_M (LP_I2C_FIFO_PRT_EN_V << LP_I2C_FIFO_PRT_EN_S) +#define LP_I2C_FIFO_PRT_EN_V 0x00000001U +#define LP_I2C_FIFO_PRT_EN_S 14 -/** I2C_DATA_REG register +/** LP_I2C_DATA_REG register * Rx FIFO read data. */ -#define I2C_DATA_REG (DR_REG_I2C_BASE + 0x1c) -/** I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; +#define LP_I2C_DATA_REG (DR_REG_LP_I2C_BASE + 0x1c) +/** LP_I2C_FIFO_RDATA : RO; bitpos: [7:0]; default: 0; * The value of rx FIFO read data. */ -#define I2C_FIFO_RDATA 0x000000FFU -#define I2C_FIFO_RDATA_M (I2C_FIFO_RDATA_V << I2C_FIFO_RDATA_S) -#define I2C_FIFO_RDATA_V 0x000000FFU -#define I2C_FIFO_RDATA_S 0 +#define LP_I2C_FIFO_RDATA 0x000000FFU +#define LP_I2C_FIFO_RDATA_M (LP_I2C_FIFO_RDATA_V << LP_I2C_FIFO_RDATA_S) +#define LP_I2C_FIFO_RDATA_V 0x000000FFU +#define LP_I2C_FIFO_RDATA_S 0 -/** I2C_INT_RAW_REG register +/** LP_I2C_INT_RAW_REG register * Raw interrupt status */ -#define I2C_INT_RAW_REG (DR_REG_I2C_BASE + 0x20) -/** I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_RAW_REG (DR_REG_LP_I2C_BASE + 0x20) +/** LP_I2C_RXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (I2C_RXFIFO_WM_INT_RAW_V << I2C_RXFIFO_WM_INT_RAW_S) -#define I2C_RXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_WM_INT_RAW_S 0 -/** I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; - * The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_RAW_M (LP_I2C_RXFIFO_WM_INT_RAW_V << LP_I2C_RXFIFO_WM_INT_RAW_S) +#define LP_I2C_RXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_RAW_S 0 +/** LP_I2C_TXFIFO_WM_INT_RAW : R/SS/WTC; bitpos: [1]; default: 1; + * The raw interrupt bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (I2C_TXFIFO_WM_INT_RAW_V << I2C_TXFIFO_WM_INT_RAW_S) -#define I2C_TXFIFO_WM_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_WM_INT_RAW_S 1 -/** I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_RAW_M (LP_I2C_TXFIFO_WM_INT_RAW_V << LP_I2C_TXFIFO_WM_INT_RAW_S) +#define LP_I2C_TXFIFO_WM_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_RAW_S 1 +/** LP_I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [2]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (I2C_RXFIFO_OVF_INT_RAW_V << I2C_RXFIFO_OVF_INT_RAW_S) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_RAW_S 2 -/** I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_RAW_M (LP_I2C_RXFIFO_OVF_INT_RAW_V << LP_I2C_RXFIFO_OVF_INT_RAW_S) +#define LP_I2C_RXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_RAW_S 2 +/** LP_I2C_END_DETECT_INT_RAW : R/SS/WTC; bitpos: [3]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (I2C_END_DETECT_INT_RAW_V << I2C_END_DETECT_INT_RAW_S) -#define I2C_END_DETECT_INT_RAW_V 0x00000001U -#define I2C_END_DETECT_INT_RAW_S 3 -/** I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; - * The raw interrupt bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_RAW (BIT(3)) +#define LP_I2C_END_DETECT_INT_RAW_M (LP_I2C_END_DETECT_INT_RAW_V << LP_I2C_END_DETECT_INT_RAW_S) +#define LP_I2C_END_DETECT_INT_RAW_V 0x00000001U +#define LP_I2C_END_DETECT_INT_RAW_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC; bitpos: [4]; default: 0; + * The raw interrupt bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (I2C_BYTE_TRANS_DONE_INT_RAW_V << I2C_BYTE_TRANS_DONE_INT_RAW_S) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 -/** I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; - * The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_M (LP_I2C_BYTE_TRANS_DONE_INT_RAW_V << LP_I2C_BYTE_TRANS_DONE_INT_RAW_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_RAW_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC; bitpos: [5]; default: 0; + * The raw interrupt bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (I2C_ARBITRATION_LOST_INT_RAW_V << I2C_ARBITRATION_LOST_INT_RAW_S) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 -/** I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; - * The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_M (LP_I2C_ARBITRATION_LOST_INT_RAW_V << LP_I2C_ARBITRATION_LOST_INT_RAW_S) +#define LP_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_RAW_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [6]; default: 0; + * The raw interrupt bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (I2C_MST_TXFIFO_UDF_INT_RAW_V << I2C_MST_TXFIFO_UDF_INT_RAW_S) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 -/** I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; - * The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_M (LP_I2C_MST_TXFIFO_UDF_INT_RAW_V << LP_I2C_MST_TXFIFO_UDF_INT_RAW_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_RAW_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC; bitpos: [7]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (I2C_TRANS_COMPLETE_INT_RAW_V << I2C_TRANS_COMPLETE_INT_RAW_S) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 -/** I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; - * The raw interrupt bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_M (LP_I2C_TRANS_COMPLETE_INT_RAW_V << LP_I2C_TRANS_COMPLETE_INT_RAW_S) +#define LP_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_RAW_S 7 +/** LP_I2C_TIME_OUT_INT_RAW : R/SS/WTC; bitpos: [8]; default: 0; + * The raw interrupt bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (I2C_TIME_OUT_INT_RAW_V << I2C_TIME_OUT_INT_RAW_S) -#define I2C_TIME_OUT_INT_RAW_V 0x00000001U -#define I2C_TIME_OUT_INT_RAW_S 8 -/** I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; - * The raw interrupt bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_RAW (BIT(8)) +#define LP_I2C_TIME_OUT_INT_RAW_M (LP_I2C_TIME_OUT_INT_RAW_V << LP_I2C_TIME_OUT_INT_RAW_S) +#define LP_I2C_TIME_OUT_INT_RAW_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_RAW_S 8 +/** LP_I2C_TRANS_START_INT_RAW : R/SS/WTC; bitpos: [9]; default: 0; + * The raw interrupt bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (I2C_TRANS_START_INT_RAW_V << I2C_TRANS_START_INT_RAW_S) -#define I2C_TRANS_START_INT_RAW_V 0x00000001U -#define I2C_TRANS_START_INT_RAW_S 9 -/** I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; - * The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_RAW (BIT(9)) +#define LP_I2C_TRANS_START_INT_RAW_M (LP_I2C_TRANS_START_INT_RAW_V << LP_I2C_TRANS_START_INT_RAW_S) +#define LP_I2C_TRANS_START_INT_RAW_V 0x00000001U +#define LP_I2C_TRANS_START_INT_RAW_S 9 +/** LP_I2C_NACK_INT_RAW : R/SS/WTC; bitpos: [10]; default: 0; + * The raw interrupt bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (I2C_NACK_INT_RAW_V << I2C_NACK_INT_RAW_S) -#define I2C_NACK_INT_RAW_V 0x00000001U -#define I2C_NACK_INT_RAW_S 10 -/** I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; - * The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_RAW (BIT(10)) +#define LP_I2C_NACK_INT_RAW_M (LP_I2C_NACK_INT_RAW_V << LP_I2C_NACK_INT_RAW_S) +#define LP_I2C_NACK_INT_RAW_V 0x00000001U +#define LP_I2C_NACK_INT_RAW_S 10 +/** LP_I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC; bitpos: [11]; default: 0; + * The raw interrupt bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (I2C_TXFIFO_OVF_INT_RAW_V << I2C_TXFIFO_OVF_INT_RAW_S) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_RAW_S 11 -/** I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; - * The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_RAW_M (LP_I2C_TXFIFO_OVF_INT_RAW_V << LP_I2C_TXFIFO_OVF_INT_RAW_S) +#define LP_I2C_TXFIFO_OVF_INT_RAW_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_RAW_S 11 +/** LP_I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC; bitpos: [12]; default: 0; + * The raw interrupt bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (I2C_RXFIFO_UDF_INT_RAW_V << I2C_RXFIFO_UDF_INT_RAW_S) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_RAW_S 12 -/** I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; - * The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_RAW_M (LP_I2C_RXFIFO_UDF_INT_RAW_V << LP_I2C_RXFIFO_UDF_INT_RAW_S) +#define LP_I2C_RXFIFO_UDF_INT_RAW_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_RAW_S 12 +/** LP_I2C_SCL_ST_TO_INT_RAW : R/SS/WTC; bitpos: [13]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (I2C_SCL_ST_TO_INT_RAW_V << I2C_SCL_ST_TO_INT_RAW_S) -#define I2C_SCL_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_ST_TO_INT_RAW_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; - * The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_RAW_M (LP_I2C_SCL_ST_TO_INT_RAW_V << LP_I2C_SCL_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_RAW_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC; bitpos: [14]; default: 0; + * The raw interrupt bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (I2C_SCL_MAIN_ST_TO_INT_RAW_V << I2C_SCL_MAIN_ST_TO_INT_RAW_S) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 -/** I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; - * The raw interrupt bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_M (LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V << LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/** LP_I2C_DET_START_INT_RAW : R/SS/WTC; bitpos: [15]; default: 0; + * The raw interrupt bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (I2C_DET_START_INT_RAW_V << I2C_DET_START_INT_RAW_S) -#define I2C_DET_START_INT_RAW_V 0x00000001U -#define I2C_DET_START_INT_RAW_S 15 +#define LP_I2C_DET_START_INT_RAW (BIT(15)) +#define LP_I2C_DET_START_INT_RAW_M (LP_I2C_DET_START_INT_RAW_V << LP_I2C_DET_START_INT_RAW_S) +#define LP_I2C_DET_START_INT_RAW_V 0x00000001U +#define LP_I2C_DET_START_INT_RAW_S 15 -/** I2C_INT_CLR_REG register +/** LP_I2C_INT_CLR_REG register * Interrupt clear bits */ -#define I2C_INT_CLR_REG (DR_REG_I2C_BASE + 0x24) -/** I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_CLR_REG (DR_REG_LP_I2C_BASE + 0x24) +/** LP_I2C_RXFIFO_WM_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (I2C_RXFIFO_WM_INT_CLR_V << I2C_RXFIFO_WM_INT_CLR_S) -#define I2C_RXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_WM_INT_CLR_S 0 -/** I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_CLR_M (LP_I2C_RXFIFO_WM_INT_CLR_V << LP_I2C_RXFIFO_WM_INT_CLR_S) +#define LP_I2C_RXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_CLR_S 0 +/** LP_I2C_TXFIFO_WM_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (I2C_TXFIFO_WM_INT_CLR_V << I2C_TXFIFO_WM_INT_CLR_S) -#define I2C_TXFIFO_WM_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_WM_INT_CLR_S 1 -/** I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_CLR_M (LP_I2C_TXFIFO_WM_INT_CLR_V << LP_I2C_TXFIFO_WM_INT_CLR_S) +#define LP_I2C_TXFIFO_WM_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_CLR_S 1 +/** LP_I2C_RXFIFO_OVF_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (I2C_RXFIFO_OVF_INT_CLR_V << I2C_RXFIFO_OVF_INT_CLR_S) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_CLR_S 2 -/** I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_CLR_M (LP_I2C_RXFIFO_OVF_INT_CLR_V << LP_I2C_RXFIFO_OVF_INT_CLR_S) +#define LP_I2C_RXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_CLR_S 2 +/** LP_I2C_END_DETECT_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (I2C_END_DETECT_INT_CLR_V << I2C_END_DETECT_INT_CLR_S) -#define I2C_END_DETECT_INT_CLR_V 0x00000001U -#define I2C_END_DETECT_INT_CLR_S 3 -/** I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_CLR (BIT(3)) +#define LP_I2C_END_DETECT_INT_CLR_M (LP_I2C_END_DETECT_INT_CLR_V << LP_I2C_END_DETECT_INT_CLR_S) +#define LP_I2C_END_DETECT_INT_CLR_V 0x00000001U +#define LP_I2C_END_DETECT_INT_CLR_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (I2C_BYTE_TRANS_DONE_INT_CLR_V << I2C_BYTE_TRANS_DONE_INT_CLR_S) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 -/** I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_M (LP_I2C_BYTE_TRANS_DONE_INT_CLR_V << LP_I2C_BYTE_TRANS_DONE_INT_CLR_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_CLR_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (I2C_ARBITRATION_LOST_INT_CLR_V << I2C_ARBITRATION_LOST_INT_CLR_S) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 -/** I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_M (LP_I2C_ARBITRATION_LOST_INT_CLR_V << LP_I2C_ARBITRATION_LOST_INT_CLR_S) +#define LP_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_CLR_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (I2C_MST_TXFIFO_UDF_INT_CLR_V << I2C_MST_TXFIFO_UDF_INT_CLR_S) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 -/** I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_M (LP_I2C_MST_TXFIFO_UDF_INT_CLR_V << LP_I2C_MST_TXFIFO_UDF_INT_CLR_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_CLR_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (I2C_TRANS_COMPLETE_INT_CLR_V << I2C_TRANS_COMPLETE_INT_CLR_S) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 -/** I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_M (LP_I2C_TRANS_COMPLETE_INT_CLR_V << LP_I2C_TRANS_COMPLETE_INT_CLR_S) +#define LP_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_CLR_S 7 +/** LP_I2C_TIME_OUT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (I2C_TIME_OUT_INT_CLR_V << I2C_TIME_OUT_INT_CLR_S) -#define I2C_TIME_OUT_INT_CLR_V 0x00000001U -#define I2C_TIME_OUT_INT_CLR_S 8 -/** I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_CLR (BIT(8)) +#define LP_I2C_TIME_OUT_INT_CLR_M (LP_I2C_TIME_OUT_INT_CLR_V << LP_I2C_TIME_OUT_INT_CLR_S) +#define LP_I2C_TIME_OUT_INT_CLR_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_CLR_S 8 +/** LP_I2C_TRANS_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (I2C_TRANS_START_INT_CLR_V << I2C_TRANS_START_INT_CLR_S) -#define I2C_TRANS_START_INT_CLR_V 0x00000001U -#define I2C_TRANS_START_INT_CLR_S 9 -/** I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_CLR (BIT(9)) +#define LP_I2C_TRANS_START_INT_CLR_M (LP_I2C_TRANS_START_INT_CLR_V << LP_I2C_TRANS_START_INT_CLR_S) +#define LP_I2C_TRANS_START_INT_CLR_V 0x00000001U +#define LP_I2C_TRANS_START_INT_CLR_S 9 +/** LP_I2C_NACK_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (I2C_NACK_INT_CLR_V << I2C_NACK_INT_CLR_S) -#define I2C_NACK_INT_CLR_V 0x00000001U -#define I2C_NACK_INT_CLR_S 10 -/** I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_CLR (BIT(10)) +#define LP_I2C_NACK_INT_CLR_M (LP_I2C_NACK_INT_CLR_V << LP_I2C_NACK_INT_CLR_S) +#define LP_I2C_NACK_INT_CLR_V 0x00000001U +#define LP_I2C_NACK_INT_CLR_S 10 +/** LP_I2C_TXFIFO_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (I2C_TXFIFO_OVF_INT_CLR_V << I2C_TXFIFO_OVF_INT_CLR_S) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_CLR_S 11 -/** I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_CLR_M (LP_I2C_TXFIFO_OVF_INT_CLR_V << LP_I2C_TXFIFO_OVF_INT_CLR_S) +#define LP_I2C_TXFIFO_OVF_INT_CLR_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_CLR_S 11 +/** LP_I2C_RXFIFO_UDF_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (I2C_RXFIFO_UDF_INT_CLR_V << I2C_RXFIFO_UDF_INT_CLR_S) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_CLR_S 12 -/** I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_CLR_M (LP_I2C_RXFIFO_UDF_INT_CLR_V << LP_I2C_RXFIFO_UDF_INT_CLR_S) +#define LP_I2C_RXFIFO_UDF_INT_CLR_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_CLR_S 12 +/** LP_I2C_SCL_ST_TO_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (I2C_SCL_ST_TO_INT_CLR_V << I2C_SCL_ST_TO_INT_CLR_S) -#define I2C_SCL_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_ST_TO_INT_CLR_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_CLR_M (LP_I2C_SCL_ST_TO_INT_CLR_V << LP_I2C_SCL_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_CLR_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (I2C_SCL_MAIN_ST_TO_INT_CLR_V << I2C_SCL_MAIN_ST_TO_INT_CLR_S) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 -/** I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_M (LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V << LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/** LP_I2C_DET_START_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (I2C_DET_START_INT_CLR_V << I2C_DET_START_INT_CLR_S) -#define I2C_DET_START_INT_CLR_V 0x00000001U -#define I2C_DET_START_INT_CLR_S 15 +#define LP_I2C_DET_START_INT_CLR (BIT(15)) +#define LP_I2C_DET_START_INT_CLR_M (LP_I2C_DET_START_INT_CLR_V << LP_I2C_DET_START_INT_CLR_S) +#define LP_I2C_DET_START_INT_CLR_V 0x00000001U +#define LP_I2C_DET_START_INT_CLR_S 15 -/** I2C_INT_ENA_REG register +/** LP_I2C_INT_ENA_REG register * Interrupt enable bits */ -#define I2C_INT_ENA_REG (DR_REG_I2C_BASE + 0x28) -/** I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_ENA_REG (DR_REG_LP_I2C_BASE + 0x28) +/** LP_I2C_RXFIFO_WM_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (I2C_RXFIFO_WM_INT_ENA_V << I2C_RXFIFO_WM_INT_ENA_S) -#define I2C_RXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ENA_S 0 -/** I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ENA_M (LP_I2C_RXFIFO_WM_INT_ENA_V << LP_I2C_RXFIFO_WM_INT_ENA_S) +#define LP_I2C_RXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ENA_S 0 +/** LP_I2C_TXFIFO_WM_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (I2C_TXFIFO_WM_INT_ENA_V << I2C_TXFIFO_WM_INT_ENA_S) -#define I2C_TXFIFO_WM_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ENA_S 1 -/** I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ENA_M (LP_I2C_TXFIFO_WM_INT_ENA_V << LP_I2C_TXFIFO_WM_INT_ENA_S) +#define LP_I2C_TXFIFO_WM_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ENA_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (I2C_RXFIFO_OVF_INT_ENA_V << I2C_RXFIFO_OVF_INT_ENA_S) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ENA_S 2 -/** I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ENA_M (LP_I2C_RXFIFO_OVF_INT_ENA_V << LP_I2C_RXFIFO_OVF_INT_ENA_S) +#define LP_I2C_RXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ENA_S 2 +/** LP_I2C_END_DETECT_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (I2C_END_DETECT_INT_ENA_V << I2C_END_DETECT_INT_ENA_S) -#define I2C_END_DETECT_INT_ENA_V 0x00000001U -#define I2C_END_DETECT_INT_ENA_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_ENA (BIT(3)) +#define LP_I2C_END_DETECT_INT_ENA_M (LP_I2C_END_DETECT_INT_ENA_V << LP_I2C_END_DETECT_INT_ENA_S) +#define LP_I2C_END_DETECT_INT_ENA_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ENA_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (I2C_BYTE_TRANS_DONE_INT_ENA_V << I2C_BYTE_TRANS_DONE_INT_ENA_S) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 -/** I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_M (LP_I2C_BYTE_TRANS_DONE_INT_ENA_V << LP_I2C_BYTE_TRANS_DONE_INT_ENA_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ENA_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (I2C_ARBITRATION_LOST_INT_ENA_V << I2C_ARBITRATION_LOST_INT_ENA_S) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_M (LP_I2C_ARBITRATION_LOST_INT_ENA_V << LP_I2C_ARBITRATION_LOST_INT_ENA_S) +#define LP_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ENA_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (I2C_MST_TXFIFO_UDF_INT_ENA_V << I2C_MST_TXFIFO_UDF_INT_ENA_S) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 -/** I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_M (LP_I2C_MST_TXFIFO_UDF_INT_ENA_V << LP_I2C_MST_TXFIFO_UDF_INT_ENA_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ENA_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (I2C_TRANS_COMPLETE_INT_ENA_V << I2C_TRANS_COMPLETE_INT_ENA_S) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 -/** I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_M (LP_I2C_TRANS_COMPLETE_INT_ENA_V << LP_I2C_TRANS_COMPLETE_INT_ENA_S) +#define LP_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ENA_S 7 +/** LP_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (I2C_TIME_OUT_INT_ENA_V << I2C_TIME_OUT_INT_ENA_S) -#define I2C_TIME_OUT_INT_ENA_V 0x00000001U -#define I2C_TIME_OUT_INT_ENA_S 8 -/** I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_ENA (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ENA_M (LP_I2C_TIME_OUT_INT_ENA_V << LP_I2C_TIME_OUT_INT_ENA_S) +#define LP_I2C_TIME_OUT_INT_ENA_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ENA_S 8 +/** LP_I2C_TRANS_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (I2C_TRANS_START_INT_ENA_V << I2C_TRANS_START_INT_ENA_S) -#define I2C_TRANS_START_INT_ENA_V 0x00000001U -#define I2C_TRANS_START_INT_ENA_S 9 -/** I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_ENA (BIT(9)) +#define LP_I2C_TRANS_START_INT_ENA_M (LP_I2C_TRANS_START_INT_ENA_V << LP_I2C_TRANS_START_INT_ENA_S) +#define LP_I2C_TRANS_START_INT_ENA_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ENA_S 9 +/** LP_I2C_NACK_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (I2C_NACK_INT_ENA_V << I2C_NACK_INT_ENA_S) -#define I2C_NACK_INT_ENA_V 0x00000001U -#define I2C_NACK_INT_ENA_S 10 -/** I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_ENA (BIT(10)) +#define LP_I2C_NACK_INT_ENA_M (LP_I2C_NACK_INT_ENA_V << LP_I2C_NACK_INT_ENA_S) +#define LP_I2C_NACK_INT_ENA_V 0x00000001U +#define LP_I2C_NACK_INT_ENA_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (I2C_TXFIFO_OVF_INT_ENA_V << I2C_TXFIFO_OVF_INT_ENA_S) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ENA_S 11 -/** I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ENA_M (LP_I2C_TXFIFO_OVF_INT_ENA_V << LP_I2C_TXFIFO_OVF_INT_ENA_S) +#define LP_I2C_TXFIFO_OVF_INT_ENA_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ENA_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (I2C_RXFIFO_UDF_INT_ENA_V << I2C_RXFIFO_UDF_INT_ENA_S) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ENA_S 12 -/** I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ENA_M (LP_I2C_RXFIFO_UDF_INT_ENA_V << LP_I2C_RXFIFO_UDF_INT_ENA_S) +#define LP_I2C_RXFIFO_UDF_INT_ENA_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ENA_S 12 +/** LP_I2C_SCL_ST_TO_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (I2C_SCL_ST_TO_INT_ENA_V << I2C_SCL_ST_TO_INT_ENA_S) -#define I2C_SCL_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ENA_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ENA_M (LP_I2C_SCL_ST_TO_INT_ENA_V << LP_I2C_SCL_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ENA_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (I2C_SCL_MAIN_ST_TO_INT_ENA_V << I2C_SCL_MAIN_ST_TO_INT_ENA_S) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 -/** I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_M (LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V << LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/** LP_I2C_DET_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (I2C_DET_START_INT_ENA_V << I2C_DET_START_INT_ENA_S) -#define I2C_DET_START_INT_ENA_V 0x00000001U -#define I2C_DET_START_INT_ENA_S 15 +#define LP_I2C_DET_START_INT_ENA (BIT(15)) +#define LP_I2C_DET_START_INT_ENA_M (LP_I2C_DET_START_INT_ENA_V << LP_I2C_DET_START_INT_ENA_S) +#define LP_I2C_DET_START_INT_ENA_V 0x00000001U +#define LP_I2C_DET_START_INT_ENA_S 15 -/** I2C_INT_STATUS_REG register +/** LP_I2C_INT_STATUS_REG register * Status of captured I2C communication events */ -#define I2C_INT_STATUS_REG (DR_REG_I2C_BASE + 0x2c) -/** I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt. +#define LP_I2C_INT_STATUS_REG (DR_REG_LP_I2C_BASE + 0x2c) +/** LP_I2C_RXFIFO_WM_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_WM_INT interrupt. */ -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (I2C_RXFIFO_WM_INT_ST_V << I2C_RXFIFO_WM_INT_ST_S) -#define I2C_RXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_RXFIFO_WM_INT_ST_S 0 -/** I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt. +#define LP_I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define LP_I2C_RXFIFO_WM_INT_ST_M (LP_I2C_RXFIFO_WM_INT_ST_V << LP_I2C_RXFIFO_WM_INT_ST_S) +#define LP_I2C_RXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_WM_INT_ST_S 0 +/** LP_I2C_TXFIFO_WM_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_WM_INT interrupt. */ -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (I2C_TXFIFO_WM_INT_ST_V << I2C_TXFIFO_WM_INT_ST_S) -#define I2C_TXFIFO_WM_INT_ST_V 0x00000001U -#define I2C_TXFIFO_WM_INT_ST_S 1 -/** I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt. +#define LP_I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define LP_I2C_TXFIFO_WM_INT_ST_M (LP_I2C_TXFIFO_WM_INT_ST_V << LP_I2C_TXFIFO_WM_INT_ST_S) +#define LP_I2C_TXFIFO_WM_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_WM_INT_ST_S 1 +/** LP_I2C_RXFIFO_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_OVF_INT interrupt. */ -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (I2C_RXFIFO_OVF_INT_ST_V << I2C_RXFIFO_OVF_INT_ST_S) -#define I2C_RXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_OVF_INT_ST_S 2 -/** I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define LP_I2C_RXFIFO_OVF_INT_ST_M (LP_I2C_RXFIFO_OVF_INT_ST_V << LP_I2C_RXFIFO_OVF_INT_ST_S) +#define LP_I2C_RXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_OVF_INT_ST_S 2 +/** LP_I2C_END_DETECT_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (I2C_END_DETECT_INT_ST_V << I2C_END_DETECT_INT_ST_S) -#define I2C_END_DETECT_INT_ST_V 0x00000001U -#define I2C_END_DETECT_INT_ST_S 3 -/** I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * The masked interrupt status bit for the I2C_END_DETECT_INT interrupt. +#define LP_I2C_END_DETECT_INT_ST (BIT(3)) +#define LP_I2C_END_DETECT_INT_ST_M (LP_I2C_END_DETECT_INT_ST_V << LP_I2C_END_DETECT_INT_ST_S) +#define LP_I2C_END_DETECT_INT_ST_V 0x00000001U +#define LP_I2C_END_DETECT_INT_ST_S 3 +/** LP_I2C_BYTE_TRANS_DONE_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for the LP_I2C_END_DETECT_INT interrupt. */ -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (I2C_BYTE_TRANS_DONE_INT_ST_V << I2C_BYTE_TRANS_DONE_INT_ST_S) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 -/** I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; - * The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt. +#define LP_I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_M (LP_I2C_BYTE_TRANS_DONE_INT_ST_V << LP_I2C_BYTE_TRANS_DONE_INT_ST_S) +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_V 0x00000001U +#define LP_I2C_BYTE_TRANS_DONE_INT_ST_S 4 +/** LP_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for the LP_I2C_ARBITRATION_LOST_INT interrupt. */ -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (I2C_ARBITRATION_LOST_INT_ST_V << I2C_ARBITRATION_LOST_INT_ST_S) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U -#define I2C_ARBITRATION_LOST_INT_ST_S 5 -/** I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; - * The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define LP_I2C_ARBITRATION_LOST_INT_ST_M (LP_I2C_ARBITRATION_LOST_INT_ST_V << LP_I2C_ARBITRATION_LOST_INT_ST_S) +#define LP_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U +#define LP_I2C_ARBITRATION_LOST_INT_ST_S 5 +/** LP_I2C_MST_TXFIFO_UDF_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (I2C_MST_TXFIFO_UDF_INT_ST_V << I2C_MST_TXFIFO_UDF_INT_ST_S) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 -/** I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt. +#define LP_I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_M (LP_I2C_MST_TXFIFO_UDF_INT_ST_V << LP_I2C_MST_TXFIFO_UDF_INT_ST_S) +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_MST_TXFIFO_UDF_INT_ST_S 6 +/** LP_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_COMPLETE_INT interrupt. */ -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (I2C_TRANS_COMPLETE_INT_ST_V << I2C_TRANS_COMPLETE_INT_ST_S) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U -#define I2C_TRANS_COMPLETE_INT_ST_S 7 -/** I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; - * The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. +#define LP_I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define LP_I2C_TRANS_COMPLETE_INT_ST_M (LP_I2C_TRANS_COMPLETE_INT_ST_V << LP_I2C_TRANS_COMPLETE_INT_ST_S) +#define LP_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_COMPLETE_INT_ST_S 7 +/** LP_I2C_TIME_OUT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for the LP_I2C_TIME_OUT_INT interrupt. */ -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (I2C_TIME_OUT_INT_ST_V << I2C_TIME_OUT_INT_ST_S) -#define I2C_TIME_OUT_INT_ST_V 0x00000001U -#define I2C_TIME_OUT_INT_ST_S 8 -/** I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; - * The masked interrupt status bit for the I2C_TRANS_START_INT interrupt. +#define LP_I2C_TIME_OUT_INT_ST (BIT(8)) +#define LP_I2C_TIME_OUT_INT_ST_M (LP_I2C_TIME_OUT_INT_ST_V << LP_I2C_TIME_OUT_INT_ST_S) +#define LP_I2C_TIME_OUT_INT_ST_V 0x00000001U +#define LP_I2C_TIME_OUT_INT_ST_S 8 +/** LP_I2C_TRANS_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for the LP_I2C_TRANS_START_INT interrupt. */ -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (I2C_TRANS_START_INT_ST_V << I2C_TRANS_START_INT_ST_S) -#define I2C_TRANS_START_INT_ST_V 0x00000001U -#define I2C_TRANS_START_INT_ST_S 9 -/** I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; - * The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt. +#define LP_I2C_TRANS_START_INT_ST (BIT(9)) +#define LP_I2C_TRANS_START_INT_ST_M (LP_I2C_TRANS_START_INT_ST_V << LP_I2C_TRANS_START_INT_ST_S) +#define LP_I2C_TRANS_START_INT_ST_V 0x00000001U +#define LP_I2C_TRANS_START_INT_ST_S 9 +/** LP_I2C_NACK_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for LP_I2C_SLAVE_STRETCH_INT interrupt. */ -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (I2C_NACK_INT_ST_V << I2C_NACK_INT_ST_S) -#define I2C_NACK_INT_ST_V 0x00000001U -#define I2C_NACK_INT_ST_S 10 -/** I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; - * The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt. +#define LP_I2C_NACK_INT_ST (BIT(10)) +#define LP_I2C_NACK_INT_ST_M (LP_I2C_NACK_INT_ST_V << LP_I2C_NACK_INT_ST_S) +#define LP_I2C_NACK_INT_ST_V 0x00000001U +#define LP_I2C_NACK_INT_ST_S 10 +/** LP_I2C_TXFIFO_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for LP_I2C_TXFIFO_OVF_INT interrupt. */ -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (I2C_TXFIFO_OVF_INT_ST_V << I2C_TXFIFO_OVF_INT_ST_S) -#define I2C_TXFIFO_OVF_INT_ST_V 0x00000001U -#define I2C_TXFIFO_OVF_INT_ST_S 11 -/** I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; - * The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt. +#define LP_I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define LP_I2C_TXFIFO_OVF_INT_ST_M (LP_I2C_TXFIFO_OVF_INT_ST_V << LP_I2C_TXFIFO_OVF_INT_ST_S) +#define LP_I2C_TXFIFO_OVF_INT_ST_V 0x00000001U +#define LP_I2C_TXFIFO_OVF_INT_ST_S 11 +/** LP_I2C_RXFIFO_UDF_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for LP_I2C_RXFIFO_UDF_INT interrupt. */ -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (I2C_RXFIFO_UDF_INT_ST_V << I2C_RXFIFO_UDF_INT_ST_S) -#define I2C_RXFIFO_UDF_INT_ST_V 0x00000001U -#define I2C_RXFIFO_UDF_INT_ST_S 12 -/** I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; - * The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt. +#define LP_I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define LP_I2C_RXFIFO_UDF_INT_ST_M (LP_I2C_RXFIFO_UDF_INT_ST_V << LP_I2C_RXFIFO_UDF_INT_ST_S) +#define LP_I2C_RXFIFO_UDF_INT_ST_V 0x00000001U +#define LP_I2C_RXFIFO_UDF_INT_ST_S 12 +/** LP_I2C_SCL_ST_TO_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_ST_TO_INT interrupt. */ -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (I2C_SCL_ST_TO_INT_ST_V << I2C_SCL_ST_TO_INT_ST_S) -#define I2C_SCL_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_ST_TO_INT_ST_S 13 -/** I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; - * The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt. +#define LP_I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define LP_I2C_SCL_ST_TO_INT_ST_M (LP_I2C_SCL_ST_TO_INT_ST_V << LP_I2C_SCL_ST_TO_INT_ST_S) +#define LP_I2C_SCL_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_ST_TO_INT_ST_S 13 +/** LP_I2C_SCL_MAIN_ST_TO_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for LP_I2C_SCL_MAIN_ST_TO_INT interrupt. */ -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (I2C_SCL_MAIN_ST_TO_INT_ST_V << I2C_SCL_MAIN_ST_TO_INT_ST_S) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 -/** I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; - * The masked interrupt status bit for I2C_DET_START_INT interrupt. +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_M (LP_I2C_SCL_MAIN_ST_TO_INT_ST_V << LP_I2C_SCL_MAIN_ST_TO_INT_ST_S) +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_V 0x00000001U +#define LP_I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/** LP_I2C_DET_START_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for LP_I2C_DET_START_INT interrupt. */ -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (I2C_DET_START_INT_ST_V << I2C_DET_START_INT_ST_S) -#define I2C_DET_START_INT_ST_V 0x00000001U -#define I2C_DET_START_INT_ST_S 15 +#define LP_I2C_DET_START_INT_ST (BIT(15)) +#define LP_I2C_DET_START_INT_ST_M (LP_I2C_DET_START_INT_ST_V << LP_I2C_DET_START_INT_ST_S) +#define LP_I2C_DET_START_INT_ST_V 0x00000001U +#define LP_I2C_DET_START_INT_ST_S 15 -/** I2C_SDA_HOLD_REG register +/** LP_I2C_SDA_HOLD_REG register * Configures the hold time after a negative SCL edge. */ -#define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) -/** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_HOLD_REG (DR_REG_LP_I2C_BASE + 0x30) +/** LP_I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure the time to hold the data after the negativeedge * of SCL, in I2C module clock cycles. */ -#define I2C_SDA_HOLD_TIME 0x000001FFU -#define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) -#define I2C_SDA_HOLD_TIME_V 0x000001FFU -#define I2C_SDA_HOLD_TIME_S 0 +#define LP_I2C_SDA_HOLD_TIME 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_M (LP_I2C_SDA_HOLD_TIME_V << LP_I2C_SDA_HOLD_TIME_S) +#define LP_I2C_SDA_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SDA_HOLD_TIME_S 0 -/** I2C_SDA_SAMPLE_REG register +/** LP_I2C_SDA_SAMPLE_REG register * Configures the sample time after a positive SCL edge. */ -#define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) -/** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SDA_SAMPLE_REG (DR_REG_LP_I2C_BASE + 0x34) +/** LP_I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SDA is sampled, in I2C module clock * cycles. */ -#define I2C_SDA_SAMPLE_TIME 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) -#define I2C_SDA_SAMPLE_TIME_V 0x000001FFU -#define I2C_SDA_SAMPLE_TIME_S 0 +#define LP_I2C_SDA_SAMPLE_TIME 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_M (LP_I2C_SDA_SAMPLE_TIME_V << LP_I2C_SDA_SAMPLE_TIME_S) +#define LP_I2C_SDA_SAMPLE_TIME_V 0x000001FFU +#define LP_I2C_SDA_SAMPLE_TIME_S 0 -/** I2C_SCL_HIGH_PERIOD_REG register +/** LP_I2C_SCL_HIGH_PERIOD_REG register * Configures the high level width of SCL */ -#define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) -/** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD_REG (DR_REG_LP_I2C_BASE + 0x38) +/** LP_I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; * This register is used to configure for how long SCL setup to high level and remains * high in master mode, in I2C module clock cycles. */ -#define I2C_SCL_HIGH_PERIOD 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) -#define I2C_SCL_HIGH_PERIOD_V 0x000001FFU -#define I2C_SCL_HIGH_PERIOD_S 0 -/** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; +#define LP_I2C_SCL_HIGH_PERIOD 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_M (LP_I2C_SCL_HIGH_PERIOD_V << LP_I2C_SCL_HIGH_PERIOD_S) +#define LP_I2C_SCL_HIGH_PERIOD_V 0x000001FFU +#define LP_I2C_SCL_HIGH_PERIOD_S 0 +/** LP_I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; * This register is used to configure for the SCL_FSM's waiting period for SCL high * level in master mode, in I2C module clock cycles. */ -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 +#define LP_I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_M (LP_I2C_SCL_WAIT_HIGH_PERIOD_V << LP_I2C_SCL_WAIT_HIGH_PERIOD_S) +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_V 0x0000007FU +#define LP_I2C_SCL_WAIT_HIGH_PERIOD_S 9 -/** I2C_SCL_START_HOLD_REG register +/** LP_I2C_SCL_START_HOLD_REG register * Configures the delay between the SDA and SCL negative edge for a start condition */ -#define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) -/** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_START_HOLD_REG (DR_REG_LP_I2C_BASE + 0x40) +/** LP_I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the negative edgeof SDA and the * negative edge of SCL for a START condition, in I2C module clock cycles. */ -#define I2C_SCL_START_HOLD_TIME 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) -#define I2C_SCL_START_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_START_HOLD_TIME_S 0 +#define LP_I2C_SCL_START_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_M (LP_I2C_SCL_START_HOLD_TIME_V << LP_I2C_SCL_START_HOLD_TIME_S) +#define LP_I2C_SCL_START_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_START_HOLD_TIME_S 0 -/** I2C_SCL_RSTART_SETUP_REG register +/** LP_I2C_SCL_RSTART_SETUP_REG register * Configures the delay between the positive * edge of SCL and the negative edge of SDA */ -#define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) -/** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_RSTART_SETUP_REG (DR_REG_LP_I2C_BASE + 0x44) +/** LP_I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positiveedge of SCL and the * negative edge of SDA for a RESTART condition, in I2C module clock cycles. */ -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_RSTART_SETUP_TIME_S 0 +#define LP_I2C_SCL_RSTART_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_M (LP_I2C_SCL_RSTART_SETUP_TIME_V << LP_I2C_SCL_RSTART_SETUP_TIME_S) +#define LP_I2C_SCL_RSTART_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_RSTART_SETUP_TIME_S 0 -/** I2C_SCL_STOP_HOLD_REG register +/** LP_I2C_SCL_STOP_HOLD_REG register * Configures the delay after the SCL clock * edge for a stop condition */ -#define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) -/** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_HOLD_REG (DR_REG_LP_I2C_BASE + 0x48) +/** LP_I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the delay after the STOP condition,in I2C module * clock cycles. */ -#define I2C_SCL_STOP_HOLD_TIME 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) -#define I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU -#define I2C_SCL_STOP_HOLD_TIME_S 0 +#define LP_I2C_SCL_STOP_HOLD_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_M (LP_I2C_SCL_STOP_HOLD_TIME_V << LP_I2C_SCL_STOP_HOLD_TIME_S) +#define LP_I2C_SCL_STOP_HOLD_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_HOLD_TIME_S 0 -/** I2C_SCL_STOP_SETUP_REG register +/** LP_I2C_SCL_STOP_SETUP_REG register * Configures the delay between the SDA and * SCL positive edge for a stop condition */ -#define I2C_SCL_STOP_SETUP_REG (DR_REG_I2C_BASE + 0x4c) -/** I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; +#define LP_I2C_SCL_STOP_SETUP_REG (DR_REG_LP_I2C_BASE + 0x4c) +/** LP_I2C_SCL_STOP_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * This register is used to configure the time between the positive edgeof SCL and the * positive edge of SDA, in I2C module clock cycles. */ -#define I2C_SCL_STOP_SETUP_TIME 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_M (I2C_SCL_STOP_SETUP_TIME_V << I2C_SCL_STOP_SETUP_TIME_S) -#define I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU -#define I2C_SCL_STOP_SETUP_TIME_S 0 +#define LP_I2C_SCL_STOP_SETUP_TIME 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_M (LP_I2C_SCL_STOP_SETUP_TIME_V << LP_I2C_SCL_STOP_SETUP_TIME_S) +#define LP_I2C_SCL_STOP_SETUP_TIME_V 0x000001FFU +#define LP_I2C_SCL_STOP_SETUP_TIME_S 0 -/** I2C_FILTER_CFG_REG register +/** LP_I2C_FILTER_CFG_REG register * SCL and SDA filter configuration register */ -#define I2C_FILTER_CFG_REG (DR_REG_I2C_BASE + 0x50) -/** I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; +#define LP_I2C_FILTER_CFG_REG (DR_REG_LP_I2C_BASE + 0x50) +/** LP_I2C_SCL_FILTER_THRES : R/W; bitpos: [3:0]; default: 0; * When a pulse on the SCL input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SCL_FILTER_THRES 0x0000000FU -#define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) -#define I2C_SCL_FILTER_THRES_V 0x0000000FU -#define I2C_SCL_FILTER_THRES_S 0 -/** I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; +#define LP_I2C_SCL_FILTER_THRES 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_M (LP_I2C_SCL_FILTER_THRES_V << LP_I2C_SCL_FILTER_THRES_S) +#define LP_I2C_SCL_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SCL_FILTER_THRES_S 0 +/** LP_I2C_SDA_FILTER_THRES : R/W; bitpos: [7:4]; default: 0; * When a pulse on the SDA input has smaller width than this register valuein I2C * module clock cycles, the I2C controller will ignore that pulse. */ -#define I2C_SDA_FILTER_THRES 0x0000000FU -#define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) -#define I2C_SDA_FILTER_THRES_V 0x0000000FU -#define I2C_SDA_FILTER_THRES_S 4 -/** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; +#define LP_I2C_SDA_FILTER_THRES 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_M (LP_I2C_SDA_FILTER_THRES_V << LP_I2C_SDA_FILTER_THRES_S) +#define LP_I2C_SDA_FILTER_THRES_V 0x0000000FU +#define LP_I2C_SDA_FILTER_THRES_S 4 +/** LP_I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; * This is the filter enable bit for SCL. */ -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) -#define I2C_SCL_FILTER_EN_V 0x00000001U -#define I2C_SCL_FILTER_EN_S 8 -/** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; +#define LP_I2C_SCL_FILTER_EN (BIT(8)) +#define LP_I2C_SCL_FILTER_EN_M (LP_I2C_SCL_FILTER_EN_V << LP_I2C_SCL_FILTER_EN_S) +#define LP_I2C_SCL_FILTER_EN_V 0x00000001U +#define LP_I2C_SCL_FILTER_EN_S 8 +/** LP_I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; * This is the filter enable bit for SDA. */ -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) -#define I2C_SDA_FILTER_EN_V 0x00000001U -#define I2C_SDA_FILTER_EN_S 9 +#define LP_I2C_SDA_FILTER_EN (BIT(9)) +#define LP_I2C_SDA_FILTER_EN_M (LP_I2C_SDA_FILTER_EN_V << LP_I2C_SDA_FILTER_EN_S) +#define LP_I2C_SDA_FILTER_EN_V 0x00000001U +#define LP_I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register +/** LP_I2C_CLK_CONF_REG register * I2C CLK configuration register */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; +#define LP_I2C_CLK_CONF_REG (DR_REG_LP_I2C_BASE + 0x54) +/** LP_I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; * the integral part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; +#define LP_I2C_SCLK_DIV_NUM 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_M (LP_I2C_SCLK_DIV_NUM_V << LP_I2C_SCLK_DIV_NUM_S) +#define LP_I2C_SCLK_DIV_NUM_V 0x000000FFU +#define LP_I2C_SCLK_DIV_NUM_S 0 +/** LP_I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; * the numerator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; +#define LP_I2C_SCLK_DIV_A 0x0000003FU +#define LP_I2C_SCLK_DIV_A_M (LP_I2C_SCLK_DIV_A_V << LP_I2C_SCLK_DIV_A_S) +#define LP_I2C_SCLK_DIV_A_V 0x0000003FU +#define LP_I2C_SCLK_DIV_A_S 8 +/** LP_I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; * the denominator of the fractional part of the fractional divisor for i2c module */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; +#define LP_I2C_SCLK_DIV_B 0x0000003FU +#define LP_I2C_SCLK_DIV_B_M (LP_I2C_SCLK_DIV_B_V << LP_I2C_SCLK_DIV_B_S) +#define LP_I2C_SCLK_DIV_B_V 0x0000003FU +#define LP_I2C_SCLK_DIV_B_S 14 +/** LP_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; +#define LP_I2C_SCLK_SEL (BIT(20)) +#define LP_I2C_SCLK_SEL_M (LP_I2C_SCLK_SEL_V << LP_I2C_SCLK_SEL_S) +#define LP_I2C_SCLK_SEL_V 0x00000001U +#define LP_I2C_SCLK_SEL_S 20 +/** LP_I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; * The clock switch for i2c module */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 +#define LP_I2C_SCLK_ACTIVE (BIT(21)) +#define LP_I2C_SCLK_ACTIVE_M (LP_I2C_SCLK_ACTIVE_V << LP_I2C_SCLK_ACTIVE_S) +#define LP_I2C_SCLK_ACTIVE_V 0x00000001U +#define LP_I2C_SCLK_ACTIVE_S 21 -/** I2C_COMD0_REG register +/** LP_I2C_COMD0_REG register * I2C command register 0 */ -#define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) -/** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD0_REG (DR_REG_LP_I2C_BASE + 0x58) +/** LP_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 0. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND0 0x00003FFFU -#define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) -#define I2C_COMMAND0_V 0x00003FFFU -#define I2C_COMMAND0_S 0 -/** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND0 0x00003FFFU +#define LP_I2C_COMMAND0_M (LP_I2C_COMMAND0_V << LP_I2C_COMMAND0_S) +#define LP_I2C_COMMAND0_V 0x00003FFFU +#define LP_I2C_COMMAND0_S 0 +/** LP_I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 0 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) -#define I2C_COMMAND0_DONE_V 0x00000001U -#define I2C_COMMAND0_DONE_S 31 +#define LP_I2C_COMMAND0_DONE (BIT(31)) +#define LP_I2C_COMMAND0_DONE_M (LP_I2C_COMMAND0_DONE_V << LP_I2C_COMMAND0_DONE_S) +#define LP_I2C_COMMAND0_DONE_V 0x00000001U +#define LP_I2C_COMMAND0_DONE_S 31 -/** I2C_COMD1_REG register +/** LP_I2C_COMD1_REG register * I2C command register 1 */ -#define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) -/** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD1_REG (DR_REG_LP_I2C_BASE + 0x5c) +/** LP_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 1. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND1 0x00003FFFU -#define I2C_COMMAND1_M (I2C_COMMAND1_V << I2C_COMMAND1_S) -#define I2C_COMMAND1_V 0x00003FFFU -#define I2C_COMMAND1_S 0 -/** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND1 0x00003FFFU +#define LP_I2C_COMMAND1_M (LP_I2C_COMMAND1_V << LP_I2C_COMMAND1_S) +#define LP_I2C_COMMAND1_V 0x00003FFFU +#define LP_I2C_COMMAND1_S 0 +/** LP_I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 1 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) -#define I2C_COMMAND1_DONE_V 0x00000001U -#define I2C_COMMAND1_DONE_S 31 +#define LP_I2C_COMMAND1_DONE (BIT(31)) +#define LP_I2C_COMMAND1_DONE_M (LP_I2C_COMMAND1_DONE_V << LP_I2C_COMMAND1_DONE_S) +#define LP_I2C_COMMAND1_DONE_V 0x00000001U +#define LP_I2C_COMMAND1_DONE_S 31 -/** I2C_COMD2_REG register +/** LP_I2C_COMD2_REG register * I2C command register 2 */ -#define I2C_COMD2_REG (DR_REG_I2C_BASE + 0x60) -/** I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD2_REG (DR_REG_LP_I2C_BASE + 0x60) +/** LP_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 2. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND2 0x00003FFFU -#define I2C_COMMAND2_M (I2C_COMMAND2_V << I2C_COMMAND2_S) -#define I2C_COMMAND2_V 0x00003FFFU -#define I2C_COMMAND2_S 0 -/** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND2 0x00003FFFU +#define LP_I2C_COMMAND2_M (LP_I2C_COMMAND2_V << LP_I2C_COMMAND2_S) +#define LP_I2C_COMMAND2_V 0x00003FFFU +#define LP_I2C_COMMAND2_S 0 +/** LP_I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 2 is done in I2C Master mode, this bit changes to highLevel. */ -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) -#define I2C_COMMAND2_DONE_V 0x00000001U -#define I2C_COMMAND2_DONE_S 31 +#define LP_I2C_COMMAND2_DONE (BIT(31)) +#define LP_I2C_COMMAND2_DONE_M (LP_I2C_COMMAND2_DONE_V << LP_I2C_COMMAND2_DONE_S) +#define LP_I2C_COMMAND2_DONE_V 0x00000001U +#define LP_I2C_COMMAND2_DONE_S 31 -/** I2C_COMD3_REG register +/** LP_I2C_COMD3_REG register * I2C command register 3 */ -#define I2C_COMD3_REG (DR_REG_I2C_BASE + 0x64) -/** I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD3_REG (DR_REG_LP_I2C_BASE + 0x64) +/** LP_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 3. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND3 0x00003FFFU -#define I2C_COMMAND3_M (I2C_COMMAND3_V << I2C_COMMAND3_S) -#define I2C_COMMAND3_V 0x00003FFFU -#define I2C_COMMAND3_S 0 -/** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND3 0x00003FFFU +#define LP_I2C_COMMAND3_M (LP_I2C_COMMAND3_V << LP_I2C_COMMAND3_S) +#define LP_I2C_COMMAND3_V 0x00003FFFU +#define LP_I2C_COMMAND3_S 0 +/** LP_I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 3 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) -#define I2C_COMMAND3_DONE_V 0x00000001U -#define I2C_COMMAND3_DONE_S 31 +#define LP_I2C_COMMAND3_DONE (BIT(31)) +#define LP_I2C_COMMAND3_DONE_M (LP_I2C_COMMAND3_DONE_V << LP_I2C_COMMAND3_DONE_S) +#define LP_I2C_COMMAND3_DONE_V 0x00000001U +#define LP_I2C_COMMAND3_DONE_S 31 -/** I2C_COMD4_REG register +/** LP_I2C_COMD4_REG register * I2C command register 4 */ -#define I2C_COMD4_REG (DR_REG_I2C_BASE + 0x68) -/** I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD4_REG (DR_REG_LP_I2C_BASE + 0x68) +/** LP_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 4. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND4 0x00003FFFU -#define I2C_COMMAND4_M (I2C_COMMAND4_V << I2C_COMMAND4_S) -#define I2C_COMMAND4_V 0x00003FFFU -#define I2C_COMMAND4_S 0 -/** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND4 0x00003FFFU +#define LP_I2C_COMMAND4_M (LP_I2C_COMMAND4_V << LP_I2C_COMMAND4_S) +#define LP_I2C_COMMAND4_V 0x00003FFFU +#define LP_I2C_COMMAND4_S 0 +/** LP_I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 4 is done in I2C Master mode, this bit changes to highlevel. */ -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) -#define I2C_COMMAND4_DONE_V 0x00000001U -#define I2C_COMMAND4_DONE_S 31 +#define LP_I2C_COMMAND4_DONE (BIT(31)) +#define LP_I2C_COMMAND4_DONE_M (LP_I2C_COMMAND4_DONE_V << LP_I2C_COMMAND4_DONE_S) +#define LP_I2C_COMMAND4_DONE_V 0x00000001U +#define LP_I2C_COMMAND4_DONE_S 31 -/** I2C_COMD5_REG register +/** LP_I2C_COMD5_REG register * I2C command register 5 */ -#define I2C_COMD5_REG (DR_REG_I2C_BASE + 0x6c) -/** I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD5_REG (DR_REG_LP_I2C_BASE + 0x6c) +/** LP_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 5. It consists of three parts:op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND5 0x00003FFFU -#define I2C_COMMAND5_M (I2C_COMMAND5_V << I2C_COMMAND5_S) -#define I2C_COMMAND5_V 0x00003FFFU -#define I2C_COMMAND5_S 0 -/** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND5 0x00003FFFU +#define LP_I2C_COMMAND5_M (LP_I2C_COMMAND5_V << LP_I2C_COMMAND5_S) +#define LP_I2C_COMMAND5_V 0x00003FFFU +#define LP_I2C_COMMAND5_S 0 +/** LP_I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 5 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) -#define I2C_COMMAND5_DONE_V 0x00000001U -#define I2C_COMMAND5_DONE_S 31 +#define LP_I2C_COMMAND5_DONE (BIT(31)) +#define LP_I2C_COMMAND5_DONE_M (LP_I2C_COMMAND5_DONE_V << LP_I2C_COMMAND5_DONE_S) +#define LP_I2C_COMMAND5_DONE_V 0x00000001U +#define LP_I2C_COMMAND5_DONE_S 31 -/** I2C_COMD6_REG register +/** LP_I2C_COMD6_REG register * I2C command register 6 */ -#define I2C_COMD6_REG (DR_REG_I2C_BASE + 0x70) -/** I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD6_REG (DR_REG_LP_I2C_BASE + 0x70) +/** LP_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 6. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND6 0x00003FFFU -#define I2C_COMMAND6_M (I2C_COMMAND6_V << I2C_COMMAND6_S) -#define I2C_COMMAND6_V 0x00003FFFU -#define I2C_COMMAND6_S 0 -/** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND6 0x00003FFFU +#define LP_I2C_COMMAND6_M (LP_I2C_COMMAND6_V << LP_I2C_COMMAND6_S) +#define LP_I2C_COMMAND6_V 0x00003FFFU +#define LP_I2C_COMMAND6_S 0 +/** LP_I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 6 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) -#define I2C_COMMAND6_DONE_V 0x00000001U -#define I2C_COMMAND6_DONE_S 31 +#define LP_I2C_COMMAND6_DONE (BIT(31)) +#define LP_I2C_COMMAND6_DONE_M (LP_I2C_COMMAND6_DONE_V << LP_I2C_COMMAND6_DONE_S) +#define LP_I2C_COMMAND6_DONE_V 0x00000001U +#define LP_I2C_COMMAND6_DONE_S 31 -/** I2C_COMD7_REG register +/** LP_I2C_COMD7_REG register * I2C command register 7 */ -#define I2C_COMD7_REG (DR_REG_I2C_BASE + 0x74) -/** I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; +#define LP_I2C_COMD7_REG (DR_REG_LP_I2C_BASE + 0x74) +/** LP_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 0; * This is the content of command 7. It consists of three parts: op_code is the * command, 1: WRITE, 2: STOP, 3: READ, 4: END, 6: RSTART. Byte_num represents the * number of bytes that need to be sent or received.ack_check_en, ack_exp and ack are * used to control the ACK bit. See I2C cmd structure for moreInformation. */ -#define I2C_COMMAND7 0x00003FFFU -#define I2C_COMMAND7_M (I2C_COMMAND7_V << I2C_COMMAND7_S) -#define I2C_COMMAND7_V 0x00003FFFU -#define I2C_COMMAND7_S 0 -/** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; +#define LP_I2C_COMMAND7 0x00003FFFU +#define LP_I2C_COMMAND7_M (LP_I2C_COMMAND7_V << LP_I2C_COMMAND7_S) +#define LP_I2C_COMMAND7_V 0x00003FFFU +#define LP_I2C_COMMAND7_S 0 +/** LP_I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; * When command 7 is done in I2C Master mode, this bit changes to high level. */ -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) -#define I2C_COMMAND7_DONE_V 0x00000001U -#define I2C_COMMAND7_DONE_S 31 +#define LP_I2C_COMMAND7_DONE (BIT(31)) +#define LP_I2C_COMMAND7_DONE_M (LP_I2C_COMMAND7_DONE_V << LP_I2C_COMMAND7_DONE_S) +#define LP_I2C_COMMAND7_DONE_V 0x00000001U +#define LP_I2C_COMMAND7_DONE_S 31 -/** I2C_SCL_ST_TIME_OUT_REG register +/** LP_I2C_SCL_ST_TIME_OUT_REG register * SCL status time out register */ -#define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) -/** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x78) +/** LP_I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_FSM state unchanged period. It should be o more than 23 */ -#define I2C_SCL_ST_TO_I2C 0x0000001FU -#define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) -#define I2C_SCL_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_ST_TO_I2C_S 0 +#define LP_I2C_SCL_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_M (LP_I2C_SCL_ST_TO_LP_I2C_V << LP_I2C_SCL_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_ST_TO_LP_I2C_S 0 -/** I2C_SCL_MAIN_ST_TIME_OUT_REG register +/** LP_I2C_SCL_MAIN_ST_TIME_OUT_REG register * SCL main status time out register */ -#define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) -/** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; +#define LP_I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_LP_I2C_BASE + 0x7c) +/** LP_I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more * than 23 */ -#define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) -#define I2C_SCL_MAIN_ST_TO_I2C_V 0x0000001FU -#define I2C_SCL_MAIN_ST_TO_I2C_S 0 +#define LP_I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_M (LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V << LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S) +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_V 0x0000001FU +#define LP_I2C_SCL_MAIN_ST_TO_LP_I2C_S 0 -/** I2C_SCL_SP_CONF_REG register +/** LP_I2C_SCL_SP_CONF_REG register * Power configuration register */ -#define I2C_SCL_SP_CONF_REG (DR_REG_I2C_BASE + 0x80) -/** I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; +#define LP_I2C_SCL_SP_CONF_REG (DR_REG_LP_I2C_BASE + 0x80) +/** LP_I2C_SCL_RST_SLV_EN : R/W/SC; bitpos: [0]; default: 0; * When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses * equals to reg_scl_rst_slv_num[4:0]. */ -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (I2C_SCL_RST_SLV_EN_V << I2C_SCL_RST_SLV_EN_S) -#define I2C_SCL_RST_SLV_EN_V 0x00000001U -#define I2C_SCL_RST_SLV_EN_S 0 -/** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; +#define LP_I2C_SCL_RST_SLV_EN (BIT(0)) +#define LP_I2C_SCL_RST_SLV_EN_M (LP_I2C_SCL_RST_SLV_EN_V << LP_I2C_SCL_RST_SLV_EN_S) +#define LP_I2C_SCL_RST_SLV_EN_V 0x00000001U +#define LP_I2C_SCL_RST_SLV_EN_S 0 +/** LP_I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; * Configure the pulses of SCL generated in I2C master mode. Valid when * reg_scl_rst_slv_en is 1. */ -#define I2C_SCL_RST_SLV_NUM 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) -#define I2C_SCL_RST_SLV_NUM_V 0x0000001FU -#define I2C_SCL_RST_SLV_NUM_S 1 -/** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; +#define LP_I2C_SCL_RST_SLV_NUM 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_M (LP_I2C_SCL_RST_SLV_NUM_V << LP_I2C_SCL_RST_SLV_NUM_S) +#define LP_I2C_SCL_RST_SLV_NUM_V 0x0000001FU +#define LP_I2C_SCL_RST_SLV_NUM_S 1 +/** LP_I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; * The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power * down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low. */ -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (I2C_SCL_PD_EN_V << I2C_SCL_PD_EN_S) -#define I2C_SCL_PD_EN_V 0x00000001U -#define I2C_SCL_PD_EN_S 6 -/** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; +#define LP_I2C_SCL_PD_EN (BIT(6)) +#define LP_I2C_SCL_PD_EN_M (LP_I2C_SCL_PD_EN_V << LP_I2C_SCL_PD_EN_S) +#define LP_I2C_SCL_PD_EN_V 0x00000001U +#define LP_I2C_SCL_PD_EN_S 6 +/** LP_I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; * The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power * down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low. */ -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (I2C_SDA_PD_EN_V << I2C_SDA_PD_EN_S) -#define I2C_SDA_PD_EN_V 0x00000001U -#define I2C_SDA_PD_EN_S 7 +#define LP_I2C_SDA_PD_EN (BIT(7)) +#define LP_I2C_SDA_PD_EN_M (LP_I2C_SDA_PD_EN_V << LP_I2C_SDA_PD_EN_S) +#define LP_I2C_SDA_PD_EN_V 0x00000001U +#define LP_I2C_SDA_PD_EN_S 7 -/** I2C_DATE_REG register +/** LP_I2C_DATE_REG register * Version register */ -#define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; +#define LP_I2C_DATE_REG (DR_REG_LP_I2C_BASE + 0xf8) +/** LP_I2C_DATE : R/W; bitpos: [31:0]; default: 37765408; * This is the the version register. */ -#define I2C_DATE 0xFFFFFFFFU -#define I2C_DATE_M (I2C_DATE_V << I2C_DATE_S) -#define I2C_DATE_V 0xFFFFFFFFU -#define I2C_DATE_S 0 +#define LP_I2C_DATE 0xFFFFFFFFU +#define LP_I2C_DATE_M (LP_I2C_DATE_V << LP_I2C_DATE_S) +#define LP_I2C_DATE_V 0xFFFFFFFFU +#define LP_I2C_DATE_S 0 -/** I2C_TXFIFO_START_ADDR_REG register +/** LP_I2C_TXFIFO_START_ADDR_REG register * I2C TXFIFO base address register */ -#define I2C_TXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x100) -/** I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_TXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x100) +/** LP_I2C_TXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C txfifo first address. */ -#define I2C_TXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_M (I2C_TXFIFO_START_ADDR_V << I2C_TXFIFO_START_ADDR_S) -#define I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_TXFIFO_START_ADDR_S 0 +#define LP_I2C_TXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_M (LP_I2C_TXFIFO_START_ADDR_V << LP_I2C_TXFIFO_START_ADDR_S) +#define LP_I2C_TXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_TXFIFO_START_ADDR_S 0 -/** I2C_RXFIFO_START_ADDR_REG register +/** LP_I2C_RXFIFO_START_ADDR_REG register * I2C RXFIFO base address register */ -#define I2C_RXFIFO_START_ADDR_REG (DR_REG_I2C_BASE + 0x180) -/** I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; +#define LP_I2C_RXFIFO_START_ADDR_REG (DR_REG_LP_I2C_BASE + 0x180) +/** LP_I2C_RXFIFO_START_ADDR : HRO; bitpos: [31:0]; default: 0; * This is the I2C rxfifo first address. */ -#define I2C_RXFIFO_START_ADDR 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_M (I2C_RXFIFO_START_ADDR_V << I2C_RXFIFO_START_ADDR_S) -#define I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU -#define I2C_RXFIFO_START_ADDR_S 0 +#define LP_I2C_RXFIFO_START_ADDR 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_M (LP_I2C_RXFIFO_START_ADDR_V << LP_I2C_RXFIFO_START_ADDR_S) +#define LP_I2C_RXFIFO_START_ADDR_V 0xFFFFFFFFU +#define LP_I2C_RXFIFO_START_ADDR_S 0 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h index 0735efd6be..db7e40838d 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_spi_struct.h @@ -813,245 +813,19 @@ typedef union { } lp_spi_sleep_conf1_reg_t; -/** Group: LP SPI W0 REG */ -/** Type of spi_w0 register +/** Group: LP SPI Wn REG */ +/** Type of spi_wn register * SPI CPU-controlled buffer0 */ typedef union { struct { - /** reg_buf0 : R/W/SS; bitpos: [31:0]; default: 0; + /** reg_buf : R/W/SS; bitpos: [31:0]; default: 0; * data buffer */ - uint32_t reg_buf0:32; + uint32_t reg_buf:32; }; uint32_t val; -} lp_spi_w0_reg_t; - - -/** Group: LP SPI W1 REG */ -/** Type of spi_w1 register - * SPI CPU-controlled buffer1 - */ -typedef union { - struct { - /** reg_buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf1:32; - }; - uint32_t val; -} lp_spi_w1_reg_t; - - -/** Group: LP SPI W2 REG */ -/** Type of spi_w2 register - * SPI CPU-controlled buffer2 - */ -typedef union { - struct { - /** reg_buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf2:32; - }; - uint32_t val; -} lp_spi_w2_reg_t; - - -/** Group: LP SPI W3 REG */ -/** Type of spi_w3 register - * SPI CPU-controlled buffer3 - */ -typedef union { - struct { - /** reg_buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf3:32; - }; - uint32_t val; -} lp_spi_w3_reg_t; - - -/** Group: LP SPI W4 REG */ -/** Type of spi_w4 register - * SPI CPU-controlled buffer4 - */ -typedef union { - struct { - /** reg_buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf4:32; - }; - uint32_t val; -} lp_spi_w4_reg_t; - - -/** Group: LP SPI W5 REG */ -/** Type of spi_w5 register - * SPI CPU-controlled buffer5 - */ -typedef union { - struct { - /** reg_buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf5:32; - }; - uint32_t val; -} lp_spi_w5_reg_t; - - -/** Group: LP SPI W6 REG */ -/** Type of spi_w6 register - * SPI CPU-controlled buffer6 - */ -typedef union { - struct { - /** reg_buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf6:32; - }; - uint32_t val; -} lp_spi_w6_reg_t; - - -/** Group: LP SPI W7 REG */ -/** Type of spi_w7 register - * SPI CPU-controlled buffer7 - */ -typedef union { - struct { - /** reg_buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf7:32; - }; - uint32_t val; -} lp_spi_w7_reg_t; - - -/** Group: LP SPI W8 REG */ -/** Type of spi_w8 register - * SPI CPU-controlled buffer8 - */ -typedef union { - struct { - /** reg_buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf8:32; - }; - uint32_t val; -} lp_spi_w8_reg_t; - - -/** Group: LP SPI W9 REG */ -/** Type of spi_w9 register - * SPI CPU-controlled buffer9 - */ -typedef union { - struct { - /** reg_buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf9:32; - }; - uint32_t val; -} lp_spi_w9_reg_t; - - -/** Group: LP SPI W10 REG */ -/** Type of spi_w10 register - * SPI CPU-controlled buffer10 - */ -typedef union { - struct { - /** reg_buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf10:32; - }; - uint32_t val; -} lp_spi_w10_reg_t; - - -/** Group: LP SPI W11 REG */ -/** Type of spi_w11 register - * SPI CPU-controlled buffer11 - */ -typedef union { - struct { - /** reg_buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf11:32; - }; - uint32_t val; -} lp_spi_w11_reg_t; - - -/** Group: LP SPI W12 REG */ -/** Type of spi_w12 register - * SPI CPU-controlled buffer12 - */ -typedef union { - struct { - /** reg_buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf12:32; - }; - uint32_t val; -} lp_spi_w12_reg_t; - - -/** Group: LP SPI W13 REG */ -/** Type of spi_w13 register - * SPI CPU-controlled buffer13 - */ -typedef union { - struct { - /** reg_buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf13:32; - }; - uint32_t val; -} lp_spi_w13_reg_t; - - -/** Group: LP SPI W14 REG */ -/** Type of spi_w14 register - * SPI CPU-controlled buffer14 - */ -typedef union { - struct { - /** reg_buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf14:32; - }; - uint32_t val; -} lp_spi_w14_reg_t; - - -/** Group: LP SPI W15 REG */ -/** Type of spi_w15 register - * SPI CPU-controlled buffer15 - */ -typedef union { - struct { - /** reg_buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t reg_buf15:32; - }; - uint32_t val; -} lp_spi_w15_reg_t; - +} lp_spi_wn_reg_t; /** Group: LP SPI SLAVE REG */ /** Type of spi_slave register @@ -1238,22 +1012,7 @@ typedef struct { volatile lp_spi_sleep_conf1_reg_t spi_sleep_conf1; volatile lp_spi_dma_int_set_reg_t spi_dma_int_set; uint32_t reserved_050[18]; - volatile lp_spi_w0_reg_t spi_w0; - volatile lp_spi_w1_reg_t spi_w1; - volatile lp_spi_w2_reg_t spi_w2; - volatile lp_spi_w3_reg_t spi_w3; - volatile lp_spi_w4_reg_t spi_w4; - volatile lp_spi_w5_reg_t spi_w5; - volatile lp_spi_w6_reg_t spi_w6; - volatile lp_spi_w7_reg_t spi_w7; - volatile lp_spi_w8_reg_t spi_w8; - volatile lp_spi_w9_reg_t spi_w9; - volatile lp_spi_w10_reg_t spi_w10; - volatile lp_spi_w11_reg_t spi_w11; - volatile lp_spi_w12_reg_t spi_w12; - volatile lp_spi_w13_reg_t spi_w13; - volatile lp_spi_w14_reg_t spi_w14; - volatile lp_spi_w15_reg_t spi_w15; + volatile lp_spi_wn_reg_t data_buf[16]; uint32_t reserved_0d8[2]; volatile lp_spi_slave_reg_t spi_slave; volatile lp_spi_slave1_reg_t spi_slave1; @@ -1263,12 +1022,12 @@ typedef struct { volatile lp_rnd_eco_cs_reg_t rnd_eco_cs; volatile lp_rnd_eco_low_reg_t rnd_eco_low; volatile lp_rnd_eco_high_reg_t rnd_eco_high; -} lp_dev_t; +} lp_spi_dev_t; -extern lp_dev_t LP_SPI; +extern lp_spi_dev_t LP_SPI; #ifndef __cplusplus -_Static_assert(sizeof(lp_dev_t) == 0x100, "Invalid size of lp_dev_t structure"); +_Static_assert(sizeof(lp_spi_dev_t) == 0x100, "Invalid size of lp_spi_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h index 683e3596ac..68abe42e33 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/lp_timer_reg.h @@ -11,331 +11,331 @@ extern "C" { #endif -/** RTC_TIMER_TAR0_LOW_REG register +/** LP_TIMER_TAR0_LOW_REG register * need_des */ -#define RTC_TIMER_TAR0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x0) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x0) +/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_M (RTC_TIMER_MAIN_TIMER_TAR_LOW0_V << RTC_TIMER_MAIN_TIMER_TAR_LOW0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW0_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0 -/** RTC_TIMER_TAR0_HIGH_REG register +/** LP_TIMER_TAR0_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x4) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x4) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_M (RTC_TIMER_MAIN_TIMER_TAR_EN0_V << RTC_TIMER_MAIN_TIMER_TAR_EN0_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN0_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31 -/** RTC_TIMER_TAR1_LOW_REG register +/** LP_TIMER_TAR1_LOW_REG register * need_des */ -#define RTC_TIMER_TAR1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x8) -/** RTC_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; +#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x8) +/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_M (RTC_TIMER_MAIN_TIMER_TAR_LOW1_V << RTC_TIMER_MAIN_TIMER_TAR_LOW1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_LOW1_S 0 +#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S) +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0 -/** RTC_TIMER_TAR1_HIGH_REG register +/** LP_TIMER_TAR1_HIGH_REG register * need_des */ -#define RTC_TIMER_TAR1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0xc) -/** RTC_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; +#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0xc) +/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_M (RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V << RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 -/** RTC_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S) +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0 +/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_M (RTC_TIMER_MAIN_TIMER_TAR_EN1_V << RTC_TIMER_MAIN_TIMER_TAR_EN1_S) -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_TAR_EN1_S 31 +#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31)) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S) +#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31 -/** RTC_TIMER_UPDATE_REG register +/** LP_TIMER_UPDATE_REG register * need_des */ -#define RTC_TIMER_UPDATE_REG (DR_REG_RTC_TIMER_BASE + 0x10) -/** RTC_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; +#define LP_TIMER_UPDATE_REG (DR_REG_LP_TIMER_BASE + 0x10) +/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [28]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_UPDATE (BIT(28)) -#define RTC_TIMER_MAIN_TIMER_UPDATE_M (RTC_TIMER_MAIN_TIMER_UPDATE_V << RTC_TIMER_MAIN_TIMER_UPDATE_S) -#define RTC_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_UPDATE_S 28 -/** RTC_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; +#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(28)) +#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S) +#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_UPDATE_S 28 +/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_M (RTC_TIMER_MAIN_TIMER_XTAL_OFF_V << RTC_TIMER_MAIN_TIMER_XTAL_OFF_S) -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_XTAL_OFF_S 29 -/** RTC_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29)) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S) +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29 +/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_M (RTC_TIMER_MAIN_TIMER_SYS_STALL_V << RTC_TIMER_MAIN_TIMER_SYS_STALL_S) -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_STALL_S 30 -/** RTC_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30)) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S) +#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30 +/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_M (RTC_TIMER_MAIN_TIMER_SYS_RST_V << RTC_TIMER_MAIN_TIMER_SYS_RST_S) -#define RTC_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_SYS_RST_S 31 +#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S) +#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31 -/** RTC_TIMER_MAIN_BUF0_LOW_REG register +/** LP_TIMER_MAIN_BUF0_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x14) -/** RTC_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_TIMER_BASE + 0x14) +/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_M (RTC_TIMER_MAIN_TIMER_BUF0_LOW_V << RTC_TIMER_MAIN_TIMER_BUF0_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0 -/** RTC_TIMER_MAIN_BUF0_HIGH_REG register +/** LP_TIMER_MAIN_BUF0_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x18) -/** RTC_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x18) +/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0 -/** RTC_TIMER_MAIN_BUF1_LOW_REG register +/** LP_TIMER_MAIN_BUF1_LOW_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_LOW_REG (DR_REG_RTC_TIMER_BASE + 0x1c) -/** RTC_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_TIMER_BASE + 0x1c) +/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_M (RTC_TIMER_MAIN_TIMER_BUF1_LOW_V << RTC_TIMER_MAIN_TIMER_BUF1_LOW_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_LOW_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S) +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0 -/** RTC_TIMER_MAIN_BUF1_HIGH_REG register +/** LP_TIMER_MAIN_BUF1_HIGH_REG register * need_des */ -#define RTC_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_RTC_TIMER_BASE + 0x20) -/** RTC_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; +#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_TIMER_BASE + 0x20) +/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_M (RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V << RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S) -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU -#define RTC_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S) +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU +#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0 -/** RTC_TIMER_MAIN_OVERFLOW_REG register +/** LP_TIMER_MAIN_OVERFLOW_REG register * need_des */ -#define RTC_TIMER_MAIN_OVERFLOW_REG (DR_REG_RTC_TIMER_BASE + 0x24) -/** RTC_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_OVERFLOW_REG (DR_REG_LP_TIMER_BASE + 0x24) +/** LP_TIMER_MAIN_TIMER_ALARM_LOAD : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_M (RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V << RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S) -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD (BIT(31)) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_M (LP_TIMER_MAIN_TIMER_ALARM_LOAD_V << LP_TIMER_MAIN_TIMER_ALARM_LOAD_S) +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_ALARM_LOAD_S 31 -/** RTC_TIMER_INT_RAW_REG register +/** LP_TIMER_INT_RAW_REG register * need_des */ -#define RTC_TIMER_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x28) -/** RTC_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x28) +/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_RAW (BIT(30)) -#define RTC_TIMER_OVERFLOW_RAW_M (RTC_TIMER_OVERFLOW_RAW_V << RTC_TIMER_OVERFLOW_RAW_S) -#define RTC_TIMER_OVERFLOW_RAW_V 0x00000001U -#define RTC_TIMER_OVERFLOW_RAW_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_RAW (BIT(30)) +#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S) +#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U +#define LP_TIMER_OVERFLOW_RAW_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_M (RTC_TIMER_SOC_WAKEUP_INT_RAW_V << RTC_TIMER_SOC_WAKEUP_INT_RAW_S) -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_RAW_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S) +#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31 -/** RTC_TIMER_INT_ST_REG register +/** LP_TIMER_INT_ST_REG register * need_des */ -#define RTC_TIMER_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x2c) -/** RTC_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x2c) +/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ST (BIT(30)) -#define RTC_TIMER_OVERFLOW_ST_M (RTC_TIMER_OVERFLOW_ST_V << RTC_TIMER_OVERFLOW_ST_S) -#define RTC_TIMER_OVERFLOW_ST_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ST_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ST (BIT(30)) +#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S) +#define LP_TIMER_OVERFLOW_ST_V 0x00000001U +#define LP_TIMER_OVERFLOW_ST_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_M (RTC_TIMER_SOC_WAKEUP_INT_ST_V << RTC_TIMER_SOC_WAKEUP_INT_ST_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ST_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S) +#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31 -/** RTC_TIMER_INT_ENA_REG register +/** LP_TIMER_INT_ENA_REG register * need_des */ -#define RTC_TIMER_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x30) -/** RTC_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x30) +/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_ENA (BIT(30)) -#define RTC_TIMER_OVERFLOW_ENA_M (RTC_TIMER_OVERFLOW_ENA_V << RTC_TIMER_OVERFLOW_ENA_S) -#define RTC_TIMER_OVERFLOW_ENA_V 0x00000001U -#define RTC_TIMER_OVERFLOW_ENA_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_ENA (BIT(30)) +#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S) +#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U +#define LP_TIMER_OVERFLOW_ENA_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_M (RTC_TIMER_SOC_WAKEUP_INT_ENA_V << RTC_TIMER_SOC_WAKEUP_INT_ENA_S) -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_ENA_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S) +#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31 -/** RTC_TIMER_INT_CLR_REG register +/** LP_TIMER_INT_CLR_REG register * need_des */ -#define RTC_TIMER_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x34) -/** RTC_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x34) +/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_OVERFLOW_CLR (BIT(30)) -#define RTC_TIMER_OVERFLOW_CLR_M (RTC_TIMER_OVERFLOW_CLR_V << RTC_TIMER_OVERFLOW_CLR_S) -#define RTC_TIMER_OVERFLOW_CLR_V 0x00000001U -#define RTC_TIMER_OVERFLOW_CLR_S 30 -/** RTC_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_OVERFLOW_CLR (BIT(30)) +#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S) +#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U +#define LP_TIMER_OVERFLOW_CLR_S 30 +/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_M (RTC_TIMER_SOC_WAKEUP_INT_CLR_V << RTC_TIMER_SOC_WAKEUP_INT_CLR_S) -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U -#define RTC_TIMER_SOC_WAKEUP_INT_CLR_S 31 +#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31)) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S) +#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U +#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31 -/** RTC_TIMER_LP_INT_RAW_REG register +/** LP_TIMER_LP_INT_RAW_REG register * need_des */ -#define RTC_TIMER_LP_INT_RAW_REG (DR_REG_RTC_TIMER_BASE + 0x38) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_TIMER_BASE + 0x38) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_M (RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V << RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31 -/** RTC_TIMER_LP_INT_ST_REG register +/** LP_TIMER_LP_INT_ST_REG register * need_des */ -#define RTC_TIMER_LP_INT_ST_REG (DR_REG_RTC_TIMER_BASE + 0x3c) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_TIMER_BASE + 0x3c) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_M (RTC_TIMER_MAIN_TIMER_LP_INT_ST_V << RTC_TIMER_MAIN_TIMER_LP_INT_ST_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ST_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31 -/** RTC_TIMER_LP_INT_ENA_REG register +/** LP_TIMER_LP_INT_ENA_REG register * need_des */ -#define RTC_TIMER_LP_INT_ENA_REG (DR_REG_RTC_TIMER_BASE + 0x40) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_TIMER_BASE + 0x40) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_M (RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V << RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31 -/** RTC_TIMER_LP_INT_CLR_REG register +/** LP_TIMER_LP_INT_CLR_REG register * need_des */ -#define RTC_TIMER_LP_INT_CLR_REG (DR_REG_RTC_TIMER_BASE + 0x44) -/** RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; +#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_TIMER_BASE + 0x44) +/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 -/** RTC_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30)) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30 +/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_M (RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V << RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S) -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U -#define RTC_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31)) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S) +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U +#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31 -/** RTC_TIMER_DATE_REG register +/** LP_TIMER_DATE_REG register * need_des */ -#define RTC_TIMER_DATE_REG (DR_REG_RTC_TIMER_BASE + 0x3fc) -/** RTC_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; +#define LP_TIMER_DATE_REG (DR_REG_LP_TIMER_BASE + 0x3fc) +/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 34672976; * need_des */ -#define RTC_TIMER_DATE 0x7FFFFFFFU -#define RTC_TIMER_DATE_M (RTC_TIMER_DATE_V << RTC_TIMER_DATE_S) -#define RTC_TIMER_DATE_V 0x7FFFFFFFU -#define RTC_TIMER_DATE_S 0 -/** RTC_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; +#define LP_TIMER_DATE 0x7FFFFFFFU +#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S) +#define LP_TIMER_DATE_V 0x7FFFFFFFU +#define LP_TIMER_DATE_S 0 +/** LP_TIMER_CLK_EN : R/W; bitpos: [31]; default: 0; * need_des */ -#define RTC_TIMER_CLK_EN (BIT(31)) -#define RTC_TIMER_CLK_EN_M (RTC_TIMER_CLK_EN_V << RTC_TIMER_CLK_EN_S) -#define RTC_TIMER_CLK_EN_V 0x00000001U -#define RTC_TIMER_CLK_EN_S 31 +#define LP_TIMER_CLK_EN (BIT(31)) +#define LP_TIMER_CLK_EN_M (LP_TIMER_CLK_EN_V << LP_TIMER_CLK_EN_S) +#define LP_TIMER_CLK_EN_V 0x00000001U +#define LP_TIMER_CLK_EN_S 31 #ifdef __cplusplus } diff --git a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h index 32b477ef10..676f27357a 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/pmu_struct.h @@ -5,6 +5,7 @@ */ #pragma once +#include #include #include "pmu_reg.h" #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h index 95ce3b2fe2..c8978c0f54 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/usb_serial_jtag_reg.h @@ -14,1272 +14,1272 @@ extern "C" { /** USB_DEVICE_EP1_REG register * FIFO access for the CDC-ACM data IN and OUT endpoints. */ -#define USB_DEVICE_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) -/** USB_DEVICE_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) +/** USB_SERIAL_JTAG_RDWR_BYTE : RO; bitpos: [7:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. When * USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) * into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check * USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is * received, then read data from UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_M (USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V << USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S) -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_RDWR_BYTE_S 0 +#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S) +#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FFU +#define USB_SERIAL_JTAG_RDWR_BYTE_S 0 /** USB_DEVICE_EP1_CONF_REG register * Configuration and control registers for the CDC-ACM FIFOs. */ -#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) -/** USB_DEVICE_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) +/** USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. */ -#define USB_DEVICE_SERIAL_JTAG_WR_DONE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_M (USB_DEVICE_SERIAL_JTAG_WR_DONE_V << USB_DEVICE_SERIAL_JTAG_WR_DONE_S) -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_WR_DONE_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_WR_DONE (BIT(0)) +#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S) +#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001U +#define USB_SERIAL_JTAG_WR_DONE_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1; * 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing * USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB * Host. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0; * 1'b1: Indicate there is data in UART Rx FIFO. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2 /** USB_DEVICE_INT_RAW_REG register * Interrupt raw status register. */ -#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when flush cmd is received for IN * endpoint 2 of JTAG. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0 +/** USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; * The raw interrupt bit turns to high level when SOF frame is received. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_RAW_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; +#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S) +#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; * default: 0; * The raw interrupt bit turns to high level when Serial Port OUT Endpoint received * one packet. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1; * The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; * The raw interrupt bit turns to high level when pid error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw interrupt bit turns to high level when CRC5 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; * The raw interrupt bit turns to high level when CRC16 error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; * The raw interrupt bit turns to high level when stuff error is detected. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; * default: 0; * The raw interrupt bit turns to high level when IN token for IN endpoint 1 is * received. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw interrupt bit turns to high level when usb bus reset is detected. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 1 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; * default: 0; * The raw interrupt bit turns to high level when OUT endpoint 2 received packet with * zero palyload. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; * The raw interrupt bit turns to high level when level of RTS from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_M (USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V << USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_RAW_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; * The raw interrupt bit turns to high level when level of DTR from usb serial channel * is changed. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_M (USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V << USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_RAW_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; * The raw interrupt bit turns to high level when level of GET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_RAW_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; * The raw interrupt bit turns to high level when level of SET LINE CODING request is * received. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_RAW_S 15 /** USB_DEVICE_INT_ST_REG register * Interrupt status register. */ -#define USB_DEVICE_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ST_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S) +#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ST_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0; * The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ST_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0; * The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0; * The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0; * The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0; * The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0; * The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ST : RO; bitpos: [12]; default: 0; * The raw interrupt status bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_M (USB_SERIAL_JTAG_RTS_CHG_INT_ST_V << USB_SERIAL_JTAG_RTS_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ST_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ST : RO; bitpos: [13]; default: 0; * The raw interrupt status bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_M (USB_SERIAL_JTAG_DTR_CHG_INT_ST_V << USB_SERIAL_JTAG_DTR_CHG_INT_ST_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ST_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST : RO; bitpos: [14]; default: 0; * The raw interrupt status bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ST_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST : RO; bitpos: [15]; default: 0; * The raw interrupt status bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ST_S 15 /** USB_DEVICE_INT_ENA_REG register * Interrupt enable status register. */ -#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0 +/** USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0; * The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_ENA_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S) +#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0; * The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; * The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; * The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; * The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0; * The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0; * The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0; * The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_ENA : R/W; bitpos: [12]; default: 0; * The interrupt enable bit for the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_M (USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V << USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_ENA_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_ENA : R/W; bitpos: [13]; default: 0; * The interrupt enable bit for the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_M (USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V << USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_ENA_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA : R/W; bitpos: [14]; default: 0; * The interrupt enable bit for the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_ENA_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA : R/W; bitpos: [15]; default: 0; * The interrupt enable bit for the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_ENA_S 15 /** USB_DEVICE_INT_CLR_REG register * Interrupt clear status register. */ -#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) -/** USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) +/** USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0)) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S) +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0 +/** USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0; * Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SOF_INT_CLR_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1)) +#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S) +#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2 +/** USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0; * Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 -/** USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3 +/** USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0; * Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 -/** USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4)) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4 +/** USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0; * Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 -/** USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5)) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5 +/** USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0; * Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 -/** USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6)) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6 +/** USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0; * Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7)) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S) +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7 +/** USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0; * Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8)) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S) +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8 +/** USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0; * Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10)) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10 +/** USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0; * Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 -/** USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11)) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S) +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11 +/** USB_SERIAL_JTAG_RTS_CHG_INT_CLR : WT; bitpos: [12]; default: 0; * Set this bit to clear the USB_DEVICE_RTS_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 -/** USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR (BIT(12)) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_M (USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V << USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_CHG_INT_CLR_S 12 +/** USB_SERIAL_JTAG_DTR_CHG_INT_CLR : WT; bitpos: [13]; default: 0; * Set this bit to clear the USB_DEVICE_DTR_CHG_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 -/** USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR (BIT(13)) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_M (USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V << USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S) +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_CHG_INT_CLR_S 13 +/** USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR : WT; bitpos: [14]; default: 0; * Set this bit to clear the USB_DEVICE_GET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 -/** USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR (BIT(14)) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_GET_LINE_CODE_INT_CLR_S 14 +/** USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR : WT; bitpos: [15]; default: 0; * Set this bit to clear the USB_DEVICE_SET_LINE_CODE_INT interrupt. */ -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR (BIT(15)) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_M (USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V << USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S) +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_V 0x00000001U +#define USB_SERIAL_JTAG_SET_LINE_CODE_INT_CLR_S 15 /** USB_DEVICE_CONF0_REG register * PHY hardware configuration. */ -#define USB_DEVICE_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) -/** USB_DEVICE_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) +/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY */ -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_M (USB_DEVICE_SERIAL_JTAG_PHY_SEL_V << USB_DEVICE_SERIAL_JTAG_PHY_SEL_S) -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PHY_SEL_S 0 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) +#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) +#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_PHY_SEL_S 0 +/** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; * Enable software control USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 -/** USB_DEVICE_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1)) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1 +/** USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0; * USB D+ D- exchange */ -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_M (USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V << USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S) -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_EXCHG_PINS_S 2 -/** USB_DEVICE_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; +#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2)) +#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S) +#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001U +#define USB_SERIAL_JTAG_EXCHG_PINS_S 2 +/** USB_SERIAL_JTAG_VREFH : R/W; bitpos: [4:3]; default: 0; * Control single-end input high threshold,1.76V to 2V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFH 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_M (USB_DEVICE_SERIAL_JTAG_VREFH_V << USB_DEVICE_SERIAL_JTAG_VREFH_S) -#define USB_DEVICE_SERIAL_JTAG_VREFH_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFH_S 3 -/** USB_DEVICE_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; +#define USB_SERIAL_JTAG_VREFH 0x00000003U +#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S) +#define USB_SERIAL_JTAG_VREFH_V 0x00000003U +#define USB_SERIAL_JTAG_VREFH_S 3 +/** USB_SERIAL_JTAG_VREFL : R/W; bitpos: [6:5]; default: 0; * Control single-end input low threshold,0.8V to 1.04V, step 80mV */ -#define USB_DEVICE_SERIAL_JTAG_VREFL 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_M (USB_DEVICE_SERIAL_JTAG_VREFL_V << USB_DEVICE_SERIAL_JTAG_VREFL_S) -#define USB_DEVICE_SERIAL_JTAG_VREFL_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_VREFL_S 5 -/** USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_VREFL 0x00000003U +#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S) +#define USB_SERIAL_JTAG_VREFL_V 0x00000003U +#define USB_SERIAL_JTAG_VREFL_S 5 +/** USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0; * Enable software control input threshold */ -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_VREF_OVERRIDE_S 7 -/** USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7)) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S) +#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7 +/** USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0; * Enable software control USB D+ D- pullup pulldown */ -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8)) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S) +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001U +#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8 +/** USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1; * Control USB D+ pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLUP_S 9 -/** USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9)) +#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S) +#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLUP_S 9 +/** USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0; * Control USB D+ pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DP_PULLDOWN_S 10 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; +#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10)) +#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S) +#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10 +/** USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0; * Control USB D- pull up. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP (BIT(11)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_M (USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V << USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLUP_S 11 -/** USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11)) +#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S) +#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLUP_S 11 +/** USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0; * Control USB D- pull down. */ -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_M (USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V << USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S) -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DM_PULLDOWN_S 12 -/** USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; +#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12)) +#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S) +#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001U +#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12 +/** USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0; * Control pull up value. */ -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_M (USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V << USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S) -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_PULLUP_VALUE_S 13 -/** USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; +#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13)) +#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S) +#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001U +#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13 +/** USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1; * Enable USB pad function. */ -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_PAD_ENABLE_S 14 -/** USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; +#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14)) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S) +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14 +/** USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W; bitpos: [15]; default: 0; * Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is * disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input * through GPIO Matrix. */ -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(15)) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 /** USB_DEVICE_TEST_REG register * Registers used for debugging the PHY. */ -#define USB_DEVICE_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) -/** USB_DEVICE_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) +/** USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB pad */ -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_M (USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V << USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_ENABLE_S 0 -/** USB_DEVICE_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0)) +#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S) +#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_ENABLE_S 0 +/** USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0; * USB pad oen in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_M (USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V << USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_USB_OE_S 1 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1)) +#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S) +#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_USB_OE_S 1 +/** USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0; * USB D+ tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DP_S 2 -/** USB_DEVICE_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2)) +#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S) +#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DP_S 2 +/** USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0; * USB D- tx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_TX_DM_S 3 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3)) +#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S) +#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_TX_DM_S 3 +/** USB_SERIAL_JTAG_TEST_RX_RCV : RO; bitpos: [4]; default: 1; * USB RCV value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_RCV_S 4 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; +#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4)) +#define USB_SERIAL_JTAG_TEST_RX_RCV_M (USB_SERIAL_JTAG_TEST_RX_RCV_V << USB_SERIAL_JTAG_TEST_RX_RCV_S) +#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4 +/** USB_SERIAL_JTAG_TEST_RX_DP : RO; bitpos: [5]; default: 1; * USB D+ rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DP_S 5 -/** USB_DEVICE_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; +#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5)) +#define USB_SERIAL_JTAG_TEST_RX_DP_M (USB_SERIAL_JTAG_TEST_RX_DP_V << USB_SERIAL_JTAG_TEST_RX_DP_S) +#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DP_S 5 +/** USB_SERIAL_JTAG_TEST_RX_DM : RO; bitpos: [6]; default: 0; * USB D- rx value in test */ -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_M (USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V << USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S) -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_TEST_RX_DM_S 6 +#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6)) +#define USB_SERIAL_JTAG_TEST_RX_DM_M (USB_SERIAL_JTAG_TEST_RX_DM_V << USB_SERIAL_JTAG_TEST_RX_DM_S) +#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x00000001U +#define USB_SERIAL_JTAG_TEST_RX_DM_S 6 /** USB_DEVICE_JFIFO_ST_REG register * JTAG FIFO status and control registers. */ -#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) +/** USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [1:0]; default: 0; * JTAT in fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_CNT_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; +#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S) +#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0 +/** USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1; * 1: JTAG in fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2)) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2 +/** USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0; * 1: JTAG in fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_FULL_S 3 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3)) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S) +#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3 +/** USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [5:4]; default: 0; * JTAT out fifo counter. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_CNT_S 4 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; +#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S) +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4 +/** USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1; * 1: JTAG out fifo is empty. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6)) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S) +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6 +/** USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0; * 1: JTAG out fifo is full. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_FULL_S 7 -/** USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; +#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7)) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S) +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7 +/** USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0; * Write 1 to reset JTAG in fifo. */ -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_IN_FIFO_RESET_S 8 -/** USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; +#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8)) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S) +#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8 +/** USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0; * Write 1 to reset JTAG out fifo. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_OUT_FIFO_RESET_S 9 +#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9)) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S) +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001U +#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9 /** USB_DEVICE_FRAM_NUM_REG register * Last received SOF frame index register. */ -#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) -/** USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; +#define USB_DEVICE_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) +/** USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [10:0]; default: 0; * Frame index of received SOF frame. */ -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S) -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU -#define USB_DEVICE_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S) +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FFU +#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0 /** USB_DEVICE_IN_EP0_ST_REG register * Control IN endpoint status information. */ -#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) +/** USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S) +#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9 /** USB_DEVICE_IN_EP1_ST_REG register * CDC-ACM IN endpoint status information. */ -#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) +/** USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S) +#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9 /** USB_DEVICE_IN_EP2_ST_REG register * CDC-ACM interrupt IN endpoint status information. */ -#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) +/** USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S) +#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9 /** USB_DEVICE_IN_EP3_ST_REG register * JTAG IN endpoint status information. */ -#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; +#define USB_DEVICE_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) +/** USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [1:0]; default: 1; * State of IN Endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S) +#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0 +/** USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of IN endpoint 3. */ -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S) +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP0_ST_REG register * Control OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) +/** USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 0. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9 /** USB_DEVICE_OUT_EP1_ST_REG register * CDC-ACM OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) +/** USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 1. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9 +/** USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [22:16]; default: 0; * Data count in OUT endpoint 1 when one packet is received. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S) +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16 /** USB_DEVICE_OUT_EP2_ST_REG register * JTAG OUT endpoint status information. */ -#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; +#define USB_DEVICE_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) +/** USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [1:0]; default: 0; * State of OUT Endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_STATE_S 0 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S) +#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003U +#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0 +/** USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [8:2]; default: 0; * Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is * detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 -/** USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2 +/** USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [15:9]; default: 0; * Read data address of OUT endpoint 2. */ -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU -#define USB_DEVICE_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S) +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007FU +#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9 /** USB_DEVICE_MISC_CONF_REG register * Clock enable control */ -#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) -/** USB_DEVICE_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) +/** USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when application writes * registers. */ -#define USB_DEVICE_SERIAL_JTAG_CLK_EN (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CLK_EN_S 0 +#define USB_SERIAL_JTAG_CLK_EN (BIT(0)) +#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S) +#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_CLK_EN_S 0 -/** USB_DEVICE_MEM_CONF_REG register +/** USB_SERIAL_JTAG_MEM_CONF_REG register * Memory power control */ -#define USB_DEVICE_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) +/** USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_PD_S 0 -/** USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; +#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0)) +#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S) +#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_PD_S 0 +/** USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1; * 1: Force clock on for usb memory. */ -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S) -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1)) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S) +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001U +#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1 /** USB_DEVICE_CHIP_RST_REG register * CDC-ACM chip reset control. */ -#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_DEVICE_BASE + 0x4c) -/** USB_DEVICE_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_CHIP_RST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4c) +/** USB_SERIAL_JTAG_RTS : RO; bitpos: [0]; default: 0; * 1: Chip reset is detected from usb serial channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_RTS (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RTS_M (USB_DEVICE_SERIAL_JTAG_RTS_V << USB_DEVICE_SERIAL_JTAG_RTS_S) -#define USB_DEVICE_SERIAL_JTAG_RTS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RTS_S 0 -/** USB_DEVICE_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RTS (BIT(0)) +#define USB_SERIAL_JTAG_RTS_M (USB_SERIAL_JTAG_RTS_V << USB_SERIAL_JTAG_RTS_S) +#define USB_SERIAL_JTAG_RTS_V 0x00000001U +#define USB_SERIAL_JTAG_RTS_S 0 +/** USB_SERIAL_JTAG_DTR : RO; bitpos: [1]; default: 0; * 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it. */ -#define USB_DEVICE_SERIAL_JTAG_DTR (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_DTR_M (USB_DEVICE_SERIAL_JTAG_DTR_V << USB_DEVICE_SERIAL_JTAG_DTR_S) -#define USB_DEVICE_SERIAL_JTAG_DTR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_DTR_S 1 -/** USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_DTR (BIT(1)) +#define USB_SERIAL_JTAG_DTR_M (USB_SERIAL_JTAG_DTR_V << USB_SERIAL_JTAG_DTR_S) +#define USB_SERIAL_JTAG_DTR_V 0x00000001U +#define USB_SERIAL_JTAG_DTR_S 1 +/** USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS : R/W; bitpos: [2]; default: 0; * Set this bit to disable chip reset from usb serial channel to reset chip. */ -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS (BIT(2)) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_M (USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V << USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S) +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_V 0x00000001U +#define USB_SERIAL_JTAG_USB_UART_CHIP_RST_DIS_S 2 /** USB_DEVICE_SET_LINE_CODE_W0_REG register * W0 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x50) -/** USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x50) +/** USB_SERIAL_JTAG_DW_DTE_RATE : RO; bitpos: [31:0]; default: 0; * The value of dwDTERate set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_M (USB_SERIAL_JTAG_DW_DTE_RATE_V << USB_SERIAL_JTAG_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DW_DTE_RATE_S 0 /** USB_DEVICE_SET_LINE_CODE_W1_REG register * W1 of SET_LINE_CODING command. */ -#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x54) -/** USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; +#define USB_DEVICE_SET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x54) +/** USB_SERIAL_JTAG_BCHAR_FORMAT : RO; bitpos: [7:0]; default: 0; * The value of bCharFormat set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BCHAR_FORMAT_S 0 -/** USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_M (USB_SERIAL_JTAG_BCHAR_FORMAT_V << USB_SERIAL_JTAG_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_BCHAR_FORMAT_S 0 +/** USB_SERIAL_JTAG_BPARITY_TYPE : RO; bitpos: [15:8]; default: 0; * The value of bParityTpye set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_M (USB_SERIAL_JTAG_BPARITY_TYPE_V << USB_SERIAL_JTAG_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_BDATA_BITS : RO; bitpos: [23:16]; default: 0; * The value of bDataBits set by host through SET_LINE_CODING command. */ -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_BDATA_BITS_S 16 +#define USB_SERIAL_JTAG_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_M (USB_SERIAL_JTAG_BDATA_BITS_V << USB_SERIAL_JTAG_BDATA_BITS_S) +#define USB_SERIAL_JTAG_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_BDATA_BITS_S 16 /** USB_DEVICE_GET_LINE_CODE_W0_REG register * W0 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_DEVICE_BASE + 0x58) -/** USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x58) +/** USB_SERIAL_JTAG_GET_DW_DTE_RATE : R/W; bitpos: [31:0]; default: 0; * The value of dwDTERate set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_M (USB_SERIAL_JTAG_GET_DW_DTE_RATE_V << USB_SERIAL_JTAG_GET_DW_DTE_RATE_S) +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_GET_DW_DTE_RATE_S 0 /** USB_DEVICE_GET_LINE_CODE_W1_REG register * W1 of GET_LINE_CODING command. */ -#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_DEVICE_BASE + 0x5c) -/** USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; +#define USB_DEVICE_GET_LINE_CODE_W1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x5c) +/** USB_SERIAL_JTAG_GET_BDATA_BITS : R/W; bitpos: [7:0]; default: 0; * The value of bCharFormat set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_M (USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V << USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BDATA_BITS_S 0 -/** USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; +#define USB_SERIAL_JTAG_GET_BDATA_BITS 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_M (USB_SERIAL_JTAG_GET_BDATA_BITS_V << USB_SERIAL_JTAG_GET_BDATA_BITS_S) +#define USB_SERIAL_JTAG_GET_BDATA_BITS_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BDATA_BITS_S 0 +/** USB_SERIAL_JTAG_GET_BPARITY_TYPE : R/W; bitpos: [15:8]; default: 0; * The value of bParityTpye set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 -/** USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_M (USB_SERIAL_JTAG_GET_BPARITY_TYPE_V << USB_SERIAL_JTAG_GET_BPARITY_TYPE_S) +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BPARITY_TYPE_S 8 +/** USB_SERIAL_JTAG_GET_BCHAR_FORMAT : R/W; bitpos: [23:16]; default: 0; * The value of bDataBits set by software which is requested by GET_LINE_CODING * command. */ -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S) -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU -#define USB_DEVICE_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_M (USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V << USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S) +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_V 0x000000FFU +#define USB_SERIAL_JTAG_GET_BCHAR_FORMAT_S 16 /** USB_DEVICE_CONFIG_UPDATE_REG register * Configuration registers' value update */ -#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_DEVICE_BASE + 0x60) -/** USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; +#define USB_DEVICE_CONFIG_UPDATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x60) +/** USB_SERIAL_JTAG_CONFIG_UPDATE : WT; bitpos: [0]; default: 0; * Write 1 to this register would update the value of configure registers from APB * clock domain to 48MHz clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_M (USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V << USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S) -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_CONFIG_UPDATE_S 0 +#define USB_SERIAL_JTAG_CONFIG_UPDATE (BIT(0)) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_M (USB_SERIAL_JTAG_CONFIG_UPDATE_V << USB_SERIAL_JTAG_CONFIG_UPDATE_S) +#define USB_SERIAL_JTAG_CONFIG_UPDATE_V 0x00000001U +#define USB_SERIAL_JTAG_CONFIG_UPDATE_S 0 /** USB_DEVICE_SER_AFIFO_CONFIG_REG register * Serial AFIFO configure register */ -#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_DEVICE_BASE + 0x64) -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; +#define USB_DEVICE_SER_AFIFO_CONFIG_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x64) +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR : R/W; bitpos: [0]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR (BIT(0)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_WR_S 0 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD : R/W; bitpos: [1]; default: 0; * Write 1 to reset CDC_ACM IN async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD (BIT(1)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_RESET_RD_S 1 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR : R/W; bitpos: [2]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR (BIT(2)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_WR_S 2 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD : R/W; bitpos: [3]; default: 0; * Write 1 to reset CDC_ACM OUT async FIFO read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD (BIT(3)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S 3 +/** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1; * CDC_ACM OUTPUT async FIFO empty signal in read clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 -/** USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY (BIT(4)) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S) +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S 4 +/** USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL : RO; bitpos: [5]; default: 0; * CDC_ACM OUT IN async FIFO empty signal in write clock domain. */ -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL (BIT(5)) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_M (USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V << USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S) +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_V 0x00000001U +#define USB_SERIAL_JTAG_SERIAL_IN_AFIFO_WFULL_S 5 /** USB_DEVICE_BUS_RESET_ST_REG register * USB Bus reset status register */ -#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_DEVICE_BASE + 0x68) -/** USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; +#define USB_DEVICE_BUS_RESET_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x68) +/** USB_SERIAL_JTAG_USB_BUS_RESET_ST : RO; bitpos: [0]; default: 1; * USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus * reset is released. */ -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S) -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST (BIT(0)) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_ST_S) +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_V 0x00000001U +#define USB_SERIAL_JTAG_USB_BUS_RESET_ST_S 0 /** USB_DEVICE_ECO_LOW_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_DEVICE_BASE + 0x6c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x6c) +/** USB_SERIAL_JTAG_RND_ECO_LOW_48 : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_M (USB_SERIAL_JTAG_RND_ECO_LOW_48_V << USB_SERIAL_JTAG_RND_ECO_LOW_48_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_48_S 0 /** USB_DEVICE_ECO_HIGH_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_DEVICE_BASE + 0x70) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x70) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_48 : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_M (USB_SERIAL_JTAG_RND_ECO_HIGH_48_V << USB_SERIAL_JTAG_RND_ECO_HIGH_48_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_48_S 0 /** USB_DEVICE_ECO_CELL_CTRL_48_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_DEVICE_BASE + 0x74) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_48_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x74) +/** USB_SERIAL_JTAG_RDN_RESULT_48 : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_48_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_48 (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_48_M (USB_SERIAL_JTAG_RDN_RESULT_48_V << USB_SERIAL_JTAG_RDN_RESULT_48_S) +#define USB_SERIAL_JTAG_RDN_RESULT_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_48_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_48 : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_48_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_48 (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_48_M (USB_SERIAL_JTAG_RDN_ENA_48_V << USB_SERIAL_JTAG_RDN_ENA_48_S) +#define USB_SERIAL_JTAG_RDN_ENA_48_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_48_S 1 /** USB_DEVICE_ECO_LOW_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_DEVICE_BASE + 0x78) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; +#define USB_DEVICE_ECO_LOW_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x78) +/** USB_SERIAL_JTAG_RND_ECO_LOW_APB : R/W; bitpos: [31:0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_M (USB_SERIAL_JTAG_RND_ECO_LOW_APB_V << USB_SERIAL_JTAG_RND_ECO_LOW_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_LOW_APB_S 0 /** USB_DEVICE_ECO_HIGH_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_DEVICE_BASE + 0x7c) -/** USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; +#define USB_DEVICE_ECO_HIGH_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x7c) +/** USB_SERIAL_JTAG_RND_ECO_HIGH_APB : R/W; bitpos: [31:0]; default: 4294967295; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_M (USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V << USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S) +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_RND_ECO_HIGH_APB_S 0 /** USB_DEVICE_ECO_CELL_CTRL_APB_REG register * Reserved. */ -#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_DEVICE_BASE + 0x80) -/** USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; +#define USB_DEVICE_ECO_CELL_CTRL_APB_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) +/** USB_SERIAL_JTAG_RDN_RESULT_APB : RO; bitpos: [0]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_RESULT_APB_S 0 -/** USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; +#define USB_SERIAL_JTAG_RDN_RESULT_APB (BIT(0)) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_M (USB_SERIAL_JTAG_RDN_RESULT_APB_V << USB_SERIAL_JTAG_RDN_RESULT_APB_S) +#define USB_SERIAL_JTAG_RDN_RESULT_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_RESULT_APB_S 0 +/** USB_SERIAL_JTAG_RDN_ENA_APB : R/W; bitpos: [1]; default: 0; * Reserved. */ -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_M (USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V << USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S) -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U -#define USB_DEVICE_SERIAL_JTAG_RDN_ENA_APB_S 1 +#define USB_SERIAL_JTAG_RDN_ENA_APB (BIT(1)) +#define USB_SERIAL_JTAG_RDN_ENA_APB_M (USB_SERIAL_JTAG_RDN_ENA_APB_V << USB_SERIAL_JTAG_RDN_ENA_APB_S) +#define USB_SERIAL_JTAG_RDN_ENA_APB_V 0x00000001U +#define USB_SERIAL_JTAG_RDN_ENA_APB_S 1 /** USB_DEVICE_SRAM_CTRL_REG register * PPA SRAM Control Register */ -#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_DEVICE_BASE + 0x84) -/** USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; +#define USB_DEVICE_SRAM_CTRL_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x84) +/** USB_SERIAL_JTAG_MEM_AUX_CTRL : R/W; bitpos: [13:0]; default: 4896; * Control signals */ -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S) -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU -#define USB_DEVICE_SERIAL_JTAG_MEM_AUX_CTRL_S 0 +#define USB_SERIAL_JTAG_MEM_AUX_CTRL 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_M (USB_SERIAL_JTAG_MEM_AUX_CTRL_V << USB_SERIAL_JTAG_MEM_AUX_CTRL_S) +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_V 0x00003FFFU +#define USB_SERIAL_JTAG_MEM_AUX_CTRL_S 0 /** USB_DEVICE_DATE_REG register * Date register */ -#define USB_DEVICE_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x88) -/** USB_DEVICE_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; +#define USB_DEVICE_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x88) +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 34676752; * register version. */ -#define USB_DEVICE_SERIAL_JTAG_DATE 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_M (USB_DEVICE_SERIAL_JTAG_DATE_V << USB_DEVICE_SERIAL_JTAG_DATE_S) -#define USB_DEVICE_SERIAL_JTAG_DATE_V 0xFFFFFFFFU -#define USB_DEVICE_SERIAL_JTAG_DATE_S 0 +#define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S) +#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFFU +#define USB_SERIAL_JTAG_DATE_S 0 #ifdef __cplusplus }