From 37ee778e9a7ea1ef1079ed131404a73ffe32227e Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 30 Dec 2025 13:21:40 +0800 Subject: [PATCH] fix(parlio_rx): fixed opposite sample edge issue Closes https://github.com/espressif/esp-idf/issues/18012 --- .../test_apps/parlio/main/test_parlio_rx.c | 2 +- components/hal/esp32c5/include/hal/parlio_ll.h | 10 ++++++---- components/hal/esp32h2/include/hal/parlio_ll.h | 10 ++++++---- components/hal/esp32p4/include/hal/parlio_ll.h | 10 ++++++---- 4 files changed, 19 insertions(+), 13 deletions(-) diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c index 138637e62f..a8d4737ebe 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c @@ -391,7 +391,7 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]") { parlio_rx_pulse_delimiter_config_t pls_deli_cfg = { .valid_sig_line_id = TEST_VALID_SIG, - .sample_edge = PARLIO_SAMPLE_EDGE_NEG, + .sample_edge = PARLIO_SAMPLE_EDGE_POS, .bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB, .eof_data_len = TEST_EOF_DATA_LEN, .timeout_ticks = 0, diff --git a/components/hal/esp32c5/include/hal/parlio_ll.h b/components/hal/esp32c5/include/hal/parlio_ll.h index 26f714c693..1e3cb294ef 100644 --- a/components/hal/esp32c5/include/hal/parlio_ll.h +++ b/components/hal/esp32c5/include/hal/parlio_ll.h @@ -255,8 +255,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en) __attribute__((always_inline)) static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->rx_clk_cfg.rx_clk_i_inv = edge; - dev->rx_clk_cfg.rx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->rx_clk_cfg.rx_clk_i_inv = invert; + dev->rx_clk_cfg.rx_clk_o_inv = invert; } /** @@ -559,8 +560,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta */ static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->tx_clk_cfg.tx_clk_i_inv = edge; - dev->tx_clk_cfg.tx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->tx_clk_cfg.tx_clk_i_inv = invert; + dev->tx_clk_cfg.tx_clk_o_inv = invert; } /** diff --git a/components/hal/esp32h2/include/hal/parlio_ll.h b/components/hal/esp32h2/include/hal/parlio_ll.h index e8964cc00c..4f00a41f36 100644 --- a/components/hal/esp32h2/include/hal/parlio_ll.h +++ b/components/hal/esp32h2/include/hal/parlio_ll.h @@ -258,8 +258,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en) __attribute__((always_inline)) static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->rx_clk_cfg.rx_clk_i_inv = edge; - dev->rx_clk_cfg.rx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->rx_clk_cfg.rx_clk_i_inv = invert; + dev->rx_clk_cfg.rx_clk_o_inv = invert; } /** @@ -567,8 +568,9 @@ static inline bool parlio_ll_tx_set_valid_delay(parl_io_dev_t *dev, uint32_t sta */ static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->tx_clk_cfg.tx_clk_i_inv = edge; - dev->tx_clk_cfg.tx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->tx_clk_cfg.tx_clk_i_inv = invert; + dev->tx_clk_cfg.tx_clk_o_inv = invert; } /** diff --git a/components/hal/esp32p4/include/hal/parlio_ll.h b/components/hal/esp32p4/include/hal/parlio_ll.h index a9bce617b4..21cb27c632 100644 --- a/components/hal/esp32p4/include/hal/parlio_ll.h +++ b/components/hal/esp32p4/include/hal/parlio_ll.h @@ -295,8 +295,9 @@ static inline void parlio_ll_rx_start_soft_recv(parl_io_dev_t *dev, bool en) __attribute__((always_inline)) static inline void parlio_ll_rx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->rx_clk_cfg.rx_clk_i_inv = edge; - dev->rx_clk_cfg.rx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->rx_clk_cfg.rx_clk_i_inv = invert; + dev->rx_clk_cfg.rx_clk_o_inv = invert; } /** @@ -592,8 +593,9 @@ static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en) */ static inline void parlio_ll_tx_set_sample_clock_edge(parl_io_dev_t *dev, parlio_sample_edge_t edge) { - dev->tx_clk_cfg.tx_clk_i_inv = edge; - dev->tx_clk_cfg.tx_clk_o_inv = edge; + bool invert = edge == PARLIO_SAMPLE_EDGE_NEG; + dev->tx_clk_cfg.tx_clk_i_inv = invert; + dev->tx_clk_cfg.tx_clk_o_inv = invert; } /**