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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example

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Marius Vikhammer
2021-06-23 14:54:36 +08:00
parent 67743ac444
commit 386739595f
38 changed files with 369 additions and 25 deletions
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examples/system/ulp_fsm/ulp/Makefile
+8
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#
# This is a project Makefile. It is assumed the directory this Makefile resides in is a
# project subdirectory.
#
PROJECT_NAME := ulp-example
include $(IDF_PATH)/make/project.mk