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RISCV-ULP: Add DS18B20 1wire RISCV-ULP example

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This commit is contained in:
Marius Vikhammer
2021-06-23 14:54:36 +08:00
parent 67743ac444
commit 386739595f
38 changed files with 369 additions and 25 deletions
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examples/system/ulp_fsm/ulp/sdkconfig.defaults
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# Enable ULP
CONFIG_ESP32_ULP_COPROC_ENABLED=y
CONFIG_ESP32_ULP_COPROC_RESERVE_MEM=1024
# Set log level to Warning to produce clean output
CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
CONFIG_BOOTLOADER_LOG_LEVEL=2
CONFIG_LOG_DEFAULT_LEVEL_WARN=y
CONFIG_LOG_DEFAULT_LEVEL=2
CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y