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Merge branch 'refactor/mspi_ll' into 'master'

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mspi: rename mspi_timing_tuning_ll.h to mspi_ll.h

Closes IDF-11918

See merge request espressif/esp-idf!36039
This commit is contained in:
Armando (Dou Yiwen)
2025-01-08 16:29:28 +08:00
parent b92e993d56 4c869d1f23
commit 3aba0ff704
39 changed files with 762 additions and 531 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+1 -1
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@@ -28,7 +28,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "bootloader_flash_override.h"
void bootloader_flash_update_id()
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+1 -1
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@@ -24,7 +24,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
static const char *TAG __attribute__((unused)) = "boot.esp32c61";
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
+2 -1
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@@ -24,6 +24,7 @@
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_ll.h"
#include "soc/pcr_reg.h"
void bootloader_flash_update_id()
@@ -87,7 +88,7 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
static void IRAM_ATTR bootloader_flash_clock_init(void)
{
// At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
+2 -1
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@@ -17,6 +17,7 @@
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "hal/mspi_ll.h"
#include "soc/pcr_reg.h"
static const char *TAG = "boot.esp32h21";
@@ -80,7 +81,7 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
static void IRAM_ATTR bootloader_flash_clock_init(void)
{
// At this moment, BBPLL should be enabled, safe to switch MSPI clock source to PLL_F64M (default clock src) to raise speed
REG_SET_FIELD(PCR_MSPI_CONF_REG, PCR_MSPI_CLK_SEL, 2);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+1 -1
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@@ -19,7 +19,7 @@
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/mspi_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_private/bootloader_flash_internal.h"