spi: bringup c6 spi master & slave driver support
This commit is contained in:
wanlei
@@ -7,7 +7,7 @@ SPI Master driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
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Overview of {IDF_TARGET_NAME}'s SPI peripherals
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-----------------------------------------------
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{IDF_TARGET_MAX_PERIPH_NUM:default="4", esp32c3="3", esp32c2="3"}
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{IDF_TARGET_MAX_PERIPH_NUM:default="4", esp32c3="3", esp32c2="3", esp32c6="3"}
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{IDF_TARGET_SPI2_CS_NUM:default="6", esp32="3"}
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{IDF_TARGET_SPI3_CS_NUM:default="3"}
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@@ -32,7 +32,7 @@ Overview of {IDF_TARGET_NAME}'s SPI peripherals
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- SPI2 and SPI3 are general purpose SPI controllers. They are open to users. SPI2 and SPI3 have independent signal buses with the same respective names. SPI2 has {IDF_TARGET_SPI2_CS_NUM} CS lines. SPI3 has {IDF_TARGET_SPI3_CS_NUM} CS lines. Each CS line can be used to drive one SPI slave.
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.. only:: esp32c3 or esp32c2
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.. only:: esp32c3 or esp32c2 or esp32c6
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- SPI2 is a general purpose SPI controller. It has an independent signal bus with the same name. The bus has {IDF_TARGET_SPI2_CS_NUM} CS lines to drive up to {IDF_TARGET_SPI2_CS_NUM} SPI slaves.
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@@ -230,7 +230,7 @@ If using more than one data lines to transmit, please set `SPI_DEVICE_HALFDUPLEX
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Half-duplex transactions with both read and write phases are not supported when using DMA. For details and workarounds, see :ref:`spi_known_issues`.
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.. only:: esp32s3 or esp32c3 or esp32c2
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.. only:: esp32s3 or esp32c3 or esp32c2 or esp32c6
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.. note::
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@@ -423,7 +423,7 @@ GPIO Matrix and IO_MUX
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* Only the first Device attached to the bus can use the CS0 pin.
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.. only:: esp32s2 or esp32s3
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.. only:: not esp32
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Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
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@@ -431,6 +431,8 @@ GPIO Matrix and IO_MUX
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The IO_MUX pins for SPI buses are given below.
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.. only:: esp32s2 or esp32s3
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+----------+------+------+
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| Pin Name | SPI2 | SPI3 |
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+ +------+------+
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@@ -449,16 +451,8 @@ GPIO Matrix and IO_MUX
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| QUADHD | 9 | N/A |
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+----------+------+------+
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* Only the first Device attached to the bus can use the CS0 pin.
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.. only:: esp32c2 or esp32c3
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Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
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When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
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The IO_MUX pins for SPI buses are given below.
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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@@ -468,18 +462,39 @@ GPIO Matrix and IO_MUX
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+----------+-------------+
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| SCLK | 6 |
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+----------+-------------+
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| MISO | 2 |
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+----------+-------------+
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| MOSI | 7 |
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+----------+-------------+
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| QUADWP | 5 |
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| MISO | 2 |
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+----------+-------------+
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| QUADHD | 4 |
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+----------+-------------+
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| QUADWP | 5 |
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+----------+-------------+
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.. only:: esp32c6
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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| | GPIO Number |
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+==========+=============+
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| CS0* | 16 |
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+----------+-------------+
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| SCLK | 6 |
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+----------+-------------+
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| MOSI | 7 |
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+----------+-------------+
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| MISO | 2 |
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+----------+-------------+
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| QUADHD | 4 |
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+----------+-------------+
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| QUADWP | 5 |
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+----------+-------------+
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.. only:: not esp32
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* Only the first Device attached to the bus can use the CS0 pin.
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.. _speed_considerations:
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Transfer Speed Considerations
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@@ -7,21 +7,13 @@ SPI Slave driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
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Overview of {IDF_TARGET_NAME}'s SPI peripherals
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-----------------------------------------------
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.. only:: esp32 or esp32s2 or esp32s3
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On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has independent signal bus with the same name.
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{IDF_TARGET_NAME} integrates two general purpose SPI controllers which can be used as slave nodes driven by an off-chip SPI master.
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.. only:: esp32
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.. only:: esp32
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- SPI2, sometimes referred to as HSPI
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- SPI3, sometimes referred to as VSPI
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SPI2 and SPI3 have independent signal buses with the same respective names.
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.. only:: esp32c3 or esp32c2
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{IDF_TARGET_NAME} integrates one general purpose SPI controller which can be used as a slave node driven by an off-chip SPI master. The controller is called SPI2 and has an independent signal bus with the same name.
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.. note::
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On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
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Terminology
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-----------
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@@ -146,7 +138,7 @@ GPIO Matrix and IO_MUX
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| QUADHD | 4 | 21 |
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+----------+------+------+
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.. only:: esp32s2 or esp32s3
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.. only:: not esp32
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Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
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@@ -154,6 +146,8 @@ GPIO Matrix and IO_MUX
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The IO_MUX pins for SPI buses are given below.
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.. only:: esp32s2 or esp32s3
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+----------+------+------+
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| Pin Name | SPI2 | SPI3 |
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+ +------+------+
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@@ -174,12 +168,6 @@ GPIO Matrix and IO_MUX
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.. only:: esp32c2 or esp32c3
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Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
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When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
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The IO_MUX pins for SPI buses are given below.
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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@@ -198,6 +186,26 @@ GPIO Matrix and IO_MUX
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| QUADHD | 4 |
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+----------+-------------+
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.. only:: esp32c6
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+----------+-------------+
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| Pin Name | SPI2 |
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+ +-------------+
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| | GPIO Number |
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+==========+=============+
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| CS0* | 16 |
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+----------+-------------+
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| SCLK | 6 |
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+----------+-------------+
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| MISO | 2 |
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+----------+-------------+
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| MOSI | 7 |
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+----------+-------------+
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| QUADWP | 5 |
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+----------+-------------+
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| QUADHD | 4 |
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+----------+-------------+
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* Only the first Device attached to the bus can use the CS0 pin.
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