diff --git a/.gitlab/ci/default-build-test-rules.yml b/.gitlab/ci/default-build-test-rules.yml index 0d4f0e2ead..11a291dd3c 100644 --- a/.gitlab/ci/default-build-test-rules.yml +++ b/.gitlab/ci/default-build-test-rules.yml @@ -14,7 +14,6 @@ extra_default_build_targets: bypass_check_test_targets: - esp32h21 - - esp32c61 - esp32h4 - esp32c5 diff --git a/components/app_update/test_apps/test_app_update/.build-test-rules.yml b/components/app_update/test_apps/test_app_update/.build-test-rules.yml index 7c118f2bb1..b0fce92576 100644 --- a/components/app_update/test_apps/test_app_update/.build-test-rules.yml +++ b/components/app_update/test_apps/test_app_update/.build-test-rules.yml @@ -7,6 +7,7 @@ components/app_update/test_apps: - if: CONFIG_NAME == "xip_psram" and SOC_SPIRAM_XIP_SUPPORTED == 1 # S2 doesn't have ROM for flash - if: CONFIG_NAME == "xip_psram_with_rom_impl" and (SOC_SPIRAM_XIP_SUPPORTED == 1 and IDF_TARGET != "esp32s2") + - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 disable: - if: IDF_TARGET in ["esp32h21", "esp32h4"] temporary: true @@ -14,3 +15,7 @@ components/app_update/test_apps: - if: IDF_TARGET == "esp32c61" and CONFIG_NAME == "xip_psram_with_rom_impl" temporary: true reason: not supported yet # TODO: [ESP32C61] IDF-12784 + disable_test: + - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 and IDF_TARGET == "esp32c61" + temporary: true + reason: lack of runners # TODO: [ESP32C61] IDF-13165 diff --git a/components/app_update/test_apps/test_app_update/main/CMakeLists.txt b/components/app_update/test_apps/test_app_update/main/CMakeLists.txt index a83ae6af90..b029b0e3a1 100644 --- a/components/app_update/test_apps/test_app_update/main/CMakeLists.txt +++ b/components/app_update/test_apps/test_app_update/main/CMakeLists.txt @@ -1,4 +1,15 @@ -idf_component_register(SRC_DIRS "." - PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES cmock test_utils app_update bootloader_support nvs_flash driver spi_flash esp_psram - WHOLE_ARCHIVE) +idf_component_register( + SRC_DIRS "." + PRIV_INCLUDE_DIRS "." + PRIV_REQUIRES + cmock + test_utils + app_update + bootloader_support + nvs_flash + driver + spi_flash + esp_psram + efuse + WHOLE_ARCHIVE +) diff --git a/components/app_update/test_apps/test_app_update/main/test_bootloader_update.c b/components/app_update/test_apps/test_app_update/main/test_bootloader_update.c new file mode 100644 index 0000000000..f4009f01ce --- /dev/null +++ b/components/app_update/test_apps/test_app_update/main/test_bootloader_update.c @@ -0,0 +1,87 @@ +/* + * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* + * Tests bootloader update. + */ + +#include "unity.h" +#include "esp_log.h" +#include "esp_efuse.h" +#include "esp_flash_internal.h" +#include "esp_rom_sys.h" +#include "utils_update.h" +#include "sdkconfig.h" + +#define BOOT_COUNT_NAMESPACE "boot_count" + +static __attribute__((unused)) const char *TAG = "btldr_update"; + +#if CONFIG_BOOTLOADER_RECOVERY_ENABLE + +/* @brief Checks and prepares the partition so that the factory app is launched after that. + */ +static void start_test(void) +{ + ESP_LOGI(TAG, "boot count 1 - reset"); + set_boot_count_in_nvs(1); + erase_ota_data(); + ESP_LOGI(TAG, "ota_data erased"); + ESP_LOGI(TAG, "Bootloader offset: 0x%x", esp_rom_get_bootloader_offset()); + reboot_as_deep_sleep(); +} + +static void test_flow1(void) +{ + uint8_t boot_count = get_boot_count_from_nvs(); + boot_count++; + set_boot_count_in_nvs(boot_count); + ESP_LOGI(TAG, "boot count %d", boot_count); + + ESP_LOGI(TAG, "Bootloader offset: 0x%x", esp_rom_get_bootloader_offset()); + + const esp_partition_t *primary_bootloader; + TEST_ESP_OK(esp_partition_register_external(NULL, ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader)); + const esp_partition_t *recovery_bootloader; + TEST_ESP_OK(esp_partition_register_external(NULL, CONFIG_BOOTLOADER_RECOVERY_OFFSET, ESP_BOOTLOADER_SIZE, "RecoveryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_RECOVERY, &recovery_bootloader)); + ESP_LOGI(TAG, "Bootloaders are registered"); + + // Remove write protection for the bootloader + esp_flash_set_dangerous_write_protection(esp_flash_default_chip, false); + switch (boot_count) { + case 2: + TEST_ASSERT_EQUAL_HEX32(ESP_PRIMARY_BOOTLOADER_OFFSET, esp_rom_get_bootloader_offset()); + + TEST_ESP_OK(esp_partition_erase_range(recovery_bootloader, 0, recovery_bootloader->size)); + ESP_LOGI(TAG, "Erase recovery bootloader"); + + TEST_ESP_OK(esp_efuse_set_recovery_bootloader_offset(CONFIG_BOOTLOADER_RECOVERY_OFFSET)); + + ESP_LOGI(TAG, "Backup, copy <%s> -> <%s>", primary_bootloader->label, recovery_bootloader->label); + TEST_ESP_OK(esp_partition_copy(recovery_bootloader, 0, primary_bootloader, 0, primary_bootloader->size)); + + TEST_ESP_OK(esp_partition_erase_range(primary_bootloader, 0, primary_bootloader->size)); + ESP_LOGI(TAG, "Erase primary bootloader"); + reboot_as_deep_sleep(); + break; + case 3: + TEST_ASSERT_EQUAL_HEX32(CONFIG_BOOTLOADER_RECOVERY_OFFSET, esp_rom_get_bootloader_offset()); + + ESP_LOGI(TAG, "Return to primary bootloader..."); + ESP_LOGI(TAG, "Copy <%s> -> <%s>", recovery_bootloader->label, primary_bootloader->label); + TEST_ESP_OK(esp_partition_copy(primary_bootloader, 0, recovery_bootloader, 0, primary_bootloader->size)); + + TEST_ESP_OK(esp_partition_erase_range(recovery_bootloader, 0, recovery_bootloader->size)); + ESP_LOGI(TAG, "Erase recovery bootloader"); + break; + default: + TEST_FAIL_MESSAGE("Unexpected stage"); + break; + } +} + +TEST_CASE_MULTIPLE_STAGES("Recovery bootloader feature", "[recovery_bootloader][timeout=90][reset=DEEPSLEEP_RESET, DEEPSLEEP_RESET]", start_test, test_flow1, test_flow1); + +#endif // CONFIG_BOOTLOADER_RECOVERY_ENABLE diff --git a/components/app_update/test_apps/test_app_update/main/test_switch_ota.c b/components/app_update/test_apps/test_app_update/main/test_switch_ota.c index b1bbb832bd..68531919ac 100644 --- a/components/app_update/test_apps/test_app_update/main/test_switch_ota.c +++ b/components/app_update/test_apps/test_app_update/main/test_switch_ota.c @@ -7,315 +7,16 @@ * Tests for switching between partitions: factory, OTAx, test. */ -#include -#include -#include "string.h" -#include -#include "sdkconfig.h" - -#include "esp_rom_spiflash.h" - -#include "freertos/FreeRTOS.h" -#include "freertos/task.h" -#include "freertos/semphr.h" -#include "freertos/queue.h" -#include "unity.h" - +#include "esp_system.h" #include "bootloader_common.h" #include "../bootloader_flash/include/bootloader_flash_priv.h" - -#include "esp_err.h" #include "esp_log.h" -#include "esp_ota_ops.h" -#include "esp_partition.h" -#include "esp_flash_partitions.h" -#include "esp_image_format.h" -#include "nvs_flash.h" - -#include "driver/gpio.h" -#include "esp_sleep.h" -#include "test_utils.h" - -#define BOOT_COUNT_NAMESPACE "boot_count" +#include "unity.h" +#include "utils_update.h" +#include "sdkconfig.h" static const char *TAG = "ota_test"; -static void set_boot_count_in_nvs(uint8_t boot_count) -{ - nvs_handle_t boot_count_handle; - esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle); - if (err != ESP_OK) { - TEST_ESP_OK(nvs_flash_erase()); - TEST_ESP_OK(nvs_flash_init()); - TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle)); - } - TEST_ESP_OK(nvs_set_u8(boot_count_handle, "boot_count", boot_count)); - TEST_ESP_OK(nvs_commit(boot_count_handle)); - nvs_close(boot_count_handle); -} - -static uint8_t get_boot_count_from_nvs(void) -{ - nvs_handle_t boot_count_handle; - esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READONLY, &boot_count_handle); - if (err == ESP_ERR_NVS_NOT_FOUND) { - set_boot_count_in_nvs(0); - } - uint8_t boot_count; - TEST_ESP_OK(nvs_get_u8(boot_count_handle, "boot_count", &boot_count)); - nvs_close(boot_count_handle); - return boot_count; -} - -/* @brief Copies a current app to next partition using handle. - * - * @param[in] update_handle - Handle of API ota. - * @param[in] cur_app - Current app. - */ -static void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app) -{ - const void *partition_bin = NULL; - esp_partition_mmap_handle_t data_map; - ESP_LOGI(TAG, "start the copy process"); - TEST_ESP_OK(esp_partition_mmap(curr_app, 0, curr_app->size, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map)); - TEST_ESP_OK(esp_ota_write(update_handle, (const void *)partition_bin, curr_app->size)); - esp_partition_munmap(data_map); - ESP_LOGI(TAG, "finish the copy process"); -} - -/* @brief Copies a current app to next partition using handle. - * - * @param[in] update_handle - Handle of API ota. - * @param[in] cur_app - Current app. - */ -static void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app) -{ - const void *partition_bin = NULL; - esp_partition_mmap_handle_t data_map; - ESP_LOGI(TAG, "start the copy process"); - uint32_t offset = 0, bytes_to_write = curr_app->size; - uint32_t write_bytes; - while (bytes_to_write > 0) { - write_bytes = (bytes_to_write > (4 * 1024)) ? (4 * 1024) : bytes_to_write; - TEST_ESP_OK(esp_partition_mmap(curr_app, offset, write_bytes, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map)); - TEST_ESP_OK(esp_ota_write_with_offset(update_handle, (const void *)partition_bin, write_bytes, offset)); - esp_partition_munmap(data_map); - bytes_to_write -= write_bytes; - offset += write_bytes; - } - ESP_LOGI(TAG, "finish the copy process"); -} - -/* @brief Get the next partition of OTA for the update. - * - * @return The next partition of OTA(OTA0-15). - */ -static const esp_partition_t * get_next_update_partition(void) -{ - const esp_partition_t *update_partition = esp_ota_get_next_update_partition(NULL); - TEST_ASSERT_NOT_EQUAL(NULL, update_partition); - ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, update_partition->subtype, update_partition->address); - return update_partition; -} - -/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition. - * - * @param[in] cur_app_partition - Current app. - * @param[in] next_app_partition - Next app for boot. - */ -static void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition) -{ - esp_ota_get_next_update_partition(NULL); - TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition); - ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address); - - esp_ota_handle_t update_handle = 0; - TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle)); - - copy_app_partition(update_handle, cur_app_partition); - - TEST_ESP_OK(esp_ota_end(update_handle)); - TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition)); -} - -/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition. - * - * @param[in] cur_app_partition - Current app. - * @param[in] next_app_partition - Next app for boot. - */ -static void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition) -{ - esp_ota_get_next_update_partition(NULL); - TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition); - ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address); - - esp_ota_handle_t update_handle = 0; - TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle)); - - copy_app_partition_with_offset(update_handle, cur_app_partition); - - TEST_ESP_OK(esp_ota_end(update_handle)); - TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition)); -} - -/* @brief Erase otadata partition - */ -static void erase_ota_data(void) -{ - const esp_partition_t *data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL); - TEST_ASSERT_NOT_EQUAL(NULL, data_partition); - TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * data_partition->erase_size)); -} - -/* @brief Reboots ESP using mode deep sleep. This mode guaranty that RTC_DATA_ATTR variables is not reset. - */ -static void reboot_as_deep_sleep(void) -{ - ESP_LOGI(TAG, "reboot as deep sleep"); - esp_deep_sleep(20000); - TEST_FAIL_MESSAGE("Should never be reachable except when sleep is rejected, abort"); -} - -/* @brief Copies a current app to next partition (OTA0-15), after that ESP is rebooting and run this (the next) OTAx. - */ -static void copy_current_app_to_next_part_and_reboot(void) -{ - const esp_partition_t *cur_app = esp_ota_get_running_partition(); - ESP_LOGI(TAG, "copy current app to next part"); - copy_current_app_to_next_part(cur_app, get_next_update_partition()); - reboot_as_deep_sleep(); -} - -/* @brief Copies a current app to next partition (OTA0-15) using esp_ota_write_with_offest(), after that ESP is rebooting and run this (the next) OTAx. - */ -static void copy_current_app_to_next_part_with_offset_and_reboot(void) -{ - const esp_partition_t *cur_app = esp_ota_get_running_partition(); - ESP_LOGI(TAG, "copy current app to next part"); - copy_current_app_to_next_part_with_offset(cur_app, get_next_update_partition()); - reboot_as_deep_sleep(); -} - -/* @brief Get running app. - * - * @return The next partition of OTA(OTA0-15). - */ -static const esp_partition_t* get_running_firmware(void) -{ - const esp_partition_t *configured = esp_ota_get_boot_partition(); - const esp_partition_t *running = esp_ota_get_running_partition(); - ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08"PRIx32")", - running->type, running->subtype, running->address); - ESP_LOGI(TAG, "Configured partition type %d subtype %d (offset 0x%08"PRIx32")", - configured->type, configured->subtype, configured->address); - TEST_ASSERT_NOT_EQUAL(NULL, configured); - TEST_ASSERT_NOT_EQUAL(NULL, running); - if (running->subtype != ESP_PARTITION_SUBTYPE_APP_TEST) { - TEST_ASSERT_EQUAL_PTR(running, configured); - } - return running; -} - -// type of a corrupt ota_data -typedef enum { - CORR_CRC_1_SECTOR_OTA_DATA = (1 << 0), /*!< Corrupt CRC only 1 sector of ota_data */ - CORR_CRC_2_SECTOR_OTA_DATA = (1 << 1), /*!< Corrupt CRC only 2 sector of ota_data */ -} corrupt_ota_data_t; - -/* @brief Get two copies ota_data from otadata partition. - * - * @param[in] otadata_partition - otadata partition. - * @param[out] ota_data_0 - First copy from otadata_partition. - * @param[out] ota_data_1 - Second copy from otadata_partition. - */ -static void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1) -{ - uint32_t offset = otadata_partition->address; - uint32_t size = otadata_partition->size; - if (offset != 0) { - const esp_ota_select_entry_t *ota_select_map; - ota_select_map = bootloader_mmap(offset, size); - TEST_ASSERT_NOT_EQUAL(NULL, ota_select_map); - - memcpy(ota_data_0, ota_select_map, sizeof(esp_ota_select_entry_t)); - memcpy(ota_data_1, (uint8_t *)ota_select_map + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t)); - bootloader_munmap(ota_select_map); - } -} - -/* @brief Writes a ota_data into required sector of otadata_partition. - * - * @param[in] otadata_partition - Partition information otadata. - * @param[in] ota_data - otadata structure. - * @param[in] sec_id - Sector number 0 or 1. - */ -static void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id) -{ - esp_partition_write(otadata_partition, otadata_partition->erase_size * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t)); -} - -/* @brief Makes a corrupt of ota_data. - * @param[in] err - type error - */ -static void corrupt_ota_data(corrupt_ota_data_t err) -{ - esp_ota_select_entry_t ota_data[2]; - - const esp_partition_t *otadata_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL); - TEST_ASSERT_NOT_EQUAL(NULL, otadata_partition); - get_ota_data(otadata_partition, &ota_data[0], &ota_data[1]); - - if (err & CORR_CRC_1_SECTOR_OTA_DATA) { - ota_data[0].crc = 0; - } - if (err & CORR_CRC_2_SECTOR_OTA_DATA) { - ota_data[1].crc = 0; - } - TEST_ESP_OK(esp_partition_erase_range(otadata_partition, 0, otadata_partition->size)); - write_ota_data(otadata_partition, &ota_data[0], 0); - write_ota_data(otadata_partition, &ota_data[1], 1); -} - -#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST) -/* @brief Sets the pin number to output and sets output level as low. After reboot (deep sleep) this pin keep the same level. - * - * The output level of the pad will be force locked and can not be changed. - * Power down or call gpio_hold_dis will disable this function. - * - * @param[in] num_pin - Pin number - */ -static void set_output_pin(uint32_t num_pin) -{ - TEST_ESP_OK(gpio_hold_dis(num_pin)); - - gpio_config_t io_conf; - io_conf.intr_type = GPIO_INTR_DISABLE; - io_conf.mode = GPIO_MODE_OUTPUT; - io_conf.pin_bit_mask = (1ULL << num_pin); - io_conf.pull_down_en = 0; - io_conf.pull_up_en = 0; - TEST_ESP_OK(gpio_config(&io_conf)); - - TEST_ESP_OK(gpio_set_level(num_pin, 0)); - TEST_ESP_OK(gpio_hold_en(num_pin)); -} - -/* @brief Unset the pin number hold function. - */ -static void reset_output_pin(uint32_t num_pin) -{ - TEST_ESP_OK(gpio_hold_dis(num_pin)); - TEST_ESP_OK(gpio_reset_pin(num_pin)); -} -#endif - -static void mark_app_valid(void) -{ -#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE - TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback()); -#endif -} - /* @brief Checks and prepares the partition so that the factory app is launched after that. */ static void start_test(void) @@ -546,20 +247,6 @@ static void test_flow5(void) TEST_CASE_MULTIPLE_STAGES("Switching between factory, test, factory", "[app_update][timeout=90][reset=SW_CPU_RESET, SW_CPU_RESET, DEEPSLEEP_RESET]", start_test, test_flow5, test_flow5, test_flow5); #endif -static const esp_partition_t* app_update(void) -{ - const esp_partition_t *cur_app = get_running_firmware(); - const esp_partition_t* update_partition = esp_ota_get_next_update_partition(NULL); - TEST_ASSERT_NOT_NULL(update_partition); - esp_ota_handle_t update_handle = 0; - TEST_ESP_OK(esp_ota_begin(update_partition, OTA_SIZE_UNKNOWN, &update_handle)); - copy_app_partition(update_handle, cur_app); - TEST_ESP_OK(esp_ota_end(update_handle)); - TEST_ESP_OK(esp_ota_set_boot_partition(update_partition)); - return update_partition; -} - - static void test_rollback1(void) { uint8_t boot_count = get_boot_count_from_nvs(); diff --git a/components/app_update/test_apps/test_app_update/main/utils_update.c b/components/app_update/test_apps/test_app_update/main/utils_update.c new file mode 100644 index 0000000000..29d12607ce --- /dev/null +++ b/components/app_update/test_apps/test_app_update/main/utils_update.c @@ -0,0 +1,307 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_rom_spiflash.h" +#include "driver/gpio.h" +#include "nvs_flash.h" +#include "esp_partition.h" +#include "esp_flash_partitions.h" +#include "esp_image_format.h" +#include "../bootloader_flash/include/bootloader_flash_priv.h" +#include "esp_sleep.h" +#include "esp_ota_ops.h" +#include "esp_err.h" +#include "esp_log.h" +#include "test_utils.h" +#include "utils_update.h" +#include "unity.h" +#include "sdkconfig.h" + +#define BOOT_COUNT_NAMESPACE "boot_count" + +static const char *TAG = "ota_test"; + + +void set_boot_count_in_nvs(uint8_t boot_count) +{ + nvs_handle_t boot_count_handle; + esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle); + if (err != ESP_OK) { + TEST_ESP_OK(nvs_flash_erase()); + TEST_ESP_OK(nvs_flash_init()); + TEST_ESP_OK(nvs_open(BOOT_COUNT_NAMESPACE, NVS_READWRITE, &boot_count_handle)); + } + TEST_ESP_OK(nvs_set_u8(boot_count_handle, "boot_count", boot_count)); + TEST_ESP_OK(nvs_commit(boot_count_handle)); + nvs_close(boot_count_handle); +} + +uint8_t get_boot_count_from_nvs(void) +{ + nvs_handle_t boot_count_handle; + esp_err_t err = nvs_open(BOOT_COUNT_NAMESPACE, NVS_READONLY, &boot_count_handle); + if (err == ESP_ERR_NVS_NOT_FOUND) { + set_boot_count_in_nvs(0); + } + uint8_t boot_count; + TEST_ESP_OK(nvs_get_u8(boot_count_handle, "boot_count", &boot_count)); + nvs_close(boot_count_handle); + return boot_count; +} + +/* @brief Copies a current app to next partition using handle. + * + * @param[in] update_handle - Handle of API ota. + * @param[in] cur_app - Current app. + */ +void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app) +{ + const void *partition_bin = NULL; + esp_partition_mmap_handle_t data_map; + ESP_LOGI(TAG, "start the copy process"); + TEST_ESP_OK(esp_partition_mmap(curr_app, 0, curr_app->size, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map)); + TEST_ESP_OK(esp_ota_write(update_handle, (const void *)partition_bin, curr_app->size)); + esp_partition_munmap(data_map); + ESP_LOGI(TAG, "finish the copy process"); +} + +/* @brief Copies a current app to next partition using handle. + * + * @param[in] update_handle - Handle of API ota. + * @param[in] cur_app - Current app. + */ +void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app) +{ + const void *partition_bin = NULL; + esp_partition_mmap_handle_t data_map; + ESP_LOGI(TAG, "start the copy process"); + uint32_t offset = 0, bytes_to_write = curr_app->size; + uint32_t write_bytes; + while (bytes_to_write > 0) { + write_bytes = (bytes_to_write > (4 * 1024)) ? (4 * 1024) : bytes_to_write; + TEST_ESP_OK(esp_partition_mmap(curr_app, offset, write_bytes, ESP_PARTITION_MMAP_DATA, &partition_bin, &data_map)); + TEST_ESP_OK(esp_ota_write_with_offset(update_handle, (const void *)partition_bin, write_bytes, offset)); + esp_partition_munmap(data_map); + bytes_to_write -= write_bytes; + offset += write_bytes; + } + ESP_LOGI(TAG, "finish the copy process"); +} + +/* @brief Get the next partition of OTA for the update. + * + * @return The next partition of OTA(OTA0-15). + */ +const esp_partition_t * get_next_update_partition(void) +{ + const esp_partition_t *update_partition = esp_ota_get_next_update_partition(NULL); + TEST_ASSERT_NOT_EQUAL(NULL, update_partition); + ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, update_partition->subtype, update_partition->address); + return update_partition; +} + +/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition. + * + * @param[in] cur_app_partition - Current app. + * @param[in] next_app_partition - Next app for boot. + */ +void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition) +{ + esp_ota_get_next_update_partition(NULL); + TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition); + ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address); + + esp_ota_handle_t update_handle = 0; + TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle)); + + copy_app_partition(update_handle, cur_app_partition); + + TEST_ESP_OK(esp_ota_end(update_handle)); + TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition)); +} + +/* @brief Copies a current app to next partition (OTA0-15) and then configure OTA data for a new boot partition. + * + * @param[in] cur_app_partition - Current app. + * @param[in] next_app_partition - Next app for boot. + */ +void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition) +{ + esp_ota_get_next_update_partition(NULL); + TEST_ASSERT_NOT_EQUAL(NULL, next_app_partition); + ESP_LOGI(TAG, "Writing to partition subtype %d at offset 0x%"PRIx32, next_app_partition->subtype, next_app_partition->address); + + esp_ota_handle_t update_handle = 0; + TEST_ESP_OK(esp_ota_begin(next_app_partition, OTA_SIZE_UNKNOWN, &update_handle)); + + copy_app_partition_with_offset(update_handle, cur_app_partition); + + TEST_ESP_OK(esp_ota_end(update_handle)); + TEST_ESP_OK(esp_ota_set_boot_partition(next_app_partition)); +} + +/* @brief Erase otadata partition + */ +void erase_ota_data(void) +{ + const esp_partition_t *data_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL); + TEST_ASSERT_NOT_EQUAL(NULL, data_partition); + TEST_ESP_OK(esp_partition_erase_range(data_partition, 0, 2 * data_partition->erase_size)); +} + +/* @brief Reboots ESP using mode deep sleep. This mode guaranty that RTC_DATA_ATTR variables is not reset. + */ +void reboot_as_deep_sleep(void) +{ + ESP_LOGI(TAG, "reboot as deep sleep"); + esp_deep_sleep(20000); + TEST_FAIL_MESSAGE("Should never be reachable except when sleep is rejected, abort"); +} + +/* @brief Copies a current app to next partition (OTA0-15), after that ESP is rebooting and run this (the next) OTAx. + */ +void copy_current_app_to_next_part_and_reboot(void) +{ + const esp_partition_t *cur_app = esp_ota_get_running_partition(); + ESP_LOGI(TAG, "copy current app to next part"); + copy_current_app_to_next_part(cur_app, get_next_update_partition()); + reboot_as_deep_sleep(); +} + +/* @brief Copies a current app to next partition (OTA0-15) using esp_ota_write_with_offest(), after that ESP is rebooting and run this (the next) OTAx. + */ +void copy_current_app_to_next_part_with_offset_and_reboot(void) +{ + const esp_partition_t *cur_app = esp_ota_get_running_partition(); + ESP_LOGI(TAG, "copy current app to next part"); + copy_current_app_to_next_part_with_offset(cur_app, get_next_update_partition()); + reboot_as_deep_sleep(); +} + +/* @brief Get running app. + * + * @return The next partition of OTA(OTA0-15). + */ +const esp_partition_t* get_running_firmware(void) +{ + const esp_partition_t *configured = esp_ota_get_boot_partition(); + const esp_partition_t *running = esp_ota_get_running_partition(); + // If a reboot hasn't occurred after app_update(), the configured and running partitions may differ + ESP_LOGI(TAG, "Running partition type %d subtype %d (offset 0x%08"PRIx32")", + running->type, running->subtype, running->address); + ESP_LOGI(TAG, "Configured partition type %d subtype %d (offset 0x%08"PRIx32")", + configured->type, configured->subtype, configured->address); + TEST_ASSERT_NOT_EQUAL(NULL, configured); + TEST_ASSERT_NOT_EQUAL(NULL, running); + return running; +} + +/* @brief Get two copies ota_data from otadata partition. + * + * @param[in] otadata_partition - otadata partition. + * @param[out] ota_data_0 - First copy from otadata_partition. + * @param[out] ota_data_1 - Second copy from otadata_partition. + */ +void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1) +{ + uint32_t offset = otadata_partition->address; + uint32_t size = otadata_partition->size; + if (offset != 0) { + const esp_ota_select_entry_t *ota_select_map; + ota_select_map = bootloader_mmap(offset, size); + TEST_ASSERT_NOT_EQUAL(NULL, ota_select_map); + + memcpy(ota_data_0, ota_select_map, sizeof(esp_ota_select_entry_t)); + memcpy(ota_data_1, (uint8_t *)ota_select_map + otadata_partition->erase_size, sizeof(esp_ota_select_entry_t)); + bootloader_munmap(ota_select_map); + } +} + +/* @brief Writes a ota_data into required sector of otadata_partition. + * + * @param[in] otadata_partition - Partition information otadata. + * @param[in] ota_data - otadata structure. + * @param[in] sec_id - Sector number 0 or 1. + */ +void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id) +{ + esp_partition_write(otadata_partition, otadata_partition->erase_size * sec_id, &ota_data[sec_id], sizeof(esp_ota_select_entry_t)); +} + +/* @brief Makes a corrupt of ota_data. + * @param[in] err - type error + */ +void corrupt_ota_data(corrupt_ota_data_t err) +{ + esp_ota_select_entry_t ota_data[2]; + + const esp_partition_t *otadata_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_OTA, NULL); + TEST_ASSERT_NOT_EQUAL(NULL, otadata_partition); + get_ota_data(otadata_partition, &ota_data[0], &ota_data[1]); + + if (err & CORR_CRC_1_SECTOR_OTA_DATA) { + ota_data[0].crc = 0; + } + if (err & CORR_CRC_2_SECTOR_OTA_DATA) { + ota_data[1].crc = 0; + } + TEST_ESP_OK(esp_partition_erase_range(otadata_partition, 0, otadata_partition->size)); + write_ota_data(otadata_partition, &ota_data[0], 0); + write_ota_data(otadata_partition, &ota_data[1], 1); +} + +#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST) +/* @brief Sets the pin number to output and sets output level as low. After reboot (deep sleep) this pin keep the same level. + * + * The output level of the pad will be force locked and can not be changed. + * Power down or call gpio_hold_dis will disable this function. + * + * @param[in] num_pin - Pin number + */ +void set_output_pin(uint32_t num_pin) +{ + TEST_ESP_OK(gpio_hold_dis(num_pin)); + + gpio_config_t io_conf; + io_conf.intr_type = GPIO_INTR_DISABLE; + io_conf.mode = GPIO_MODE_OUTPUT; + io_conf.pin_bit_mask = (1ULL << num_pin); + io_conf.pull_down_en = 0; + io_conf.pull_up_en = 0; + TEST_ESP_OK(gpio_config(&io_conf)); + + TEST_ESP_OK(gpio_set_level(num_pin, 0)); + TEST_ESP_OK(gpio_hold_en(num_pin)); +} + +/* @brief Unset the pin number hold function. + */ +void reset_output_pin(uint32_t num_pin) +{ + TEST_ESP_OK(gpio_hold_dis(num_pin)); + TEST_ESP_OK(gpio_reset_pin(num_pin)); +} +#endif + +void mark_app_valid(void) +{ +#ifdef CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE + TEST_ESP_OK(esp_ota_mark_app_valid_cancel_rollback()); +#endif +} + +const esp_partition_t* app_update(void) +{ + const esp_partition_t *cur_app = get_running_firmware(); + const esp_partition_t* update_partition = esp_ota_get_next_update_partition(NULL); + TEST_ASSERT_NOT_NULL(update_partition); + esp_ota_handle_t update_handle = 0; + TEST_ESP_OK(esp_ota_begin(update_partition, OTA_SIZE_UNKNOWN, &update_handle)); + copy_app_partition(update_handle, cur_app); + TEST_ESP_OK(esp_ota_end(update_handle)); + TEST_ESP_OK(esp_ota_set_boot_partition(update_partition)); + return update_partition; +} diff --git a/components/app_update/test_apps/test_app_update/main/utils_update.h b/components/app_update/test_apps/test_app_update/main/utils_update.h new file mode 100644 index 0000000000..05efd2df18 --- /dev/null +++ b/components/app_update/test_apps/test_app_update/main/utils_update.h @@ -0,0 +1,148 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include +#include "esp_ota_ops.h" +#include "esp_partition.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + * @brief Enumeration for specifying which OTA data sectors' CRCs to corrupt. + */ +typedef enum { + CORR_CRC_1_SECTOR_OTA_DATA = (1 << 0), /*!< Corrupt CRC only 1 sector of ota_data */ + CORR_CRC_2_SECTOR_OTA_DATA = (1 << 1), /*!< Corrupt CRC only 2 sector of ota_data */ +} corrupt_ota_data_t; + +/** + * @brief Set boot count value in NVS. + * @param boot_count Value to set. + */ +void set_boot_count_in_nvs(uint8_t boot_count); + +/** + * @brief Get boot count value from NVS. + * @return Boot count value. + */ +uint8_t get_boot_count_from_nvs(void); + +/** + * @brief Copy current app to next partition using OTA handle. + * @param update_handle OTA update handle. + * @param curr_app Current app partition. + */ +void copy_app_partition(esp_ota_handle_t update_handle, const esp_partition_t *curr_app); + +/** + * @brief Copy current app to next partition using OTA handle with offset. + * @param update_handle OTA update handle. + * @param curr_app Current app partition. + */ +void copy_app_partition_with_offset(esp_ota_handle_t update_handle, const esp_partition_t *curr_app); + +/** + * @brief Get the next OTA update partition. + * @return Pointer to next OTA partition. + */ +const esp_partition_t * get_next_update_partition(void); + +/** + * @brief Copy current app to next partition and set boot partition. + * @param cur_app_partition Current app partition. + * @param next_app_partition Next app partition. + */ +void copy_current_app_to_next_part(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition); + +/** + * @brief Copy current app to next partition with offset and set boot partition. + * @param cur_app_partition Current app partition. + * @param next_app_partition Next app partition. + */ +void copy_current_app_to_next_part_with_offset(const esp_partition_t *cur_app_partition, const esp_partition_t *next_app_partition); + +/** + * @brief Erase OTA data partition. + */ +void erase_ota_data(void); + +/** + * @brief Reboot ESP using deep sleep mode. + */ +void reboot_as_deep_sleep(void); + +/** + * @brief Copy current app to next partition and reboot. + */ +void copy_current_app_to_next_part_and_reboot(void); + +/** + * @brief Copy current app to next partition with offset and reboot. + */ +void copy_current_app_to_next_part_with_offset_and_reboot(void); + +/** + * @brief Get running firmware partition. + * @return Pointer to running firmware partition. + */ +const esp_partition_t* get_running_firmware(void); + +/** + * @brief Get two OTA data copies from OTA data partition. + * @param otadata_partition OTA data partition. + * @param ota_data_0 First OTA data copy. + * @param ota_data_1 Second OTA data copy. + */ +void get_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data_0, esp_ota_select_entry_t *ota_data_1); + +/** + * @brief Write OTA data into required sector of OTA data partition. + * @param otadata_partition OTA data partition. + * @param ota_data OTA data structure. + * @param sec_id Sector number (0 or 1). + */ +void write_ota_data(const esp_partition_t *otadata_partition, esp_ota_select_entry_t *ota_data, int sec_id); + +/** + * @brief Corrupt OTA data for testing. + * @param err Type of corruption. + */ +void corrupt_ota_data(corrupt_ota_data_t err); + +#if defined(CONFIG_BOOTLOADER_FACTORY_RESET) || defined(CONFIG_BOOTLOADER_APP_TEST) +/** + * @brief Set output pin to low and hold state. + * @param num_pin Pin number. + */ +void set_output_pin(uint32_t num_pin); + +/** + * @brief Reset output pin hold function. + * @param num_pin Pin number. + */ +void reset_output_pin(uint32_t num_pin); +#endif + +/** + * @brief Mark app as valid and cancel rollback. + */ +void mark_app_valid(void); + +/** + * @brief Perform app update and set new boot partition. + * @return Pointer to updated partition. + */ +const esp_partition_t* app_update(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py b/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py index a461072dcb..8e7c634241 100644 --- a/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py +++ b/components/app_update/test_apps/test_app_update/pytest_app_update_ut.py @@ -60,3 +60,18 @@ def test_app_update_xip_psram_rom_impl(dut: Dut) -> None: @idf_parametrize('target', ['esp32', 'esp32c3', 'esp32s3', 'esp32p4'], indirect=['target']) def test_app_update_with_rollback(dut: Dut) -> None: dut.run_all_single_board_cases(timeout=90) + + +@pytest.mark.recovery_bootloader +@pytest.mark.parametrize( + 'config', + ['recovery_bootloader'], + indirect=True, +) +@idf_parametrize('target', ['esp32c5'], indirect=['target']) +def test_recovery_bootloader_update(dut: Dut) -> None: + try: + dut.run_all_single_board_cases(group='recovery_bootloader', timeout=90) + finally: + # Erase recovery bootloader after test because it may interfere with other tests using this runner + dut.serial.erase_flash() diff --git a/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader new file mode 100644 index 0000000000..457356ac57 --- /dev/null +++ b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader @@ -0,0 +1,3 @@ +CONFIG_BOOTLOADER_RECOVERY_ENABLE=y +CONFIG_BOOTLOADER_RECOVERY_OFFSET=0x3F0000 +CONFIG_PARTITION_TABLE_OFFSET=0x9000 diff --git a/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c5 b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c5 new file mode 100644 index 0000000000..1e9b4e16a8 --- /dev/null +++ b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c5 @@ -0,0 +1,2 @@ +# ESP32C5 supports the Recovery bootloader feature in ROM starting from v1.0 (ECO2) +CONFIG_IDF_TARGET="esp32c5" diff --git a/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c61 b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c61 new file mode 100644 index 0000000000..c40bd234eb --- /dev/null +++ b/components/app_update/test_apps/test_app_update/sdkconfig.ci.recovery_bootloader.esp32c61 @@ -0,0 +1,2 @@ +# ESP32C61 supports the Recovery bootloader feature in ROM starting from v1.0 (ECO3) +CONFIG_IDF_TARGET="esp32c61" diff --git a/components/bootloader/Kconfig.bootloader_rollback b/components/bootloader/Kconfig.bootloader_rollback index f8c74dae15..7a905cbf92 100644 --- a/components/bootloader/Kconfig.bootloader_rollback +++ b/components/bootloader/Kconfig.bootloader_rollback @@ -1,8 +1,37 @@ -menu "Bootloader Rollback" +menu "Recovery Bootloader and Rollback" + + config BOOTLOADER_RECOVERY_ENABLE + bool "Enable Recovery Bootloader" + depends on SOC_RECOVERY_BOOTLOADER_SUPPORTED + default n + help + The recovery bootloader feature is implemented in the ROM bootloader. It is required for safe OTA + updates of the bootloader. The feature is activated when the eFuse field + (ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR) is set, which defines the flash address of the + recovery bootloader. If activated and the primary bootloader fails to load, the ROM bootloader + will attempt to load the recovery bootloader from the address specified in eFuse. + + config BOOTLOADER_RECOVERY_OFFSET + hex "Recovery Bootloader Flash Offset" + depends on BOOTLOADER_RECOVERY_ENABLE + default 0x3F0000 + range 0x0 0xFFE000 + help + Flash address where the recovery bootloader is stored. + This value must be written to the eFuse field (ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR) + to activate the recovery bootloader in the ROM bootloader. The eFuse can be programmed + using espefuse.py or in the user application with the API esp_efuse_set_recovery_bootloader_offset(). + Setting this value in the config allows parttool.py to verify that it does not overlap with existing + partitions in the partition table. + + The address must be a multiple of the flash sector size (0x1000 bytes). + The eFuse field stores the offset in sectors. + If the feature is no longer needed or unused, you can burn the 0xFFF value to disable this feature in + the ROM bootloader. config BOOTLOADER_ANTI_ROLLBACK_ENABLE bool "Enable bootloader rollback support" - depends on SOC_RECOVERY_BOOTLOADER_SUPPORTED + depends on BOOTLOADER_RECOVERY_ENABLE default n help This option prevents rollback to previous bootloader image with lower security version. diff --git a/components/bootloader_support/src/bootloader_init.c b/components/bootloader_support/src/bootloader_init.c index bff1b922dc..0e8dcd7621 100644 --- a/components/bootloader_support/src/bootloader_init.c +++ b/components/bootloader_support/src/bootloader_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,6 +19,7 @@ #include "hal/wdt_hal.h" #include "hal/efuse_hal.h" #include "esp_bootloader_desc.h" +#include "esp_rom_sys.h" static const char *TAG = "boot"; @@ -34,7 +35,12 @@ void bootloader_clear_bss_section(void) esp_err_t bootloader_read_bootloader_header(void) { /* load bootloader image header */ - if (bootloader_flash_read(ESP_BOOTLOADER_OFFSET, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) { +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED + const uint32_t bootloader_flash_offset = esp_rom_get_bootloader_offset(); +#else + const uint32_t bootloader_flash_offset = ESP_PRIMARY_BOOTLOADER_OFFSET; +#endif + if (bootloader_flash_read(bootloader_flash_offset, &bootloader_image_hdr, sizeof(esp_image_header_t), true) != ESP_OK) { ESP_EARLY_LOGE(TAG, "failed to load bootloader image header!"); return ESP_FAIL; } diff --git a/components/bootloader_support/src/bootloader_mem.c b/components/bootloader_support/src/bootloader_mem.c index b8dbd700d6..6ae07f70e6 100644 --- a/components/bootloader_support/src/bootloader_mem.c +++ b/components/bootloader_support/src/bootloader_mem.c @@ -25,20 +25,19 @@ void bootloader_init_mem(void) * So, at boot disabling these filters. They will enable as per the * use case by TEE initialization code. */ -#ifdef SOC_APM_CTRL_FILTER_SUPPORTED - apm_hal_apm_ctrl_filter_enable_all(false); - /* [APM] On power-up, only the HP CPU starts in TEE mode; others default to REE2. - * APM blocks REE0–REE2 access by default. C5 ECO2 adds per-peripheral control - * (default REEx blocking), but config support is pending. As a workaround, - * all masters are set to TEE mode. +#if SOC_APM_CTRL_FILTER_SUPPORTED + apm_hal_enable_ctrl_filter_all(false); + /* [APM] On power-up, only the HP CPU starts in TEE mode; others + * default to REE2. APM blocks REE0–REE2 access by default. + * Thus, all masters are set to TEE mode. */ #if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL - apm_tee_hal_set_master_secure_mode_all(APM_LL_SECURE_MODE_TEE); + apm_hal_set_master_sec_mode_all(APM_SEC_MODE_TEE); #endif // SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL #endif // SOC_APM_CTRL_FILTER_SUPPORTED #endif -#ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE +#if CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE // protect memory region esp_cpu_configure_region_protection(); #endif diff --git a/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c index bc1aa83e37..7ccb0ef4e7 100644 --- a/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c +++ b/components/bootloader_support/src/esp32c5/flash_encryption_secure_features.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -71,12 +71,9 @@ esp_err_t esp_flash_encryption_enable_secure_features(void) esp_err_t esp_flash_encryption_enable_key_mgr(void) { - // Enable and reset key manager - // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV - int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); - key_mgr_ll_enable_bus_clock(true); - key_mgr_ll_enable_peripheral_clock(true); - key_mgr_ll_reset_register(); + _key_mgr_ll_enable_bus_clock(true); + _key_mgr_ll_enable_peripheral_clock(true); + _key_mgr_ll_reset_register(); while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) { }; diff --git a/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c index 57cdd84b31..264188e0c2 100644 --- a/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c +++ b/components/bootloader_support/src/esp32p4/flash_encryption_secure_features.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -53,12 +53,9 @@ esp_err_t esp_flash_encryption_enable_secure_features(void) esp_err_t esp_flash_encryption_enable_key_mgr(void) { - // Enable and reset key manager - // To suppress build errors about spinlock's __DECLARE_RCC_ATOMIC_ENV - int __DECLARE_RCC_ATOMIC_ENV __attribute__ ((unused)); - key_mgr_ll_enable_bus_clock(true); - key_mgr_ll_enable_peripheral_clock(true); - key_mgr_ll_reset_register(); + _key_mgr_ll_enable_bus_clock(true); + _key_mgr_ll_enable_peripheral_clock(true); + _key_mgr_ll_reset_register(); while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) { }; diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c index d0644cdcb3..a4f415c1e5 100644 --- a/components/bootloader_support/src/esp_image_format.c +++ b/components/bootloader_support/src/esp_image_format.c @@ -23,6 +23,7 @@ #include "soc/soc_caps.h" #include "hal/cache_ll.h" #include "spi_flash_mmap.h" +#include "hal/efuse_hal.h" #define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) @@ -119,11 +120,26 @@ void esp_image_bootloader_offset_set(const uint32_t offset) { s_bootloader_partition_offset = offset; ESP_LOGI(TAG, "Bootloader offsets for PRIMARY: 0x%x, Secondary: 0x%" PRIx32, ESP_PRIMARY_BOOTLOADER_OFFSET, s_bootloader_partition_offset); +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED + uint32_t recovery_offset = efuse_hal_get_recovery_bootloader_address(); + if (efuse_hal_recovery_bootloader_enabled()) { + ESP_LOGI(TAG, "Bootloader offset for RECOVERY: 0x%" PRIx32, recovery_offset); + } else if (recovery_offset == 0) { + ESP_LOGI(TAG, "Bootloader offset for RECOVERY: has not been set yet"); + } else { + ESP_LOGI(TAG, "Bootloader offset for RECOVERY: is disabled"); + } +#endif } static bool is_bootloader(uint32_t offset) { - return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET) || (offset == s_bootloader_partition_offset)); + return ((offset == ESP_PRIMARY_BOOTLOADER_OFFSET) + || (offset == s_bootloader_partition_offset) +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED + || (efuse_hal_recovery_bootloader_enabled() ? offset == efuse_hal_get_recovery_bootloader_address() : false) +#endif + ); } static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_t *part, esp_image_metadata_t *data) diff --git a/components/driver/deprecated/adc_dma_legacy.c b/components/driver/deprecated/adc_dma_legacy.c index 9c7800e0fc..5e135ca53d 100644 --- a/components/driver/deprecated/adc_dma_legacy.c +++ b/components/driver/deprecated/adc_dma_legacy.c @@ -480,7 +480,7 @@ esp_err_t adc_digi_start(void) adc_hal_digi_init(&s_adc_digi_ctx->hal); #if !CONFIG_IDF_TARGET_ESP32 - esp_clk_tree_enable_src((soc_module_clk_t)(s_adc_digi_ctx->hal_digi_ctrlr_cfg.clk_src), true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(s_adc_digi_ctx->hal_digi_ctrlr_cfg.clk_src), true)); #endif adc_hal_digi_controller_config(&s_adc_digi_ctx->hal, &s_adc_digi_ctx->hal_digi_ctrlr_cfg); @@ -524,6 +524,7 @@ esp_err_t adc_digi_stop(void) if (s_adc_digi_ctx->use_adc1) { adc_lock_release(ADC_UNIT_1); } + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(s_adc_digi_ctx->hal_digi_ctrlr_cfg.clk_src), false)); sar_periph_ctrl_adc_continuous_power_release(); return ESP_OK; diff --git a/components/driver/deprecated/adc_legacy.c b/components/driver/deprecated/adc_legacy.c index 2cbbcf083b..e331e0c30e 100644 --- a/components/driver/deprecated/adc_legacy.c +++ b/components/driver/deprecated/adc_legacy.c @@ -756,7 +756,7 @@ int adc1_get_raw(adc1_channel_t channel) adc_apb_periph_claim(); sar_periph_ctrl_adc_oneshot_power_acquire(); - esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true)); adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT); adc_atten_t atten = s_atten1_single[channel]; @@ -775,6 +775,7 @@ int adc1_get_raw(adc1_channel_t channel) adc_hal_convert(ADC_UNIT_1, channel, clk_src_freq_hz, &raw_out); ADC_REG_LOCK_EXIT(); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, false)); sar_periph_ctrl_adc_oneshot_power_release(); adc_apb_periph_free(); adc_lock_release(ADC_UNIT_1); @@ -820,7 +821,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * adc_apb_periph_claim(); sar_periph_ctrl_adc_oneshot_power_acquire(); - esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, true)); adc_ll_digi_clk_sel(ADC_DIGI_CLK_SRC_DEFAULT); #if SOC_ADC_ARBITER_SUPPORTED @@ -838,6 +839,7 @@ esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int * ret = adc_hal_convert(ADC_UNIT_2, channel, clk_src_freq_hz, raw_out); ADC_REG_LOCK_EXIT(); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)ADC_DIGI_CLK_SRC_DEFAULT, false)); sar_periph_ctrl_adc_oneshot_power_release(); adc_apb_periph_free(); adc_lock_release(ADC_UNIT_2); diff --git a/components/driver/deprecated/mcpwm_legacy.c b/components/driver/deprecated/mcpwm_legacy.c index 94723decdd..9be6b29518 100644 --- a/components/driver/deprecated/mcpwm_legacy.c +++ b/components/driver/deprecated/mcpwm_legacy.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -470,7 +470,7 @@ esp_err_t mcpwm_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpw uint32_t group_pre_scale = clk_src_hz / group_resolution; uint32_t timer_pre_scale = group_resolution / timer_resolution; - esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true)); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT); mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale); @@ -868,7 +868,7 @@ esp_err_t mcpwm_capture_enable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_cha uint32_t group_resolution = mcpwm_group_get_resolution(mcpwm_num); uint32_t group_pre_scale = clk_src_hz / group_resolution; - esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true)); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(mcpwm_num, (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT); mcpwm_ll_group_set_clock_prescale(mcpwm_num, group_pre_scale); @@ -910,6 +910,7 @@ esp_err_t mcpwm_capture_disable_channel(mcpwm_unit_t mcpwm_num, mcpwm_capture_ch mcpwm_ll_capture_enable_channel(hal->dev, cap_channel, false); mcpwm_ll_intr_enable(hal->dev, MCPWM_LL_EVENT_CAPTURE(cap_channel), false); mcpwm_critical_exit(mcpwm_num); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, false)); mcpwm_mutex_lock(mcpwm_num); context[mcpwm_num].cap_isr_func[cap_channel].fn = NULL; diff --git a/components/driver/deprecated/rmt_legacy.c b/components/driver/deprecated/rmt_legacy.c index baff30aa46..254aa46c06 100644 --- a/components/driver/deprecated/rmt_legacy.c +++ b/components/driver/deprecated/rmt_legacy.c @@ -440,7 +440,7 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk) { ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); - esp_clk_tree_enable_src((soc_module_clk_t)base_clk, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)base_clk, true)); // `rmt_clock_source_t` and `rmt_source_clk_t` are binary compatible, as the underlying enum entries come from the same `soc_module_clk_t` RMT_CLOCK_SRC_ATOMIC() { rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, (rmt_clock_source_t)base_clk, 1, 0, 0); @@ -606,7 +606,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #endif } esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &rmt_source_clk_hz); - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); RMT_CLOCK_SRC_ATOMIC() { rmt_ll_set_group_clock_src(dev, channel, clk_src, 1, 0, 0); rmt_ll_enable_group_clock(dev, true); diff --git a/components/driver/deprecated/timer_legacy.c b/components/driver/deprecated/timer_legacy.c index 27c446836b..48c8aeb725 100644 --- a/components/driver/deprecated/timer_legacy.c +++ b/components/driver/deprecated/timer_legacy.c @@ -328,7 +328,7 @@ esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer if (config->clk_src) { clk_src = config->clk_src; } - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); GPTIMER_CLOCK_SRC_ATOMIC() { // although `clk_src` is of `timer_src_clk_t` type, but it's binary compatible with `gptimer_clock_source_t`, // as the underlying enum entries come from the same `soc_module_clk_t` @@ -364,6 +364,7 @@ esp_err_t timer_deinit(timer_group_t group_num, timer_idx_t timer_num) GPTIMER_CLOCK_SRC_ATOMIC() { timer_ll_enable_clock(group_num, hal->timer_id, false); } + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)p_timer_obj[group_num][timer_num]->clk_src, false)); TIMER_ENTER_CRITICAL(&timer_spinlock[group_num]); timer_ll_enable_intr(hal->dev, TIMER_LL_EVENT_ALARM(timer_num), false); timer_ll_clear_intr_status(hal->dev, TIMER_LL_EVENT_ALARM(timer_num)); diff --git a/components/efuse/esp32c5/esp_efuse_table.c b/components/efuse/esp32c5/esp_efuse_table.c index 5b1b0dc9da..2986775f3b 100644 --- a/components/efuse/esp32c5/esp_efuse_table.c +++ b/components/efuse/esp32c5/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 0c453d200f282e320677c1ac46786658 +// md5_digest_table a89a21bde56c3936f31af16ba1de1fe3 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -599,10 +599,6 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { {EFUSE_BLK0, 116, 2}, // [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode.0: Security level is SEC\_DPA\_OFF1: Security level is SEC\_DPA\_LOW2: Security level is SEC\_DPA\_MIDDLE3: Security level is SEC\_DPA\_HIGHFor more information; please refer to Chapter \ref{mod:sysreg} \textit{\nameref{mod:sysreg}} > Section \ref{sec:sysreg-anti-dpa-attack-security-control} \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}., }; -static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[] = { - {EFUSE_BLK0, 118, 3}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field), -}; - static const esp_efuse_desc_t SECURE_BOOT_EN[] = { {EFUSE_BLK0, 121, 1}, // [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled, }; @@ -691,8 +687,9 @@ static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { {EFUSE_BLK0, 173, 1}, // [] Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force1: Force, }; -static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[] = { - {EFUSE_BLK0, 174, 9}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field), +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + {EFUSE_BLK0, 174, 9}, // [] Low 9 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled., + {EFUSE_BLK0, 118, 3}, // [] High 3 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled., }; static const esp_efuse_desc_t MAC[] = { @@ -1642,11 +1639,6 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[] = { - &RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field) - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { &SECURE_BOOT_EN[0], // [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled NULL @@ -1757,8 +1749,9 @@ const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[] = { - &RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field) +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR[0], // [] Low 9 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. + &RECOVERY_BOOTLOADER_FLASH_SECTOR[1], // [] High 3 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. NULL }; diff --git a/components/efuse/esp32c5/esp_efuse_table.csv b/components/efuse/esp32c5/esp_efuse_table.csv index 4c0ca2eda9..bb8065a4e7 100644 --- a/components/efuse/esp32c5/esp_efuse_table.csv +++ b/components/efuse/esp32c5/esp_efuse_table.csv @@ -157,7 +157,6 @@ KEY_PURPOSE_3, EFUSE_BLK0, 101, 5, [KEY3_PUR KEY_PURPOSE_4, EFUSE_BLK0, 106, 5, [KEY4_PURPOSE] Represents the purpose of Key4. See Table \ref{tab:efuse-key-purpose} KEY_PURPOSE_5, EFUSE_BLK0, 111, 5, [KEY5_PURPOSE] Represents the purpose of Key5. See Table \ref{tab:efuse-key-purpose} SEC_DPA_LEVEL, EFUSE_BLK0, 116, 2, [] Represents the security level of anti-DPA attack. The level is adjusted by configuring the clock random frequency division mode.0: Security level is SEC\_DPA\_OFF1: Security level is SEC\_DPA\_LOW2: Security level is SEC\_DPA\_MIDDLE3: Security level is SEC\_DPA\_HIGHFor more information; please refer to Chapter \ref{mod:sysreg} \textit{\nameref{mod:sysreg}} > Section \ref{sec:sysreg-anti-dpa-attack-security-control} \textit{\nameref{sec:sysreg-anti-dpa-attack-security-control}}. -RECOVERY_BOOTLOADER_FLASH_SECTOR_HI, EFUSE_BLK0, 118, 3, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The high part of the field) SECURE_BOOT_EN, EFUSE_BLK0, 121, 1, [] Represents whether Secure Boot is enabled.1: Enabled0: Disabled SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 122, 1, [] Represents whether aggressive revocation of Secure Boot is enabled.1: Enabled0: Disabled KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 123, 1, [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key @@ -180,7 +179,8 @@ HUK_GEN_STATE, EFUSE_BLK0, 160, 9, [] Repres XTAL_48M_SEL, EFUSE_BLK0, 169, 3, [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL XTAL_48M_SEL_MODE, EFUSE_BLK0, 172, 1, [] Represents what determines the XTAL frequency in \textbf{Joint Download Boot} mode. For more information; please refer to Chapter \ref{mod:bootctrl} \textit{\nameref{mod:bootctrl}}.0: Strapping PAD state1: \hyperref[fielddesc:EFUSEXTAL48MSEL]{EFUSE\_XTAL\_48M\_SEL} in eFuse ECC_FORCE_CONST_TIME, EFUSE_BLK0, 173, 1, [] Represents whether to force ECC to use constant-time mode for point multiplication calculation. 0: Not force1: Force -RECOVERY_BOOTLOADER_FLASH_SECTOR_LO, EFUSE_BLK0, 174, 9, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. (The low part of the field) +RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 174, 9, [] Low 9 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. +, EFUSE_BLK0, 118, 3, [] High 3 bits. Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled. MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address diff --git a/components/efuse/esp32c5/include/esp_efuse_table.h b/components/efuse/esp32c5/include/esp_efuse_table.h index a52f8beef9..b736956047 100644 --- a/components/efuse/esp32c5/include/esp_efuse_table.h +++ b/components/efuse/esp32c5/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 0c453d200f282e320677c1ac46786658 +// md5_digest_table a89a21bde56c3936f31af16ba1de1fe3 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -193,7 +193,6 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; #define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5 extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_HI[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[]; @@ -216,7 +215,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_XTAL_48M_SEL_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[]; diff --git a/components/efuse/esp32c61/esp_efuse_table.c b/components/efuse/esp32c61/esp_efuse_table.c index 4ff8c7c62f..1130f42b5a 100644 --- a/components/efuse/esp32c61/esp_efuse_table.c +++ b/components/efuse/esp32c61/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table af9aaa79feb0970d90f35360a5113f03 +// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -231,6 +231,34 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; +static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP, +}; + static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; @@ -368,43 +396,43 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_SYS_DATA2[] = { }; static const esp_efuse_desc_t DIS_ICACHE[] = { - {EFUSE_BLK0, 39, 1}, // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 39, 1}, // [] Represents whether cache is disabled. 1: Disabled 0: Enabled., }; static const esp_efuse_desc_t DIS_USB_JTAG[] = { - {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 40, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { - {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 42, 1}, // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t SPI_DOWNLOAD_MSPI_DIS[] = { - {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 43, 1}, // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled, }; static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { - {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled, + {EFUSE_BLK0, 44, 1}, // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled, }; static const esp_efuse_desc_t DIS_PAD_JTAG[] = { - {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 45, 1}, // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled, }; static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled, + {EFUSE_BLK0, 46, 1}, // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled, }; static const esp_efuse_desc_t USB_EXCHG_PINS[] = { - {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged, + {EFUSE_BLK0, 51, 1}, // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged, }; static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { - {EFUSE_BLK0, 52, 1}, // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned, + {EFUSE_BLK0, 52, 1}, // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 53, 2}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16, + {EFUSE_BLK0, 53, 2}, // [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)), }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { @@ -452,11 +480,11 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { }; static const esp_efuse_desc_t SECURE_BOOT_EN[] = { - {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled, + {EFUSE_BLK0, 90, 1}, // [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable, }; static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled, + {EFUSE_BLK0, 91, 1}, // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable, }; static const esp_efuse_desc_t FLASH_TPUW[] = { @@ -464,23 +492,23 @@ static const esp_efuse_desc_t FLASH_TPUW[] = { }; static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 96, 1}, // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_DIRECT_BOOT[] = { - {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 97, 1}, // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - {EFUSE_BLK0, 98, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable, + {EFUSE_BLK0, 98, 1}, // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable, }; static const esp_efuse_desc_t DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable, + {EFUSE_BLK0, 99, 1}, // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable, }; static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { - {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable, + {EFUSE_BLK0, 100, 1}, // [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable, }; static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { @@ -500,27 +528,47 @@ static const esp_efuse_desc_t SECURE_BOOT_DISABLE_FAST_WAKE[] = { }; static const esp_efuse_desc_t HYS_EN_PAD[] = { - {EFUSE_BLK0, 121, 1}, // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled, + {EFUSE_BLK0, 121, 1}, // [] Set bits to enable hysteresis function of PAD0~27, }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 122, 1}, // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable, + {EFUSE_BLK0, 122, 1}, // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable., }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { - {EFUSE_BLK0, 123, 2}, // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration, + {EFUSE_BLK0, 123, 2}, // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled, }; static const esp_efuse_desc_t DIS_WIFI6[] = { - {EFUSE_BLK0, 125, 1}, // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled., + {EFUSE_BLK0, 125, 1}, // [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled, }; static const esp_efuse_desc_t ECDSA_DISABLE_P192[] = { - {EFUSE_BLK0, 126, 1}, // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable, + {EFUSE_BLK0, 126, 1}, // [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled, }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 127, 1}, // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable, + {EFUSE_BLK0, 127, 1}, // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { + {EFUSE_BLK0, 128, 4}, // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = { + {EFUSE_BLK0, 132, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled, +}; + +static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { + {EFUSE_BLK0, 133, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable, +}; + +static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + {EFUSE_BLK0, 134, 12}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, +}; + +static const esp_efuse_desc_t REPEAT_DATA4[] = { + {EFUSE_BLK0, 160, 24}, // [] Reserved, }; static const esp_efuse_desc_t MAC[] = { @@ -580,6 +628,34 @@ static const esp_efuse_desc_t PKG_VERSION[] = { {EFUSE_BLK1, 90, 3}, // [] Package version, }; +static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK1, 93, 4}, // [] Active HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK1, 97, 4}, // [] Active LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBG[] = { + {EFUSE_BLK1, 101, 2}, // [] LSLP HP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBIAS[] = { + {EFUSE_BLK1, 103, 4}, // [] LSLP HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBG[] = { + {EFUSE_BLK1, 107, 4}, // [] DSLP LP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBIAS[] = { + {EFUSE_BLK1, 111, 5}, // [] DSLP LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK1, 116, 5}, // [] DBIAS gap between LP and HP, +}; + static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; @@ -950,6 +1026,41 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { + &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { + &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = { + &WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = { + &WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = { + &WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = { + &WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + &WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { &WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID NULL @@ -1121,52 +1232,52 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { - &DIS_ICACHE[0], // [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_ICACHE[0], // [] Represents whether cache is disabled. 1: Disabled 0: Enabled. NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { - &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { - &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled + &DIS_FORCE_DOWNLOAD[0], // [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[] = { - &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled + &SPI_DOWNLOAD_MSPI_DIS[0], // [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { - &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled + &JTAG_SEL_ENABLE[0], // [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { - &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled + &DIS_PAD_JTAG[0], // [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { - &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { - &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged + &USB_EXCHG_PINS[0], // [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged NULL }; const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { - &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned + &VDD_SPI_AS_GPIO[0], // [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 + &WDT_DELAY_SEL[0], // [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) NULL }; @@ -1226,12 +1337,12 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { - &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled + &SECURE_BOOT_EN[0], // [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable NULL }; const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { - &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable NULL }; @@ -1241,27 +1352,27 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { - &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable + &DIS_DOWNLOAD_MODE[0], // [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[] = { - &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable + &DIS_DIRECT_BOOT[0], // [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { - &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable + &DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { - &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable + &DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { - &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable + &ENABLE_SECURITY_DOWNLOAD[0], // [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable NULL }; @@ -1286,32 +1397,57 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[] = { - &HYS_EN_PAD[0], // [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled + &HYS_EN_PAD[0], // [] Set bits to enable hysteresis function of PAD0~27 NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. NULL }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[] = { - &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration + &XTS_DPA_PSEUDO_LEVEL[0], // [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[] = { - &DIS_WIFI6[0], // [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled. + &DIS_WIFI6[0], // [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[] = { - &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable + &ECDSA_DISABLE_P192[0], // [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable + &ECC_FORCE_CONST_TIME[0], // [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { + &BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[0], // [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = { + &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { + &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { + &RECOVERY_BOOTLOADER_FLASH_SECTOR[0], // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[] = { + &REPEAT_DATA4[0], // [] Reserved NULL }; @@ -1385,6 +1521,41 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { + &ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { + &ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = { + &LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = { + &LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = { + &DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = { + &DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = { + &LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID NULL diff --git a/components/efuse/esp32c61/esp_efuse_table.csv b/components/efuse/esp32c61/esp_efuse_table.csv index 2a82ff95b5..a4ce7e0a20 100644 --- a/components/efuse/esp32c61/esp_efuse_table.csv +++ b/components/efuse/esp32c61/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d +# This file was generated by regtools.py based on the efuses.yaml file with the version: d435ade68d90ef96b0522478b2d8ba75 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -65,6 +65,13 @@ WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG +WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS +WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG +WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS +WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE @@ -99,16 +106,16 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5 RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2 -DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ -JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ -DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\ -DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\ -USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\ -VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\ -WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\ +DIS_ICACHE, EFUSE_BLK0, 39, 1, [] Represents whether cache is disabled. 1: Disabled 0: Enabled. +DIS_USB_JTAG, EFUSE_BLK0, 40, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled +DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 42, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled +SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 43, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled +JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled +DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled +DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled +USB_EXCHG_PINS, EFUSE_BLK0, 51, 1, [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged +VDD_SPI_AS_GPIO, EFUSE_BLK0, 52, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned 0: not functioned +WDT_DELAY_SEL, EFUSE_BLK0, 53, 2, [] lp wdt timeout threshold at startup = initial timeout value * (2 ^ (EFUSE_WDT_DELAY_SEL + 1)) SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 55, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 58, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 59, 1, [] Revoke 2nd secure boot key @@ -120,24 +127,29 @@ KEY_PURPOSE_3, EFUSE_BLK0, 76, 4, [KEY3_PUR KEY_PURPOSE_4, EFUSE_BLK0, 80, 4, [KEY4_PURPOSE] Represents the purpose of Key4 KEY_PURPOSE_5, EFUSE_BLK0, 84, 4, [KEY5_PURPOSE] Represents the purpose of Key5 SEC_DPA_LEVEL, EFUSE_BLK0, 88, 2, [] Represents the spa secure level by configuring the clock random divide mode -SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ -SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\ +SECURE_BOOT_EN, EFUSE_BLK0, 90, 1, [] Represents whether secure boot is enabled or disabled. 1. Enable 0: Disable +SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 91, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1. Enable 0: Disable FLASH_TPUW, EFUSE_BLK0, 92, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is programmed value. Otherwise; the waiting time is 2 times the programmed value -DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ -DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ -DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. Disable\\ 0: Enable\\ -DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\ -ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\ +DIS_DOWNLOAD_MODE, EFUSE_BLK0, 96, 1, [] Represents whether Download mode is disable or enable. 1. Disable 0: Enable +DIS_DIRECT_BOOT, EFUSE_BLK0, 97, 1, [] Represents whether direct boot mode is disabled or enabled. 1. Disable 0: Enable +DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable 0: Enable +DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable +ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled. 1: Enable 0: Disable UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Represents the types of UART printing FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable -HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\ -XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: Disable\\ -XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: Low\\ 0: Decided by register configuration\\ -DIS_WIFI6, EFUSE_BLK0, 125, 1, [] Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is disable\\ 0: WiFi 6 is enabled.\\ -ECDSA_DISABLE_P192, EFUSE_BLK0, 126, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable -ECC_FORCE_CONST_TIME, EFUSE_BLK0, 127, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable +HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Set bits to enable hysteresis function of PAD0~27 +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 122, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable. +XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled +DIS_WIFI6, EFUSE_BLK0, 125, 1, [] Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable; 0: WIFI6 is enabled +ECDSA_DISABLE_P192, EFUSE_BLK0, 126, 1, [] Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 127, 1, [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable +BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 128, 4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader +BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 132, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled +BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 133, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable +RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 134, 12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled +REPEAT_DATA4, EFUSE_BLK0, 160, 24, [] Reserved MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address @@ -156,6 +168,13 @@ PSRAM_CAP, EFUSE_BLK1, 83, 3, [] PSRAM PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] PSRAM vendor TEMP, EFUSE_BLK1, 88, 2, [] Temperature PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version +ACTIVE_HP_DBIAS, EFUSE_BLK1, 93, 4, [] Active HP DBIAS of fixed voltage +ACTIVE_LP_DBIAS, EFUSE_BLK1, 97, 4, [] Active LP DBIAS of fixed voltage +LSLP_HP_DBG, EFUSE_BLK1, 101, 2, [] LSLP HP DBG of fixed voltage +LSLP_HP_DBIAS, EFUSE_BLK1, 103, 4, [] LSLP HP DBIAS of fixed voltage +DSLP_LP_DBG, EFUSE_BLK1, 107, 4, [] DSLP LP DBG of fixed voltage +DSLP_LP_DBIAS, EFUSE_BLK1, 111, 5, [] DSLP LP DBIAS of fixed voltage +LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 116, 5, [] DBIAS gap between LP and HP OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode calibration diff --git a/components/efuse/esp32c61/include/esp_efuse_table.h b/components/efuse/esp32c61/include/esp_efuse_table.h index 40844a0581..81b5a77bef 100644 --- a/components/efuse/esp32c61/include/esp_efuse_table.h +++ b/components/efuse/esp32c61/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table af9aaa79feb0970d90f35360a5113f03 +// md5_digest_table 0edc6a5b20a41c88fdc0cf51a810c53e // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -78,6 +78,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; @@ -174,6 +181,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_WIFI6[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[]; extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[]; +extern const esp_efuse_desc_t* ESP_EFUSE_REPEAT_DATA4[]; extern const esp_efuse_desc_t* ESP_EFUSE_MAC[]; #define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[]; @@ -188,6 +200,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; diff --git a/components/efuse/include/esp_efuse.h b/components/efuse/include/esp_efuse.h index d18348fe47..8e8bde2279 100644 --- a/components/efuse/include/esp_efuse.h +++ b/components/efuse/include/esp_efuse.h @@ -282,6 +282,22 @@ esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size */ uint32_t esp_efuse_get_pkg_ver(void); +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED || __DOXYGEN__ +/** + * @brief Sets the recovery bootloader flash offset in eFuse. + * + * This function is used to set the flash offset in eFuse for the recovery bootloader. + * If an offset is already set in eFuse, it will be validated against the provided offset. + * + * @param offset Flash offset where the recovery bootloader is located. + * @return + * - ESP_OK: Successfully set or given offset is already set. + * - ESP_ERR_NOT_ALLOWED: Recovery bootloader feature is disabled in eFuse. + * - ESP_FAIL: Failed to update the recovery bootloader flash offset. + * - Error code from eFuse read/write operations if an error occurs. + */ +esp_err_t esp_efuse_set_recovery_bootloader_offset(const uint32_t offset); +#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED /** * @brief Reset efuse write registers diff --git a/components/efuse/src/esp_efuse_fields.c b/components/efuse/src/esp_efuse_fields.c index af35572dd8..9bd1ef6156 100644 --- a/components/efuse/src/esp_efuse_fields.c +++ b/components/efuse/src/esp_efuse_fields.c @@ -12,8 +12,11 @@ #include "esp_types.h" #include "assert.h" #include "esp_err.h" +#include "esp_check.h" #include "esp_fault.h" #include "esp_log.h" +#include "hal/efuse_ll.h" +#include "hal/efuse_hal.h" #include "soc/efuse_periph.h" #include "sys/param.h" #include "soc/soc_caps.h" @@ -151,3 +154,34 @@ esp_err_t esp_efuse_enable_ecdsa_p192_curve_mode(void) return ESP_OK; } #endif /* SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED */ + +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED +esp_err_t esp_efuse_set_recovery_bootloader_offset(const uint32_t offset) +{ + // The eFuse field stores the sector number instead of the full address to conserve eFuse bits. + if (efuse_ll_get_recovery_bootloader_sector() == 0) { + ESP_LOGI(TAG, "Recovery bootloader offset has not been set yet."); + uint32_t recovery_flash_sector = efuse_hal_convert_recovery_bootloader_address_to_flash_sectors(offset); + ESP_RETURN_ON_FALSE((recovery_flash_sector & ((1U << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LEN) - 1)) == recovery_flash_sector, ESP_ERR_INVALID_ARG, TAG, + "Given address exceeds the allowed range of the efuse field"); + + size_t recovery_flash_sector_len = esp_efuse_get_field_size(ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR); + assert(recovery_flash_sector_len == EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_LEN); + ESP_RETURN_ON_ERROR(esp_efuse_write_field_blob(ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR, &recovery_flash_sector, recovery_flash_sector_len), TAG, + "Failed to burn recovery bootloader offset to eFuse"); + + } else if (!efuse_hal_recovery_bootloader_enabled()) { + ESP_LOGE(TAG, "Recovery bootloader offset is disabled"); + return ESP_ERR_NOT_ALLOWED; + } + + uint32_t programmed_offset = efuse_hal_get_recovery_bootloader_address(); + if (programmed_offset != offset) { + ESP_LOGE(TAG, "Verification failed. eFuse recovery bootloader offset=0x%" PRIx32 ", expected=0x%" PRIx32, programmed_offset, offset); + return ESP_FAIL; + } + + ESP_LOGI(TAG, "Recovery bootloader offset in eFuse = 0x%" PRIx32, programmed_offset); + return ESP_OK; +} +#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED diff --git a/components/esp_adc/adc_continuous.c b/components/esp_adc/adc_continuous.c index 4f220bd6a5..c3757afd32 100644 --- a/components/esp_adc/adc_continuous.c +++ b/components/esp_adc/adc_continuous.c @@ -319,10 +319,10 @@ esp_err_t adc_continuous_start(adc_continuous_handle_t handle) adc_hal_set_controller(ADC_UNIT_2, ADC_HAL_CONTINUOUS_READ_MODE); } - adc_hal_digi_init(&handle->hal); #if !CONFIG_IDF_TARGET_ESP32 - esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), true)); #endif + adc_hal_digi_init(&handle->hal); adc_hal_digi_controller_config(&handle->hal, &handle->hal_digi_ctrlr_cfg); adc_hal_digi_enable(false); @@ -360,7 +360,9 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle) #endif adc_hal_digi_deinit(); - +#if !CONFIG_IDF_TARGET_ESP32 + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal_digi_ctrlr_cfg.clk_src), false)); +#endif if (handle->use_adc2) { adc_lock_release(ADC_UNIT_2); } @@ -373,7 +375,6 @@ esp_err_t adc_continuous_stop(adc_continuous_handle_t handle) if (handle->pm_lock) { ESP_RETURN_ON_ERROR(esp_pm_lock_release(handle->pm_lock), ADC_TAG, "release pm_lock failed"); } - ANALOG_CLOCK_DISABLE(); return ESP_OK; diff --git a/components/esp_adc/adc_oneshot.c b/components/esp_adc/adc_oneshot.c index aba44c2748..cd85a76281 100644 --- a/components/esp_adc/adc_oneshot.c +++ b/components/esp_adc/adc_oneshot.c @@ -156,6 +156,9 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a if (init_config->ulp_mode == ADC_ULP_MODE_DISABLE) { sar_periph_ctrl_adc_oneshot_power_acquire(); } else { +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(unit->hal.clk_src), true), err, TAG, "clock source enable failed"); +#endif #if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED esp_sleep_sub_mode_config(ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE, true); #endif @@ -189,9 +192,6 @@ esp_err_t adc_oneshot_config_channel(adc_oneshot_unit_handle_t handle, adc_chann portENTER_CRITICAL(&rtc_spinlock); adc_oneshot_hal_channel_config(hal, &cfg, channel); if (handle->ulp_mode) { -#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED - esp_clk_tree_enable_src((soc_module_clk_t)(hal->clk_src), true); -#endif adc_oneshot_hal_setup(hal, channel); } portEXIT_CRITICAL(&rtc_spinlock); @@ -210,7 +210,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan, portENTER_CRITICAL(&rtc_spinlock); #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED - esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true)); #endif ANALOG_CLOCK_ENABLE(); adc_oneshot_hal_setup(&(handle->hal), chan); @@ -222,6 +222,9 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan, bool valid = false; valid = adc_oneshot_hal_convert(&(handle->hal), out_raw); ANALOG_CLOCK_DISABLE(); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false)); +#endif portEXIT_CRITICAL(&rtc_spinlock); adc_lock_release(handle->unit_id); @@ -238,7 +241,7 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c portENTER_CRITICAL_SAFE(&rtc_spinlock); #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED - esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), true)); #endif ANALOG_CLOCK_ENABLE(); adc_oneshot_hal_setup(&(handle->hal), chan); @@ -249,6 +252,9 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c #endif adc_oneshot_hal_convert(&(handle->hal), out_raw); ANALOG_CLOCK_DISABLE(); +#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false)); +#endif portEXIT_CRITICAL_SAFE(&rtc_spinlock); @@ -271,7 +277,6 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle) _lock_release(&s_ctx.mutex); ESP_LOGD(TAG, "adc unit%"PRId32" is deleted", handle->unit_id); - free(handle); if (ulp_mode == ADC_ULP_MODE_DISABLE) { sar_periph_ctrl_adc_oneshot_power_release(); @@ -279,7 +284,9 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle) #if SOC_LIGHT_SLEEP_SUPPORTED || SOC_DEEP_SLEEP_SUPPORTED esp_sleep_sub_mode_config(ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE, false); #endif + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(handle->hal.clk_src), false)); } + free(handle); #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED //To free the APB_SARADC periph if needed diff --git a/components/esp_adc/esp32c5/curve_fitting_coefficients.c b/components/esp_adc/esp32c5/curve_fitting_coefficients.c index 49c6dcefd3..aa326f98b6 100644 --- a/components/esp_adc/esp32c5/curve_fitting_coefficients.c +++ b/components/esp_adc/esp32c5/curve_fitting_coefficients.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -28,10 +28,10 @@ const static uint64_t adc1_error_coef_atten[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX][2] = { /* Coefficients of calibration version 1 */ { - {{2941017829027464, 1e16}, {7368674918527, 1e16}, {0, 0}}, //atten0 - {{3224276125615327, 1e16}, {5325658467636, 1e16}, {0, 0}}, //atten1 - {{3307554632960901, 1e16}, {409244304226, 1e15}, {0, 0}}, //atten2 - {{1463642578413965, 1e15}, {3349642363147, 1e15}, {11676836451, 1e16}}, //atten3 + {{2941017829027464, 1e16}, {7368674918527, 1e16}, {0, 1}}, //atten0 + {{3224276125615327, 1e16}, {5325658467636, 1e16}, {0, 1}}, //atten1 + {{3307554632960901, 1e16}, {409244304226, 1e15}, {0, 1}}, //atten2 + {{1463642578413965, 1e15}, {3349642363147, 1e15}, {11676836451, 1e16}}, //atten3 }, }; @@ -41,9 +41,9 @@ const static uint64_t adc1_error_coef_atten[COEFF_VERSION_NUM][COEFF_GROUP_NUM][ const static int32_t adc1_error_sign[COEFF_VERSION_NUM][COEFF_GROUP_NUM][TERM_MAX] = { /* Coefficient sign of calibration version 1 */ { - {1, -1, 0}, //atten0 - {1, -1, 0}, //atten1 - {1, -1, 0}, //atten2 + {-1, 1, 1}, //atten0 + {-1, 1, 1}, //atten1 + {-1, 1, 1}, //atten2 {1, -1, 1}, //atten3 }, }; @@ -54,7 +54,7 @@ void curve_fitting_get_second_step_coeff(const adc_cali_curve_fitting_config_t * assert((adc_calib_ver >= ESP_EFUSE_ADC_CALIB_VER_MIN) && (adc_calib_ver <= ESP_EFUSE_ADC_CALIB_VER_MAX)); - ctx->term_num = 2; + ctx->term_num = 3; ctx->coeff = adc1_error_coef_atten[VER2IDX(adc_calib_ver)][config->atten]; ctx->sign = adc1_error_sign[VER2IDX(adc_calib_ver)][config->atten]; } diff --git a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c index 3f6c2b56d4..a5aa1a4382 100644 --- a/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c +++ b/components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c @@ -119,7 +119,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_ #endif mipi_csi_phy_clock_source_t clk_src = !config->clk_src ? MIPI_CSI_PHY_CLK_SRC_DEFAULT : config->clk_src; - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed"); PERIPH_RCC_ATOMIC() { // phy clock source setting mipi_csi_ll_set_phy_clock_source(ctlr->csi_id, clk_src); diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c index 24a95e2d53..a1f3568b14 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c @@ -333,7 +333,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e } } - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); PERIPH_RCC_ATOMIC() { cam_ll_enable_clk(ctlr_id, true); cam_ll_select_clk_src(ctlr_id, clk_src); diff --git a/components/esp_driver_gptimer/src/gptimer.c b/components/esp_driver_gptimer/src/gptimer.c index 49f77e230b..af2fe34c8d 100644 --- a/components/esp_driver_gptimer/src/gptimer.c +++ b/components/esp_driver_gptimer/src/gptimer.c @@ -108,6 +108,9 @@ static void gptimer_unregister_from_group(gptimer_t *timer) static esp_err_t gptimer_destroy(gptimer_t *timer) { + if (timer->clk_src) { + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(timer->clk_src), false), TAG, "clock source disable failed"); + } if (timer->pm_lock) { ESP_RETURN_ON_ERROR(esp_pm_lock_delete(timer->pm_lock), TAG, "delete pm_lock failed"); } @@ -155,6 +158,7 @@ esp_err_t gptimer_new_timer(const gptimer_config_t *config, gptimer_handle_t *re // initialize HAL layer timer_hal_init(&timer->hal, group_id, timer_id); // select clock source, set clock resolution + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)config->clk_src, true), err, TAG, "clock source enable failed"); ESP_GOTO_ON_ERROR(gptimer_select_periph_clock(timer, config->clk_src, config->resolution_hz), err, TAG, "set periph clock failed"); // initialize counter value to zero timer_hal_set_counter_value(&timer->hal, 0); diff --git a/components/esp_driver_gptimer/src/gptimer_common.c b/components/esp_driver_gptimer/src/gptimer_common.c index 6b89e8a957..7662b1a784 100644 --- a/components/esp_driver_gptimer/src/gptimer_common.c +++ b/components/esp_driver_gptimer/src/gptimer_common.c @@ -99,6 +99,7 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s periph_rtc_dig_clk8m_enable(); } #endif // SOC_TIMER_GROUP_SUPPORT_RC_FAST + timer->clk_src = src_clk; // get clock source frequency ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)src_clk, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &counter_src_hz), @@ -140,7 +141,6 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s } #endif // CONFIG_PM_ENABLE - esp_clk_tree_enable_src((soc_module_clk_t)src_clk, true); // !!! HARDWARE SHARED RESOURCE !!! // on some ESP chip, different peripheral's clock source setting are mixed in the same register // so we need to make this done in an atomic way @@ -148,7 +148,6 @@ esp_err_t gptimer_select_periph_clock(gptimer_t *timer, gptimer_clock_source_t s timer_ll_set_clock_source(group_id, timer_id, src_clk); timer_ll_enable_clock(group_id, timer_id, true); } - timer->clk_src = src_clk; uint32_t prescale = counter_src_hz / resolution_hz; // potential resolution loss here timer_ll_set_clock_prescale(timer->hal.dev, timer_id, prescale); timer->resolution_hz = counter_src_hz / prescale; // this is the real resolution diff --git a/components/esp_driver_gptimer/src/gptimer_priv.h b/components/esp_driver_gptimer/src/gptimer_priv.h index a4a2114162..797bf4c4c5 100644 --- a/components/esp_driver_gptimer/src/gptimer_priv.h +++ b/components/esp_driver_gptimer/src/gptimer_priv.h @@ -28,6 +28,7 @@ #include "hal/timer_hal.h" #include "hal/timer_ll.h" #include "clk_ctrl_os.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/sleep_retention.h" #include "esp_private/periph_ctrl.h" diff --git a/components/esp_driver_isp/include/esp_private/isp_private.h b/components/esp_driver_isp/include/esp_private/isp_private.h index 9d0ec92e25..7bcb151c1d 100644 --- a/components/esp_driver_isp/include/esp_private/isp_private.h +++ b/components/esp_driver_isp/include/esp_private/isp_private.h @@ -53,6 +53,7 @@ typedef enum { ---------------------------------------------------------------*/ typedef struct isp_processor_t { int proc_id; + isp_clk_src_t clk_src; isp_hal_context_t hal; #if SOC_ISP_SHARE_CSI_BRG int csi_brg_id; diff --git a/components/esp_driver_isp/src/isp_core.c b/components/esp_driver_isp/src/isp_core.c index fd5aa59213..d6dd2bbeae 100644 --- a/components/esp_driver_isp/src/isp_core.c +++ b/components/esp_driver_isp/src/isp_core.c @@ -112,14 +112,13 @@ esp_err_t esp_isp_new_processor(const esp_isp_processor_cfg_t *proc_config, isp_ if (out_clk_freq_hz != proc_config->clk_hz) { ESP_LOGW(TAG, "precision loss, real output frequency: %"PRIu32"Hz", out_clk_freq_hz); } - ; isp_hal_init(&proc->hal, proc->proc_id); - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed"); PERIPH_RCC_ATOMIC() { isp_ll_select_clk_source(proc->hal.hw, clk_src); isp_ll_set_clock_div(proc->hal.hw, &clk_div); } - + proc->clk_src = clk_src; proc->isp_fsm = ISP_FSM_INIT; proc->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED; @@ -197,6 +196,7 @@ esp_err_t esp_isp_del_processor(isp_proc_handle_t proc) #if SOC_ISP_SHARE_CSI_BRG ESP_RETURN_ON_ERROR(mipi_csi_brg_declaim(proc->csi_brg_id), TAG, "declaim csi bridge fail"); #endif + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(proc->clk_src), false), TAG, "clock source disable failed"); free(proc); return ESP_OK; diff --git a/components/esp_driver_ledc/src/ledc.c b/components/esp_driver_ledc/src/ledc.c index 904e708d36..4d9eaa3b94 100644 --- a/components/esp_driver_ledc/src/ledc.c +++ b/components/esp_driver_ledc/src/ledc.c @@ -699,7 +699,7 @@ static esp_err_t ledc_set_timer_div(ledc_mode_t speed_mode, ledc_timer_t timer_n if (p_ledc_obj[speed_mode]->glb_clk != glb_clk) { // TODO: release old glb_clk (if not UNINIT), and acquire new glb_clk [clk_tree] p_ledc_obj[speed_mode]->glb_clk = glb_clk; - esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)glb_clk, true), LEDC_TAG, "clock source enable failed"); LEDC_FUNC_CLOCK_ATOMIC() { ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), glb_clk); } @@ -864,7 +864,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf) else if (new_speed_mode_ctx_created) { portENTER_CRITICAL(&ledc_spinlock); if (p_ledc_obj[speed_mode]->glb_clk == LEDC_SLOW_CLK_UNINIT) { - esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)LEDC_LL_GLOBAL_CLK_DEFAULT, true)); ledc_hal_set_slow_clk_sel(&(p_ledc_obj[speed_mode]->ledc_hal), LEDC_LL_GLOBAL_CLK_DEFAULT); } portEXIT_CRITICAL(&ledc_spinlock); diff --git a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c index 226232911d..268f523511 100644 --- a/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c +++ b/components/esp_driver_ledc/test_apps/ledc/main/test_ledc.c @@ -466,7 +466,7 @@ static void timer_frequency_test(ledc_channel_t channel, ledc_timer_bit_t timer_ } else if (clk_src_freq == 60 * 1000 * 1000) { theoretical_freq = 8993; } - frequency_set_get(speed_mode, timer, 9000, theoretical_freq, 50); + frequency_set_get(speed_mode, timer, 9000, theoretical_freq, 60); #endif // Pause and de-configure the timer so that it won't affect the following test cases diff --git a/components/esp_driver_mcpwm/src/mcpwm_com.c b/components/esp_driver_mcpwm/src/mcpwm_com.c index 6ece740fb5..e187e73282 100644 --- a/components/esp_driver_mcpwm/src/mcpwm_com.c +++ b/components/esp_driver_mcpwm/src/mcpwm_com.c @@ -199,7 +199,7 @@ esp_err_t mcpwm_select_periph_clock(mcpwm_group_t *group, soc_module_clk_t clk_s ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed"); #endif // CONFIG_PM_ENABLE - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed"); MCPWM_CLOCK_SRC_ATOMIC() { mcpwm_ll_group_set_clock_source(group_id, clk_src); } diff --git a/components/esp_driver_parlio/include/driver/parlio_tx.h b/components/esp_driver_parlio/include/driver/parlio_tx.h index 933d8b81a9..2f050d6389 100644 --- a/components/esp_driver_parlio/include/driver/parlio_tx.h +++ b/components/esp_driver_parlio/include/driver/parlio_tx.h @@ -116,6 +116,7 @@ esp_err_t parlio_tx_unit_disable(parlio_tx_unit_handle_t unit); */ typedef struct { parlio_tx_done_callback_t on_trans_done; /*!< Event callback, invoked when one transmission is finished */ + parlio_tx_buffer_switched_callback_t on_buffer_switched; /*!< Event callback, invoked when the buffer is switched in loop transmission */ } parlio_tx_event_callbacks_t; /** diff --git a/components/esp_driver_parlio/include/driver/parlio_types.h b/components/esp_driver_parlio/include/driver/parlio_types.h index aa75b35468..f8d7479aae 100644 --- a/components/esp_driver_parlio/include/driver/parlio_types.h +++ b/components/esp_driver_parlio/include/driver/parlio_types.h @@ -37,6 +37,14 @@ typedef struct parlio_rx_delimiter_t *parlio_rx_delimiter_handle_t; typedef struct { } parlio_tx_done_event_data_t; +/** + * @brief Type of Parallel IO TX buffer switched event data + */ +typedef struct { + void *old_buffer_addr; /*!< Address of the previous buffer used before switching */ + void *new_buffer_addr; /*!< Address of the new buffer switched to */ +} parlio_tx_buffer_switched_event_data_t; + /** * @brief Prototype of parlio tx event callback * @param[in] tx_unit Parallel IO TX unit that created by `parlio_new_tx_unit` @@ -48,6 +56,17 @@ typedef struct { */ typedef bool (*parlio_tx_done_callback_t)(parlio_tx_unit_handle_t tx_unit, const parlio_tx_done_event_data_t *edata, void *user_ctx); +/** + * @brief Prototype of parlio tx buffer switched event callback + * @param[in] tx_unit Parallel IO TX unit that created by `parlio_new_tx_unit` + * @param[in] edata Point to Parallel IO TX event data. The lifecycle of this pointer memory is inside this function, + * user should copy it into static memory if used outside this function. + * @param[in] user_ctx User registered context, passed from `parlio_tx_unit_register_event_callbacks` + * + * @return Whether a high priority task has been waken up by this callback function + */ +typedef bool (*parlio_tx_buffer_switched_callback_t)(parlio_tx_unit_handle_t tx_unit, const parlio_tx_buffer_switched_event_data_t *edata, void *user_ctx); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_parlio/linker.lf b/components/esp_driver_parlio/linker.lf index d596914d27..76b5b7f0cf 100644 --- a/components/esp_driver_parlio/linker.lf +++ b/components/esp_driver_parlio/linker.lf @@ -5,6 +5,10 @@ entries: parlio_tx: parlio_tx_default_isr (noflash) parlio_tx: parlio_tx_do_transaction (noflash) parlio_tx: parlio_mount_buffer (noflash) + + if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION = y: + parlio_tx: parlio_tx_gdma_eof_callback (noflash) + if PARLIO_RX_ISR_HANDLER_IN_IRAM = y: parlio_rx: parlio_rx_default_eof_callback (noflash) parlio_rx: parlio_rx_default_desc_done_callback (noflash) @@ -18,3 +22,6 @@ entries: gdma_link: gdma_link_mount_buffers (noflash) gdma_link: gdma_link_concat (noflash) gdma_link: gdma_link_get_head_addr (noflash) + + if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION = y: + gdma_link: gdma_link_get_buffer (noflash) diff --git a/components/esp_driver_parlio/src/parlio_priv.h b/components/esp_driver_parlio/src/parlio_priv.h index 93bf931f93..fe54ea8123 100644 --- a/components/esp_driver_parlio/src/parlio_priv.h +++ b/components/esp_driver_parlio/src/parlio_priv.h @@ -168,6 +168,10 @@ typedef esp_err_t (*parlio_tx_bs_disable_fn_t)(parlio_tx_unit_handle_t tx_unit); typedef struct parlio_tx_unit_t { struct parlio_unit_t base; // base unit size_t data_width; // data width + gpio_num_t data_gpio_nums[SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH]; // data GPIO numbers + gpio_num_t valid_gpio_num; // valid signal GPIO number + gpio_num_t clk_out_gpio_num; // output clock GPIO number + gpio_num_t clk_in_gpio_num; // input clock GPIO number intr_handle_t intr; // allocated interrupt handle esp_pm_lock_handle_t pm_lock; // power management lock gdma_channel_handle_t dma_chan; // DMA channel @@ -187,7 +191,9 @@ typedef struct parlio_tx_unit_t { parlio_tx_trans_desc_t *cur_trans; // points to current transaction uint32_t idle_value_mask; // mask of idle value _Atomic parlio_tx_fsm_t fsm; // Driver FSM state + _Atomic bool buffer_need_switch; // whether the buffer need to be switched parlio_tx_done_callback_t on_trans_done; // callback function when the transmission is done + parlio_tx_buffer_switched_callback_t on_buffer_switched; // callback function when the buffer is switched in loop transmission void *user_data; // user data passed to the callback function bitscrambler_handle_t bs_handle; // bitscrambler handle parlio_tx_bs_enable_fn_t bs_enable_fn; // bitscrambler enable function diff --git a/components/esp_driver_parlio/src/parlio_rx.c b/components/esp_driver_parlio/src/parlio_rx.c index 1c126c0bdb..b413cc21f4 100644 --- a/components/esp_driver_parlio/src/parlio_rx.c +++ b/components/esp_driver_parlio/src/parlio_rx.c @@ -491,6 +491,7 @@ static esp_err_t parlio_select_periph_clock(parlio_rx_unit_handle_t rx_unit, con { parlio_hal_context_t *hal = &rx_unit->base.group->hal; parlio_clock_source_t clk_src = config->clk_src; + rx_unit->clk_src = clk_src; uint32_t src_freq_hz = 0; uint32_t exp_freq_hz = 0; hal_utils_clk_div_t clk_div = { @@ -536,14 +537,12 @@ static esp_err_t parlio_select_periph_clock(parlio_rx_unit_handle_t rx_unit, con } #endif - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); /* Set clock configuration */ PARLIO_CLOCK_SRC_ATOMIC() { parlio_ll_rx_set_clock_source(hal->regs, clk_src); parlio_ll_rx_set_clock_div(hal->regs, &clk_div); } - rx_unit->clk_src = clk_src; /* warning if precision lost due to division */ if ((clk_src != PARLIO_CLK_SRC_EXTERNAL) && (config->exp_clk_freq_hz != rx_unit->cfg.exp_clk_freq_hz)) { @@ -595,6 +594,9 @@ static esp_err_t parlio_destroy_rx_unit(parlio_rx_unit_handle_t rx_unit) if (rx_unit->base.group) { parlio_unregister_unit_from_group(&rx_unit->base); } + if (rx_unit->clk_src) { + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)rx_unit->clk_src, false), TAG, "clock source disable failed"); + } /* Free the RX unit */ free(rx_unit); return ESP_OK; @@ -661,6 +663,7 @@ esp_err_t parlio_new_rx_unit(const parlio_rx_unit_config_t *config, parlio_rx_un } parlio_ll_rx_start(hal->regs, false); /* parlio_ll_clock_source_t and parlio_clock_source_t are binary compatible if the clock source is from internal */ + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(config->clk_src), true), err, TAG, "clock source enable failed"); ESP_GOTO_ON_ERROR(parlio_select_periph_clock(unit, config), err, TAG, "set clock source failed"); /* Set the data width */ parlio_ll_rx_set_bus_width(hal->regs, config->data_width); diff --git a/components/esp_driver_parlio/src/parlio_tx.c b/components/esp_driver_parlio/src/parlio_tx.c index e5987cfaf7..fe6fb59fd1 100644 --- a/components/esp_driver_parlio/src/parlio_tx.c +++ b/components/esp_driver_parlio/src/parlio_tx.c @@ -10,6 +10,9 @@ #include "driver/parlio_tx.h" #include "parlio_priv.h" +#if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION +static bool parlio_tx_gdma_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data); +#endif static void parlio_tx_default_isr(void *args); static esp_err_t parlio_tx_create_trans_queue(parlio_tx_unit_t *tx_unit, const parlio_tx_unit_config_t *config) @@ -72,6 +75,9 @@ static esp_err_t parlio_destroy_tx_unit(parlio_tx_unit_t *tx_unit) ESP_RETURN_ON_ERROR(gdma_del_link_list(tx_unit->dma_link[i]), TAG, "delete dma link list failed"); } } + if (tx_unit->clk_src) { + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)tx_unit->clk_src, false), TAG, "clock source disable failed"); + } free(tx_unit); return ESP_OK; } @@ -94,6 +100,7 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->data_gpio_nums[i], parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[i], false, false); + tx_unit->data_gpio_nums[i] = config->data_gpio_nums[i]; } } @@ -118,6 +125,7 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const parlio_periph_signals.groups[group_id].tx_units[unit_id].data_sigs[PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG], config->flags.invert_valid_out, false); #endif // !PARLIO_LL_TX_DATA_LINE_AS_VALID_SIG + tx_unit->valid_gpio_num = config->valid_gpio_num; } if (config->clk_out_gpio_num >= 0) { gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO); @@ -130,6 +138,7 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const // connect the signal to the GPIO by matrix, it will also enable the output path properly esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num, parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_out_sig, false, false); + tx_unit->clk_out_gpio_num = config->clk_out_gpio_num; } if (config->clk_in_gpio_num >= 0) { gpio_input_enable(config->clk_in_gpio_num); @@ -141,6 +150,7 @@ static esp_err_t parlio_tx_unit_configure_gpio(parlio_tx_unit_t *tx_unit, const esp_rom_gpio_connect_in_signal(config->clk_in_gpio_num, parlio_periph_signals.groups[group_id].tx_units[unit_id].clk_in_sig, false); + tx_unit->clk_in_gpio_num = config->clk_in_gpio_num; } return ESP_OK; } @@ -202,6 +212,7 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par { parlio_hal_context_t *hal = &tx_unit->base.group->hal; parlio_clock_source_t clk_src = config->clk_src; + tx_unit->clk_src = clk_src; if (config->clk_in_gpio_num >= 0 && clk_src != PARLIO_CLK_SRC_EXTERNAL) { ESP_LOGW(TAG, "input clock GPIO is set, use external clk src"); clk_src = PARLIO_CLK_SRC_EXTERNAL; @@ -244,7 +255,6 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par #else tx_unit->out_clk_freq_hz = hal_utils_calc_clk_div_integer(&clk_info, &clk_div.integer); #endif - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); PARLIO_CLOCK_SRC_ATOMIC() { // turn on the tx module clock to sync the clock divider configuration because of the CDC (Cross Domain Crossing) parlio_ll_tx_enable_clock(hal->regs, true); @@ -256,8 +266,6 @@ static esp_err_t parlio_select_periph_clock(parlio_tx_unit_t *tx_unit, const par if (tx_unit->out_clk_freq_hz != config->output_clk_freq_hz) { ESP_LOGW(TAG, "precision loss, real output frequency: %"PRIu32, tx_unit->out_clk_freq_hz); } - tx_unit->clk_src = clk_src; - return ESP_OK; } @@ -305,6 +313,7 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un parlio_group_t *group = unit->base.group; parlio_hal_context_t *hal = &group->hal; // select the clock source + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)(config->clk_src), true), err, TAG, "clock source enable failed"); ESP_GOTO_ON_ERROR(parlio_select_periph_clock(unit, config), err, TAG, "set clock source failed"); // install interrupt service @@ -357,9 +366,6 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un // set sample clock edge parlio_ll_tx_set_sample_clock_edge(hal->regs, config->sample_edge); - // In default, use DATA LEN EOF as the Parlio TX EOF - parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN); - // clear any pending interrupt parlio_ll_clear_interrupt_status(hal->regs, PARLIO_LL_EVENT_TX_MASK); @@ -374,6 +380,7 @@ esp_err_t parlio_new_tx_unit(const parlio_tx_unit_config_t *config, parlio_tx_un portMUX_INITIALIZE(&unit->spinlock); atomic_init(&unit->fsm, PARLIO_TX_FSM_INIT); + atomic_init(&unit->buffer_need_switch, false); // return TX unit handle *ret_unit = unit; ESP_LOGD(TAG, "new tx unit(%d,%d) at %p, out clk=%"PRIu32"Hz, queue_depth=%zu, idle_mask=%"PRIx32, @@ -392,6 +399,22 @@ esp_err_t parlio_del_tx_unit(parlio_tx_unit_handle_t unit) ESP_RETURN_ON_FALSE(unit, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); ESP_RETURN_ON_FALSE(atomic_load(&unit->fsm) == PARLIO_TX_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "unit not in init state"); ESP_LOGD(TAG, "del tx unit(%d,%d)", unit->base.group->group_id, unit->base.unit_id); + for (size_t i = 0; i < unit->data_width; i++) { + if (unit->data_gpio_nums[i] >= 0) { + gpio_output_disable(unit->data_gpio_nums[i]); + } + } + if (unit->valid_gpio_num >= 0) { + gpio_output_disable(unit->valid_gpio_num); + } + if (unit->clk_out_gpio_num >= 0) { + gpio_output_disable(unit->clk_out_gpio_num); + } + if (unit->clk_in_gpio_num >= 0) { + esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, + parlio_periph_signals.groups[unit->base.group->group_id].tx_units[unit->base.unit_id].clk_in_sig, + false); + } return parlio_destroy_tx_unit(unit); } @@ -420,12 +443,30 @@ esp_err_t parlio_tx_unit_register_event_callbacks(parlio_tx_unit_handle_t tx_uni if (cbs->on_trans_done) { ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_trans_done), ESP_ERR_INVALID_ARG, TAG, "on_trans_done callback not in IRAM"); } + if (cbs->on_buffer_switched) { + ESP_RETURN_ON_FALSE(esp_ptr_in_iram(cbs->on_buffer_switched), ESP_ERR_INVALID_ARG, TAG, "on_buffer_switched callback not in IRAM"); + } if (user_data) { ESP_RETURN_ON_FALSE(esp_ptr_internal(user_data), ESP_ERR_INVALID_ARG, TAG, "user context not in internal RAM"); } #endif + if (cbs->on_buffer_switched) { +#if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION + // workaround for DIG-559 + ESP_RETURN_ON_FALSE(tx_unit->data_width > 1, ESP_ERR_NOT_SUPPORTED, TAG, "on_buffer_switched callback is not supported for 1-bit data width"); + + gdma_tx_event_callbacks_t gdma_cbs = { + .on_trans_eof = parlio_tx_gdma_eof_callback, + }; + ESP_RETURN_ON_ERROR(gdma_register_tx_event_callbacks(tx_unit->dma_chan, &gdma_cbs, tx_unit), TAG, "install DMA callback failed"); +#else + ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "on_buffer_switched callback is not supported"); +#endif + } + tx_unit->on_trans_done = cbs->on_trans_done; + tx_unit->on_buffer_switched = cbs->on_buffer_switched; tx_unit->user_data = user_data; return ESP_OK; } @@ -437,8 +478,8 @@ static void parlio_mount_buffer(parlio_tx_unit_t *tx_unit, parlio_tx_trans_desc_ .buffer = (void *)t->payload, .length = (t->payload_bits + 7) / 8, .flags = { - // if transmission is loop, we don't need to generate the EOF, as well as the final mark - .mark_eof = !t->flags.loop_transmission, + // if transmission is loop, we don't need to generate the EOF for 1-bit data width, DIG-559 + .mark_eof = tx_unit->data_width == 1 ? !t->flags.loop_transmission : true, .mark_final = !t->flags.loop_transmission, } }; @@ -456,12 +497,6 @@ static void parlio_mount_buffer(parlio_tx_unit_t *tx_unit, parlio_tx_trans_desc_ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_desc_t *t) { parlio_hal_context_t *hal = &tx_unit->base.group->hal; - - if (t->flags.loop_transmission) { - // Once a loop transmission is started, it cannot be stopped until it is disabled - parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF); - } - tx_unit->cur_trans = t; // If the external clock is a non-free-running clock, it needs to be switched to the internal free-running clock first. @@ -490,7 +525,30 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_ // reset tx fifo after disabling tx core clk to avoid unexpected rempty interrupt parlio_ll_tx_reset_fifo(hal->regs); parlio_ll_tx_set_idle_data_value(hal->regs, t->idle_value); - parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits); + + // set EOF condition + if (t->flags.loop_transmission) { + if (tx_unit->data_width == 1) { + // for 1-bit data width, we need to set the EOF condition to DMA EOF + parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF); + } else { + // for other data widths, we still use the data length EOF condition, + // but let the `bit counter` + `data width` for each cycle is never equal to the configured bit lens. + // Thus, we can skip the exact match, prevents EOF + parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN); + parlio_ll_tx_set_trans_bit_len(hal->regs, 0x01); + } + } else { + // non-loop transmission +#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + // for DMA EOF supported target, we need to set the EOF condition to DMA EOF + parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF); +#else + // for DMA EOF not supported target, we need to set the bit length to the configured bit lens + parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN); + parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits); +#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + } if (tx_unit->bs_handle) { // load the bitscrambler program and start it @@ -583,10 +641,6 @@ esp_err_t parlio_tx_unit_disable(parlio_tx_unit_handle_t tx_unit) parlio_ll_tx_start(hal->regs, false); parlio_ll_enable_interrupt(hal->regs, PARLIO_LL_EVENT_TX_MASK, false); - // Once a loop teansmission transaction is started, it can only be stopped in disable function - // change the EOF condition to be the data length, so the EOF will be triggered normally - parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN); - // release power management lock if (tx_unit->pm_lock) { esp_pm_lock_release(tx_unit->pm_lock); @@ -609,18 +663,20 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p #if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION if (config->flags.loop_transmission) { - ESP_RETURN_ON_FALSE(parlio_ll_tx_support_dma_eof(NULL), ESP_ERR_NOT_SUPPORTED, TAG, "loop transmission is not supported by this chip revision"); + ESP_RETURN_ON_FALSE(parlio_ll_tx_support_dma_eof(NULL) || tx_unit->data_width > 1, ESP_ERR_NOT_SUPPORTED, TAG, + "1-bit data width loop transmission is not supported by this chip revision"); } #else ESP_RETURN_ON_FALSE(config->flags.loop_transmission == false, ESP_ERR_NOT_SUPPORTED, TAG, "loop transmission is not supported on this chip"); #endif - // check the max payload size if it's not a loop transmission - // workaround for EOF limitation, when DMA EOF issue is fixed, we can remove this check +#if !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + // check the max payload size if it's not a loop transmission and the DMA EOF is not supported if (!config->flags.loop_transmission) { ESP_RETURN_ON_FALSE(tx_unit->max_transfer_bits <= PARLIO_LL_TX_MAX_BITS_PER_FRAME, - ESP_ERR_INVALID_ARG, TAG, "invalid transfer size"); + ESP_ERR_INVALID_ARG, TAG, "invalid transfer size, max transfer size should be less than %d", PARLIO_LL_TX_MAX_BITS_PER_FRAME / 8); } +#endif // !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA size_t cache_line_size = 0; size_t alignment = 0; @@ -643,6 +699,7 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p tx_unit->cur_trans->payload = payload; tx_unit->cur_trans->payload_bits = payload_bits; parlio_mount_buffer(tx_unit, tx_unit->cur_trans); + atomic_store(&tx_unit->buffer_need_switch, true); } else { TickType_t queue_wait_ticks = portMAX_DELAY; if (config->flags.queue_nonblocking) { @@ -691,6 +748,31 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p return ESP_OK; } +#if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION +static bool parlio_tx_gdma_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data) +{ + parlio_tx_unit_t *tx_unit = (parlio_tx_unit_t *) user_data; + bool need_yield = false; + bool expected_state = true; + // invoke callback to notify the application + parlio_tx_buffer_switched_callback_t on_buffer_switched = tx_unit->on_buffer_switched; + if (on_buffer_switched) { + if (atomic_compare_exchange_strong(&tx_unit->buffer_need_switch, &expected_state, false)) { + parlio_tx_buffer_switched_event_data_t edata = { + // we use 2 dma links to do the buffer switch in loop transmission + .old_buffer_addr = gdma_link_get_buffer(tx_unit->dma_link[1 - tx_unit->cur_trans->dma_link_idx], 0), + .new_buffer_addr = gdma_link_get_buffer(tx_unit->dma_link[tx_unit->cur_trans->dma_link_idx], 0), + }; + if (on_buffer_switched(tx_unit, &edata, tx_unit->user_data)) { + need_yield = true; + } + } + } + + return need_yield; +} +#endif // SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION + static void parlio_tx_default_isr(void *args) { parlio_tx_unit_t *tx_unit = (parlio_tx_unit_t *)args; diff --git a/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt b/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt index bdcb01f6a0..928db0ab8b 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt +++ b/components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt @@ -10,6 +10,10 @@ if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED) list(APPEND srcs "test_parlio_bitscrambler.c") endif() +if(CONFIG_PARLIO_TX_ISR_CACHE_SAFE) + list(APPEND srcs "test_parlio_tx_cache_safe.c") +endif() + # In order for the cases defined by `TEST_CASE` to be linked into the final elf, # the component can be registered as WHOLE_ARCHIVE idf_component_register(SRCS ${srcs} @@ -21,4 +25,6 @@ idf_component_register(SRCS ${srcs} if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED) target_bitscrambler_add_src("test_parlio_tx_LSB_to_MSB.bsasm") target_bitscrambler_add_src("test_parlio_tx_multiply.bsasm") + target_bitscrambler_add_src("test_parlio_tx_in8_out32.bsasm") + target_bitscrambler_add_src("test_parlio_tx_in32_out8.bsasm") endif() diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c index 7670128be3..da09362379 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c @@ -21,13 +21,21 @@ BITSCRAMBLER_PROGRAM(bitscrambler_program_test_tx_LSB_to_MSB, "test_parlio_tx_LSB_to_MSB"); BITSCRAMBLER_PROGRAM(bitscrambler_program_test_tx_multiply, "test_parlio_tx_multiply"); +BITSCRAMBLER_PROGRAM(bitscrambler_program_test_tx_in8_out32, "test_parlio_tx_in8_out32"); +BITSCRAMBLER_PROGRAM(bitscrambler_program_test_tx_in32_out8, "test_parlio_tx_in32_out8"); + +typedef struct { + TaskHandle_t task; + size_t recv_bytes; +} test_parlio_bitscrambler_rx_ctx_t; TEST_PARLIO_CALLBACK_ATTR static bool test_parlio_rx_done_callback(parlio_rx_unit_handle_t rx_unit, const parlio_rx_event_data_t *edata, void *user_ctx) { BaseType_t high_task_wakeup = pdFALSE; - TaskHandle_t task = (TaskHandle_t)user_ctx; - vTaskNotifyGiveFromISR(task, &high_task_wakeup); + test_parlio_bitscrambler_rx_ctx_t *ctx = (test_parlio_bitscrambler_rx_ctx_t *)user_ctx; + ctx->recv_bytes = edata->recv_bytes; + vTaskNotifyGiveFromISR(ctx->task, &high_task_wakeup); return high_task_wakeup == pdTRUE; } @@ -105,10 +113,13 @@ static void test_parlio_bitscrambler(void) }; TEST_ESP_OK(parlio_new_rx_level_delimiter(&lvl_deli_cfg, &deli)); printf("register receive_done event callback\r\n"); + test_parlio_bitscrambler_rx_ctx_t rx_ctx = { + .task = xTaskGetCurrentTaskHandle(), + }; parlio_rx_event_callbacks_t rx_cbs = { .on_receive_done = test_parlio_rx_done_callback, }; - TEST_ESP_OK(parlio_rx_unit_register_event_callbacks(rx_unit, &rx_cbs, xTaskGetCurrentTaskHandle())); + TEST_ESP_OK(parlio_rx_unit_register_event_callbacks(rx_unit, &rx_cbs, &rx_ctx)); parlio_receive_config_t recv_config = { .delimiter = deli, @@ -121,11 +132,12 @@ static void test_parlio_bitscrambler(void) // Rx in MSB mode printf("enable parlio and transmit\r\n"); TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); - TEST_ESP_OK(parlio_rx_unit_enable(rx_unit, 1)); + TEST_ESP_OK(parlio_rx_unit_enable(rx_unit, true)); TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, rx_payload, TEST_PAYLOAD_SIZE, &recv_config)); TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, TEST_PAYLOAD_SIZE * sizeof(uint8_t) * 8, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(TEST_PAYLOAD_SIZE, rx_ctx.recv_bytes); for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) { printf("%.3d ", (rx_payload[i])); @@ -148,6 +160,7 @@ static void test_parlio_bitscrambler(void) TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, TEST_PAYLOAD_SIZE * sizeof(uint8_t) * 8, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(TEST_PAYLOAD_SIZE, rx_ctx.recv_bytes); for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) { printf("%.3d ", (rx_payload[i])); @@ -166,6 +179,7 @@ static void test_parlio_bitscrambler(void) TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, TEST_PAYLOAD_SIZE * sizeof(uint8_t) * 8, &transmit_config)); TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(TEST_PAYLOAD_SIZE, rx_ctx.recv_bytes); for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) { printf("%.3d ", (rx_payload[i])); @@ -187,3 +201,156 @@ TEST_CASE("parlio_tx_bitscrambler_test", "[parlio_bitscrambler]") { test_parlio_bitscrambler(); } + +#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA +static void test_parlio_bitscrambler_different_input_output_sizes(void) +{ + parlio_tx_unit_handle_t tx_unit = NULL; + parlio_tx_unit_config_t tx_config = { + .clk_src = PARLIO_CLK_SRC_DEFAULT, + .data_width = 4, + .clk_in_gpio_num = -1, // use internal clock source + .valid_gpio_num = TEST_VALID_GPIO, + .clk_out_gpio_num = TEST_CLK_GPIO, + .data_gpio_nums = { + TEST_DATA0_GPIO, + TEST_DATA1_GPIO, + TEST_DATA2_GPIO, + TEST_DATA3_GPIO, + }, + .output_clk_freq_hz = 1 * 1000 * 1000, + .trans_queue_depth = 8, + .max_transfer_size = 256, + .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, + .sample_edge = PARLIO_SAMPLE_EDGE_POS, + }; + + parlio_rx_unit_handle_t rx_unit = NULL; + parlio_rx_unit_config_t rx_config = { + .trans_queue_depth = 10, + .max_recv_size = 1024, + .data_width = 4, + .clk_src = PARLIO_CLK_SRC_DEFAULT, + .ext_clk_freq_hz = 0, + .clk_in_gpio_num = -1, + .exp_clk_freq_hz = 1 * 1000 * 1000, + .clk_out_gpio_num = -1, + .valid_gpio_num = TEST_VALID_GPIO, + .data_gpio_nums = { + TEST_DATA0_GPIO, + TEST_DATA1_GPIO, + TEST_DATA2_GPIO, + TEST_DATA3_GPIO, + }, + .flags = { + .clk_gate_en = false, + } + }; + + printf("install parlio unit\r\n"); + TEST_ESP_OK(parlio_new_tx_unit(&tx_config, &tx_unit)); + TEST_ESP_OK(parlio_new_rx_unit(&rx_config, &rx_unit)); + + printf("decorate tx unit with bitscrambler\r\n"); + TEST_ESP_OK(parlio_tx_unit_decorate_bitscrambler(tx_unit)); + + parlio_transmit_config_t transmit_config = { + .idle_value = 0x00, + .bitscrambler_program = bitscrambler_program_test_tx_in32_out8, + }; + + parlio_rx_delimiter_handle_t deli = NULL; + parlio_rx_level_delimiter_config_t lvl_deli_cfg = { + .valid_sig_line_id = PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1, + .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, + .eof_data_len = TEST_PAYLOAD_SIZE, + .timeout_ticks = 0, + .flags = { + .active_low_en = 0, + }, + }; + TEST_ESP_OK(parlio_new_rx_level_delimiter(&lvl_deli_cfg, &deli)); + printf("register receive_done event callback\r\n"); + test_parlio_bitscrambler_rx_ctx_t rx_ctx = { + .task = xTaskGetCurrentTaskHandle(), + }; + parlio_rx_event_callbacks_t rx_cbs = { + .on_receive_done = test_parlio_rx_done_callback, + }; + TEST_ESP_OK(parlio_rx_unit_register_event_callbacks(rx_unit, &rx_cbs, &rx_ctx)); + + parlio_receive_config_t recv_config = { + .delimiter = deli, + .flags.partial_rx_en = false, + }; + + uint8_t tx_payload[TEST_PAYLOAD_SIZE * 4] = {0}; + for (int i = 0; i < TEST_PAYLOAD_SIZE * 4; i++) { + tx_payload[i] = i; + } + + __attribute__((aligned(TEST_PAYLOAD_SIZE))) uint8_t rx_payload[TEST_PAYLOAD_SIZE] = {0}; + TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); + TEST_ESP_OK(parlio_rx_unit_enable(rx_unit, true)); + + // test input size is larger than output size + TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, rx_payload, TEST_PAYLOAD_SIZE, &recv_config)); + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, 4 * TEST_PAYLOAD_SIZE * sizeof(uint8_t) * 8, &transmit_config)); + + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(TEST_PAYLOAD_SIZE, rx_ctx.recv_bytes); + + for (int i = 0; i < TEST_PAYLOAD_SIZE; i++) { + printf("%.3d ", (rx_payload[i])); + TEST_ASSERT_EQUAL(tx_payload[i * 4 + 3], rx_payload[i]); + if ((i + 1) % 16 == 0) { + printf("\n"); + } + } + printf("\n"); + + // test input size is smaller than output size + transmit_config.bitscrambler_program = bitscrambler_program_test_tx_in8_out32; + + TEST_ESP_OK(parlio_rx_unit_receive(rx_unit, rx_payload, TEST_PAYLOAD_SIZE, &recv_config)); + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, tx_payload, (TEST_PAYLOAD_SIZE / 4) * sizeof(uint8_t) * 8, &transmit_config)); + + TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000))); + TEST_ASSERT_EQUAL(TEST_PAYLOAD_SIZE, rx_ctx.recv_bytes); + + for (int i = 0; i < TEST_PAYLOAD_SIZE / 4; i++) { + uint32_t *test_value = (uint32_t *)&rx_payload[i * 4]; + printf("0x%lx ", *test_value); + switch (i % 4) { + case 0: + TEST_ASSERT_EQUAL(0x11111, *test_value); + break; + case 1: + TEST_ASSERT_EQUAL(0x22222, *test_value); + break; + case 2: + TEST_ASSERT_EQUAL(0x33333, *test_value); + break; + case 3: + TEST_ASSERT_EQUAL(0x00000, *test_value); + break; + } + if ((i + 1) % 4 == 0) { + printf("\n"); + } + } + + TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); + TEST_ESP_OK(parlio_tx_unit_undecorate_bitscrambler(tx_unit)); + TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); + TEST_ESP_OK(parlio_rx_unit_disable(rx_unit)); + TEST_ESP_OK(parlio_del_rx_delimiter(deli)); + TEST_ESP_OK(parlio_del_rx_unit(rx_unit)); +} + +TEST_CASE("parlio_tx_bitscrambler_different_input_output_sizes_test", "[parlio_bitscrambler]") +{ + test_parlio_bitscrambler_different_input_output_sizes(); +} +#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c index e32472f4ec..942e037608 100644 --- a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c @@ -518,6 +518,22 @@ TEST_CASE("parallel tx unit use external non-free running clock", "[parlio_tx]") }; #if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION +typedef struct { + uint32_t switch_count; + void *old_buffer_addr[5]; + void *new_buffer_addr[5]; +} test_parlio_tx_buffer_switched_context_t; + +TEST_PARLIO_CALLBACK_ATTR +static bool test_parlio_tx_buffer_switched_callback(parlio_tx_unit_handle_t tx_unit, const parlio_tx_buffer_switched_event_data_t *edata, void *user_ctx) +{ + test_parlio_tx_buffer_switched_context_t *context = (test_parlio_tx_buffer_switched_context_t *)user_ctx; + context->old_buffer_addr[context->switch_count] = edata->old_buffer_addr; + context->new_buffer_addr[context->switch_count] = edata->new_buffer_addr; + context->switch_count++; + return false; +} + TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]") { printf("install parlio tx unit\r\n"); @@ -545,6 +561,16 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]") .sample_edge = PARLIO_SAMPLE_EDGE_POS, }; TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); + + printf("register trans_done event callback\r\n"); + parlio_tx_event_callbacks_t cbs = { + .on_buffer_switched = test_parlio_tx_buffer_switched_callback, + }; + test_parlio_tx_buffer_switched_context_t context = { + .switch_count = 0, + }; + TEST_ESP_OK(parlio_tx_unit_register_event_callbacks(tx_unit, &cbs, &context)); + TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); printf("send packets and check event is fired\r\n"); @@ -560,37 +586,48 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]") payload_loop2[i] = 255 - i; payload_oneshot[i] = i * 2 + 1; } - if (parlio_ll_tx_support_dma_eof(NULL)) { // for some chips, only support in particular ECO version - transmit_config.flags.loop_transmission = true; - int lopp_count = 3; - while (lopp_count--) { - TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_loop1, 256 * sizeof(uint8_t) * 8, &transmit_config)); - vTaskDelay(pdMS_TO_TICKS(10)); - // Should be sent after the previous frame has been completely sent - TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_loop2, 256 * sizeof(uint8_t) * 8, &transmit_config)); - vTaskDelay(pdMS_TO_TICKS(10)); - } - transmit_config.flags.loop_transmission = false; - // should be pending in queue - TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_oneshot, 256 * sizeof(uint8_t) * 8, &transmit_config)); - transmit_config.flags.loop_transmission = true; - // there is a oneshot trans in queue, should also be pending in queue + transmit_config.flags.loop_transmission = true; + int lopp_count = 3; + while (lopp_count--) { TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_loop1, 256 * sizeof(uint8_t) * 8, &transmit_config)); - - TEST_ESP_ERR(ESP_ERR_TIMEOUT, parlio_tx_unit_wait_all_done(tx_unit, 50)); - - // stop infinite loop transmission - parlio_tx_unit_disable(tx_unit); - // We should see 1 oneshot frame and 1 loop transmission (both pending in queue) - parlio_tx_unit_enable(tx_unit); - vTaskDelay(pdMS_TO_TICKS(10)); - // stop the second infinite loop transmission - parlio_tx_unit_disable(tx_unit); - parlio_tx_unit_enable(tx_unit); - } else { - TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, parlio_tx_unit_transmit(tx_unit, payload_loop1, 256 * sizeof(uint8_t) * 8, &transmit_config)); + // Should be sent after the previous frame has been completely sent + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_loop2, 256 * sizeof(uint8_t) * 8, &transmit_config)); + vTaskDelay(pdMS_TO_TICKS(10)); + } + + transmit_config.flags.loop_transmission = false; + // should be pending in queue + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_oneshot, 256 * sizeof(uint8_t) * 8, &transmit_config)); + transmit_config.flags.loop_transmission = true; + // there is a oneshot trans in queue, should also be pending in queue + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload_loop1, 256 * sizeof(uint8_t) * 8, &transmit_config)); + + TEST_ESP_ERR(ESP_ERR_TIMEOUT, parlio_tx_unit_wait_all_done(tx_unit, 50)); + + // stop infinite loop transmission + parlio_tx_unit_disable(tx_unit); + // We should see 1 oneshot frame and 1 loop transmission (both pending in queue) + parlio_tx_unit_enable(tx_unit); + + vTaskDelay(pdMS_TO_TICKS(10)); + // stop the second infinite loop transmission + parlio_tx_unit_disable(tx_unit); + parlio_tx_unit_enable(tx_unit); + + // total 5 switch events + TEST_ASSERT_EQUAL(5, context.switch_count); + for (int i = 0; i < context.switch_count; i++) { + void *old_buffer_addr = context.old_buffer_addr[i]; + void *new_buffer_addr = context.new_buffer_addr[i]; + if (i % 2 == 0) { + TEST_ASSERT_EQUAL(payload_loop1, old_buffer_addr); + TEST_ASSERT_EQUAL(payload_loop2, new_buffer_addr); + } else { + TEST_ASSERT_EQUAL(payload_loop2, old_buffer_addr); + TEST_ASSERT_EQUAL(payload_loop1, new_buffer_addr); + } } TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1)); @@ -598,3 +635,51 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]") TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); } #endif // SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION + +#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA +TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen_eof", "[parlio_tx]") +{ + printf("install parlio tx unit\r\n"); + parlio_tx_unit_handle_t tx_unit = NULL; + parlio_tx_unit_config_t config = { + .clk_src = PARLIO_CLK_SRC_DEFAULT, + .data_width = 4, + .clk_in_gpio_num = -1, // use internal clock source + .valid_gpio_num = TEST_VALID_GPIO, // generate the valid signal + .clk_out_gpio_num = TEST_CLK_GPIO, + .data_gpio_nums = { + TEST_DATA0_GPIO, + TEST_DATA1_GPIO, + TEST_DATA2_GPIO, + TEST_DATA3_GPIO, + }, + .output_clk_freq_hz = 10 * 1000 * 1000, + .trans_queue_depth = 1, + .max_transfer_size = 100 * 1024, + .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, + .sample_edge = PARLIO_SAMPLE_EDGE_POS, + .flags.clk_gate_en = true, + }; + + TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); + TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); + + const size_t buffer_size = 100 * 1024; // 100KB, larger than the 65535 bytes limit + uint8_t *buffer = heap_caps_malloc(buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(buffer); + for (int i = 0; i < buffer_size; i++) { + buffer[i] = i; + } + + parlio_transmit_config_t transmit_config = { + .idle_value = 0x00, + }; + + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, buffer, buffer_size * 8, &transmit_config)); + TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1)); + + TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); + TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); + free(buffer); +} +#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c new file mode 100644 index 0000000000..1255fd9c72 --- /dev/null +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_cache_safe.c @@ -0,0 +1,76 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "unity.h" +#include "unity_test_utils.h" +#include "driver/parlio_tx.h" +#include "driver/gpio.h" +#include "hal/parlio_ll.h" +#include "soc/soc_caps.h" +#include "esp_attr.h" +#include "test_board.h" + +static void IRAM_ATTR test_delay_post_cache_disable(void *args) +{ + esp_rom_delay_us(100000); +} + +static void test_parlio_tx_cache_safe(void) +{ + printf("install parlio tx unit\r\n"); + parlio_tx_unit_handle_t tx_unit = NULL; + parlio_tx_unit_config_t config = { + .clk_src = PARLIO_CLK_SRC_DEFAULT, + .data_width = 1, + .clk_in_gpio_num = -1, // use internal clock source + .valid_gpio_num = TEST_VALID_GPIO, // generate the valid signal + .clk_out_gpio_num = TEST_CLK_GPIO, + .data_gpio_nums = { + TEST_DATA0_GPIO, + }, + .output_clk_freq_hz = 10 * 1000 * 1000, + .trans_queue_depth = 4, + .max_transfer_size = 65535, + .bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB, + .sample_edge = PARLIO_SAMPLE_EDGE_POS, + }; + + TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit)); + TEST_ESP_OK(parlio_tx_unit_enable(tx_unit)); + + const size_t buffer_size = 160 * 1000; + const size_t chunk_size = buffer_size / 4; // 40KB per trunk + uint8_t *buffer = heap_caps_malloc(buffer_size, MALLOC_CAP_8BIT | MALLOC_CAP_DMA); + TEST_ASSERT_NOT_NULL(buffer); + for (int i = 0; i < buffer_size; i++) { + buffer[i] = i; + } + + parlio_transmit_config_t transmit_config = { + .idle_value = 0x00, + }; + + for (int i = 0; i < 20; i++) { + TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, buffer + (i % 4) * chunk_size, chunk_size * 8, &transmit_config)); + } + // during the cache disabled period, the parlio tx unit can be scheduled as well + unity_utils_run_cache_disable_stub(test_delay_post_cache_disable, NULL); + TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1)); + + TEST_ESP_OK(parlio_tx_unit_disable(tx_unit)); + TEST_ESP_OK(parlio_del_tx_unit(tx_unit)); + free(buffer); + +} + +TEST_CASE("parlio tx works with cache disabled", "[parlio]") +{ + test_parlio_tx_cache_safe(); +} diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in32_out8.bsasm b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in32_out8.bsasm new file mode 100644 index 0000000000..947003b2a8 --- /dev/null +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in32_out8.bsasm @@ -0,0 +1,14 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 + + +cfg prefetch true # enable data prefetch +cfg eof_on upstream # set EOF on upstream +cfg trailing_bytes 9 # due to prefetch is enable, upstream is 8 bytes ahead of downstream + +loop: + set 0..7 24..31, + + write 8, + read 32, + jmp loop diff --git a/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in8_out32.bsasm b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in8_out32.bsasm new file mode 100644 index 0000000000..486430fc82 --- /dev/null +++ b/components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx_in8_out32.bsasm @@ -0,0 +1,21 @@ +# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: Unlicense OR CC0-1.0 + +cfg prefetch false # disable data prefetch +cfg eof_on upstream # set EOF on upstream +cfg trailing_bytes 9 +cfg lut_width_bits 32 + +# Define contents that stored in the lookup table +lut 0x00011111 # index 0 +lut 0x00022222 # index 1 +lut 0x00033333 # index 2 +lut 0x00000000 # index 3 + +set 16..18 L # init the LUT index: 0 (0b000) + +loop: + read 8, + set 31..0 L31..L0, + write 32, + jmp loop diff --git a/components/esp_driver_rmt/src/rmt_common.c b/components/esp_driver_rmt/src/rmt_common.c index ba6c0a5e7d..6bd08bf63b 100644 --- a/components/esp_driver_rmt/src/rmt_common.c +++ b/components/esp_driver_rmt/src/rmt_common.c @@ -240,7 +240,7 @@ esp_err_t rmt_select_periph_clock(rmt_channel_handle_t chan, rmt_clock_source_t ESP_RETURN_ON_ERROR(ret, TAG, "create pm lock failed"); #endif // CONFIG_PM_ENABLE - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed"); uint32_t real_div; #if SOC_RMT_CHANNEL_CLK_INDEPENDENT uint32_t periph_src_clk_hz = 0; diff --git a/components/esp_driver_spi/src/gpspi/spi_master.c b/components/esp_driver_spi/src/gpspi/spi_master.c index daf953fb92..1a0519724f 100644 --- a/components/esp_driver_spi/src/gpspi/spi_master.c +++ b/components/esp_driver_spi/src/gpspi/spi_master.c @@ -424,7 +424,7 @@ esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interfa spi_clock_source_t clk_src = dev_config->clock_source ? dev_config->clock_source : SPI_CLK_SRC_DEFAULT; uint32_t clock_source_hz = 0; uint32_t clock_source_div = 1; - esp_clk_tree_enable_src(clk_src, true); + SPI_CHECK(esp_clk_tree_enable_src(clk_src, true) == ESP_OK, "clock source enable failed", ESP_ERR_INVALID_STATE); esp_clk_tree_src_get_freq_hz(clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_source_hz); #if SPI_LL_SUPPORT_CLK_SRC_PRE_DIV SPI_CHECK((dev_config->clock_speed_hz > 0) && (dev_config->clock_speed_hz <= MIN(clock_source_hz / 2, (80 * 1000000))), "invalid sclk speed", ESP_ERR_INVALID_ARG); @@ -601,7 +601,7 @@ esp_err_t spi_bus_remove_device(spi_device_handle_t handle) periph_rtc_dig_clk8m_disable(); } #endif - esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false); + SPI_CHECK(esp_clk_tree_enable_src(handle->hal_dev.timing_conf.clock_source, false) == ESP_OK, "clock source disable failed", ESP_ERR_INVALID_STATE); //return int spics_io_num = handle->cfg.spics_io_num; diff --git a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c index b078abbe17..20dfd46b9e 100644 --- a/components/esp_driver_spi/test_apps/master/main/test_spi_master.c +++ b/components/esp_driver_spi/test_apps/master/main/test_spi_master.c @@ -150,7 +150,9 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]") spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_source = spi_clk_sour[sour_idx]; devcfg.clock_speed_hz = MIN(IDF_TARGET_MAX_SPI_CLK_FREQ, clock_source_hz) >> test_time; +#if CONFIG_IDF_TARGET_ESP32 devcfg.flags |= SPI_DEVICE_HALFDUPLEX; //esp32 half duplex to work on high freq +#endif #if SOC_SPI_SUPPORT_CLK_RC_FAST if (devcfg.clock_source == SPI_CLK_SRC_RC_FAST) { devcfg.clock_speed_hz /= 2; //rc_fast have bad accuracy, test at low speed @@ -160,6 +162,13 @@ TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]") // one trans first to trigger lazy load TEST_ESP_OK(spi_device_polling_transmit(handle, &trans)); + // test single tx/rx under full duplex mode, refer to `TEST_CASE_MULTIPLE_DEVICES("SPI Master: FD, DMA, Master Single Direction Test"...` + if (!(devcfg.flags && SPI_DEVICE_HALFDUPLEX)) { + trans.tx_buffer = NULL; + trans.rxlength = trans.length; + trans.rx_buffer = sendbuf; + } + // calculate theoretical transaction time by actual freq and trans length int real_freq_khz; spi_device_get_actual_freq(handle, &real_freq_khz); diff --git a/components/esp_driver_tsens/src/temperature_sensor.c b/components/esp_driver_tsens/src/temperature_sensor.c index ef002f1538..52e487bb9d 100644 --- a/components/esp_driver_tsens/src/temperature_sensor.c +++ b/components/esp_driver_tsens/src/temperature_sensor.c @@ -66,9 +66,18 @@ static esp_err_t temperature_sensor_choose_best_range(temperature_sensor_handle_ for (int i = 0 ; i < TEMPERATURE_SENSOR_ATTR_RANGE_NUM; i++) { if ((tsens_config->range_min >= s_tsens_attribute_copy[i].range_min) && (tsens_config->range_max <= s_tsens_attribute_copy[i].range_max)) { tsens->tsens_attribute = &s_tsens_attribute_copy[i]; + int original_idx = -1; + for (int j = 0; j < TEMPERATURE_SENSOR_ATTR_RANGE_NUM; j++) { + if (temperature_sensor_attributes[j].reg_val == s_tsens_attribute_copy[i].reg_val) { + original_idx = j; + break; + } + } + if (original_idx != -1) { + temp_sensor_sync_tsens_idx(original_idx); + } break; } - temp_sensor_sync_tsens_idx(i); } ESP_RETURN_ON_FALSE(tsens->tsens_attribute != NULL, ESP_ERR_INVALID_ARG, TAG, "Out of testing range"); return ESP_OK; diff --git a/components/esp_driver_twai/esp_twai_onchip.c b/components/esp_driver_twai/esp_twai_onchip.c index 481e9dfcb4..d05e1e8cbc 100644 --- a/components/esp_driver_twai/esp_twai_onchip.c +++ b/components/esp_driver_twai/esp_twai_onchip.c @@ -381,6 +381,8 @@ static esp_err_t _node_set_bit_timing(twai_node_handle_t node, const twai_timing #endif if (new_clock_src != twai_ctx->curr_clk_src) { + // TODO: IDF-13144 + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)(new_clock_src), true)); twai_ctx->curr_clk_src = new_clock_src; _twai_rcc_clock_sel(twai_ctx->ctrlr_id, new_clock_src); } diff --git a/components/esp_driver_uart/src/uart.c b/components/esp_driver_uart/src/uart.c index 12733ec167..8eb9caa1eb 100644 --- a/components/esp_driver_uart/src/uart.c +++ b/components/esp_driver_uart/src/uart.c @@ -109,6 +109,7 @@ static const char *UART_TAG = "uart"; #define UART_CONTEXT_INIT_DEF(uart_num) { \ .port_id = uart_num, \ .hal.dev = UART_LL_GET_HW(uart_num), \ + .sclk_sel = -1, \ INIT_CRIT_SECTION_LOCK_IN_STRUCT(spinlock) \ .hw_enabled = false, \ .tx_io_num = -1, \ @@ -175,6 +176,7 @@ typedef struct uart_context_t { _lock_t mutex; /*!< Protect uart_module_enable, uart_module_disable, retention, etc. */ uart_port_t port_id; uart_hal_context_t hal; /*!< UART hal context*/ + soc_module_clk_t sclk_sel; /*!< UART port clock source selection*/ DECLARE_CRIT_SECTION_LOCK_IN_STRUCT(spinlock) bool hw_enabled; int tx_io_num; @@ -973,6 +975,56 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf uart_module_enable(uart_num); + soc_module_clk_t uart_sclk_sel = 0; // initialize to an invalid module clock ID + if (uart_num < SOC_UART_HP_NUM) { + uart_sclk_sel = (soc_module_clk_t)((uart_config->source_clk) ? uart_config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock + } +#if (SOC_UART_LP_NUM >= 1) + else { + uart_sclk_sel = (soc_module_clk_t)((uart_config->lp_source_clk) ? uart_config->lp_source_clk : LP_UART_SCLK_DEFAULT); + } +#endif + uint32_t sclk_freq; + ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "invalid src_clk"); + + // Enable the newly selected clock source. + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), UART_TAG, "clock source enable failed"); +#if SOC_UART_SUPPORT_RTC_CLK + if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { + periph_rtc_dig_clk8m_enable(); + } +#endif + + bool success = false; + UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); + soc_module_clk_t uart_old_sclk_sel = uart_context[uart_num].sclk_sel; + uart_context[uart_num].sclk_sel = uart_sclk_sel; + uart_hal_init(&(uart_context[uart_num].hal), uart_num); + if (uart_num < SOC_UART_HP_NUM) { + HP_UART_SRC_CLK_ATOMIC() { + uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel); + success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); + } + } +#if (SOC_UART_LP_NUM >= 1) + else { + LP_UART_SRC_CLK_ATOMIC() { + lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel); + } + success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq); + } +#endif + // Disable the previously selected clock source + uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); + uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits); + uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits); + uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT); + uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh); + UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); + uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); + uart_hal_txfifo_rst(&(uart_context[uart_num].hal)); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_old_sclk_sel, false), UART_TAG, "clock source disable failed"); + ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable"); #if SOC_UART_SUPPORT_SLEEP_RETENTION && CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP // Create sleep retention link if desired if (uart_num != CONFIG_ESP_CONSOLE_UART_NUM && uart_num < SOC_UART_HP_NUM) { @@ -994,52 +1046,6 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf _lock_release(&(uart_context[uart_num].mutex)); } #endif - - soc_module_clk_t uart_sclk_sel = 0; // initialize to an invalid module clock ID - if (uart_num < SOC_UART_HP_NUM) { - uart_sclk_sel = (soc_module_clk_t)((uart_config->source_clk) ? uart_config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock - } -#if (SOC_UART_LP_NUM >= 1) - else { - uart_sclk_sel = (soc_module_clk_t)((uart_config->lp_source_clk) ? uart_config->lp_source_clk : LP_UART_SCLK_DEFAULT); - } -#endif - -#if SOC_UART_SUPPORT_RTC_CLK - if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { - periph_rtc_dig_clk8m_enable(); - } -#endif - uint32_t sclk_freq; - ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), UART_TAG, "invalid src_clk"); - - bool success = false; - UART_ENTER_CRITICAL(&(uart_context[uart_num].spinlock)); - uart_hal_init(&(uart_context[uart_num].hal), uart_num); - if (uart_num < SOC_UART_HP_NUM) { - esp_clk_tree_enable_src((soc_module_clk_t)uart_sclk_sel, true); - HP_UART_SRC_CLK_ATOMIC() { - uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel); - success = uart_hal_set_baudrate(&(uart_context[uart_num].hal), uart_config->baud_rate, sclk_freq); - } - } -#if (SOC_UART_LP_NUM >= 1) - else { - LP_UART_SRC_CLK_ATOMIC() { - lp_uart_ll_set_source_clk(uart_context[uart_num].hal.dev, (soc_periph_lp_uart_clk_src_t)uart_sclk_sel); - } - success = lp_uart_ll_set_baudrate(uart_context[uart_num].hal.dev, uart_config->baud_rate, sclk_freq); - } -#endif - uart_hal_set_parity(&(uart_context[uart_num].hal), uart_config->parity); - uart_hal_set_data_bit_num(&(uart_context[uart_num].hal), uart_config->data_bits); - uart_hal_set_stop_bits(&(uart_context[uart_num].hal), uart_config->stop_bits); - uart_hal_set_tx_idle_num(&(uart_context[uart_num].hal), UART_TX_IDLE_NUM_DEFAULT); - uart_hal_set_hw_flow_ctrl(&(uart_context[uart_num].hal), uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh); - UART_EXIT_CRITICAL(&(uart_context[uart_num].spinlock)); - uart_hal_rxfifo_rst(&(uart_context[uart_num].hal)); - uart_hal_txfifo_rst(&(uart_context[uart_num].hal)); - ESP_RETURN_ON_FALSE(success, ESP_FAIL, UART_TAG, "baud rate unachievable"); return ESP_OK; } @@ -1910,6 +1916,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num) uart_free_driver_obj(p_uart_obj[uart_num]); p_uart_obj[uart_num] = NULL; + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed"); #if SOC_UART_SUPPORT_RTC_CLK soc_module_clk_t sclk = 0; uart_hal_get_sclk(&(uart_context[uart_num].hal), &sclk); @@ -2118,7 +2125,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det uart_sclk_sel = (soc_module_clk_t)((config->source_clk) ? config->source_clk : UART_SCLK_DEFAULT); // if no specifying the clock source (soc_module_clk_t starts from 1), then just use the default clock uint32_t sclk_freq = 0; ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz(uart_sclk_sel, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq), err, UART_TAG, "invalid source_clk"); - esp_clk_tree_enable_src(uart_sclk_sel, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src(uart_sclk_sel, true), err, UART_TAG, "clock source enable failed"); #if SOC_UART_SUPPORT_RTC_CLK if (uart_sclk_sel == (soc_module_clk_t)UART_SCLK_RTC) { periph_rtc_dig_clk8m_enable(); @@ -2180,6 +2187,7 @@ esp_err_t uart_detect_bitrate_stop(uart_port_t uart_num, bool deinit, uart_bitra if (deinit) { // release the port uart_release_pin(uart_num); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed"); #if SOC_UART_SUPPORT_RTC_CLK if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) { periph_rtc_dig_clk8m_disable(); diff --git a/components/esp_eth/src/mac/esp_eth_mac_esp.c b/components/esp_eth/src/mac/esp_eth_mac_esp.c index 0b7dc19268..c9f9084b8e 100644 --- a/components/esp_eth/src/mac/esp_eth_mac_esp.c +++ b/components/esp_eth/src/mac/esp_eth_mac_esp.c @@ -521,7 +521,7 @@ static esp_err_t emac_config_pll_clock(emac_esp32_t *emac) real_freq /= div; } // Enable 50MHz MPLL derived clock - esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F50M, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F50M, true), TAG, "clock source enable failed"); #endif // If the difference of real RMII CLK frequency is not within 50 ppm, i.e. 2500 Hz, the (A/M)PLL is unusable ESP_RETURN_ON_FALSE(abs((int)real_freq - (int)expt_freq) <= 2500, diff --git a/components/esp_hw_support/dma/gdma_link.c b/components/esp_hw_support/dma/gdma_link.c index 6a3199ea91..f5a9dbe009 100644 --- a/components/esp_hw_support/dma/gdma_link.c +++ b/components/esp_hw_support/dma/gdma_link.c @@ -283,3 +283,27 @@ size_t gdma_link_count_buffer_size_till_eof(gdma_link_list_handle_t list, int st } return buf_size; } + +void *gdma_link_get_buffer(gdma_link_list_handle_t list, int item_index) +{ + if (!list) { + return NULL; + } + int num_items = list->num_items; + // ensure the item_index is between 0 and `num_items - 1` + item_index = (item_index % num_items + num_items) % num_items; + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + return lli->buffer; +} + +size_t gdma_link_get_length(gdma_link_list_handle_t list, int item_index) +{ + if (!list) { + return 0; + } + int num_items = list->num_items; + // ensure the item_index is between 0 and `num_items - 1` + item_index = (item_index % num_items + num_items) % num_items; + gdma_link_list_item_t *lli = (gdma_link_list_item_t *)(list->items_nc + item_index * list->item_size); + return lli->dw0.length; +} diff --git a/components/esp_hw_support/dma/include/esp_private/gdma_link.h b/components/esp_hw_support/dma/include/esp_private/gdma_link.h index 7ab326edcc..bd1dd60f5b 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma_link.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma_link.h @@ -176,6 +176,24 @@ esp_err_t gdma_link_get_owner(gdma_link_list_handle_t list, int item_index, gdma */ size_t gdma_link_count_buffer_size_till_eof(gdma_link_list_handle_t list, int start_item_index); +/** + * @brief Get the buffer of a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item + * @return Buffer of the link list item + */ +void* gdma_link_get_buffer(gdma_link_list_handle_t list, int item_index); + +/** + * @brief Get the length of the buffer of a DMA link list item + * + * @param[in] list Link list handle, allocated by `gdma_new_link_list` + * @param[in] item_index Index of the link list item + * @return Length of the buffer of the link list item + */ +size_t gdma_link_get_length(gdma_link_list_handle_t list, int item_index); + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_crypto_lock.h b/components/esp_hw_support/include/esp_crypto_lock.h index c17333700e..b399686819 100644 --- a/components/esp_hw_support/include/esp_crypto_lock.h +++ b/components/esp_hw_support/include/esp_crypto_lock.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/components/esp_hw_support/include/esp_hmac.h b/components/esp_hw_support/include/esp_hmac.h index c663aef2c6..566deea0d6 100644 --- a/components/esp_hw_support/include/esp_hmac.h +++ b/components/esp_hw_support/include/esp_hmac.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,7 @@ #include #include "esp_err.h" #include "soc/soc_caps.h" +#include "hal/hmac_types.h" #if !SOC_HMAC_SUPPORTED && !CI_HEADER_CHECK #error "HMAC peripheral is not supported for the selected target" @@ -18,19 +19,6 @@ extern "C" { #endif -/** - * The possible efuse keys for the HMAC peripheral - */ -typedef enum { - HMAC_KEY0 = 0, - HMAC_KEY1, - HMAC_KEY2, - HMAC_KEY3, - HMAC_KEY4, - HMAC_KEY5, - HMAC_KEY_MAX -} hmac_key_id_t; - /** * @brief * Calculate the HMAC of a given message. diff --git a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h index 4a3c895b4f..5755cd8232 100644 --- a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h +++ b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -78,20 +78,25 @@ uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t prec /** * @brief Enable / Disable the clock gate of the clock source * + * @note The clock enable status is maintained by reference counter and + * its status is not reset after software restart. + * * @param[in] clk_src Clock source available to modules, in soc_module_clk_t * @param[in] enable Enable / Disable the clock gate * - * @note !!! WARNING !!! - * There's no reference counter to protect the clock source status, the caller should use the interface - * with CAUTION to disable the clock source to avoid damaging other peripherals that are dependent on - * the clock source. - * * @return * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error */ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable); +#if SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED +/** + * @brief Set the clock source not in use on the clock tree to the gated state. + */ +void esp_clk_tree_initialize(void); +#endif + #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h index fcdebb41ac..14fa6bf54c 100644 --- a/components/esp_hw_support/include/esp_private/regi2c_ctrl.h +++ b/components/esp_hw_support/include/esp_private/regi2c_ctrl.h @@ -7,6 +7,7 @@ #pragma once #include +#include #include "sdkconfig.h" #include "esp_rom_regi2c.h" #include "soc/regi2c_defs.h" @@ -14,6 +15,10 @@ #include "esp_private/periph_ctrl.h" #include "hal/regi2c_ctrl_ll.h" +#ifndef BOOTLOADER_BUILD +#include "esp_private/esp_clk_tree_common.h" +#endif + #ifdef __cplusplus extern "C" { #endif @@ -26,22 +31,32 @@ extern "C" { #else // !BOOTLOADER_BUILD +static inline __attribute__((always_inline)) void ANA_I2C_SRC_CLOCK_ENABLE(bool enable) { +#if SOC_CLK_ANA_I2C_MST_DEPENDS_ON_MODEM_APB + esp_clk_tree_enable_src(SOC_MOD_CLK_MODEM_APB, enable); +#endif +} + #if SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE // This clock needs to be enabled for regi2c write/read, pll calibaration, PHY, RNG, ADC, etc. // Use reference count to manage the analog i2c master clock -#define ANALOG_CLOCK_ENABLE() \ +#define ANALOG_CLOCK_ENABLE() { \ + ANA_I2C_SRC_CLOCK_ENABLE(true); \ PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \ if (ref_count == 0) { \ regi2c_ctrl_ll_master_enable_clock(true); \ } \ - } + } \ + } -#define ANALOG_CLOCK_DISABLE() \ +#define ANALOG_CLOCK_DISABLE() { \ PERIPH_RCC_RELEASE_ATOMIC(PERIPH_ANA_I2C_MASTER_MODULE, ref_count) { \ if (ref_count == 0) { \ regi2c_ctrl_ll_master_enable_clock(false); \ } \ - } + } \ + ANA_I2C_SRC_CLOCK_ENABLE(false); \ + } #else #define ANALOG_CLOCK_ENABLE() diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index 9218409e71..1ee15d6e2f 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -16,6 +16,7 @@ entries: if PM_SLP_IRAM_OPT = y: rtc_clk (noflash) rtc_time (noflash_text) + esp_clk_tree: esp_clk_tree_enable_src (noflash) if IDF_TARGET_ESP32 = y: rtc_clk:rtc_clk_cpu_freq_to_pll_mhz (noflash) rtc_clk:rtc_clk_cpu_freq_to_xtal (noflash) diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c index 3e6117ddff..8bae15abc3 100644 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c +++ b/components/esp_hw_support/lowpower/port/esp32c61/sleep_clock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,24 +19,24 @@ esp_err_t sleep_clock_system_retention_init(void *arg) { const static sleep_retention_entries_config_t pcr_regs_retention[] = { /* Enable i2c master clock */ - [0] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(0), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = ENTRY(0) }, /* Start BBPLL self-calibration */ - [1] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, - [2] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(1), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(2), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, /* Wait calibration done */ - [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, + [3] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(3), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE, I2C_MST_BBPLL_CAL_DONE, 1, 0), .owner = ENTRY(0) }, /* Stop BBPLL self-calibration */ - [4] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(4), I2C_ANA_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(5), I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, I2C_MST_BBPLL_STOP_FORCE_HIGH, 1, 0), .owner = ENTRY(0) }, /* Clock configuration retention */ - [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0)}, /* Wait PMU_WAIT_XTL_STABLE done */ - [7] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */ - [8] = { .config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [6] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PCR_LINK(6), PMU_CLK_STATE0_REG, PMU_STABLE_XPD_BBPLL_STATE, PMU_STABLE_XPD_BBPLL_STATE_M, 1, 0), .owner = ENTRY(0) }, /* Wait PMU_WAIT_XTL_STABLE done */ + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(7), PCR_AHB_FREQ_CONF_REG, 0, PCR_AHB_DIV_NUM, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, /* Set AHB bus frequency to XTAL frequency */ + [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(8), PCR_BUS_CLK_UPDATE_REG, 1, PCR_BUS_CLOCK_UPDATE, 1, 0), .owner = ENTRY(0) | ENTRY(1) }, + [9] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(9), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M,0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */ + [10] = {.config = REGDMA_LINK_WRITE_INIT(REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M,1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */ #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP - [9] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(9), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }, + [11] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCR_LINK(11), DR_REG_PCR_BASE, DR_REG_PCR_BASE, 63, 0, 0, 0xfd73ffff, 0xfdffffff, 0xe001, 0x0), .owner = ENTRY(0) | ENTRY(1) }, #endif - [10] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(10), LP_ANA_POWER_GLITCH_CNTL_REG, 0, LP_ANA_POWER_GLITCH_RESET_ENA_M, 0, 1), .owner = ENTRY(0) | ENTRY(1)}, /* Disable power glitch detector on sleep backup */ - [11] = {.config = REGDMA_LINK_WRITE_INIT (REGDMA_PCR_LINK(11), LP_ANA_POWER_GLITCH_CNTL_REG, 0xF, LP_ANA_POWER_GLITCH_RESET_ENA_M, 1, 0), .owner = ENTRY(0) | ENTRY(1)}, /* Enable power glitch detector on wakeup restore */ }; esp_err_t err = sleep_retention_entries_create(pcr_regs_retention, ARRAY_SIZE(pcr_regs_retention), REGDMA_LINK_PRI_SYS_CLK, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM); @@ -82,7 +82,9 @@ bool clock_domain_pd_allowed(void) * necessary to check the state of CLOCK_MODEM to determine MODEM domain on * or off. The clock and reset of digital peripherals are managed through * PCR, with TOP domain similar to MODEM domain. */ +#if SOC_WIFI_SUPPORTED || SOC_BT_SUPPORTED sleep_retention_module_bitmap_t modem_clk_dep_modules = (sleep_retention_module_bitmap_t){ .bitmap = { 0 } }; +#endif #if SOC_WIFI_SUPPORTED modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_MAC >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_MAC % 32); modem_clk_dep_modules.bitmap[SLEEP_RETENTION_MODULE_WIFI_BB >> 5] |= BIT(SLEEP_RETENTION_MODULE_WIFI_BB % 32); diff --git a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c b/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c deleted file mode 100644 index 3a1cad1728..0000000000 --- a/components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include "esp_attr.h" -#include "esp_check.h" -#include "esp_sleep.h" -#include "esp_log.h" -#include "esp_heap_caps.h" -#include "soc/soc_caps.h" -#include "sdkconfig.h" -#include "soc/spi_mem_reg.h" -#include "esp_private/startup_internal.h" - -static const char *TAG = "sleep_mmu"; - -typedef struct { - uint32_t start; - uint32_t end; -} mmu_domain_dev_regs_region_t; - -typedef struct { - mmu_domain_dev_regs_region_t *region; - int region_num; - uint32_t *regs_frame; -} mmu_domain_dev_sleep_frame_t; - -/** - * Internal structure which holds all requested light sleep mmu retention parameters - */ -typedef struct { - struct { - mmu_domain_dev_sleep_frame_t *mmu_table_frame; - } retent; -} sleep_mmu_retention_t; - -static DRAM_ATTR __attribute__((unused)) sleep_mmu_retention_t s_mmu_retention; - -static void * mmu_domain_dev_sleep_frame_alloc_and_init(const mmu_domain_dev_regs_region_t *regions, const int region_num) -{ - const int region_sz = sizeof(mmu_domain_dev_regs_region_t) * region_num; - int regs_frame_sz = 0; - for (int num = 0; num < region_num; num++) { - regs_frame_sz += regions[num].end - regions[num].start; - } - void *frame = heap_caps_malloc(sizeof(mmu_domain_dev_sleep_frame_t) + region_sz + regs_frame_sz, MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL); - if (frame) { - mmu_domain_dev_regs_region_t *region = (mmu_domain_dev_regs_region_t *)(frame + sizeof(mmu_domain_dev_sleep_frame_t)); - memcpy(region, regions, region_num * sizeof(mmu_domain_dev_regs_region_t)); - void *regs_frame = frame + sizeof(mmu_domain_dev_sleep_frame_t) + region_sz; - memset(regs_frame, 0, regs_frame_sz); - *(mmu_domain_dev_sleep_frame_t *)frame = (mmu_domain_dev_sleep_frame_t) { - .region = region, - .region_num = region_num, - .regs_frame = (uint32_t *)regs_frame - }; - } - return frame; -} - -static inline void * mmu_domain_mmu_table_sleep_frame_alloc_and_init(void) -{ - #define MMU_TABLE_SIZE (512 * 4) - const static mmu_domain_dev_regs_region_t regions[] = { - { .start = SPI_MEM_MMU_ITEM_CONTENT_REG(0), .end = SPI_MEM_MMU_ITEM_CONTENT_REG(0) + MMU_TABLE_SIZE} - }; - return mmu_domain_dev_sleep_frame_alloc_and_init(regions, sizeof(regions) / sizeof(regions[0])); -} - -static IRAM_ATTR void mmu_domain_dev_regs_save(mmu_domain_dev_sleep_frame_t *frame) -{ - assert(frame); - mmu_domain_dev_regs_region_t *region = frame->region; - uint32_t *regs_frame = frame->regs_frame; - - int offset = 0; - for (int i = 0; i < frame->region_num; i++) { - for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) { - REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset); - regs_frame[offset++] = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); - } - } -} - -static IRAM_ATTR void mmu_domain_dev_regs_restore(mmu_domain_dev_sleep_frame_t *frame) -{ - assert(frame); - mmu_domain_dev_regs_region_t *region = frame->region; - uint32_t *regs_frame = frame->regs_frame; - - int offset = 0; - for (int i = 0; i < frame->region_num; i++) { - for (uint32_t addr = region[i].start; addr < region[i].end; addr+=4) { - REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), offset); - REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0),regs_frame[offset++]); - } - } -} - -IRAM_ATTR void esp_sleep_mmu_retention(bool backup_or_restore) -{ - if (backup_or_restore) { - mmu_domain_dev_regs_save(s_mmu_retention.retent.mmu_table_frame); - } else { - mmu_domain_dev_regs_restore(s_mmu_retention.retent.mmu_table_frame); - } -} - -static esp_err_t esp_sleep_mmu_retention_deinit(void) -{ - if (s_mmu_retention.retent.mmu_table_frame) { - heap_caps_free((void *)s_mmu_retention.retent.mmu_table_frame); - s_mmu_retention.retent.mmu_table_frame = NULL; - } - return ESP_OK; -} - -static esp_err_t esp_sleep_mmu_retention_init(void) -{ - if (s_mmu_retention.retent.mmu_table_frame == NULL) { - void *frame = mmu_domain_mmu_table_sleep_frame_alloc_and_init(); - if (frame == NULL) { - goto err; - } - s_mmu_retention.retent.mmu_table_frame = (mmu_domain_dev_sleep_frame_t *)frame; - } - return ESP_OK; -err: - esp_sleep_mmu_retention_deinit(); - return ESP_ERR_NO_MEM; -} - -bool mmu_domain_pd_allowed(void) -{ - return (s_mmu_retention.retent.mmu_table_frame != NULL); -} - -ESP_SYSTEM_INIT_FN(sleep_mmu_startup_init, SECONDARY, BIT(0), 108) -{ - esp_err_t ret; - ret = esp_sleep_mmu_retention_init(); - if (ret != ESP_OK) { - ESP_EARLY_LOGW(TAG, "Failed to enable TOP power down during light sleep."); - } - return ESP_OK; -} diff --git a/components/esp_hw_support/modem_clock.c b/components/esp_hw_support/modem_clock.c index 043d5fd544..6d027bd86f 100644 --- a/components/esp_hw_support/modem_clock.c +++ b/components/esp_hw_support/modem_clock.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -141,7 +141,7 @@ static void IRAM_ATTR modem_clock_data_dump_configure(modem_clock_context_t *ctx modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(void) { /* It should be explicitly defined in the internal RAM */ - static DRAM_ATTR modem_clock_hal_context_t modem_clock_hal = { .syscon_dev = &MODEM_SYSCON, .lpcon_dev = &MODEM_LPCON }; + static DRAM_ATTR modem_clock_hal_context_t modem_clock_hal = { .syscon_dev = NULL, .lpcon_dev = NULL }; static DRAM_ATTR modem_clock_context_t modem_clock_context = { .hal = &modem_clock_hal, .lock = portMUX_INITIALIZER_UNLOCKED, .dev = { @@ -167,6 +167,13 @@ modem_clock_context_t * __attribute__((weak)) IRAM_ATTR MODEM_CLOCK_instance(voi }, .lpclk_src = { [0 ... PERIPH_MODEM_MODULE_NUM - 1] = MODEM_CLOCK_LPCLK_SRC_INVALID } }; + if (modem_clock_hal.syscon_dev == NULL || modem_clock_hal.lpcon_dev == NULL) { + modem_clock_hal.syscon_dev = &MODEM_SYSCON; + modem_clock_hal.lpcon_dev = &MODEM_LPCON; +#if SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED + ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_MODEM_APB, true)); +#endif + } return &modem_clock_context; } diff --git a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h index f0fe12421f..488d69522e 100644 --- a/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h +++ b/components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h @@ -94,6 +94,6 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO * Timing Tuning Parameters */ //PSRAM: core clock 80M, module clock 80M, STR mode -#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 1}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} +#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}} #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 5 diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index f91284e682..c3dfa34947 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -1,16 +1,18 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include +#include "sdkconfig.h" #include "esp_clk_tree.h" #include "esp_err.h" #include "esp_check.h" #include "soc/rtc.h" #include "hal/clk_tree_hal.h" #include "hal/clk_tree_ll.h" +#include "hal/clk_gate_ll.h" #include "esp_private/esp_clk_tree_common.h" static const char *TAG = "esp_clk_tree"; @@ -67,8 +69,74 @@ uint32_t *freq_value) return ESP_OK; } +#define ENUM2ARRAY(clk_src) (clk_src - SOC_MOD_CLK_PLL_F12M) +static int16_t s_pll_src_cg_ref_cnt[9] = { 0 }; +static bool esp_clk_tree_initialized = false; + +void esp_clk_tree_initialize(void) +{ + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + if (((rst_reason == RESET_REASON_CPU0_MWDT0) || (rst_reason == RESET_REASON_CPU0_MWDT1) \ + || (rst_reason == RESET_REASON_CPU0_SW) || (rst_reason == RESET_REASON_CPU0_RTC_WDT) \ + || (rst_reason == RESET_REASON_CPU0_JTAG) || (rst_reason == RESET_REASON_CPU0_LOCKUP)) \ + && (REG_READ(RTC_CLK_SRC_REF_CNT_ARRAY_REG) == (uint32_t)s_pll_src_cg_ref_cnt)) { + esp_clk_tree_initialized = true; + return; + } + + soc_cpu_clk_src_t current_cpu_clk_src = clk_ll_cpu_get_src(); + + if (current_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) { + s_pll_src_cg_ref_cnt[ENUM2ARRAY(SOC_MOD_CLK_PLL_F160M)] = 1; + _clk_gate_ll_ref_240m_clk_en(false); + } else if (current_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M) { + s_pll_src_cg_ref_cnt[ENUM2ARRAY(SOC_MOD_CLK_PLL_F240M)] = 1; + _clk_gate_ll_ref_160m_clk_en(false); + } + _clk_gate_ll_ref_120m_clk_en(false); + _clk_gate_ll_ref_80m_clk_en(false); + _clk_gate_ll_ref_60m_clk_en(false); +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + _clk_gate_ll_ref_48m_clk_en(false); +#endif + _clk_gate_ll_ref_40m_clk_en(false); + _clk_gate_ll_ref_20m_clk_en(false); + _clk_gate_ll_ref_12m_clk_en(false); + esp_clk_tree_initialized = true; +} + esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { - (void)clk_src; (void)enable; + if (!esp_clk_tree_initialized || (clk_src < SOC_MOD_CLK_PLL_F12M) || (clk_src > SOC_MOD_CLK_PLL_F240M)) { + return ESP_OK; + } + + PERIPH_RCC_ATOMIC() { + if (enable) { + s_pll_src_cg_ref_cnt[ENUM2ARRAY(clk_src)]++; + } + if (s_pll_src_cg_ref_cnt[ENUM2ARRAY(clk_src)] == 1) { + switch (clk_src) { + case SOC_MOD_CLK_PLL_F12M: clk_gate_ll_ref_12m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F20M: clk_gate_ll_ref_20m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F40M: clk_gate_ll_ref_40m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F48M: clk_gate_ll_ref_48m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F60M: clk_gate_ll_ref_60m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F80M: clk_gate_ll_ref_80m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F120M: clk_gate_ll_ref_120m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F160M: clk_gate_ll_ref_160m_clk_en(enable); break; + case SOC_MOD_CLK_PLL_F240M: clk_gate_ll_ref_240m_clk_en(enable); break; + default: break; + } + } + if (!enable) { + s_pll_src_cg_ref_cnt[ENUM2ARRAY(clk_src)]--; + } + if (s_pll_src_cg_ref_cnt[ENUM2ARRAY(clk_src)] < 0) { + ESP_EARLY_LOGW(TAG, "soc_module_clk_t %d disabled multiple times!!", clk_src); + s_pll_src_cg_ref_cnt[ENUM2ARRAY(clk_src)] = 0; + } + } return ESP_OK; } +#undef ENUM2ARRAY diff --git a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h index 937c09b560..76109b9980 100644 --- a/components/esp_hw_support/port/esp32c5/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32c5/include/soc/rtc.h @@ -318,6 +318,7 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); */ void rtc_clk_cpu_freq_set_xtal(void); +#ifndef BOOTLOADER_BUILD /** * @brief Switch root clock source to PLL (only used by sleep) release root clock source locked by PMU * @@ -330,6 +331,7 @@ void rtc_clk_cpu_freq_set_xtal(void); * @param[in] Maximum CPU frequency, in MHz */ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz); +#endif /** * @brief Get the current APB frequency. diff --git a/components/esp_hw_support/port/esp32c5/io_mux.c b/components/esp_hw_support/port/esp32c5/io_mux.c index 90f5013dd0..6e00bb0da5 100644 --- a/components/esp_hw_support/port/esp32c5/io_mux.c +++ b/components/esp_hw_support/port/esp32c5/io_mux.c @@ -6,6 +6,7 @@ #include "sdkconfig.h" #include "freertos/FreeRTOS.h" +#include "esp_private/esp_clk_tree_common.h" #include "esp_private/io_mux.h" #include "esp_private/periph_ctrl.h" #include "hal/gpio_ll.h" @@ -40,6 +41,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) return ESP_ERR_INVALID_STATE; } + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); gpio_ll_iomux_set_clk_src(clk_src); return ESP_OK; diff --git a/components/esp_hw_support/port/esp32c5/pmu_param.c b/components/esp_hw_support/port/esp32c5/pmu_param.c index f9bfae07e8..522ff1d8d3 100644 --- a/components/esp_hw_support/port/esp32c5/pmu_param.c +++ b/components/esp_hw_support/port/esp32c5/pmu_param.c @@ -17,6 +17,12 @@ #include "hal/efuse_hal.h" #include "esp_hw_log.h" +#define PMU_CLK_SRC_VAL(src) \ + (((uint32_t)src == (uint32_t)SOC_MOD_CLK_XTAL) ? 0 : \ + ((uint32_t)src == (uint32_t)SOC_MOD_CLK_RC_FAST) ? 1 : \ + ((uint32_t)src == (uint32_t)SOC_MOD_CLK_PLL_F160M) ? 2 : \ + ((uint32_t)src == (uint32_t)SOC_MOD_CLK_PLL_F240M) ? 3 : 0) + static __attribute__((unused)) const char *TAG = "pmu_param"; #ifndef ARRAY_SIZE @@ -111,7 +117,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod .icg_sysclk_en = 1, \ .sysclk_slp_sel = 0, \ .icg_slp_sel = 0, \ - .dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \ + .dig_sysclk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL) \ } \ } @@ -127,7 +133,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod .icg_sysclk_en = 1, \ .sysclk_slp_sel = 1, \ .icg_slp_sel = 1, \ - .dig_sysclk_sel = SOC_CPU_CLK_SRC_PLL_F160M \ + .dig_sysclk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_PLL_F160M) \ } \ } @@ -142,7 +148,7 @@ const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mod .icg_sysclk_en = 0, \ .sysclk_slp_sel = 1, \ .icg_slp_sel = 1, \ - .dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \ + .dig_sysclk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL) \ } \ } @@ -289,8 +295,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_active_retention_mode = 0, \ .hp_sleep2active_retention_en = 0, \ .hp_modem2active_retention_en = 0, \ - .hp_sleep2active_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \ - .hp_modem2active_backup_clk_sel = SOC_CPU_CLK_SRC_PLL_F160M, \ + .hp_sleep2active_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \ + .hp_modem2active_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_CPU_CLK_SRC_PLL_F160M), \ .hp_sleep2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \ .hp_modem2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \ .hp_sleep2active_backup_en = 0, \ @@ -304,7 +310,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep2modem_backup_modem_clk_code = 1, \ .hp_modem_retention_mode = 0, \ .hp_sleep2modem_retention_en = 0, \ - .hp_sleep2modem_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \ + .hp_sleep2modem_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \ .hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \ .hp_sleep2modem_backup_en = 0, \ }, \ @@ -318,8 +324,8 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m .hp_sleep_retention_mode = 0, \ .hp_modem2sleep_retention_en = 0, \ .hp_active2sleep_retention_en = 0, \ - .hp_modem2sleep_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \ - .hp_active2sleep_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \ + .hp_modem2sleep_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \ + .hp_active2sleep_backup_clk_sel = PMU_CLK_SRC_VAL(SOC_MOD_CLK_XTAL), \ .hp_modem2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \ .hp_active2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \ .hp_modem2sleep_backup_en = 0, \ diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index d4ef416010..eb6a093f40 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -304,37 +304,53 @@ __attribute__((weak)) void rtc_clk_set_cpu_switch_to_pll(int event_id) { } -void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) +static void rtc_clk_update_pll_state_on_cpu_src_switching_start(soc_cpu_clk_src_t old_src, soc_cpu_clk_src_t new_src, bool fast_switching) { - soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); - if (config->source == SOC_CPU_CLK_SRC_XTAL) { - rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); - if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) { + if ((new_src == SOC_CPU_CLK_SRC_PLL_F160M) || (new_src == SOC_CPU_CLK_SRC_PLL_F240M)) { + if ((s_cur_pll_freq != CLK_LL_PLL_480M_FREQ_MHZ) && !fast_switching) { + rtc_clk_bbpll_enable(); + rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ); + } +#ifndef BOOTLOADER_BUILD + esp_clk_tree_enable_src((new_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M, true); +#endif + } +} + +static void rtc_clk_update_pll_state_on_cpu_src_switching_end(soc_cpu_clk_src_t old_src, soc_cpu_clk_src_t new_src, bool fast_switching) +{ + if ((old_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_src == SOC_CPU_CLK_SRC_PLL_F240M)) { +#ifndef BOOTLOADER_BUILD + esp_clk_tree_enable_src((old_src == SOC_CPU_CLK_SRC_PLL_F240M) ? SOC_MOD_CLK_PLL_F240M : SOC_MOD_CLK_PLL_F160M, false); +#endif + if ((new_src != SOC_CPU_CLK_SRC_PLL_F160M) && (new_src != SOC_CPU_CLK_SRC_PLL_F240M) && !s_bbpll_digi_consumers_ref_count && !fast_switching) { // We don't turn off the bbpll if some consumers depend on bbpll rtc_clk_bbpll_disable(); } + } +} + +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config) +{ + soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); + if (old_cpu_clk_src != config->source) { + rtc_clk_update_pll_state_on_cpu_src_switching_start(old_cpu_clk_src, config->source, false); + } + if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); } else if (config->source == SOC_CPU_CLK_SRC_PLL_F240M) { - if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M && old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) { - rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); - rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ); - } + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); rtc_clk_cpu_freq_to_pll_240_mhz(config->freq_mhz); rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP); } else if (config->source == SOC_CPU_CLK_SRC_PLL_F160M) { - if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F240M && old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL_F160M) { - rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); - rtc_clk_bbpll_enable(); - rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), CLK_LL_PLL_480M_FREQ_MHZ); - } + rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_START); rtc_clk_cpu_freq_to_pll_160_mhz(config->freq_mhz); rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { rtc_clk_cpu_freq_to_8m(); - if (((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F160M) || (old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL_F240M)) && !s_bbpll_digi_consumers_ref_count) { - // We don't turn off the bbpll if some consumers depend on bbpll - rtc_clk_bbpll_disable(); - } + } + if (old_cpu_clk_src != config->source) { + rtc_clk_update_pll_state_on_cpu_src_switching_end(old_cpu_clk_src, config->source, false); } } @@ -374,16 +390,25 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config) void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config) { + soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src(); if (config->source == SOC_CPU_CLK_SRC_XTAL) { + rtc_clk_update_pll_state_on_cpu_src_switching_start(old_cpu_clk_src, config->source, true); rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div); + rtc_clk_update_pll_state_on_cpu_src_switching_end(old_cpu_clk_src, config->source, true); } else if (config->source == SOC_CPU_CLK_SRC_PLL_F160M && s_cur_pll_freq == CLK_LL_PLL_480M_FREQ_MHZ) { + rtc_clk_update_pll_state_on_cpu_src_switching_start(old_cpu_clk_src, config->source, true); rtc_clk_cpu_freq_to_pll_160_mhz(config->freq_mhz); + rtc_clk_update_pll_state_on_cpu_src_switching_end(old_cpu_clk_src, config->source, true); } else if (config->source == SOC_CPU_CLK_SRC_PLL_F240M && s_cur_pll_freq == CLK_LL_PLL_480M_FREQ_MHZ) { + rtc_clk_update_pll_state_on_cpu_src_switching_start(old_cpu_clk_src, config->source, true); rtc_clk_cpu_freq_to_pll_240_mhz(config->freq_mhz); + rtc_clk_update_pll_state_on_cpu_src_switching_end(old_cpu_clk_src, config->source, true); } else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) { + rtc_clk_update_pll_state_on_cpu_src_switching_start(old_cpu_clk_src, config->source, true); rtc_clk_cpu_freq_to_8m(); + rtc_clk_update_pll_state_on_cpu_src_switching_end(old_cpu_clk_src, config->source, true); } else { /* fallback */ rtc_clk_cpu_freq_set_config(config); @@ -399,8 +424,13 @@ void rtc_clk_cpu_freq_set_xtal(void) void rtc_clk_cpu_set_to_default_config(void) { int freq_mhz = (int)rtc_clk_xtal_freq_get(); - +#ifndef BOOTLOADER_BUILD + soc_module_clk_t old_cpu_clk_src = (soc_module_clk_t)clk_ll_cpu_get_src(); +#endif rtc_clk_cpu_freq_to_xtal(freq_mhz, 1); +#ifndef BOOTLOADER_BUILD + esp_clk_tree_enable_src(old_cpu_clk_src, false); +#endif s_cur_pll_freq = 0; // no disable PLL, but set freq to 0 to trigger a PLL calibration after wake-up from sleep } @@ -409,26 +439,33 @@ void rtc_clk_cpu_freq_set_xtal_for_sleep(void) rtc_clk_cpu_set_to_default_config(); } +#ifndef BOOTLOADER_BUILD void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz) { // IDF-11064 if (cpu_freq_mhz == 240) { + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz); } else if (cpu_freq_mhz == 160) { + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); } else {// cpu_freq_mhz is 80 if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 101)) {// (use 240mhz pll if max cpu freq is 240MHz) #if CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_240 + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); rtc_clk_cpu_freq_to_pll_240_mhz(cpu_freq_mhz); #else + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); #endif } else {// (fixed for chip rev. >= ECO3) + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true); rtc_clk_cpu_freq_to_pll_160_mhz(cpu_freq_mhz); } } clk_ll_cpu_clk_src_lock_release(); } +#endif soc_xtal_freq_t rtc_clk_xtal_freq_get(void) { diff --git a/components/esp_hw_support/port/esp32c5/rtc_time.c b/components/esp_hw_support/port/esp32c5/rtc_time.c index cb1b4ee6be..b37055c2c6 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_time.c +++ b/components/esp_hw_support/port/esp32c5/rtc_time.c @@ -64,7 +64,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc rtc_dig_clk8m_enable(); } } - + clk_ll_enable_timergroup_rtc_calibration_clock(true); /* There may be another calibration process already running during we call this function, * so we should wait the last process is done. */ @@ -123,6 +123,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc } CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + clk_ll_enable_timergroup_rtc_calibration_clock(false); /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) { clk_ll_xtal32k_digi_disable(); diff --git a/components/esp_hw_support/port/esp32c61/Kconfig.hw_support b/components/esp_hw_support/port/esp32c61/Kconfig.hw_support index 7cb0fe1f89..71e247da35 100644 --- a/components/esp_hw_support/port/esp32c61/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32c61/Kconfig.hw_support @@ -1,6 +1,6 @@ choice ESP32C61_REV_MIN prompt "Minimum Supported ESP32-C61 Revision" - default ESP32C61_REV_MIN_0 + default ESP32C61_REV_MIN_100 help Required minimum chip revision. ESP-IDF will check for it and reject to boot if the chip revision fails the check. @@ -9,13 +9,13 @@ choice ESP32C61_REV_MIN The complied binary will only support chips above this revision, this will also help to reduce binary size. - config ESP32C61_REV_MIN_0 - bool "Rev v0.0" + config ESP32C61_REV_MIN_100 + bool "Rev v1.0" endchoice config ESP32C61_REV_MIN_FULL int - default 0 if ESP32C61_REV_MIN_0 + default 100 if ESP32C61_REV_MIN_100 config ESP_REV_MIN_FULL int @@ -25,7 +25,7 @@ config ESP_REV_MIN_FULL # MAX Revision # - comment "Maximum Supported ESP32-C61 Revision (Rev v0.99)" + comment "Maximum Supported ESP32-C61 Revision (Rev v1.99)" # Maximum revision that IDF supports. # It can not be changed by user. # Only Espressif can change it when a new version will be supported in IDF. @@ -33,7 +33,7 @@ config ESP_REV_MIN_FULL config ESP32C61_REV_MAX_FULL int - default 99 + default 199 # keep in sync the "Maximum Supported Revision" description with this value config ESP_REV_MAX_FULL @@ -53,6 +53,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL config ESP_EFUSE_BLOCK_REV_MAX_FULL int - default 99 + default 199 comment "Maximum Supported ESP32-C61 eFuse Block Revision (eFuse Block Rev v0.99)" # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL diff --git a/components/esp_hw_support/port/esp32c61/ocode_init.c b/components/esp_hw_support/port/esp32c61/ocode_init.c index 84592b90df..f21773509f 100644 --- a/components/esp_hw_support/port/esp32c61/ocode_init.c +++ b/components/esp_hw_support/port/esp32c61/ocode_init.c @@ -18,15 +18,15 @@ static const char *TAG = "ocode_init"; -// static void set_ocode_by_efuse(int ocode_scheme_ver) -// { - // assert(ocode_scheme_ver == 1); - // unsigned int ocode = efuse_ll_get_ocode(); +static void set_ocode_by_efuse(int ocode_scheme_ver) +{ + assert(ocode_scheme_ver == 1); + unsigned int ocode = efuse_ll_get_ocode(); - // //set ext_ocode - // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); - // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); -// } + //set ext_ocode + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1); +} static void IRAM_ATTR NOINLINE_ATTR calibrate_ocode(void) { @@ -82,9 +82,9 @@ static void IRAM_ATTR NOINLINE_ATTR calibrate_ocode(void) void esp_ocode_calib_init(void) { - // if (efuse_hal_blk_version() >= 1) { - // set_ocode_by_efuse(1); - // } else { + if (efuse_hal_blk_version() >= 1) { + set_ocode_by_efuse(1); + } else { calibrate_ocode(); - // } + } } diff --git a/components/esp_hw_support/port/esp32c61/pmu_param.c b/components/esp_hw_support/port/esp32c61/pmu_param.c index 5a13d514a6..e565209ac4 100644 --- a/components/esp_hw_support/port/esp32c61/pmu_param.c +++ b/components/esp_hw_support/port/esp32c61/pmu_param.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,6 +18,8 @@ #include "esp_hw_log.h" #include "soc/clk_tree_defs.h" +static __attribute__((unused)) const char *TAG = "pmu_param"; + #ifndef ARRAY_SIZE #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #endif @@ -200,66 +202,69 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp } #define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 1, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 1, \ + .dbg_atten = 0x0, \ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .lp_dbias_vol = 0xd, \ - .hp_dbias_vol = 0x1c,\ - .dbias_sel = 1, \ - .dbias_init = 1, \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ + .regulator0 = { \ + .slp_connect_en_active = 1, \ + .lp_dbias_vol = 0xd, \ + .hp_dbias_vol = 0x1c,\ + .dbias_sel = 1, \ + .dbias_init_active = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } #define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 0, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0,\ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = HP_CALI_DBIAS_DEFAULT \ + .regulator0 = { \ + .slp_connect_en_modem = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = HP_CALI_DBIAS_DEFAULT \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } #define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \ - .bias = { \ - .xpd_bias = 0, \ - .dbg_atten = 0x0, \ - .pd_cur = 0, \ - .bias_sleep = 0 \ + .bias = { \ + .xpd_bias = 0, \ + .dbg_atten = 0x0,\ + .pd_cur = 0, \ + .bias_sleep = 0 \ }, \ - .regulator0 = { \ - .slp_mem_xpd = 0, \ - .slp_logic_xpd = 0, \ - .xpd = 1, \ - .slp_mem_dbias = 0, \ - .slp_logic_dbias = 0, \ - .dbias = 1 \ + .regulator0 = { \ + .slp_connect_en_sleep = 1, \ + .slp_mem_xpd = 0, \ + .slp_logic_xpd = 0, \ + .xpd = 1, \ + .slp_mem_dbias = 0, \ + .slp_logic_dbias = 0, \ + .dbias = 1 \ }, \ - .regulator1 = { \ - .drv_b = 0x0 \ + .regulator1 = { \ + .drv_b = 0x0 \ } \ } @@ -416,52 +421,46 @@ const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_m uint32_t get_act_hp_dbias(void) { - // TODO: IDF-9274 /* hp_cali_dbias is read from efuse to ensure that the hp_active_voltage is close to 1.15V */ uint32_t hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - // uint32_t blk_version = efuse_hal_blk_version(); - // if (blk_version >= 3) { - // hp_cali_dbias = efuse_ll_get_active_hp_dbias(); - // if (hp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (hp_cali_dbias + 2 > 31) { - // hp_cali_dbias = 31; - // } else { - // hp_cali_dbias += 2; - // } - // } else { - // hp_cali_dbias = HP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "hp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); - // } - // } + uint32_t blk_version = efuse_hal_blk_version(); + uint32_t hp_cali_dbias_efuse = 0; + if (blk_version >= 1) { + hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias(); + } + if (hp_cali_dbias_efuse > 0) { + //efuse dbias need to add 3 to meet the CPU frequency switching + hp_cali_dbias = hp_cali_dbias_efuse + 16 + 3; + if (hp_cali_dbias > 31) { + hp_cali_dbias = 31; + } + } else { + ESP_HW_LOGW(TAG, "hp_cali_dbias not burnt in efuse, use default."); + } return hp_cali_dbias; } uint32_t get_act_lp_dbias(void) { - // TODO: IDF-9274 /* lp_cali_dbias is read from efuse to ensure that the lp_active_voltage is close to 1.15V */ uint32_t lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - // uint32_t blk_version = efuse_hal_blk_version(); - // if (blk_version >= 3) { - // lp_cali_dbias = efuse_ll_get_active_lp_dbias(); - // if (lp_cali_dbias != 0) { - // //efuse dbias need to add 2 to meet the CPU frequency switching - // if (lp_cali_dbias + 2 > 31) { - // lp_cali_dbias = 31; - // } else { - // lp_cali_dbias += 2; - // } - // } else { - // lp_cali_dbias = LP_CALI_DBIAS_DEFAULT; - // ESP_HW_LOGD(TAG, "lp_cali_dbias not burnt in efuse or wrong value was burnt in blk version: %" PRIu32 "\n", blk_version); - // } - // } else { - // ESP_HW_LOGD(TAG, "blk_version is less than 3, act dbias not burnt in efuse\n"); - // } + uint32_t blk_version = efuse_hal_blk_version(); + uint32_t lp_cali_dbias_efuse = 0; + if (blk_version >= 1) { + lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias(); + } + if (lp_cali_dbias_efuse > 0) { + //efuse dbias need to add 3 to meet the CPU frequency switching + lp_cali_dbias = lp_cali_dbias_efuse + 16 + 3; + if (lp_cali_dbias > 31) { + lp_cali_dbias = 31; + } + } else { + ESP_HW_LOGW(TAG, "lp_cali_dbias not burnt in efuse, use default."); + } return lp_cali_dbias; } diff --git a/components/esp_hw_support/port/esp32c61/pmu_sleep.c b/components/esp_hw_support/port/esp32c61/pmu_sleep.c index 22f7900c83..ca7edfb618 100644 --- a/components/esp_hw_support/port/esp32c61/pmu_sleep.c +++ b/components/esp_hw_support/port/esp32c61/pmu_sleep.c @@ -19,6 +19,9 @@ #include "hal/efuse_hal.h" #include "esp_private/esp_pmu.h" #include "pmu_param.h" +#include "esp_hw_log.h" + +static __attribute__((unused)) const char *TAG = "pmu_sleep"; #define HP(state) (PMU_MODE_HP_ ## state) #define LP(state) (PMU_MODE_LP_ ## state) @@ -26,6 +29,58 @@ static bool s_pmu_sleep_regdma_backup_enabled; +static uint32_t get_lslp_dbg(void) +{ + uint32_t pmu_dbg_atten_lightsleep = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 1) { + pmu_dbg_atten_lightsleep = efuse_ll_get_lslp_dbg(); + } else { + ESP_HW_LOGD(TAG, "lslp dbg not burnt in efuse, use default\n"); + } + + return pmu_dbg_atten_lightsleep; +} + +static uint32_t get_lslp_hp_dbias(void) +{ + uint32_t pmu_hp_dbias_lightsleep_0v6 = PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT; + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 1) { + pmu_hp_dbias_lightsleep_0v6 = efuse_ll_get_lslp_hp_dbias(); + } else { + ESP_HW_LOGD(TAG, "lslp hp dbias not burnt in efuse, use default\n"); + } + + return pmu_hp_dbias_lightsleep_0v6; +} + +static uint32_t get_dslp_dbg(void) +{ + uint32_t pmu_dbg_atten_deepsleep = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT; + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 1) { + pmu_dbg_atten_deepsleep = efuse_ll_get_dslp_dbg(); + } else { + ESP_HW_LOGD(TAG, "dslp dbg not burnt in efuse, use default\n"); + } + + return pmu_dbg_atten_deepsleep; +} + +static uint32_t get_dslp_lp_dbias(void) +{ + uint32_t pmu_lp_dbias_deepsleep_0v7 = PMU_LP_DBIAS_DEEPSLEEP_0V7_DEFAULT; + uint32_t blk_version = efuse_hal_blk_version(); + if (blk_version >= 1) { + pmu_lp_dbias_deepsleep_0v7 = efuse_ll_get_dslp_lp_dbias(); + } else { + ESP_HW_LOGD(TAG, "dslp lp dbias not burnt in efuse\n"); + } + + return pmu_lp_dbias_deepsleep_0v7; +} + void pmu_sleep_enable_regdma_backup(void) { if(!s_pmu_sleep_regdma_backup_enabled){ @@ -191,22 +246,27 @@ const pmu_sleep_config_t* pmu_sleep_config_default( config->digital = digital_default; pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags); + analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = get_dslp_dbg(); + analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_dslp_lp_dbias(); config->analog = analog_default; } else { pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags); config->digital = digital_default; pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags); + analog_default.hp_sys.analog.dbg_atten = get_lslp_dbg(); + analog_default.hp_sys.analog.dbias = get_lslp_hp_dbias(); + analog_default.lp_sys[LP(SLEEP)].analog.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT; if (!(sleep_flags & PMU_SLEEP_PD_XTAL) || !(sleep_flags & PMU_SLEEP_PD_RC_FAST)){ analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; - analog_default.hp_sys.analog.dbias = HP_CALI_DBIAS_SLP_1V1; + analog_default.hp_sys.analog.dbias = get_act_hp_dbias(); analog_default.hp_sys.analog.dbg_atten = 0; analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON; analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON; - analog_default.lp_sys[LP(SLEEP)].analog.dbias = LP_CALI_DBIAS_SLP_1V1; + analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias(); analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = 0; } diff --git a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c index a0c3e5a07d..f2b4c71017 100644 --- a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c @@ -54,5 +54,5 @@ uint32_t *freq_value) esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { (void)clk_src; (void)enable; - return ESP_ERR_NOT_SUPPORTED; + return ESP_OK; } diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c index 9e46ca5877..102ea66476 100644 --- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -91,6 +91,11 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { + if(!enable) { + // TODO: remove it after reference counter supported + return ESP_OK; + } + PERIPH_RCC_ATOMIC() { switch (clk_src) { case SOC_MOD_CLK_PLL_F20M: diff --git a/components/esp_hw_support/port/esp32p4/io_mux.c b/components/esp_hw_support/port/esp32p4/io_mux.c index e74205bf8d..89befcb95e 100644 --- a/components/esp_hw_support/port/esp32p4/io_mux.c +++ b/components/esp_hw_support/port/esp32p4/io_mux.c @@ -44,7 +44,7 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src) return ESP_ERR_INVALID_STATE; } - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); PERIPH_RCC_ATOMIC() { gpio_ll_iomux_set_clk_src(clk_src); } diff --git a/components/esp_hw_support/sar_periph_ctrl_common.c b/components/esp_hw_support/sar_periph_ctrl_common.c index f8099358ca..b4612116b6 100644 --- a/components/esp_hw_support/sar_periph_ctrl_common.c +++ b/components/esp_hw_support/sar_periph_ctrl_common.c @@ -9,6 +9,7 @@ #include "freertos/FreeRTOS.h" #include "esp_private/sar_periph_ctrl.h" #include "esp_log.h" +#include "esp_timer.h" #if SOC_TEMP_SENSOR_SUPPORTED #include "hal/temperature_sensor_ll.h" @@ -39,17 +40,22 @@ static const char *TAG_TSENS = "temperature_sensor"; # define SAR_PERIPH_CTRL_COMMON_FN_ATTR #endif +#define TSENS_LINE_REGRESSION_US (200) + static int s_record_min = INT_NOT_USED; static int s_record_max = INT_NOT_USED; static int s_temperature_sensor_power_cnt; +static bool s_first_temp_read = false; static uint8_t s_tsens_idx = 2; // Index for temperature attribute, set 2(middle) as default value +static int64_t timer1 = 0; void temperature_sensor_power_acquire(void) { portENTER_CRITICAL(&rtc_spinlock); s_temperature_sensor_power_cnt++; if (s_temperature_sensor_power_cnt == 1) { + s_first_temp_read = true; regi2c_saradc_enable(); #if !SOC_TSENS_IS_INDEPENDENT_FROM_ADC adc_apb_periph_claim(); @@ -59,6 +65,9 @@ void temperature_sensor_power_acquire(void) temperature_sensor_ll_reset_module(); } temperature_sensor_ll_enable(true); + // Set the range as recorded. + temperature_sensor_ll_set_range(temperature_sensor_attributes[s_tsens_idx].reg_val); + timer1 = esp_timer_get_time(); } portEXIT_CRITICAL(&rtc_spinlock); } @@ -100,6 +109,18 @@ int16_t temp_sensor_get_raw_value(bool *range_changed) { portENTER_CRITICAL(&rtc_spinlock); + // When this is the first time reading a value, check whether the time here minus the + // initialization time is greater than 200 microseconds (the time for linear regression). + // If it is less than 200 microseconds, continue waiting here. + if (s_first_temp_read == true) { + int64_t timer2 = esp_timer_get_time(); + int64_t diff = timer2 - timer1; + if (diff < TSENS_LINE_REGRESSION_US) { + esp_rom_delay_us(TSENS_LINE_REGRESSION_US - diff); + } + s_first_temp_read = false; + } + int degree = temperature_sensor_get_raw_value(); uint8_t temperature_dac; diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index 6bed0f6f7e..61bb2620e5 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -180,8 +180,8 @@ #define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56) #elif CONFIG_IDF_TARGET_ESP32C61 -#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318) -#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (107) +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (65) +#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (70) #elif CONFIG_IDF_TARGET_ESP32H2 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (118) #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (9) @@ -215,12 +215,8 @@ #endif #if SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD -#if CONFIG_IDF_TARGET_ESP32C61 -#define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1232) -#elif CONFIG_IDF_TARGET_ESP32C5 #define SLEEP_MMU_TABLE_RETENTION_OVERHEAD_US (1220) #endif -#endif #define RTC_MODULE_SLEEP_PREPARE_CYCLES (6) diff --git a/components/esp_hw_support/test_apps/dma/sdkconfig.defaults.esp32c61 b/components/esp_hw_support/test_apps/dma/sdkconfig.defaults.esp32c61 new file mode 100644 index 0000000000..728fbe8889 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/sdkconfig.defaults.esp32c61 @@ -0,0 +1,2 @@ +CONFIG_SPIRAM=y +CONFIG_SPIRAM_SPEED_80M=y diff --git a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c index 8fa35c55dc..33177a22e0 100644 --- a/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c +++ b/components/esp_lcd/dsi/esp_lcd_mipi_dsi_bus.c @@ -48,7 +48,7 @@ esp_err_t esp_lcd_new_dsi_bus(const esp_lcd_dsi_bus_config_t *bus_config, esp_lc if (phy_clk_src == 0) { phy_clk_src = MIPI_DSI_PHY_CLK_SRC_DEFAULT; } - esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)phy_clk_src, true), err, TAG, "clock source enable failed"); // enable the clock source for DSI PHY DSI_CLOCK_SRC_ATOMIC() { // set clock source for DSI PHY diff --git a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c index 8372bdd197..61167212e4 100644 --- a/components/esp_lcd/dsi/esp_lcd_panel_dpi.c +++ b/components/esp_lcd/dsi/esp_lcd_panel_dpi.c @@ -260,7 +260,7 @@ esp_err_t esp_lcd_new_panel_dpi(esp_lcd_dsi_bus_handle_t bus, const esp_lcd_dpi_ &dpi_clk_src_freq_hz), err, TAG, "get clock source frequency failed"); // divide the source clock to get the final DPI clock uint32_t dpi_div = mipi_dsi_hal_host_dpi_calculate_divider(hal, dpi_clk_src_freq_hz / 1000 / 1000, panel_config->dpi_clock_freq_mhz); - esp_clk_tree_enable_src((soc_module_clk_t)dpi_clk_src, true); + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)dpi_clk_src, true), err, TAG, "clock source enable failed"); // set the clock source, set the divider, and enable the dpi clock DSI_CLOCK_SRC_ATOMIC() { mipi_dsi_ll_set_dpi_clock_source(bus_id, dpi_clk_src); diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c index 2e37f4f05e..b5c913e6f1 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c @@ -572,7 +572,7 @@ static esp_err_t lcd_i80_select_periph_clock(esp_lcd_i80_bus_handle_t bus, lcd_c ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed"); LCD_CLOCK_SRC_ATOMIC() { lcd_ll_select_clk_src(bus->hal.dev, clk_src); // force to use integer division, as fractional division might lead to clock jitter diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index 72df1e8266..64592c1417 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -782,7 +782,7 @@ static esp_err_t lcd_rgb_panel_select_clock_src(esp_rgb_panel_t *rgb_panel, lcd_ ESP_RETURN_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), TAG, "get clock source frequency failed"); rgb_panel->src_clk_hz = src_clk_hz; - esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), TAG, "clock source enable failed"); LCD_CLOCK_SRC_ATOMIC() { lcd_ll_select_clk_src(rgb_panel->hal.dev, clk_src); } diff --git a/components/esp_phy/esp32c61/phy_init_data.c b/components/esp_phy/esp32c61/phy_init_data.c index 503fa18c79..b06b158688 100644 --- a/components/esp_phy/esp32c61/phy_init_data.c +++ b/components/esp_phy/esp32c61/phy_init_data.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,24 +19,24 @@ const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY_INIT_M const esp_phy_init_data_t phy_init_data= { { 0x1, 0x0, + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x54), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x34), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x3C), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x30), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x28), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x24), LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c), - LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x2c), + LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48), 0x0, 0x00, 0x00, @@ -157,14 +157,15 @@ static const char* TAG = "phy_sleep"; static esp_err_t sleep_retention_wifi_bb_init(void *arg) { - #define N_REGS_WIFI_AGC() (121) - #define N_REGS_WIFI_TX() (14) - #define N_REGS_WIFI_NRX() (136) - #define N_REGS_WIFI_BB() (53) + #define N_REGS_WIFI_AGC() (130) + #define N_REGS_WIFI_TX() (30) + #define N_REGS_WIFI_NRX() (145) + #define N_REGS_WIFI_BB() (82) #define N_REGS_WIFI_BRX() (39) - #define N_REGS_WIFI_FE_COEX() (58) - #define N_REGS_WIFI_FE_DATA() (41) - #define N_REGS_WIFI_FE_CTRL() (87) + #define N_REGS_WIFI_FE_COEX() (21) + #define N_REGS_WIFI_FE_DATA() (34) + #define N_REGS_WIFI_FE_CTRL() (56) + #define N_REGS_WIFI_FE_WIFI() (21) const static sleep_retention_entries_config_t bb_regs_retention[] = { [0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b00, 0x600a7000, 0x600a7000, N_REGS_WIFI_AGC(), 0, 0), .owner = BIT(0) | BIT(1) }, /* AGC */ @@ -175,6 +176,7 @@ static esp_err_t sleep_retention_wifi_bb_init(void *arg) [5] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b06, 0x600a8000, 0x600a8000, N_REGS_WIFI_BRX(), 0, 0), .owner = BIT(0) | BIT(1) }, /* BRX */ [6] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b07, 0x600a0400, 0x600a0400, N_REGS_WIFI_FE_DATA(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE DATA */ [7] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b08, 0x600a0800, 0x600a0800, N_REGS_WIFI_FE_CTRL(), 0, 0), .owner = BIT(0) | BIT(1) }, /* FE CTRL */ + [8] = { .config = REGDMA_LINK_CONTINUOUS_INIT(0x0b09, 0x600a0c00, 0x600a0c00, N_REGS_WIFI_FE_WIFI(), 0, 0), .owner = BIT(0) | BIT(1) } /* FE WiFi DATA */ }; esp_err_t err = sleep_retention_entries_create(bb_regs_retention, ARRAY_SIZE(bb_regs_retention), 3, SLEEP_RETENTION_MODULE_WIFI_BB); ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem (%s) retention", "WiFi BB"); diff --git a/components/esp_phy/lib b/components/esp_phy/lib index f6746ceea8..d7cf8d4b71 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit f6746ceea821b3800e8700d7e535f5df7304b8e5 +Subproject commit d7cf8d4b71f006e6924dd98fbdc7d3d8b1429c74 diff --git a/components/esp_pm/pm_impl.c b/components/esp_pm/pm_impl.c index e44f7c9c21..3e33182d91 100644 --- a/components/esp_pm/pm_impl.c +++ b/components/esp_pm/pm_impl.c @@ -929,7 +929,7 @@ void esp_pm_impl_init(void) ; } - esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true); + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_source, true)); /* When DFS is enabled, override system setting and use REFTICK as UART clock source */ HP_UART_SRC_CLK_ATOMIC() { uart_ll_set_sclk(UART_LL_GET_HW(CONFIG_ESP_CONSOLE_UART_NUM), (soc_module_clk_t)clk_source); diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index 6a811e4158..e8d5d862c7 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -67,10 +67,6 @@ if(CONFIG_ESP_ROM_HAS_FLASH_COUNT_PAGES_BUG OR CONFIG_ESP_ROM_HAS_CACHE_WRITEBAC list(APPEND sources "patches/esp_rom_cache_esp32s2_esp32s3.c") endif() -if(CONFIG_ESP_ROM_CACHE_WB_INVLD_LOW_RANGE) - list(APPEND sources "patches/esp_rom_cache_esp32c61.c") -endif() - if(CONFIG_ESP_ROM_HAS_CACHE_WRITEBACK_BUG) list(APPEND sources "patches/esp_rom_cache_writeback_esp32s3.S") endif() diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h b/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h index 6e80a7707c..f596e45f97 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/ets_sys.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -421,6 +421,30 @@ typedef enum { } STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); #endif +/** + * @brief Returns the offset from which the bootloader image is used to load. + * + * The offset can point to either the PRIMARY or RECOVERY bootloader. + * + * @note The bootloader offset variable in ROM is stored in a memory that will be reclaimed by heap component. + * Read it before the heap is initialized, otherwise it may return an invalid value. + * + * @return The offset of the active bootloader. + */ +uint32_t ets_get_bootloader_offset(void); + +/** + * @brief Sets the offset from which the bootloader image is used to load. + * + * The offset can point to either the PRIMARY or RECOVERY bootloader. + * + * @note The bootloader offset variable in ROM is stored in a memory that will be reclaimed by heap component. + * Setting it after the heap is initialized, may corrupt the heap memory. + * + * @param offset The offset value to set for the active bootloader. + */ +void ets_set_bootloader_offset(uint32_t offset); + /** * @} */ diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/key_mgr.h b/components/esp_rom/esp32c5/include/esp32c5/rom/key_mgr.h new file mode 100644 index 0000000000..15be126268 --- /dev/null +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/key_mgr.h @@ -0,0 +1,115 @@ +/* + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "soc/soc_caps.h" + +#if SOC_KEY_MANAGER_SUPPORTED + +#include "rom/ets_sys.h" +#include "esp_attr.h" +#include +#include "rom/km.h" + +#if __cplusplus +extern "C" { +#endif + +// store huk info, occupy 96 words +struct huk_info { +// store huk info, occupy 165 words +#define HUK_INFO_LEN 660 + + uint8_t info[HUK_INFO_LEN]; + uint32_t crc; +} PACKED_ATTR; + +// store key info, occupy 512 bits +struct key_info { +#define KEY_INFO_LEN 64 + uint8_t info[KEY_INFO_LEN]; + uint32_t crc; +} PACKED_ATTR; + +struct huk_key_block { +#define KEY_HUK_SECTOR_MAGIC 0xDEA5CE5A + uint32_t magic; + uint32_t version; // for backward compatibility + uint8_t reserved[16]; + struct huk_info huk_info; + struct key_info key_info[2]; // at most 2 key info (XTS-512_1 and XTS-512_2), at least use 1 +} WORD_ALIGNED_ATTR PACKED_ATTR; + +/* + * We define two info sectors "active" and "backup" here + * Most rom code would rely only on the "active" sector for the key information + * + * But there could be a situation where the huk and key information must be regenerated + * based on ageing and other factors. For that scenario, we need a "backup" sector + */ +#define KEY_HUK_SECTOR_OFFSET(i) ((i)*0x1000) +#define ACTIVE_SECTOR_OFFSET KEY_HUK_SECTOR_OFFSET(0) +#define BACKUP_SECTOR_OFFSET KEY_HUK_SECTOR_OFFSET(1) + +#define KM_PERI_ECDSA (BIT(0)) +#define KM_PERI_XTS (BIT(1)) + +struct km_deploy_ops { +#define KM_KEY_PURPOSE_ECDSA_KEY_192 1 +#define KM_KEY_PURPOSE_ECDSA_KEY_256 2 +#define KM_KEY_PURPOSE_FLASH_XTS_256_1 3 +#define KM_KEY_PURPOSE_FLASH_XTS_256_2 4 +#define KM_KEY_PURPOSE_FLASH_XTS_128 5 +#define KM_KEY_PURPOSE_HMAC 6 +#define KM_KEY_PURPOSE_DS 7 +#define KM_KEY_PURPOSE_PSRAM_XTS_256_1 8 +#define KM_KEY_PURPOSE_PSRAM_XTS_256_2 9 +#define KM_KEY_PURPOSE_PSRAM_XTS_128 10 +#define KM_KEY_PURPOSE_ECDSA_KEY_384_L 11 +#define KM_KEY_PURPOSE_ECDSA_KEY_384_H 12 + int km_key_purpose; +#define KM_DEPLOY_MODE_RANDOM 0 +#define KM_DEPLOY_MODE_AES 1 +#define KM_DEPLOY_MODE_ECDH0 2 +#define KM_DEPLOY_MODE_ECDH1 3 +#define KM_DEPLOY_MODE_RECOVER 4 +#define KM_DEPLOY_MODE_EXPORT 5 + int deploy_mode; + uint8_t *init_key; // 256 bits, only used in aes and ecdh1 deploy mode + int deploy_only_once; + int force_use_km_key; + int km_use_efuse_key; + uint32_t efuse_km_rnd_switch_cycle; // 0 means use default + uint32_t km_rnd_switch_cycle; // 0 means use default + int km_use_sw_init_key; + struct huk_info *huk_info; + struct key_info *key_info; +}; + +/* state of km */ +#define KM_STATE_IDLE 0 +#define KM_STATE_LOAD 1 +#define KM_STATE_GAIN 2 +#define KM_STATE_BUSY 3 +#define KM_STATE_INVALID 4 + +/* state of huk generator + * values defined same as km + */ +#define HUK_STATE_IDLE 0 +#define HUK_STATE_LOAD 1 +#define HUK_STATE_GAIN 2 +#define HUK_STATE_BUSY 3 + +#define HUK_NOT_GENERATED 0 +#define HUK_GEN_VALID 1 +#define HUK_GEN_INVALID 2 + +#if __cplusplus +} +#endif +#endif diff --git a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h index 3c5d3750b8..b0faf36052 100644 --- a/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h +++ b/components/esp_rom/esp32c5/include/esp32c5/rom/rtc.h @@ -58,6 +58,7 @@ extern "C" { #define RTC_SLOW_CLK_CAL_REG LP_AON_STORE1_REG #define RTC_BOOT_TIME_LOW_REG LP_AON_STORE2_REG #define RTC_BOOT_TIME_HIGH_REG LP_AON_STORE3_REG +#define RTC_CLK_SRC_REF_CNT_ARRAY_REG LP_AON_STORE4_REG #define RTC_ENTRY_LENGTH_REG LP_AON_STORE5_REG #define RTC_ENTRY_ADDR_REG LP_AON_STORE6_REG #define RTC_RESET_CAUSE_REG LP_AON_STORE6_REG diff --git a/components/esp_rom/esp32c61/Kconfig.soc_caps.in b/components/esp_rom/esp32c61/Kconfig.soc_caps.in index c3d7974600..277f27d598 100644 --- a/components/esp_rom/esp32c61/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c61/Kconfig.soc_caps.in @@ -107,10 +107,6 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC bool default y -config ESP_ROM_CACHE_WB_INVLD_LOW_RANGE - bool - default y - config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY bool default y diff --git a/components/esp_rom/esp32c61/esp_rom_caps.h b/components/esp_rom/esp32c61/esp_rom_caps.h index 72a5220656..c94e743dde 100644 --- a/components/esp_rom/esp32c61/esp_rom_caps.h +++ b/components/esp_rom/esp32c61/esp_rom_caps.h @@ -32,5 +32,4 @@ #define ESP_ROM_HAS_SW_FLOAT (1) // ROM has libgcc software floating point emulation functions #define ESP_ROM_USB_OTG_NUM (-1) // No USB_OTG CDC in the ROM, set -1 for Kconfig usage. #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart) -#define ESP_ROM_CACHE_WB_INVLD_LOW_RANGE (1) // ROM `Cache_WriteBack_Addr` and `Cache_Invalidate_Addr` can only access low vaddr parts #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access. diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h b/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h index 7160a95d80..bab7236c16 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/ets_sys.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -421,6 +421,30 @@ typedef enum { } STATUS __attribute__((deprecated("Use ETS_STATUS instead"))); #endif +/** + * @brief Returns the offset from which the bootloader image is used to load. + * + * The offset can point to either the PRIMARY or RECOVERY bootloader. + * + * @note The bootloader offset variable in ROM is stored in a memory that will be reclaimed by heap component. + * Read it before the heap is initialized, otherwise it may return an invalid value. + * + * @return The offset of the active bootloader. + */ +uint32_t ets_get_bootloader_offset(void); + +/** + * @brief Sets the offset from which the bootloader image is used to load. + * + * The offset can point to either the PRIMARY or RECOVERY bootloader. + * + * @note The bootloader offset variable in ROM is stored in a memory that will be reclaimed by heap component. + * Setting it after the heap is initialized, may corrupt the heap memory. + * + * @param offset The offset value to set for the active bootloader. + */ +void ets_set_bootloader_offset(uint32_t offset); + /** * @} */ diff --git a/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h b/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h index f4272ea6e3..abaa4a8ab0 100644 --- a/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h +++ b/components/esp_rom/esp32c61/include/esp32c61/rom/gpio.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -44,7 +44,7 @@ typedef enum { /** - * @brief Change GPIO(0-24) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). + * @brief Change GPIO(0-29) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0). * There is no particular ordering guaranteed; so if the order of writes is significant, * calling code should divide a single call into multiple calls. * @@ -61,7 +61,7 @@ typedef enum { void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask); /** - * @brief Sample the value of GPIO input pins(0-24) and returns a bitmask. + * @brief Sample the value of GPIO input pins(0-29) and returns a bitmask. * @param None * * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0. @@ -93,7 +93,7 @@ void gpio_pin_wakeup_disable(void); /** * @brief set gpio input to a signal, one gpio can input to several signals. * - * @param uint32_t gpio : gpio number, 0~24 + * @param uint32_t gpio : gpio number, 0~29 * gpio == 0x30, input 0 to signal * gpio == 0x20, input 1 to signal * @@ -108,10 +108,10 @@ void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); /** * @brief set signal output to gpio, one signal can output to several gpios. * - * @param uint32_t gpio : gpio number, 0~24 + * @param uint32_t gpio : gpio number, 0~29 * * @param uint32_t signal_idx : signal index. - * signal_idx == 0x80, cancel output put to the gpio + * signal_idx == 0x100, cancel output put to the gpio * * @param bool out_inv : the signal output is invert or not * @@ -124,7 +124,7 @@ void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_ /** * @brief Select pad as a gpio function from IOMUX. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -133,7 +133,7 @@ void gpio_pad_select_gpio(uint32_t gpio_num); /** * @brief Set pad driver capability. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @param uint32_t drv : 0-3 * @@ -144,7 +144,7 @@ void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv); /** * @brief Pull up the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -153,7 +153,7 @@ void gpio_pad_pullup(uint32_t gpio_num); /** * @brief Pull down the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -162,7 +162,7 @@ void gpio_pad_pulldown(uint32_t gpio_num); /** * @brief Unhold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -171,7 +171,7 @@ void gpio_pad_unhold(uint32_t gpio_num); /** * @brief Hold the pad from gpio number. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -180,7 +180,7 @@ void gpio_pad_hold(uint32_t gpio_num); /** * @brief enable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ @@ -189,7 +189,7 @@ void gpio_pad_input_enable(uint32_t gpio_num); /** * @brief disable gpio pad input. * - * @param uint32_t gpio_num : gpio number, 0~24 + * @param uint32_t gpio_num : gpio number, 0~29 * * @return None */ diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld index 0bc6336107..2977468580 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.coexist.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.coexist.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -35,7 +31,7 @@ coex_hw_timer_set = 0x40000a64; coex_schm_interval_set = 0x40000a68; coex_schm_lock = 0x40000a6c; coex_schm_unlock = 0x40000a70; -/*coex_status_get = 0x40000a74;*/ +coex_status_get = 0x40000a74; coex_wifi_release = 0x40000a78; esp_coex_ble_conn_dynamic_prio_get = 0x40000a7c; /* Data (.data, .bss, .rodata) */ diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld index 645b536924..390992ee54 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -54,8 +50,6 @@ software_reset_cpu = 0x40000098; ets_clk_assist_debug_clock_enable = 0x4000009c; clear_super_wdt_reset_flag = 0x400000a0; disable_default_watchdog = 0x400000a4; -esp_rom_set_rtc_wake_addr = 0x400000a8; -esp_rom_get_rtc_wake_addr = 0x400000ac; send_packet = 0x400000b0; recv_packet = 0x400000b4; GetUartDevice = 0x400000b8; @@ -192,9 +186,9 @@ MMU_Set_Page_Mode = 0x40000624; MMU_Get_Page_Mode = 0x40000628; Cache_Sync_Items = 0x4000062c; Cache_Op_Addr = 0x40000630; -/*Cache_Invalidate_Addr = 0x40000634; rom version API has issue that unable to access higher vaddr range, use IDF patch */ +Cache_Invalidate_Addr = 0x40000634; Cache_Clean_Addr = 0x40000638; -/*Cache_WriteBack_Addr = 0x4000063c; rom version API has issue that unable to access higher vaddr range, use IDF patch */ +Cache_WriteBack_Addr = 0x4000063c; Cache_WriteBack_Invalidate_Addr = 0x40000640; Cache_Invalidate_All = 0x40000644; Cache_Clean_All = 0x40000648; @@ -369,7 +363,6 @@ ets_efuse_jtag_disabled = 0x400007fc; ets_efuse_usb_print_is_disabled = 0x40000800; ets_efuse_usb_download_mode_disabled = 0x40000804; ets_efuse_usb_device_disabled = 0x40000808; -ets_efuse_secure_boot_fast_wake_enabled = 0x4000080c; /*************************************** @@ -393,3 +386,60 @@ usb_serial_device_rx_one_char = 0x40000a20; usb_serial_device_rx_one_char_block = 0x40000a24; usb_serial_device_tx_flush = 0x40000a28; usb_serial_device_tx_one_char = 0x40000a2c; + + +/*************************************** + Group lldesc + ***************************************/ + +/* Functions */ +lldesc_build_chain = 0x400014dc; + + +/*************************************** + Group sip + ***************************************/ + +/* Functions */ +sip_after_tx_complete = 0x400014e0; +sip_alloc_to_host_evt = 0x400014e4; +sip_download_begin = 0x400014e8; +sip_get_ptr = 0x400014ec; +sip_get_state = 0x400014f0; +sip_init_attach = 0x400014f4; +sip_install_rx_ctrl_cb = 0x400014f8; +sip_install_rx_data_cb = 0x400014fc; +sip_is_active = 0x40001500; +sip_post_init = 0x40001504; +sip_reclaim_from_host_cmd = 0x40001508; +sip_reclaim_tx_data_pkt = 0x4000150c; +sip_send = 0x40001510; +sip_to_host_chain_append = 0x40001514; +sip_to_host_evt_send_done = 0x40001518; + + +/*************************************** + Group slc + ***************************************/ + +/* Functions */ +slc_add_credits = 0x4000151c; +slc_enable = 0x40001520; +slc_from_host_chain_fetch = 0x40001524; +slc_from_host_chain_recycle = 0x40001528; +slc_has_pkt_to_host = 0x4000152c; +slc_init_attach = 0x40001530; +slc_init_credit = 0x40001534; +slc_reattach = 0x40001538; +slc_send_to_host_chain = 0x4000153c; +slc_set_host_io_max_window = 0x40001540; +slc_to_host_chain_recycle = 0x40001544; + + +/*************************************** + Group recovery_bootloader + ***************************************/ + +/* Functions */ +ets_get_bootloader_offset = 0x40001548; +ets_set_bootloader_offset = 0x4000154c; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld index a864189192..82e495baba 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.net80211.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -36,11 +32,11 @@ ic_reset_extra_softap_rx_ba = 0x40000ab8; ieee80211_align_eb = 0x40000abc; ieee80211_ampdu_reorder = 0x40000ac0; ieee80211_ampdu_start_age_timer = 0x40000ac4; -ieee80211_encap_esfbuf = 0x40000ac8; +/*ieee80211_encap_esfbuf = 0x40000ac8;*/ ieee80211_is_tx_allowed = 0x40000acc; ieee80211_output_pending_eb = 0x40000ad0; ieee80211_output_process = 0x40000ad4; -/*ieee80211_set_tx_desc = 0x40000ad8;*/ +ieee80211_set_tx_desc = 0x40000ad8; ieee80211_classify = 0x40000adc; ieee80211_copy_eb_header = 0x40000ae0; ieee80211_recycle_cache_eb = 0x40000ae4; @@ -60,7 +56,7 @@ ieee80211_find_ext_elem = 0x40000b18; ieee80211_find_ie = 0x40000b1c; ieee80211_find_ext_ie = 0x40000b20; ieee80211_merge_mbssid_profile = 0x40000b24; -/*ieee80211_encap_esfbuf_htc = 0x40000b28;*/ +ieee80211_encap_esfbuf_htc = 0x40000b28; wifi_get_macaddr = 0x40000b2c; wifi_rf_phy_disable = 0x40000b30; wifi_rf_phy_enable = 0x40000b34; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld index d7ab643c47..43dc22b800 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.phy.ld @@ -21,293 +21,8 @@ phy_param_addr = 0x4000104c; chip762_phyrom_version = 0x40001050; chip762_phyrom_version_num = 0x40001054; -phy_get_rc_dout = 0x40001058; -phy_rc_cal = 0x4000105c; -phy_abs_temp = 0x40001060; -phy_set_chan_cal_interp = 0x40001064; -phy_loopback_mode_en = 0x40001068; -phy_get_data_sat = 0x4000106c; -phy_byte_to_word = 0x40001070; -phy_bb_bss_cbw40 = 0x40001074; -phy_set_chan_reg = 0x40001078; -phy_i2c_master_reset = 0x4000107c; -phy_chan14_mic_enable = 0x40001080; -phy_chan14_mic_cfg = 0x40001084; -phy_freq_module_resetn = 0x40001088; -phy_freq_chan_en_sw = 0x4000108c; -phy_write_chan_freq = 0x40001090; -phy_get_freq_mem_param = 0x40001094; -phy_get_freq_mem_addr = 0x40001098; -phy_wr_rf_freq_mem = 0x4000109c; -phy_read_rf_freq_mem = 0x400010a0; -phy_freq_i2c_mem_write = 0x400010a4; -phy_freq_reg_init = 0x400010a8; -phy_freq_num_get_data = 0x400010ac; -phy_freq_i2c_num_addr = 0x400010b0; -phy_freq_i2c_write_set = 0x400010b4; -phy_pll_dac_mem_update = 0x400010b8; -phy_pll_cap_mem_update = 0x400010bc; -phy_get_rf_freq_cap = 0x400010c0; -phy_get_rf_freq_init = 0x400010c4; -phy_freq_get_i2c_data = 0x400010c8; -phy_freq_i2c_data_write = 0x400010cc; -phy_set_chan_freq_hw_init = 0x400010d0; -phy_en_hw_set_freq = 0x400010d4; -phy_dis_hw_set_freq = 0x400010d8; -phy_wait_freq_set_busy = 0x400010dc; -phy_set_chan_freq_sw_start = 0x400010e0; -phy_wait_i2c_sdm_stable = 0x400010e4; -phy_reg_init = 0x400010e8; -phy_xpd_rf = 0x400010ec; -phy_close_rf = 0x400010f0; -phy_get_mac_addr = 0x400010f4; -phy_set_mac_data = 0x400010f8; -phy_rfcal_data_sub = 0x400010fc; -phy_rf_cal_data_recovery = 0x40001100; -phy_rf_cal_data_backup = 0x40001104; -phy_rfcal_data_check = 0x40001108; -phy_pwdet_reg_init = 0x4000110c; -phy_pwdet_sar2_init = 0x40001110; -phy_en_pwdet = 0x40001114; -phy_get_sar_sig_ref = 0x40001118; -phy_pwdet_tone_start = 0x4000111c; -phy_get_tone_sar_dout = 0x40001120; -phy_get_fm_sar_dout = 0x40001124; -phy_txtone_linear_pwr = 0x40001128; -phy_linear_to_db = 0x4000112c; -phy_get_power_db = 0x40001130; -phy_meas_tone_pwr_db = 0x40001134; -phy_pwdet_wait_idle = 0x40001138; -phy_pkdet_vol_start = 0x4000113c; -phy_read_sar_dout = 0x40001140; -phy_read_sar2_code = 0x40001144; -phy_get_sar2_vol = 0x40001148; -phy_get_pll_vol = 0x4000114c; -phy_tx_pwctrl_bg_init = 0x40001150; -phy_set_most_tpw = 0x40001154; -phy_get_most_tpw = 0x40001158; -phy_tx_state_out = 0x4000115c; -phy_ant_dft_cfg = 0x40001160; -phy_ant_wifitx_cfg = 0x40001164; -phy_ant_wifirx_cfg = 0x40001168; -phy_ant_bttx_cfg = 0x4000116c; -phy_ant_btrx_cfg = 0x40001170; -phy_chan_dump_cfg = 0x40001174; -phy_enable_low_rate = 0x40001178; -phy_disable_low_rate = 0x4000117c; -phy_is_low_rate_enabled = 0x40001180; -phy_dig_reg_backup = 0x40001184; -phy_chan_filt_set = 0x40001188; -phy_rx11blr_cfg = 0x4000118c; -phy_set_cca = 0x40001190; -phy_set_rx_sense = 0x40001194; -phy_rx_gain_force = 0x40001198; -phy_mhz2ieee = 0x4000119c; -phy_chan_to_freq = 0x400011a0; -phy_restart_cal = 0x400011a4; -phy_write_rfpll_sdm = 0x400011a8; -phy_wait_rfpll_cal_end = 0x400011ac; -phy_rfpll_set_freq = 0x400011b0; -phy_set_rf_freq_offset = 0x400011b4; -phy_set_rfpll_freq = 0x400011b8; -phy_set_channel_rfpll_freq = 0x400011bc; -phy_rfpll_cap_correct = 0x400011c0; -phy_rfpll_cap_init_cal = 0x400011c4; -phy_set_freq = 0x400011c8; -phy_write_pll_cap = 0x400011cc; -phy_read_pll_cap = 0x400011d0; -phy_chip_set_chan_misc = 0x400011d4; -phy_freq_set_reg = 0x400011d8; -phy_rfpll_chgp_cal = 0x400011dc; -phy_gen_rx_gain_table = 0x400011e0; -phy_get_rxbb_dc = 0x400011e4; -phy_wr_rx_gain_mem = 0x400011e8; -phy_rfpll_cap_track = 0x400011ec; -phy_param_track = 0x400011f0; -phy_txpwr_correct = 0x400011f4; -phy_txpwr_cal_track = 0x400011f8; -phy_bt_track_tx_power = 0x400011fc; -phy_wifi_track_tx_power = 0x40001200; -phy_bt_txdc_cal = 0x40001204; -phy_bt_txiq_cal = 0x40001208; -phy_txdc_cal_pwdet = 0x4000120c; -phy_txdc_cal = 0x40001210; -phy_txiq_get_mis_pwr = 0x40001214; -phy_txiq_cover = 0x40001218; -phy_rfcal_txiq = 0x4000121c; -phy_get_power_atten = 0x40001220; -phy_pwdet_ref_code = 0x40001224; -phy_pwdet_code_cal = 0x40001228; -phy_rfcal_txcap = 0x4000122c; -phy_tx_cap_init = 0x40001230; -phy_rfcal_pwrctrl = 0x40001234; -phy_tx_pwctrl_init_cal = 0x40001238; -phy_tx_pwctrl_init = 0x4000123c; -phy_bt_tx_pwctrl_init = 0x40001240; -phy_i2c_enter_critical_ = 0x40001244; -phy_i2c_exit_critical_ = 0x40001248; -phy_i2c_clk_sel = 0x4000124c; -phy_get_i2c_read_mask_ = 0x40001250; -phy_get_i2c_mst0_mask = 0x40001254; -phy_get_i2c_hostid_ = 0x40001258; -phy_chip_i2c_readReg_org = 0x4000125c; -phy_chip_i2c_readReg = 0x40001260; -phy_i2c_paral_set_mst0 = 0x40001264; -phy_i2c_paral_set_read = 0x40001268; -phy_i2c_paral_read = 0x4000126c; -phy_i2c_paral_write = 0x40001270; -phy_i2c_paral_write_num = 0x40001274; -phy_i2c_paral_write_mask = 0x40001278; -phy_i2c_readReg = 0x4000127c; -phy_chip_i2c_writeReg = 0x40001280; -phy_i2c_writeReg = 0x40001284; -phy_i2c_readReg_Mask = 0x40001288; -phy_i2c_writeReg_Mask = 0x4000128c; -phy_set_txcap_reg = 0x40001290; -phy_i2c_sar2_init_code = 0x40001294; -phy_test_filter_band_set = 0x40001298; -phy_filter_dcap_set = 0x4000129c; -phy_i2c_init1 = 0x400012a0; -phy_i2c_init2 = 0x400012a4; -phy_bias_reg_set = 0x400012a8; -phy_i2c_rc_cal_set = 0x400012ac; -phy_i2c_bbpll_set = 0x400012b0; -phy_adc_rate_set = 0x400012b4; -phy_dac_rate_set = 0x400012b8; -phy_encode_i2c_master = 0x400012bc; -phy_i2c_master_fill = 0x400012c0; -phy_i2c_master_mem_txcap = 0x400012c4; -/* phy_i2c_master_cmd_mem_init = 0x400012c8; */ -/* phy_i2c_master_mem_cfg = 0x400012cc; */ -phy_pbus_force_mode = 0x400012d0; -phy_pbus_rd_addr = 0x400012d4; -phy_pbus_rd_shift = 0x400012d8; -phy_pbus_force_test = 0x400012dc; -phy_pbus_rd = 0x400012e0; -phy_pbus_debugmode = 0x400012e4; -phy_pbus_workmode = 0x400012e8; -phy_pbus_set_rxgain = 0x400012ec; -phy_pbus_xpd_rx_off = 0x400012f0; -phy_pbus_xpd_rx_on = 0x400012f4; -phy_pbus_xpd_tx_off = 0x400012f8; -phy_pbus_xpd_tx_on = 0x400012fc; -phy_pbus_set_dco = 0x40001300; -phy_set_loopback_gain = 0x40001304; -phy_txcal_debuge_mode_ = 0x40001308; -phy_txcal_work_mode = 0x4000130c; -phy_pbus_clear_reg = 0x40001310; -phy_save_pbus_reg = 0x40001314; -phy_write_pbus_mem = 0x40001318; -phy_set_pbus_mem = 0x4000131c; -phy_disable_agc = 0x40001320; -phy_enable_agc = 0x40001324; -phy_disable_cca = 0x40001328; -phy_enable_cca = 0x4000132c; -phy_write_gain_mem = 0x40001330; -phy_bb_bss_cbw40_dig = 0x40001334; -phy_mac_tx_chan_offset = 0x40001338; -phy_rx_11b_opt = 0x4000133c; -phy_tx_paon_set = 0x40001340; -phy_i2cmst_reg_init = 0x40001344; -phy_bt_gain_offset = 0x40001348; -phy_fe_reg_init = 0x4000134c; -phy_mac_enable_bb = 0x40001350; -phy_bb_wdg_cfg = 0x40001354; -phy_fe_txrx_reset = 0x40001358; -phy_set_rx_comp_ = 0x4000135c; -phy_agc_reg_init = 0x40001360; -phy_btbb_wifi_bb_cfg2 = 0x40001364; -phy_bb_reg_init = 0x40001368; -phy_open_i2c_xpd = 0x4000136c; -phy_force_txrx_off = 0x40001370; -phy_txiq_set_reg = 0x40001374; -phy_rxiq_set_reg = 0x40001378; -phy_set_txclk_en = 0x4000137c; -phy_set_rxclk_en = 0x40001380; -phy_start_tx_tone_step = 0x40001384; -phy_stop_tx_tone = 0x40001388; -phy_bb_wdg_test_en = 0x4000138c; -phy_noise_floor_auto_set = 0x40001390; -phy_read_hw_noisefloor = 0x40001394; -phy_iq_corr_enable = 0x40001398; -phy_wifi_agc_sat_gain = 0x4000139c; -phy_bbpll_cal = 0x400013a0; -phy_ant_init = 0x400013a4; -phy_wifi_fbw_sel = 0x400013a8; -phy_bt_filter_reg = 0x400013ac; -phy_rx_sense_set = 0x400013b0; -phy_tx_state_set = 0x400013b4; -phy_close_pa = 0x400013b8; -phy_freq_correct = 0x400013bc; -phy_set_pbus_reg = 0x400013c0; -phy_wifi_rifs_mode_en = 0x400013c4; -phy_nrx_freq_set = 0x400013c8; -phy_fe_adc_on = 0x400013cc; -phy_force_pwr_index = 0x400013d0; -phy_fft_scale_force = 0x400013d4; -phy_force_rx_gain = 0x400013d8; -phy_wifi_enable_set = 0x400013dc; -phy_bb_wdt_rst_enable = 0x400013e0; -phy_bb_wdt_int_enable = 0x400013e4; -phy_bb_wdt_timeout_clear = 0x400013e8; -phy_bb_wdt_get_status = 0x400013ec; -phy_iq_est_enable = 0x400013f0; -phy_iq_est_disable = 0x400013f4; -phy_dc_iq_est = 0x400013f8; -phy_set_cal_rxdc = 0x400013fc; -phy_rxiq_get_mis = 0x40001400; -phy_rxiq_cover_mg_mp = 0x40001404; -phy_rfcal_rxiq = 0x40001408; -phy_get_rfcal_rxiq_data = 0x4000140c; -phy_get_dco_comp = 0x40001410; -phy_pbus_rx_dco_cal = 0x40001414; -phy_rxdc_est_min = 0x40001418; -phy_pbus_rx_dco_cal_1step = 0x4000141c; -phy_get_iq_value = 0x40001420; -phy_set_lb_txiq = 0x40001424; -phy_set_rx_gain_cal_iq = 0x40001428; -phy_set_rx_gain_cal_dc = 0x4000142c; -phy_spur_reg_write_one_tone = 0x40001430; -phy_spur_cal = 0x40001434; -phy_spur_coef_cfg = 0x40001438; -phy_bb_gain_index = 0x4000143c; -phy_rfrx_gain_index = 0x40001440; -phy_set_tsens_power_ = 0x40001444; -phy_set_tsens_range_ = 0x40001448; -phy_get_tsens_value_ = 0x4000144c; -phy_tsens_read_init = 0x40001450; -phy_code_to_temp = 0x40001454; -phy_tsens_dac_to_index = 0x40001458; -phy_tsens_dac_cal = 0x4000145c; -phy_tsens_code_read = 0x40001460; -phy_tsens_temp_read = 0x40001464; -phy_tsens_temp_read_local = 0x40001468; -phy_temp_to_power = 0x4000146c; -phy_txbbgain_to_index = 0x40001470; -phy_index_to_txbbgain = 0x40001474; -phy_bt_index_to_bb = 0x40001478; -phy_bt_bb_to_index = 0x4000147c; -phy_bt_get_tx_gain = 0x40001480; -phy_dig_gain_check = 0x40001484; -phy_wifi_get_tx_gain = 0x40001488; -phy_wifi_11g_rate_chg = 0x4000148c; -phy_set_tx_gain_mem = 0x40001490; -phy_get_rate_fcc_index = 0x40001494; -phy_get_chan_target_power = 0x40001498; -phy_get_tx_gain_value = 0x4000149c; -phy_wifi_get_target_power = 0x400014a0; -phy_wifi_get_tx_tab_ = 0x400014a4; -phy_wifi_set_tx_gain = 0x400014a8; -phy_bt_get_tx_tab_ = 0x400014ac; -phy_bt_set_tx_gain = 0x400014b0; -phy_bt_tx_gain_init = 0x400014b4; -phy_rate_to_index = 0x400014b8; -phy_get_target_pwr = 0x400014bc; -phy_get_max_pwr = 0x400014c0; -phy_get_pwr_index = 0x400014c4; -phy_chip_set_chan_ana = 0x400014d4; -phy_get_romfuncs = 0x400014d8; + /* Data (.data, .bss, .rodata) */ phy_param_rom = 0x4084fc6c; -rom_phyFuns = 0x4084fb84; +rom_phyFuns = 0x4084fc68; rom_phyFuns_eco2 = 0x4084fc68; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld index aa52ae4d88..bcdba8fbc5 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.pp.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.pp.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -34,7 +30,7 @@ hal_mac_clr_txq_state = 0x40000b80; hal_mac_get_txq_complete = 0x40000b84; hal_mac_deinit_twt_tx = 0x40000b88; hal_mac_is_dma_enable = 0x40000b8c; -/*hal_he_get_bss_color = 0x40000b90;*/ +hal_he_get_bss_color = 0x40000b90; hal_he_set_ersu = 0x40000b94; hal_he_get_mplen_addr_start = 0x40000b98; hal_he_get_mplen_addr_end = 0x40000b9c; @@ -53,11 +49,6 @@ hal_tsf_get_tbttstart = 0x40000bcc; hal_get_tsf_time = 0x40000bd0; hal_get_sta_tsf = 0x40000bd4; tsf_hal_get_tbtt_interval = 0x40000bd8; -tsf_hal_get_time = 0x400014cc; -/*pm_get_tbtt_count = 0x400014c8;*/ -tsf_hal_get_counter_value = 0x400014d0; -dbg_hal_check_clr_mplen_bitmap = 0x40000bdc; -dbg_hal_check_set_mplen_bitmap = 0x40000be0; ic_get_trc = 0x40000be4; ic_mac_deinit = 0x40000be8; /* ic_mac_init = 0x40000bec; */ @@ -105,7 +96,7 @@ mac_tx_set_plcp1 = 0x40000c90; mac_tx_set_plcp2 = 0x40000c94; mac_tx_set_len = 0x40000c98; mac_tx_set_htsig = 0x40000c9c; -/*mac_tx_set_hesig = 0x40000ca0;*/ +mac_tx_set_hesig = 0x40000ca0; mac_tx_set_tb = 0x40000ca4; mac_tx_set_mplen = 0x40000ca8; mac_tx_set_txop_q = 0x40000cac; @@ -116,14 +107,14 @@ pm_disable_sleep_delay_timer = 0x40000cbc; pm_dream = 0x40000cc0; pm_mac_wakeup = 0x40000cc4; pm_mac_sleep = 0x40000cc8; -/*pm_enable_active_timer = 0x40000ccc;*/ +pm_enable_active_timer = 0x40000ccc; pm_enable_sleep_delay_timer = 0x40000cd0; pm_local_tsf_process = 0x40000cd4; -//pm_set_beacon_filter = 0x40000cd8; +/*pm_set_beacon_filter = 0x40000cd8;*/ /*pm_is_in_wifi_slice_threshold = 0x40000cdc;*/ pm_is_waked = 0x40000ce0; -//pm_keep_alive = 0x40000ce4; -/*pm_on_beacon_rx = 0x40000ce8;*/ +/*pm_keep_alive = 0x40000ce4;*/ +pm_on_beacon_rx = 0x40000ce8; pm_on_data_rx = 0x40000cec; pm_on_data_tx = 0x40000cf0; pm_on_tbtt = 0x40000cf4; @@ -133,13 +124,13 @@ pm_on_isr_set_twt_target = 0x40000d00; pm_on_isr_twt_wake = 0x40000d04; pm_on_tsf_timer = 0x40000d08; pm_on_twt_force_tx = 0x40000d0c; -/*pm_parse_beacon = 0x40000d10;*/ +pm_parse_beacon = 0x40000d10; /*pm_process_tim = 0x40000d14;*/ pm_rx_beacon_process = 0x40000d18; pm_rx_data_process = 0x40000d1c; pm_sleep = 0x40000d20; pm_sleep_for = 0x40000d24; -/*pm_tbtt_process = 0x40000d28;*/ +//pm_tbtt_process = 0x40000d28; pm_tx_data_done_process = 0x40000d2c; pm_allow_tx = 0x40000d30; pm_extend_tbtt_adaptive_servo = 0x40000d34; @@ -157,14 +148,14 @@ pm_twt_set_target_tsf = 0x40000d60; pm_enable_twt_keep_alive_timer = 0x40000d64; /*pm_mac_try_enable_modem_state = 0x40000d68;*/ pm_beacon_monitor_tbtt_timeout_process = 0x40000d6c; -pm_update_next_tbtt = 0x40000d70; +//pm_update_next_tbtt = 0x40000d70; pm_twt_disallow_tx = 0x40000d74; -pm_clear_wakeup_signal = 0x40000d78; -/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c; -pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80; -//pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84; -//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88; -//pm_mac_modem_params_rt_update = 0x40000d8c;*/ +//pm_clear_wakeup_signal = 0x40000d78; +/*pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;*/ +/*pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;*/ +/*pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;*/ +/*pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;*/ +/*pm_mac_modem_params_rt_update = 0x40000d8c;*/ pm_update_at_next_beacon = 0x40000d90; pm_get_null_max_tx_time = 0x40000d94; pm_coex_schm_overall_period_get = 0x40000d98; @@ -195,7 +186,7 @@ ppResortTxAMPDU = 0x40000df8; ppResumeTxAMPDU = 0x40000dfc; ppRxFragmentProc = 0x40000e00; /*ppRxPkt = 0x40000e04;*/ -ppRxProtoProc = 0x40000e08; +/*ppRxProtoProc = 0x40000e08;*/ ppSearchTxQueue = 0x40000e0c; ppSearchTxframe = 0x40000e10; ppSelectNextQueue = 0x40000e14; @@ -228,7 +219,7 @@ pp_coex_tx_release = 0x40000e7c; ppAdd2AMPDUTail = 0x40000e80; ppDirectRecycleAmpdu = 0x40000e84; ppRegressAmpdu = 0x40000e88; -/*pp_timer_do_process = 0x40000e8c;*/ +pp_timer_do_process = 0x40000e8c; rcGetAmpduSched = 0x40000e90; rcUpdateRxDone = 0x40000e94; rc_get_trc = 0x40000e98; @@ -238,7 +229,7 @@ rcampduuprate = 0x40000ea4; rcClearCurAMPDUSched = 0x40000ea8; rcClearCurSched = 0x40000eac; rcClearCurStat = 0x40000eb0; -/* rcGetSched = 0x40000eb4;*/ +/*rcGetSched = 0x40000eb4;*/ rcLowerSched = 0x40000eb8; rcSetTxAmpduLimit = 0x40000ebc; rcTxUpdatePer = 0x40000ec0; @@ -290,8 +281,6 @@ wdev_process_tsf_timer = 0x40000f74; wdev_process_beacon_filter = 0x40000f78; wdev_process_mac_modem_beacon_miss = 0x40000f7c; config_is_cache_tx_buf_enabled = 0x40000f80; -config_get_wifi_feature_capabilities = 0x40000f84; -config_get_wifi_ampdu_tx_hetb_tid_limit = 0x40000f88; esp_test_disable_tx_statistics = 0x40000f8c; esp_test_enable_tx_statistics = 0x40000f90; esp_test_clr_tx_statistics = 0x40000f94; @@ -451,3 +440,33 @@ g_pp_timer_info_ptr = 0x4084fc98; g_rts_threshold_bytes_ptr = 0x4084fc94; g_he_max_apep_length_tab_ptr = 0x4084fc90; s_tbttstart = 0x4084fc88; + + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +//pm_get_tbtt_count = 0x400014c8; +tsf_hal_get_time = 0x400014cc; +tsf_hal_get_counter_value = 0x400014d0; + +/*************************************** + Group rom_pp + ***************************************/ + +/* Functions */ +pm_save_tbtt_info = 0x40001550; +pm_beacon_offset_is_enabled = 0x40001554; +pm_beacon_offset_is_sampling = 0x40001558; +pm_beacon_offset_add_total_counter = 0x4000155c; +pm_beacon_offset_add_loss_counter = 0x40001560; +//pm_beacon_offset_check = 0x40001564; +//pm_beacon_offset_get_average = 0x40001568; +//pm_beacon_offset_get_expect = 0x4000156c; +//pm_beacon_offset_get_params = 0x40001570; +pm_beacon_monitor_tbtt_stop = 0x40001574; +/*pm_enable_max_idle_timer = 0x40001578;*/ +/* Data (.data, .bss, .rodata) */ +s_pm_beacon_offset_ptr = 0x4084fc64; +s_pm_beacon_offset_config_ptr = 0x4084fc60; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld index 272c33c464..48e0ee2269 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.rvfp.ld @@ -1,14 +1,10 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -/* ROM function interface esp32c61.rom.rvfp.ld for esp32c61 - * - * - * Generated from ./target/esp32c6lite/interface-esp32c6lite.yml md5sum 27eb0efac0883ee622c22767242c9457 - * - * Compatible with ROM where ECO version equal or greater to 0. + +/* ROM function interface * * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. */ @@ -61,9 +57,10 @@ __muldf3 = 0x40000a14; __nedf2 = 0x40000a18; __subdf3 = 0x40000a1c; + /*************************************** Group libgcc -***************************************/ + ***************************************/ /* Functions */ __divsf3 = 0x40000828; diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld index 9f260f5ecd..9c61433ef0 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.systimer.ld @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,9 +9,8 @@ ***************************************/ /* Functions */ -/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ -/* systimer_hal_init = 0x400003d0; */ -/* systimer_hal_deinit = 0x400003d4; */ +systimer_hal_init = 0x400003d0; +systimer_hal_deinit = 0x400003d4; systimer_hal_set_tick_rate_ops = 0x400003d8; systimer_hal_get_counter_value = 0x400003dc; systimer_hal_get_time = 0x400003e0; diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h index c8611c0ec0..1a49334e9f 100644 --- a/components/esp_rom/include/esp_rom_sys.h +++ b/components/esp_rom/include/esp_rom_sys.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,9 +7,11 @@ #pragma once #include "sdkconfig.h" #include +#include #include #include #include "soc/reset_reasons.h" +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -151,6 +153,17 @@ uint32_t esp_rom_get_cpu_ticks_per_us(void); */ void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us); +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED || __DOXYGEN__ +/** + * @brief Returns the offset from which the bootloader image is used to load. + * + * The offset can point to either the PRIMARY or RECOVERY bootloader. + * + * @return The offset of the active bootloader. + */ +uint32_t esp_rom_get_bootloader_offset(void); +#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED + #ifdef __cplusplus } #endif diff --git a/components/esp_rom/linker.lf b/components/esp_rom/linker.lf index e856312648..944abe90a8 100644 --- a/components/esp_rom/linker.lf +++ b/components/esp_rom/linker.lf @@ -9,8 +9,6 @@ entries: esp_rom_cache_esp32s2_esp32s3 (noflash) if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y: esp_rom_cache_writeback_esp32s3 (noflash) - if ESP_ROM_CACHE_WB_INVLD_LOW_RANGE = y: - esp_rom_cache_esp32c61 (noflash) if HEAP_TLSF_USE_ROM_IMPL = y && (ESP_ROM_TLSF_CHECK_PATCH = y || HEAP_TLSF_CHECK_PATCH = y): esp_rom_tlsf (noflash) if SOC_SYSTIMER_SUPPORTED = y: diff --git a/components/esp_rom/patches/esp_rom_cache_esp32c61.c b/components/esp_rom/patches/esp_rom_cache_esp32c61.c deleted file mode 100644 index 6fddfb7500..0000000000 --- a/components/esp_rom/patches/esp_rom_cache_esp32c61.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include "sdkconfig.h" -#include "esp_rom_caps.h" -#include "soc/soc_caps.h" -#include "soc/cache_reg.h" -#include "soc/cache_struct.h" -#include "soc/ext_mem_defs.h" -#include "hal/assert.h" -#include "esp32c61/rom/cache.h" - -#include "esp_rom_sys.h" - -#define CACHE_MAX_SYNC_NUM ((CACHE_SYNC_SIZE + 1) >> 1) - -/** - * @brief Sync Cache items - * - * @param type sync type - * @param addr address - * @param bytes bytes to be synced - */ -__attribute__((always_inline)) -static inline void s_cache_sync_items(uint32_t type, uint32_t addr, uint32_t bytes) -{ - REG_WRITE(CACHE_SYNC_ADDR_REG, addr); - REG_SET_FIELD(CACHE_SYNC_SIZE_REG, CACHE_SYNC_SIZE, bytes); - REG_SET_BIT(CACHE_SYNC_CTRL_REG, type); - while (!REG_GET_BIT(CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE)) - ; -} - -int Cache_Invalidate_Addr(uint32_t vaddr, uint32_t size) -{ - uint32_t plus = 0; - uint32_t cache_line_size = 32; - uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM; - if (size == 0) { - HAL_ASSERT(false); - } - //aligned start address to cache line size - plus = vaddr & (cache_line_size - 1); - vaddr -= plus; - //make the length fit the start address - size += plus; - //aligned the length to cache line size(0->0) - size = (size + cache_line_size - 1) & ~(cache_line_size - 1); - - while (size > 0) { - //aligned to cache_max_sync_size, (0->cache_max_sync_size) - uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr; - if (this_size > size) { - this_size = size; - } - s_cache_sync_items(CACHE_SYNC_INVALIDATE, vaddr, this_size); - vaddr += this_size; - size -= this_size; - } - - return 0; -} - -int Cache_WriteBack_Addr(uint32_t vaddr, uint32_t size) -{ - uint32_t plus = 0; - uint32_t cache_line_size = 32; - uint32_t cache_max_sync_size = CACHE_MAX_SYNC_NUM; - if (size == 0) { - HAL_ASSERT(false); - } - //aligned start address to cache line size - plus = vaddr & (cache_line_size - 1); - vaddr -= plus; - //make the length fit the start address - size += plus; - //aligned the length to cache line size(0->0) - size = (size + cache_line_size - 1) & ~(cache_line_size - 1); - - while (size > 0) { - //aligned to cache_max_sync_size, (0->cache_max_sync_size) - uint32_t this_size = ((vaddr + cache_max_sync_size) & ~(cache_max_sync_size - 1)) - vaddr; - if (this_size > size) { - this_size = size; - } - s_cache_sync_items(CACHE_SYNC_WRITEBACK, vaddr, this_size); - vaddr += this_size; - size -= this_size; - } - - return 0; -} diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c index ccc7fa7c61..cc840e1c73 100644 --- a/components/esp_rom/patches/esp_rom_sys.c +++ b/components/esp_rom/patches/esp_rom_sys.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -103,3 +103,14 @@ void esp_rom_set_cpu_ticks_per_us(uint32_t ticks_per_us) #endif } #endif // CONFIG_IDF_TARGET_ESP32 + +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED +uint32_t esp_rom_get_bootloader_offset(void) +{ + static uint32_t offset_of_active_bootloader = UINT32_MAX; + if (offset_of_active_bootloader == UINT32_MAX) { + offset_of_active_bootloader = ets_get_bootloader_offset(); + } + return offset_of_active_bootloader; +} +#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED diff --git a/components/esp_rom/patches/esp_rom_systimer.c b/components/esp_rom/patches/esp_rom_systimer.c index df08c91aed..52f193560f 100644 --- a/components/esp_rom/patches/esp_rom_systimer.c +++ b/components/esp_rom/patches/esp_rom_systimer.c @@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co } #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200) -#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 +#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 void systimer_hal_init(systimer_hal_context_t *hal) { hal->dev = &SYSTIMER; @@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal) systimer_ll_enable_clock(hal->dev, false); hal->dev = NULL; } -#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 +#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL diff --git a/components/esp_security/include/esp_key_mgr.h b/components/esp_security/include/esp_key_mgr.h index e32e2acada..8c7d995148 100644 --- a/components/esp_security/include/esp_key_mgr.h +++ b/components/esp_security/include/esp_key_mgr.h @@ -22,7 +22,7 @@ extern "C" { #define KEY_MGR_ASSIST_INFO_SIZE 64 #define KEY_MGR_KEY_RECOVERY_INFO_SIZE 64 -#define KEY_MGR_HUK_INFO_SIZE HUK_INFO_SIZE +#define KEY_MGR_HUK_INFO_SIZE HUK_INFO_LEN #define KEY_MGR_HUK_RISK_ALERT_LEVEL HUK_RISK_ALERT_LEVEL /* AES deploy mode */ diff --git a/components/esp_security/src/esp_crypto_periph_clk.c b/components/esp_security/src/esp_crypto_periph_clk.c index a21a0f6487..a62c804b35 100644 --- a/components/esp_security/src/esp_crypto_periph_clk.c +++ b/components/esp_security/src/esp_crypto_periph_clk.c @@ -80,7 +80,10 @@ void esp_crypto_mpi_enable_periph_clk(bool enable) MPI_RCC_ATOMIC() { mpi_ll_enable_bus_clock(enable); if (enable) { + mpi_ll_power_up(); mpi_ll_reset_register(); + } else { + mpi_ll_power_down(); } } } @@ -141,9 +144,12 @@ void esp_crypto_ecdsa_enable_periph_clk(bool enable) void esp_crypto_key_mgr_enable_periph_clk(bool enable) { KEY_MANAGER_RCC_ATOMIC() { + key_mgr_ll_power_up(); key_mgr_ll_enable_bus_clock(enable); key_mgr_ll_enable_peripheral_clock(enable); - key_mgr_ll_reset_register(); + if (enable) { + key_mgr_ll_reset_register(); + } } } #endif diff --git a/components/esp_security/src/esp_ds.c b/components/esp_security/src/esp_ds.c index 6bdcad3376..0ca22898ee 100644 --- a/components/esp_security/src/esp_ds.c +++ b/components/esp_security/src/esp_ds.c @@ -17,6 +17,7 @@ #include "esp_cpu.h" #endif +#include "soc/soc_caps.h" #include "esp_ds.h" #include "esp_crypto_lock.h" #include "esp_crypto_periph_clk.h" @@ -37,6 +38,10 @@ #include "hal/sha_ll.h" #endif /* !CONFIG_IDF_TARGET_ESP32S2 */ +#ifdef SOC_KEY_MANAGER_DS_KEY_DEPLOY +#include "hal/key_mgr_hal.h" +#endif + /** * The vtask delay \c esp_ds_sign() is using while waiting for completion of the signing operation. */ @@ -247,22 +252,16 @@ static void ds_acquire_enable(void) // We also enable SHA and HMAC here. SHA is used by HMAC, HMAC is used by DS. esp_crypto_hmac_enable_periph_clk(true); - esp_crypto_sha_enable_periph_clk(true); - + esp_crypto_mpi_enable_periph_clk(true); esp_crypto_ds_enable_periph_clk(true); - - hmac_hal_start(); } static void ds_disable_release(void) { - ds_hal_finish(); - esp_crypto_ds_enable_periph_clk(false); - + esp_crypto_mpi_enable_periph_clk(false); esp_crypto_sha_enable_periph_clk(false); - esp_crypto_hmac_enable_periph_clk(false); esp_crypto_ds_lock_release(); @@ -326,12 +325,24 @@ esp_err_t esp_ds_start_sign(const void *message, ds_acquire_enable(); - // initiate hmac - uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); - if (conf_error) { - ds_disable_release(); - return ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL; +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY + if (key_id == HMAC_KEY_KM) { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_DS_KEY, ESP_KEY_MGR_USE_OWN_KEY); + ds_hal_set_key_source(DS_KEY_SOURCE_KEY_MGR); + } else { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_DS_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); + ds_hal_set_key_source(DS_KEY_SOURCE_EFUSE); +#endif + // initiate hmac + hmac_hal_start(); + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); + if (conf_error) { + ds_disable_release(); + return ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL; + } +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY } +#endif ds_hal_start(); @@ -339,6 +350,7 @@ esp_err_t esp_ds_start_sign(const void *message, int64_t start_time = get_time_us(); while (ds_ll_busy() != 0) { if ((get_time_us() - start_time) > SOC_DS_KEY_CHECK_MAX_WAIT_US) { + ds_hal_finish(); ds_disable_release(); return ESP_ERR_HW_CRYPTO_DS_INVALID_KEY; } @@ -348,6 +360,7 @@ esp_err_t esp_ds_start_sign(const void *message, *esp_ds_ctx = malloc(sizeof(esp_ds_context_t)); #endif if (!*esp_ds_ctx) { + ds_hal_finish(); ds_disable_release(); return ESP_ERR_NO_MEM; } @@ -398,6 +411,7 @@ esp_err_t esp_ds_finish_sign(void *signature, esp_ds_context_t *esp_ds_ctx) #endif hmac_hal_clean(); + ds_hal_finish(); ds_disable_release(); diff --git a/components/esp_security/src/esp_key_mgr.c b/components/esp_security/src/esp_key_mgr.c index 275bd2d575..decc730472 100644 --- a/components/esp_security/src/esp_key_mgr.c +++ b/components/esp_security/src/esp_key_mgr.c @@ -4,53 +4,60 @@ * SPDX-License-Identifier: Apache-2.0 */ // The Hardware Support layer for Key manager +#include #include #include -#include "assert.h" #include "esp_key_mgr.h" #include "esp_crypto_periph_clk.h" #include "esp_crypto_lock.h" #include "esp_log.h" #include "esp_err.h" -#include "esp_random.h" #include "esp_heap_caps.h" #include "esp_rom_crc.h" #include "esp_efuse.h" -#include "freertos/FreeRTOS.h" -#include "freertos/semphr.h" #include "hal/key_mgr_types.h" #include "hal/key_mgr_hal.h" -#include "hal/key_mgr_ll.h" #include "hal/huk_types.h" #include "hal/huk_hal.h" #include "rom/key_mgr.h" -#if CONFIG_LOG_DEFAULT_LEVEL_VERBOSE -#include "soc/huk_reg.h" -#include "soc/keymng_reg.h" -#endif - static const char *TAG = "esp_key_mgr"; static _lock_t s_key_mgr_ecdsa_key_lock; static _lock_t s_key_mgr_xts_aes_key_lock; +static _lock_t s_key_mgr_hmac_key_lock; +static _lock_t s_key_mgr_ds_key_lock; +static _lock_t s_key_mgr_psram_key_lock; ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_recovery_info_t) == sizeof(struct huk_key_block), "Size of esp_key_mgr_key_recovery_info_t should match huk_key_block (from ROM)"); - ESP_STATIC_ASSERT(sizeof(esp_key_mgr_key_info_t) == sizeof(struct key_info), "Size of esp_key_mgr_key_info_t should match key_info (from ROM)"); - ESP_STATIC_ASSERT(sizeof(esp_key_mgr_huk_info_t) == sizeof(struct huk_info), "Size of esp_key_mgr_huk_info_t should match huk_info (from ROM)"); static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: + case ESP_KEY_MGR_ECDSA_384_KEY: _lock_acquire(&s_key_mgr_ecdsa_key_lock); break; case ESP_KEY_MGR_XTS_AES_128_KEY: case ESP_KEY_MGR_XTS_AES_256_KEY: _lock_acquire(&s_key_mgr_xts_aes_key_lock); break; + case ESP_KEY_MGR_HMAC_KEY: + _lock_acquire(&s_key_mgr_hmac_key_lock); + break; + case ESP_KEY_MGR_DS_KEY: + _lock_acquire(&s_key_mgr_ds_key_lock); + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + _lock_acquire(&s_key_mgr_psram_key_lock); + break; + default: + ESP_LOGE(TAG, "Invalid key type"); + break; } ESP_LOGV(TAG, "Key lock acquired for key type %d", key_type); } @@ -58,13 +65,28 @@ static void esp_key_mgr_acquire_key_lock(esp_key_mgr_key_type_t key_type) static void esp_key_mgr_release_key_lock(esp_key_mgr_key_type_t key_type) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: + case ESP_KEY_MGR_ECDSA_384_KEY: _lock_release(&s_key_mgr_ecdsa_key_lock); break; case ESP_KEY_MGR_XTS_AES_128_KEY: case ESP_KEY_MGR_XTS_AES_256_KEY: _lock_release(&s_key_mgr_xts_aes_key_lock); break; + case ESP_KEY_MGR_HMAC_KEY: + _lock_release(&s_key_mgr_hmac_key_lock); + break; + case ESP_KEY_MGR_DS_KEY: + _lock_release(&s_key_mgr_ds_key_lock); + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + _lock_release(&s_key_mgr_psram_key_lock); + break; + default: + ESP_LOGE(TAG, "Invalid key type"); + break; } ESP_LOGV(TAG, "Key lock released for key type %d", key_type); } @@ -116,7 +138,7 @@ static void check_huk_risk_level(void) "It is recommended to immediately regenerate HUK in order" "to avoid permanently losing the deployed keys", huk_risk_level); } else { - ESP_LOGI(TAG, "HUK Risk level - %" PRId8 " within acceptable limit (%" PRIu32 ")", huk_risk_level, (uint32_t)KEY_MGR_HUK_RISK_ALERT_LEVEL); + ESP_LOGD(TAG, "HUK Risk level - %" PRId8 " within acceptable limit (%" PRIu32 ")", huk_risk_level, (uint32_t)KEY_MGR_HUK_RISK_ALERT_LEVEL); } } @@ -147,6 +169,30 @@ typedef struct { esp_key_mgr_huk_info_t *huk_recovery_info; } huk_deploy_config_t; +static esp_err_t configure_huk(esp_huk_mode_t huk_mode, uint8_t *huk_info) +{ + esp_err_t ret = huk_hal_configure(huk_mode, huk_info); + if (ret != ESP_OK) { + return ret; + } + +#if SOC_HUK_MEM_NEEDS_RECHARGE + if (!key_mgr_hal_is_huk_valid()) { + huk_hal_recharge_huk_memory(); + ret = huk_hal_configure(huk_mode, huk_info); + if (ret != ESP_OK) { + return ret; + } + } +#endif + + if (!key_mgr_hal_is_huk_valid()) { + return ESP_FAIL; + } + + return ESP_OK; +} + static esp_err_t deploy_huk(huk_deploy_config_t *config) { esp_err_t esp_ret = ESP_FAIL; @@ -157,41 +203,41 @@ static esp_err_t deploy_huk(huk_deploy_config_t *config) if (config->use_pre_generated_huk_info) { // If HUK info is provided then recover the HUK from given info check_huk_risk_level(); + if (!check_huk_info_validity(config->pre_generated_huk_info)) { ESP_LOGE(TAG, "HUK info is not valid"); heap_caps_free(huk_recovery_info); return ESP_ERR_INVALID_ARG; } + memcpy(huk_recovery_info, config->pre_generated_huk_info->info, KEY_MGR_HUK_INFO_SIZE); - ESP_LOGI(TAG, "Recovering HUK from given HUK recovery info"); - esp_ret = huk_hal_configure(ESP_HUK_MODE_RECOVERY, huk_recovery_info); + ESP_LOGD(TAG, "Recovering HUK from given HUK recovery info"); + + esp_ret = configure_huk(ESP_HUK_MODE_RECOVERY, huk_recovery_info); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to recover HUK"); heap_caps_free(huk_recovery_info); return esp_ret; } + // Copy the pre generated huk info in the output key recovery info memcpy(config->huk_recovery_info->info, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE); config->huk_recovery_info->crc = config->pre_generated_huk_info->crc; } else { // Generate new HUK and corresponding HUK info - ESP_LOGI(TAG, "Generating new HUK"); - esp_ret = huk_hal_configure(ESP_HUK_MODE_GENERATION, huk_recovery_info); + ESP_LOGD(TAG, "Generating new HUK"); + + esp_ret = configure_huk(ESP_HUK_MODE_GENERATION, huk_recovery_info); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to generate HUK"); heap_caps_free(huk_recovery_info); return esp_ret; } + memcpy(config->huk_recovery_info->info, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE); config->huk_recovery_info->crc = esp_rom_crc32_le(0, huk_recovery_info, KEY_MGR_HUK_INFO_SIZE); } - if (!key_mgr_hal_is_huk_valid()) { - ESP_LOGE(TAG, "HUK is invalid"); - heap_caps_free(huk_recovery_info); - return ESP_FAIL; - } - ESP_LOG_BUFFER_HEX_LEVEL("HUK INFO", huk_recovery_info, KEY_MGR_HUK_INFO_SIZE, ESP_LOG_DEBUG); // Free the local buffer for huk recovery info heap_caps_free(huk_recovery_info); @@ -202,8 +248,9 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config) { esp_err_t esp_ret = ESP_FAIL; key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); + if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) { - // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 this part shall be already executed + // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed huk_deploy_config_t huk_deploy_config = {}; huk_deploy_config.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info; huk_deploy_config.pre_generated_huk_info = &config->key_config->huk_info; @@ -212,7 +259,7 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config) if (esp_ret != ESP_OK) { return esp_ret; } - ESP_LOGI(TAG, "HUK deployed successfully"); + ESP_LOGD(TAG, "HUK deployed successfully"); } // STEP 1: Init Step @@ -223,61 +270,69 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config) if (!key_recovery_info) { return ESP_ERR_NO_MEM; } - // Set key purpose (XTS/ECDSA) + + // Set key purpose ESP_LOGD(TAG, "Key purpose = %d", config->key_purpose); key_mgr_hal_set_key_purpose(config->key_purpose); // Set key length for XTS-AES key esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type; - if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_256); - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_512); + if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256); + } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512); } if (config->key_config->use_pre_generated_sw_init_key) { key_mgr_hal_use_sw_init_key(); - } else { - if (!esp_efuse_find_purpose(ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY, NULL)) { - ESP_LOGE(TAG, "Could not find key with purpose KM_INIT_KEY"); - heap_caps_free(key_recovery_info); - return ESP_FAIL; - } + } else if (!esp_efuse_find_purpose(ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY, NULL)) { + ESP_LOGE(TAG, "Could not find key with purpose KM_INIT_KEY"); + heap_caps_free(key_recovery_info); + return ESP_FAIL; } key_mgr_hal_start(); key_mgr_hal_continue(); + // Step 2: Load phase key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD); + if (config->key_config->use_pre_generated_sw_init_key) { key_mgr_hal_write_sw_init_key(config->key_config->sw_init_key, KEY_MGR_SW_INIT_KEY_SIZE); + ESP_LOG_BUFFER_HEX_LEVEL("SW_INIT_KEY", config->key_config->sw_init_key, KEY_MGR_SW_INIT_KEY_SIZE, ESP_LOG_DEBUG); } - ESP_LOG_BUFFER_HEX_LEVEL("SW_INIT_KEY", config->key_config->sw_init_key, KEY_MGR_SW_INIT_KEY_SIZE, ESP_LOG_DEBUG); ESP_LOGD(TAG, "Writing Information into Key Manager Registers"); + key_mgr_hal_write_assist_info(config->key_config->k2_info, KEY_MGR_K2_INFO_SIZE); ESP_LOG_BUFFER_HEX_LEVEL("K2_INFO", config->key_config->k2_info, KEY_MGR_K2_INFO_SIZE, ESP_LOG_DEBUG); + key_mgr_hal_write_public_info(config->k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); ESP_LOG_BUFFER_HEX_LEVEL("K1_ENCRYPTED", config->k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE, ESP_LOG_DEBUG); + key_mgr_hal_continue(); + // Step 3: Gain phase key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN); + key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); ESP_LOG_BUFFER_HEX_LEVEL("KEY_RECOVERY_INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG); - if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1) { + if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) { if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) { ESP_LOGE(TAG, "Key deployment is not valid"); heap_caps_free(key_recovery_info); return ESP_FAIL; } - ESP_LOGI(TAG, "Key deployment valid"); + ESP_LOGD(TAG, "Key deployment valid"); } + // Wait till Key Manager deployment is complete key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); - if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2) { + + if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) { memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); @@ -285,6 +340,7 @@ static esp_err_t key_mgr_deploy_key_aes_mode(aes_deploy_config_t *config) memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); } + heap_caps_free(key_recovery_info); config->key_info->key_type = config->key_config->key_type; config->key_info->magic = KEY_HUK_SECTOR_MAGIC; @@ -298,7 +354,7 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t return ESP_ERR_INVALID_ARG; } - ESP_LOGI(TAG, "Key deployment in AES mode"); + ESP_LOGD(TAG, "Key deployment in AES mode"); aes_deploy_config_t aes_deploy_config = {}; aes_deploy_config.key_config = key_config; @@ -306,13 +362,32 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t aes_deploy_config.k1_encrypted = key_config->k1_encrypted[0]; esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type; - if (key_type == ESP_KEY_MGR_ECDSA_KEY) { - aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA; - } else if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { + switch (key_type) { + case ESP_KEY_MGR_ECDSA_192_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192; + break; + case ESP_KEY_MGR_ECDSA_256_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256; + break; + case ESP_KEY_MGR_XTS_AES_128_KEY: aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128; - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { + break; + case ESP_KEY_MGR_XTS_AES_256_KEY: aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1; - } else { + break; + case ESP_KEY_MGR_HMAC_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC; + break; + case ESP_KEY_MGR_DS_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS; + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128; + break; + case ESP_KEY_MGR_PSRAM_256_KEY: + aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1; + break; + default: ESP_LOGE(TAG, "Invalid key type"); return ESP_ERR_INVALID_ARG; } @@ -322,21 +397,25 @@ esp_err_t esp_key_mgr_deploy_key_in_aes_mode(const esp_key_mgr_aes_key_config_t esp_err_t esp_ret = key_mgr_deploy_key_aes_mode(&aes_deploy_config); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Key deployment in AES mode failed"); + goto cleanup; } + aes_deploy_config.huk_deployed = true; - if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - aes_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2; + if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + aes_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2; aes_deploy_config.k1_encrypted = key_config->k1_encrypted[1]; esp_ret = key_mgr_deploy_key_aes_mode(&aes_deploy_config); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Key deployment in AES mode failed"); + goto cleanup; } } // Set the Key Manager Static Register to use own key for the respective key type key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY); +cleanup: esp_key_mgr_release_hardware(true); return esp_ret; } @@ -358,17 +437,13 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config) if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_recovered)) { check_huk_risk_level(); - esp_err_t esp_ret = huk_hal_configure(ESP_HUK_MODE_RECOVERY, config->key_recovery_info->huk_info.info); + esp_err_t esp_ret = configure_huk(ESP_HUK_MODE_RECOVERY, config->key_recovery_info->huk_info.info); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to recover HUK"); - return ESP_FAIL; + return esp_ret; } - if (!key_mgr_hal_is_huk_valid()) { - ESP_LOGE(TAG, "HUK is invalid"); - // TODO - define error code - return ESP_FAIL; - } - ESP_LOGI(TAG, "HUK recovered successfully"); + + ESP_LOGD(TAG, "HUK recovered successfully"); ESP_LOG_BUFFER_HEX_LEVEL("HUK INFO", config->key_recovery_info->huk_info.info, KEY_MGR_HUK_INFO_SIZE, ESP_LOG_DEBUG); config->huk_recovered = true; } @@ -377,17 +452,18 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config) // Set AES-XTS key len esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_recovery_info->key_type; - if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_256); - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_512); + if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256); + } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512); } key_mgr_hal_set_key_purpose(config->key_purpose); key_mgr_hal_start(); key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD); - if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2) { + + if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) { if (!check_key_info_validity(&config->key_recovery_info->key_info[1])) { ESP_LOGE(TAG, "Key info not valid"); return ESP_FAIL; @@ -405,6 +481,7 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config) key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN); + if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1) { if (!key_mgr_hal_is_key_deployment_valid(config->key_recovery_info->key_type)) { ESP_LOGD(TAG, "Key deployment is not valid"); @@ -412,6 +489,7 @@ static esp_err_t key_mgr_recover_key(key_recovery_config_t *config) } ESP_LOGD(TAG, "Key Recovery valid"); } + key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); return ESP_OK; @@ -423,60 +501,85 @@ esp_err_t esp_key_mgr_activate_key(esp_key_mgr_key_recovery_info_t *key_recovery return ESP_ERR_INVALID_ARG; } - esp_key_mgr_key_purpose_t key_purpose; ESP_LOGD(TAG, "Activating key of type %d", key_recovery_info->key_type); + esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_recovery_info->key_type; - if (key_type == ESP_KEY_MGR_ECDSA_KEY) { - key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA; - } else if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { + esp_key_mgr_key_purpose_t key_purpose; + + switch (key_type) { + case ESP_KEY_MGR_ECDSA_192_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192; + break; + case ESP_KEY_MGR_ECDSA_256_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256; + break; + case ESP_KEY_MGR_XTS_AES_128_KEY: key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128; - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { + break; + case ESP_KEY_MGR_XTS_AES_256_KEY: key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1; - } else { + break; + case ESP_KEY_MGR_HMAC_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC; + break; + case ESP_KEY_MGR_DS_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS; + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128; + break; + case ESP_KEY_MGR_PSRAM_256_KEY: + key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1; + break; + default: ESP_LOGE(TAG, "Invalid key type"); return ESP_ERR_INVALID_ARG; } esp_err_t esp_ret = ESP_FAIL; esp_key_mgr_acquire_key_lock(key_type); - key_recovery_config_t key_recovery_config = {}; - key_recovery_config.key_recovery_info = key_recovery_info; - key_recovery_config.key_purpose = key_purpose; + key_recovery_config_t key_recovery_config = { + .key_recovery_info = key_recovery_info, + .key_purpose = key_purpose, + }; esp_key_mgr_acquire_hardware(false); esp_ret = key_mgr_recover_key(&key_recovery_config); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to recover key"); + esp_key_mgr_release_key_lock(key_type); goto cleanup; } - if (key_recovery_info->key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_recovery_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2; + if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + key_recovery_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2; esp_ret = key_mgr_recover_key(&key_recovery_config); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to recover key"); + esp_key_mgr_release_key_lock(key_type); goto cleanup; } } // Set the Key Manager Static Register to use own key for the respective key type - key_mgr_hal_set_key_usage(key_recovery_info->key_type, ESP_KEY_MGR_USE_OWN_KEY); - ESP_LOGI(TAG, "Key activation for type %d successful", key_recovery_info->key_type); + key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY); + esp_key_mgr_release_key_lock(key_type); + + ESP_LOGD(TAG, "Key activation for type %d successful", key_type); return ESP_OK; cleanup: - ESP_LOGI(TAG, "Key activation failed"); + ESP_LOGE(TAG, "Key activation failed"); esp_key_mgr_release_hardware(false); return esp_ret; } esp_err_t esp_key_mgr_deactivate_key(esp_key_mgr_key_type_t key_type) { - ESP_LOGD(TAG, "Deactivating key of type %d", key_type); esp_key_mgr_release_key_lock(key_type); esp_key_mgr_release_hardware(false); - ESP_LOGI(TAG, "Key deactivation successful"); + ESP_LOGD(TAG, "Key deactivation successful for type %d", key_type); return ESP_OK; } @@ -495,7 +598,7 @@ static esp_err_t key_mgr_deploy_key_ecdh0_mode(ecdh0_deploy_config_t *config) key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) { - // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 this part shall be already executed + // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed huk_deploy_config_t huk_deploy_config; huk_deploy_config.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info; huk_deploy_config.pre_generated_huk_info = &config->key_config->huk_info; @@ -504,7 +607,7 @@ static esp_err_t key_mgr_deploy_key_ecdh0_mode(ecdh0_deploy_config_t *config) if (esp_ret != ESP_OK) { return esp_ret; } - ESP_LOGI(TAG, "HUK deployed successfully"); + ESP_LOGD(TAG, "HUK deployed successfully"); } uint8_t *key_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_KEY_RECOVERY_INFO_SIZE, MALLOC_CAP_INTERNAL); @@ -518,46 +621,50 @@ static esp_err_t key_mgr_deploy_key_ecdh0_mode(ecdh0_deploy_config_t *config) // Set AES-XTS key len esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type; - if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_256); - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_512); + if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256); + } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512); } - // Set key purpose (XTS/ECDSA) + // Set key purpose key_mgr_hal_set_key_purpose(config->key_purpose); key_mgr_hal_start(); key_mgr_hal_continue(); // Step 2: Load phase key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD); + ESP_LOGD(TAG, "Writing Information into Key Manager Registers"); key_mgr_hal_write_public_info(config->k1_G, KEY_MGR_ECDH0_INFO_SIZE); + key_mgr_hal_continue(); // Step 3: Gain phase key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN); + key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); key_mgr_hal_read_assist_info(config->ecdh0_key_info); ESP_LOG_BUFFER_HEX_LEVEL("KEY_MGR KEY INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG); - ESP_LOGI(TAG, "HUK deplpoyed is Valid"); + ESP_LOGD(TAG, "HUK deployed is valid"); - if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1) { + if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) { if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) { ESP_LOGE(TAG, "Key deployment is not valid"); heap_caps_free(key_recovery_info); return ESP_FAIL; } - ESP_LOGI(TAG, "Key deployment valid"); + ESP_LOGD(TAG, "Key deployment valid"); } + // Wait till Key Manager deployment is complete key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); - if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2) { + + if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) { memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); - } else { memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); @@ -576,25 +683,51 @@ esp_err_t esp_key_mgr_deploy_key_in_ecdh0_mode(const esp_key_mgr_ecdh0_key_confi if (key_config == NULL || key_info == NULL || ecdh0_key_info == NULL) { return ESP_ERR_INVALID_ARG; } - ESP_LOGI(TAG, "Key Deployment in ECDH0 mode"); - esp_key_mgr_key_purpose_t key_purpose; + + ESP_LOGD(TAG, "Key Deployment in ECDH0 mode"); + esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type; - ecdh0_deploy_config_t ecdh0_deploy_config = {}; - ecdh0_deploy_config.key_config = key_config; - ecdh0_deploy_config.key_info = key_info; - ecdh0_deploy_config.k1_G = key_config->k1_G[0]; + ecdh0_deploy_config_t ecdh0_deploy_config = { + .key_config = key_config, + .key_info = key_info, + .k1_G = key_config->k1_G[0], + }; - if (key_type == ESP_KEY_MGR_ECDSA_KEY) { - ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA; + switch (key_type) { + case ESP_KEY_MGR_ECDSA_192_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192; ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; - } else if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { + break; + case ESP_KEY_MGR_ECDSA_256_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256; + ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; + break; + case ESP_KEY_MGR_XTS_AES_128_KEY: ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128; ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { + break; + case ESP_KEY_MGR_XTS_AES_256_KEY: ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1; ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; - } else { + break; + case ESP_KEY_MGR_HMAC_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC; + ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; + break; + case ESP_KEY_MGR_DS_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS; + ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128; + ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; + break; + case ESP_KEY_MGR_PSRAM_256_KEY: + ecdh0_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1; + ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[0]; + break; + default: ESP_LOGE(TAG, "Invalid key type"); return ESP_ERR_INVALID_ARG; } @@ -605,13 +738,12 @@ esp_err_t esp_key_mgr_deploy_key_in_ecdh0_mode(const esp_key_mgr_ecdh0_key_confi if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Failed to deploy key in ECDH0 mode"); } + ecdh0_deploy_config.huk_deployed = true; - if (key_config->key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2; - ecdh0_deploy_config.key_purpose = key_purpose; + if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + ecdh0_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2; ecdh0_deploy_config.k1_G = key_config->k1_G[1]; - ecdh0_deploy_config.ecdh0_key_info = ecdh0_key_info->k2_G[1]; esp_ret = key_mgr_deploy_key_ecdh0_mode(&ecdh0_deploy_config); if (esp_ret != ESP_OK) { @@ -637,17 +769,20 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config) { esp_err_t esp_ret = ESP_FAIL; key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); + if ((!key_mgr_hal_is_huk_valid()) || (!config->huk_deployed)) { - // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 this part shall be already executed - huk_deploy_config_t huk_deploy_config = {}; - huk_deploy_config.use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info; - huk_deploy_config.pre_generated_huk_info = &config->key_config->huk_info; - huk_deploy_config.huk_recovery_info = &config->key_info->huk_info; + // For purpose ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 or ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 this part shall be already executed + huk_deploy_config_t huk_deploy_config = { + .use_pre_generated_huk_info = config->key_config->use_pre_generated_huk_info, + .pre_generated_huk_info = &config->key_config->huk_info, + .huk_recovery_info = &config->key_info->huk_info, + }; + esp_ret = deploy_huk(&huk_deploy_config); if (esp_ret != ESP_OK) { return esp_ret; } - ESP_LOGI(TAG, "HUK deployed successfully"); + ESP_LOGD(TAG, "HUK deployed successfully"); } // Configure deployment mode to RANDOM @@ -655,10 +790,10 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config) // Set AES-XTS key len esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) config->key_config->key_type; - if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_256); - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - key_mgr_hal_set_xts_aes_key_len(ESP_KEY_MGR_XTS_AES_LEN_512); + if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_PSRAM_128_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_256); + } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + key_mgr_hal_set_xts_aes_key_len(key_type, ESP_KEY_MGR_XTS_AES_LEN_512); } uint8_t *key_recovery_info = (uint8_t *) heap_caps_calloc(1, KEY_MGR_KEY_RECOVERY_INFO_SIZE, MALLOC_CAP_INTERNAL); @@ -673,35 +808,37 @@ static esp_err_t key_mgr_deploy_key_random_mode(random_deploy_config_t *config) key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_LOAD); key_mgr_hal_continue(); + // No configuration for Random deploy mode key_mgr_wait_for_state(ESP_KEY_MGR_STATE_GAIN); key_mgr_hal_read_public_info(key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); ESP_LOG_BUFFER_HEX_LEVEL("KEY_MGR KEY INFO", key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE, ESP_LOG_DEBUG); - if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1) { + if (config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 && config->key_purpose != ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1) { if (!key_mgr_hal_is_key_deployment_valid(config->key_config->key_type)) { ESP_LOGE(TAG, "Key deployment is not valid"); heap_caps_free(key_recovery_info); return ESP_FAIL; } - ESP_LOGI(TAG, "Key deployment valid"); + ESP_LOGD(TAG, "Key deployment valid"); } // Wait till Key Manager deployment is complete key_mgr_hal_continue(); key_mgr_wait_for_state(ESP_KEY_MGR_STATE_IDLE); - if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2) { + + if (config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 || config->key_purpose == ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2) { memcpy(config->key_info->key_info[1].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[1].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); - } else { memcpy(config->key_info->key_info[0].info, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); config->key_info->key_info[0].crc = esp_rom_crc32_le(0, key_recovery_info, KEY_MGR_KEY_RECOVERY_INFO_SIZE); } + heap_caps_free(key_recovery_info); + config->key_info->key_type = config->key_config->key_type; config->key_info->magic = KEY_HUK_SECTOR_MAGIC; - return ESP_OK; } @@ -711,20 +848,41 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con return ESP_ERR_INVALID_ARG; } - ESP_LOGI(TAG, "Key deployment in Random mode"); + ESP_LOGD(TAG, "Key deployment in Random mode"); + + random_deploy_config_t random_deploy_config = { + .key_config = key_config, + .key_info = key_recovery_info, + }; - random_deploy_config_t random_deploy_config = {}; - random_deploy_config.key_config = key_config; - random_deploy_config.key_info = key_recovery_info; esp_key_mgr_key_type_t key_type = (esp_key_mgr_key_type_t) key_config->key_type; - if (key_type == ESP_KEY_MGR_ECDSA_KEY) { - random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA; - } else if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY) { + switch (key_type) { + case ESP_KEY_MGR_ECDSA_192_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192; + break; + case ESP_KEY_MGR_ECDSA_256_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256; + break; + case ESP_KEY_MGR_XTS_AES_128_KEY: random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128; - } else if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { + break; + case ESP_KEY_MGR_XTS_AES_256_KEY: random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1; - } else { + break; + case ESP_KEY_MGR_HMAC_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_HMAC; + break; + case ESP_KEY_MGR_DS_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_DS; + break; + case ESP_KEY_MGR_PSRAM_128_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128; + break; + case ESP_KEY_MGR_PSRAM_256_KEY: + random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1; + break; + default: ESP_LOGE(TAG, "Invalid key type"); return ESP_ERR_INVALID_ARG; } @@ -736,10 +894,11 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con ESP_LOGE(TAG, "Key deployment in Random mode failed"); return ESP_FAIL; } + random_deploy_config.huk_deployed = true; - if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { - random_deploy_config.key_purpose = ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2; + if (key_type == ESP_KEY_MGR_XTS_AES_256_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + random_deploy_config.key_purpose = key_type == ESP_KEY_MGR_XTS_AES_256_KEY ? ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 : ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2; esp_ret = key_mgr_deploy_key_random_mode(&random_deploy_config); if (esp_ret != ESP_OK) { ESP_LOGE(TAG, "Key deployment in Random mode failed"); @@ -748,8 +907,9 @@ esp_err_t esp_key_mgr_deploy_key_in_random_mode(const esp_key_mgr_random_key_con } // Set the Key Manager Static Register to use own key for the respective key type - key_mgr_hal_set_key_usage(key_config->key_type, ESP_KEY_MGR_USE_OWN_KEY); + key_mgr_hal_set_key_usage(key_type, ESP_KEY_MGR_USE_OWN_KEY); esp_key_mgr_release_hardware(true); + return esp_ret; } diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c index 26b99a94a2..14ede2dc0d 100644 --- a/components/esp_security/src/init.c +++ b/components/esp_security/src/init.c @@ -14,16 +14,20 @@ #include "esp_err.h" #include "hal/efuse_hal.h" -#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY -#include "hal/key_mgr_ll.h" +#if SOC_HUK_MEM_NEEDS_RECHARGE +#include "hal/huk_hal.h" #endif +#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT +#include "hal/key_mgr_ll.h" +#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */ + __attribute__((unused)) static const char *TAG = "esp_security"; static void esp_key_mgr_init(void) { // The following code initializes the key manager. -#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY +#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT // Enable key manager clock // Using ll APIs which do not require critical section _key_mgr_ll_enable_bus_clock(true); @@ -31,7 +35,7 @@ static void esp_key_mgr_init(void) _key_mgr_ll_reset_register(); while (key_mgr_ll_get_state() != ESP_KEY_MGR_STATE_IDLE) { }; -#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY */ +#endif /* SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT */ } ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103) diff --git a/components/esp_security/test_apps/crypto_drivers/main/hmac_key.bin b/components/esp_security/test_apps/crypto_drivers/main/hmac_key.bin new file mode 100644 index 0000000000..2ea3dec3e1 --- /dev/null +++ b/components/esp_security/test_apps/crypto_drivers/main/hmac_key.bin @@ -0,0 +1,2 @@ + +  \ No newline at end of file diff --git a/components/esp_security/test_apps/crypto_drivers/main/hmac_test_cases.h b/components/esp_security/test_apps/crypto_drivers/main/hmac_test_cases.h new file mode 100644 index 0000000000..4d6e80fceb --- /dev/null +++ b/components/esp_security/test_apps/crypto_drivers/main/hmac_test_cases.h @@ -0,0 +1,1200 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#include + +/* Allow testing varying message lengths (truncating the same message) + for various results */ +typedef struct { + int msglen; + uint8_t result[32]; +} hmac_result; + +static const uint8_t key_data[32] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32 +}; + +// Results calculated with Python: +// +// import hmac, hashlib, binascii +// key = b"".join([chr(x).encode() for x in range(1,33)]) +// ", ".join("0x%x" % x for x in hmac.HMAC(key, b"\x00" * 32, hashlib.sha256).digest() ) +static const uint8_t token_data[32] = { + 0xb2, 0xa4, 0x9b, 0x1c, 0xce, 0x1b, 0xe9, 0x22, 0xbb, 0x7e, 0x43, 0x12, 0x77, 0x41, 0x3e, 0x3e, + 0x8e, 0x6c, 0x3e, 0x8e, 0x6e, 0x17, 0x62, 0x5c, 0x50, 0xac, 0x66, 0xa9, 0xa8, 0x57, 0x94, 0x9b +}; + +// Produce the HMAC of various numbers of zeroes +// +// Results calculated with Python: +// +// import hmac, hashlib, binascii +// key = b"".join([chr(x).encode() for x in range(1,33)]) +// ", ".join("0x%x" % x for x in hmac.HMAC(key, b"\x00" * 128, hashlib.sha256).digest() ) + +static const hmac_result zero_results[] = { + { + .msglen = 64, + .result = { + 0x4f, 0x34, 0x31, 0x8a, 0x45, 0x74, 0x4d, 0x71, 0x53, 0xb7, 0x18, 0xf4, 0x78, 0x1c, 0xbb, 0x10, + 0x19, 0x60, 0xba, 0x9c, 0x8c, 0xe2, 0x3b, 0xc1, 0x1d, 0x79, 0xb6, 0x3c, 0xae, 0x0f, 0x30, 0xc8, + }, + }, + { + .msglen = 128, + .result = { + 0x40, 0xd5, 0xb9, 0xe6, 0x25, 0x8f, 0x3c, 0xd0, 0x3f, 0xb9, 0x6c, 0xa3, 0xa7, 0x2b, 0x84, 0xe3, + 0x1d, 0x4b, 0x4e, 0x65, 0xf8, 0x7b, 0x3e, 0x3, 0x26, 0x2, 0xcd, 0x49, 0x73, 0xf0, 0xac, 0x25 + }, + }, + { + .msglen = 48, + .result = { + 0x84, 0x4e, 0x45, 0xcd, 0xb3, 0x8f, 0xf8, 0x96, 0xe7, 0xe7, 0x80, 0x48, 0x31, 0x89, 0x79, 0xa7, + 0x5d, 0x80, 0xd1, 0xbf, 0x3, 0xca, 0x9b, 0x78, 0x4f, 0x3b, 0x42, 0x80, 0xb9, 0x6, 0x19, 0x7d + }, + }, + { + .msglen = 32, + .result = { + 0xb2, 0xa4, 0x9b, 0x1c, 0xce, 0x1b, 0xe9, 0x22, 0xbb, 0x7e, 0x43, 0x12, 0x77, 0x41, 0x3e, 0x3e, + 0x8e, 0x6c, 0x3e, 0x8e, 0x6e, 0x17, 0x62, 0x5c, 0x50, 0xac, 0x66, 0xa9, 0xa8, 0x57, 0x94, 0x9b + }, + }, + { + .msglen = 33, + .result = { + 0x98, 0xd7, 0x44, 0xab, 0xbb, 0x89, 0xca, 0x51, 0x3e, 0x2, 0x8e, 0x5c, 0xa1, 0x61, 0x25, 0xd2, + 0x93, 0x3e, 0x85, 0x4b, 0x9f, 0x73, 0x63, 0x57, 0xab, 0xbc, 0x7a, 0x66, 0x51, 0xd2, 0x39, 0xb9 + }, + }, + { + .msglen = 1, + .result = { + 0xab, 0x7d, 0x90, 0x85, 0x8, 0xb3, 0xf3, 0x7, 0x45, 0x6c, 0x85, 0x40, 0xbf, 0xcd, 0xb4, 0x52, + 0x54, 0x2c, 0x2, 0xe0, 0x53, 0xdc, 0x16, 0x12, 0x90, 0xf1, 0x5b, 0x5b, 0xf8, 0x71, 0x65, 0x44 + }, + }, + { + .msglen = 127, + .result = { + 0x19, 0x38, 0x88, 0xb, 0x30, 0xac, 0xef, 0x4e, 0xd, 0x38, 0x7d, 0x7e, 0x42, 0x5c, 0x90, 0xc4, + 0x9b, 0xc1, 0xbd, 0x9e, 0x30, 0xc6, 0x16, 0x1f, 0x36, 0x7e, 0x46, 0xcd, 0xb2, 0xd7, 0x37, 0x70 + }, + }, + { + .msglen = 126, + .result = { + 0xf, 0xa4, 0xb5, 0x16, 0x3b, 0xf5, 0xe8, 0x6e, 0xaf, 0x38, 0xc6, 0x27, 0x9a, 0xc, 0x88, 0xaf, + 0xb5, 0x10, 0x75, 0x3d, 0x4a, 0x85, 0x10, 0x4e, 0x60, 0xe4, 0x61, 0x30, 0x8, 0x46, 0x98, 0xc7 + }, + }, + { + .msglen = 125, + .result = { + 0x3f, 0x1a, 0x90, 0x47, 0xeb, 0x44, 0xcc, 0x27, 0xfa, 0x22, 0xb3, 0x5d, 0xa2, 0x22, 0x30, 0x54, + 0x61, 0x15, 0xe5, 0x54, 0x55, 0x13, 0x7c, 0xb8, 0xc7, 0xc0, 0x28, 0xa4, 0xd4, 0xbc, 0x1c, 0xad + }, + }, + { + .msglen = 124, + .result = { + 0x14, 0xdf, 0x13, 0xa2, 0xe4, 0xfd, 0xa3, 0xa8, 0x9b, 0x71, 0x78, 0x2e, 0x24, 0xb6, 0x61, 0x13, + 0xff, 0x6c, 0x6d, 0xe8, 0x95, 0xf9, 0x68, 0xb4, 0x92, 0x7c, 0xc9, 0xf7, 0x5e, 0x14, 0x44, 0x8 + }, + }, + { + .msglen = 123, + .result = { + 0x6, 0xd0, 0xe, 0xbe, 0x90, 0x3b, 0x52, 0x85, 0xd4, 0x25, 0x7e, 0xbe, 0x71, 0x92, 0xd0, 0xf0, + 0x6a, 0x99, 0x93, 0x64, 0xe6, 0x9a, 0x27, 0xfa, 0x57, 0xcb, 0x6f, 0x9f, 0x44, 0x30, 0xf5, 0xcc + }, + }, + { + .msglen = 122, + .result = { + 0x76, 0x7a, 0x86, 0x80, 0x1e, 0x54, 0x11, 0xef, 0x2f, 0x4e, 0xf9, 0x7, 0xda, 0x42, 0xd6, 0x71, + 0x3b, 0xb9, 0x92, 0xfb, 0x8, 0x1d, 0xf2, 0x41, 0x96, 0x5f, 0x28, 0x10, 0x20, 0x1a, 0x7b, 0xef + }, + }, + { + .msglen = 121, + .result = { + 0x59, 0xb0, 0xdb, 0x73, 0xee, 0x43, 0xb9, 0x63, 0x82, 0x36, 0x11, 0x5a, 0x6b, 0x46, 0x8, 0xbb, + 0x18, 0xdd, 0x74, 0x82, 0x8f, 0xf3, 0xb3, 0x5d, 0xd1, 0xad, 0xe, 0x8e, 0x77, 0x90, 0xde, 0x70 + }, + }, + { + .msglen = 120, + .result = { + 0xe0, 0x24, 0xc5, 0x2, 0x6b, 0xe, 0xe3, 0x9b, 0x1, 0x95, 0x6, 0x21, 0xc6, 0xad, 0x0, 0x72, + 0x36, 0x9, 0x75, 0xcd, 0x10, 0xa3, 0xf, 0xa2, 0xe5, 0xcd, 0x27, 0x6b, 0x95, 0x23, 0x6, 0x72 + }, + }, + { + .msglen = 119, + .result = { + 0x70, 0x4, 0x2c, 0x78, 0xc5, 0x40, 0x3f, 0xfb, 0x71, 0xfb, 0x3e, 0xbd, 0x9f, 0x4e, 0x2f, 0xf8, + 0x3c, 0x9b, 0xd1, 0xad, 0xee, 0xc8, 0x4f, 0x40, 0xec, 0x29, 0x5a, 0xb9, 0x9a, 0xa7, 0xe9, 0x51 + }, + }, + { + .msglen = 118, + .result = { + 0x1a, 0x4b, 0x49, 0xd3, 0x6, 0x1, 0x75, 0xca, 0x3, 0x12, 0x2e, 0x9a, 0xd4, 0xda, 0xb8, 0x23, + 0xf9, 0xa0, 0xa6, 0xbc, 0xbc, 0xcc, 0xa1, 0x6f, 0xd8, 0x3b, 0x2a, 0x37, 0xd3, 0xc3, 0xca, 0x5f + }, + }, + { + .msglen = 0, + .result = { + 0x46, 0x24, 0x76, 0xa8, 0x97, 0xdd, 0xfd, 0xbd, 0x40, 0xd1, 0x42, 0xe, 0x8, 0xa5, 0xbc, 0xfe, + 0xeb, 0x25, 0xc3, 0xe2, 0xad, 0xe6, 0xa0, 0xa9, 0x8, 0x3b, 0x32, 0x7b, 0x9e, 0xf9, 0xfc, 0xa1 + }, + }, +}; + +// 257 characters of pseudo-Latin from lipsum.com (not Copyright) +static const char *message = "Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. Sunt architecto iure aspernatur soluta ut recusandae. Ut quibusdam occaecati ut qui sit dignissimos eaque.."; + +// 256 different HMAC results for different length portions of the above. Generated as follows: +// +// import hmac, hashlib, binascii +// key = b"".join([chr(x).encode() for x in range(1,33)]) +// assert len(message) == 257 +// for l in range(1, len(message)): +// print(" // %d" % l) +// mac = hmac.HMAC(key, message[:l], hashlib.sha256).digest() +// print("{ " + ", ".join("0x%x" % ord(x) for x in mac) + " }, ") +// +// (Note: the zero length case is handled in the other unit test.) +static const hmac_result results[] = { + { + .msglen = 1, + .result = { 0xf2, 0x1a, 0x8e, 0x60, 0xea, 0xd9, 0x36, 0xd1, 0xc2, 0x74, 0x24, 0xae, 0x6, 0x2d, 0x81, 0x28, 0x16, 0xa6, 0x33, 0xca, 0x9d, 0x55, 0xc0, 0x82, 0x28, 0xd9, 0x79, 0x8f, 0x5a, 0xaa, 0xfd, 0x25 }, + }, + { + .msglen = 2, + .result = { 0x1f, 0x6, 0xfc, 0x68, 0x5c, 0xa8, 0xbf, 0x3e, 0x57, 0x6d, 0x2, 0x56, 0x4a, 0x35, 0x31, 0xbd, 0xeb, 0xf4, 0x5d, 0xd5, 0x71, 0xf9, 0x65, 0x7d, 0xa9, 0x32, 0x1d, 0x68, 0x21, 0xd2, 0x9b, 0xaf }, + }, + { + .msglen = 3, + .result = { 0x2b, 0xb4, 0x4e, 0x80, 0x6e, 0xd2, 0xcb, 0xee, 0x4b, 0x40, 0xfb, 0xf9, 0x61, 0x76, 0x78, 0x2a, 0xb1, 0xc8, 0xea, 0xa3, 0x3e, 0xf7, 0x24, 0x86, 0xa0, 0x73, 0xda, 0xe, 0xaf, 0x98, 0xb, 0xf0 }, + }, + { + .msglen = 4, + .result = { 0xf, 0x39, 0xd1, 0x1a, 0x3a, 0xe9, 0xa9, 0xf8, 0xe9, 0x39, 0xed, 0x1b, 0x32, 0x3, 0xbc, 0x24, 0x32, 0xe8, 0x12, 0xd7, 0xc4, 0xed, 0x2a, 0x8a, 0xed, 0x46, 0xbf, 0xa7, 0x21, 0x31, 0x37, 0xb5 }, + }, + { + .msglen = 5, + .result = { 0x6c, 0xfc, 0xf8, 0x9a, 0x56, 0xce, 0xe6, 0x1, 0x36, 0xca, 0x36, 0x37, 0xa8, 0xb9, 0xca, 0x99, 0x3b, 0xb1, 0xf8, 0x24, 0xa5, 0xf6, 0x20, 0x4d, 0xff, 0x8c, 0x60, 0xd3, 0x9, 0x92, 0xef, 0xb3 }, + }, + { + .msglen = 6, + .result = { 0x86, 0x99, 0x7, 0xd7, 0x5b, 0xb3, 0x93, 0x95, 0x3a, 0x9e, 0xf5, 0x95, 0x9d, 0x5e, 0x7b, 0xaf, 0x9b, 0x4b, 0x19, 0x35, 0x31, 0x34, 0xba, 0x29, 0xa, 0x56, 0xb, 0xe4, 0xa4, 0xbf, 0xb8, 0x9f }, + }, + { + .msglen = 7, + .result = { 0xa9, 0x9, 0x85, 0x26, 0x7b, 0x92, 0x23, 0xe7, 0x3d, 0x44, 0xa1, 0xcc, 0xba, 0x5c, 0xda, 0xdb, 0x5a, 0xe2, 0x76, 0x78, 0xd7, 0x42, 0x77, 0x4a, 0x8e, 0x2b, 0x79, 0x73, 0x4c, 0x29, 0x6, 0x1c }, + }, + { + .msglen = 8, + .result = { 0x26, 0x15, 0x1f, 0xe3, 0x53, 0xd9, 0x8, 0xc5, 0xf0, 0x11, 0x7, 0x7, 0x5f, 0x8c, 0xf6, 0x61, 0xd2, 0x21, 0x16, 0xe4, 0xb9, 0x61, 0x29, 0x1c, 0x4d, 0x2b, 0x6d, 0x9a, 0x88, 0x8c, 0xdc, 0xa9 }, + }, + { + .msglen = 9, + .result = { 0x2, 0xf2, 0xe6, 0xc8, 0x9c, 0xdc, 0x1b, 0x64, 0xd6, 0x32, 0xc2, 0x48, 0x62, 0x51, 0x9c, 0x0, 0x90, 0xf4, 0xf1, 0x2a, 0x0, 0x2, 0xce, 0x32, 0xbb, 0x8f, 0x38, 0x9c, 0x8b, 0xaa, 0xdd, 0x5d }, + }, + { + .msglen = 10, + .result = { 0x44, 0x76, 0x8a, 0x53, 0xcf, 0xbb, 0xc1, 0xd0, 0x36, 0x96, 0xb5, 0xe9, 0xe, 0xfb, 0xce, 0xb3, 0x47, 0x21, 0xaa, 0xea, 0xac, 0x76, 0x54, 0x91, 0xc1, 0xcb, 0x88, 0x32, 0xb1, 0xea, 0xd5, 0x4c }, + }, + { + .msglen = 11, + .result = { 0x95, 0xf9, 0x78, 0x12, 0xe5, 0x7a, 0xf4, 0xc5, 0xee, 0x5e, 0x27, 0xe7, 0x5e, 0x8, 0x56, 0x60, 0x97, 0xc1, 0xee, 0xf, 0xf5, 0x24, 0x5c, 0x20, 0xbe, 0x95, 0x3c, 0xa2, 0xf5, 0x68, 0x69, 0x6f }, + }, + { + .msglen = 12, + .result = { 0x8e, 0x71, 0xa8, 0x23, 0x7a, 0x8, 0x6a, 0xf4, 0x2e, 0xab, 0x58, 0x56, 0x37, 0x55, 0x26, 0x57, 0x13, 0xc, 0x6b, 0x6b, 0x65, 0xb6, 0x4f, 0xec, 0xde, 0xc2, 0xe6, 0xb0, 0x34, 0xc0, 0x4a, 0xba }, + }, + { + .msglen = 13, + .result = { 0x75, 0xc8, 0x29, 0x60, 0x89, 0xb7, 0xba, 0xc7, 0x40, 0x18, 0x73, 0x8a, 0xa3, 0x92, 0xb2, 0x2c, 0x79, 0x74, 0x1c, 0xdc, 0xc0, 0x97, 0x14, 0xdb, 0x26, 0xcc, 0xad, 0x7f, 0x9d, 0x2f, 0xd, 0x5 }, + }, + { + .msglen = 14, + .result = { 0xe9, 0xf2, 0x97, 0x12, 0x4d, 0xc3, 0x22, 0xca, 0x7, 0xc, 0xac, 0xae, 0xcb, 0x63, 0xe2, 0x88, 0xa2, 0xf8, 0xb0, 0x94, 0xfc, 0x21, 0xf4, 0x69, 0x8e, 0xa0, 0x95, 0x3, 0x54, 0xa1, 0x61, 0xed }, + }, + { + .msglen = 15, + .result = { 0x34, 0xd4, 0x3e, 0xcd, 0xcc, 0xa, 0x5f, 0xaf, 0xf5, 0x3d, 0xb8, 0xaa, 0x18, 0x4a, 0x18, 0xef, 0x22, 0x75, 0x29, 0x17, 0x1b, 0x33, 0xf2, 0x50, 0x4e, 0x90, 0xd5, 0xa3, 0x10, 0xff, 0x79, 0xbc }, + }, + { + .msglen = 16, + .result = { 0xcf, 0x6, 0x59, 0x8d, 0x2d, 0x7b, 0xb, 0x3d, 0x1a, 0xa3, 0x9c, 0xfa, 0xa2, 0xf1, 0x88, 0x6, 0xd2, 0xb4, 0xb5, 0x2d, 0x4c, 0x56, 0x7, 0xf5, 0x20, 0xce, 0x9a, 0x79, 0x3a, 0x2e, 0x11, 0xfa }, + }, + { + .msglen = 17, + .result = { 0x55, 0x5f, 0x37, 0xd9, 0x7, 0x3a, 0x3a, 0x6b, 0x22, 0xf8, 0x1c, 0x8f, 0xd8, 0xf6, 0xf7, 0x18, 0x77, 0xf3, 0x52, 0x32, 0xc6, 0x9b, 0xe0, 0xc7, 0xa6, 0xf0, 0x6b, 0xb0, 0x6a, 0xad, 0xb2, 0x7e }, + }, + { + .msglen = 18, + .result = { 0xa0, 0x60, 0x25, 0x34, 0xd7, 0xe1, 0x66, 0x7e, 0xdd, 0xec, 0x8, 0x95, 0xb5, 0xd9, 0x2d, 0x4e, 0x29, 0x89, 0x39, 0xb9, 0xc1, 0xe4, 0xc1, 0x86, 0x10, 0x16, 0x5, 0x17, 0xd0, 0x6, 0x91, 0x2d }, + }, + { + .msglen = 19, + .result = { 0xb4, 0x45, 0xbc, 0xae, 0xb3, 0x5b, 0x61, 0xd3, 0x50, 0x8c, 0x38, 0x7a, 0x4c, 0x4c, 0xbc, 0x38, 0x89, 0x98, 0x75, 0x23, 0xa9, 0x92, 0xa4, 0xea, 0xfe, 0xe6, 0x88, 0x61, 0xb0, 0xf0, 0x8, 0x7b }, + }, + { + .msglen = 20, + .result = { 0x1d, 0x2e, 0x5c, 0x69, 0x7b, 0x2a, 0xa0, 0x9d, 0xe6, 0x5b, 0xc, 0x3, 0x53, 0x9, 0x66, 0x74, 0xd8, 0xf6, 0xe8, 0x87, 0x5d, 0xc7, 0x1, 0xf0, 0xce, 0xaf, 0xb1, 0x15, 0x34, 0x22, 0x8e, 0x83 }, + }, + { + .msglen = 21, + .result = { 0x8e, 0xd9, 0xb1, 0xc7, 0x99, 0x91, 0x1, 0x9a, 0xe, 0xfa, 0xd2, 0xed, 0xc4, 0xae, 0x47, 0xf2, 0xa2, 0x48, 0x53, 0xa8, 0x92, 0xff, 0xe4, 0xcc, 0x95, 0x5e, 0x25, 0x1a, 0x2a, 0x49, 0x6c, 0xfd }, + }, + { + .msglen = 22, + .result = { 0x14, 0xba, 0x32, 0xbe, 0x21, 0x6, 0x6e, 0x6a, 0x28, 0x2b, 0x4e, 0xfc, 0x97, 0xa5, 0x6, 0x32, 0x62, 0x7, 0xf3, 0x61, 0x41, 0x43, 0x5e, 0x34, 0x93, 0x0, 0xa8, 0xb3, 0x9, 0x55, 0x37, 0x3f }, + }, + { + .msglen = 23, + .result = { 0xa1, 0xf0, 0xe6, 0xf1, 0x9d, 0x5d, 0x30, 0x10, 0x17, 0xce, 0x39, 0x5e, 0x93, 0x2b, 0xe6, 0xeb, 0x6b, 0x5b, 0x64, 0x47, 0x65, 0xe8, 0x93, 0x2e, 0x39, 0x74, 0x6a, 0x71, 0xf3, 0xdb, 0xb6, 0x8d }, + }, + { + .msglen = 24, + .result = { 0xab, 0xf4, 0xe1, 0x78, 0xc1, 0x63, 0x95, 0xf2, 0x6c, 0x54, 0xc, 0xac, 0xce, 0x88, 0x17, 0xf6, 0x1c, 0x84, 0x5b, 0x26, 0xa3, 0x5c, 0xea, 0xf7, 0x66, 0xcb, 0x84, 0xed, 0xbe, 0x52, 0xd, 0x25 }, + }, + { + .msglen = 25, + .result = { 0xd8, 0x94, 0x77, 0xa7, 0x6c, 0x51, 0x30, 0x3c, 0xd7, 0x4f, 0xc4, 0x6e, 0x1a, 0x25, 0xf8, 0x87, 0x93, 0x49, 0x28, 0x6b, 0x1b, 0x3, 0x79, 0x5, 0x14, 0x15, 0xd1, 0xee, 0x51, 0x7b, 0x9f, 0x94 }, + }, + { + .msglen = 26, + .result = { 0xbb, 0x8a, 0x5f, 0x73, 0x8d, 0x4e, 0x8a, 0x11, 0x95, 0x5d, 0xf5, 0xcf, 0x25, 0xea, 0x79, 0x38, 0xc4, 0x4b, 0xb4, 0x6f, 0xa3, 0x1f, 0x18, 0x23, 0x73, 0x1e, 0x46, 0xcb, 0x5d, 0x97, 0xcf, 0x6c }, + }, + { + .msglen = 27, + .result = { 0xe2, 0xad, 0x4b, 0x4e, 0x43, 0xf1, 0x6d, 0x62, 0x1a, 0xb4, 0x65, 0xbb, 0xb3, 0x34, 0x8, 0xf7, 0x14, 0x14, 0xd2, 0x6f, 0x41, 0x8f, 0xa7, 0x6f, 0xab, 0x6e, 0x61, 0xe2, 0x5, 0x5b, 0x2a, 0xe6 }, + }, + { + .msglen = 28, + .result = { 0xd9, 0xea, 0x5, 0x72, 0x59, 0x12, 0xff, 0xb, 0x33, 0x87, 0x17, 0x9d, 0xb2, 0x9, 0x4f, 0xfc, 0xba, 0xd7, 0xc, 0x45, 0x3b, 0xbe, 0x6a, 0x12, 0x59, 0x38, 0x40, 0x30, 0x8c, 0xa4, 0xf, 0x7d }, + }, + { + .msglen = 29, + .result = { 0x29, 0xe, 0x6d, 0x59, 0x2a, 0xaf, 0x5f, 0x93, 0xc7, 0x97, 0xbb, 0x29, 0x92, 0x2c, 0xba, 0x6b, 0xa5, 0xcb, 0x7e, 0x88, 0x5b, 0xcd, 0xd4, 0xfe, 0xb4, 0xc7, 0x65, 0xae, 0x6b, 0x7f, 0x78, 0xb6 }, + }, + { + .msglen = 30, + .result = { 0x5e, 0xea, 0x58, 0xb5, 0x93, 0x4b, 0xb7, 0x32, 0x50, 0xcb, 0xc6, 0x6c, 0x63, 0x9d, 0x5d, 0xa9, 0x3f, 0x80, 0xc4, 0x91, 0xbc, 0xe3, 0x2a, 0xd6, 0x20, 0xfb, 0xf9, 0x43, 0x59, 0xcf, 0x86, 0x1d }, + }, + { + .msglen = 31, + .result = { 0x46, 0xee, 0x3a, 0x2a, 0x1, 0xf6, 0x43, 0xe, 0xbb, 0xc6, 0x90, 0x4f, 0x66, 0xa5, 0xe9, 0xd7, 0xa8, 0x29, 0x7e, 0x16, 0x4, 0x57, 0xee, 0x5c, 0xf4, 0x6c, 0xc8, 0x4a, 0x92, 0x27, 0x83, 0x42 }, + }, + { + .msglen = 32, + .result = { 0x82, 0x36, 0xe6, 0xf, 0xa, 0x37, 0x2d, 0x7b, 0x2, 0x75, 0xc4, 0x48, 0x36, 0xbf, 0xdf, 0x79, 0x35, 0xdf, 0xcb, 0x65, 0x25, 0xae, 0x11, 0x2c, 0xfa, 0x54, 0x4a, 0x99, 0xfe, 0x2a, 0x63, 0xbd }, + }, + { + .msglen = 33, + .result = { 0x9e, 0x35, 0xc8, 0x6c, 0xa7, 0xe8, 0x8b, 0xb2, 0x0, 0x4c, 0x41, 0x51, 0x5b, 0xd2, 0x4b, 0x9f, 0x10, 0xea, 0xfe, 0xd7, 0xc1, 0xd1, 0x36, 0xfb, 0x52, 0xd6, 0xe3, 0xe2, 0x23, 0xc9, 0x53, 0x33 }, + }, + { + .msglen = 34, + .result = { 0x52, 0xe9, 0x15, 0x90, 0x65, 0xb, 0x75, 0x89, 0xb3, 0xed, 0x7a, 0xb6, 0x12, 0xe6, 0xe, 0xeb, 0x7c, 0x25, 0xb4, 0xf3, 0x2a, 0xf6, 0xfe, 0x6a, 0x3c, 0xd9, 0xf0, 0x2a, 0xaf, 0xc7, 0x1b, 0xbc }, + }, + { + .msglen = 35, + .result = { 0xfc, 0xa5, 0xf1, 0x9a, 0xa0, 0xfa, 0x42, 0x7b, 0x49, 0xf, 0xd7, 0x76, 0xe0, 0xf9, 0x31, 0x17, 0x87, 0x70, 0x19, 0x90, 0x26, 0x96, 0xcd, 0xd6, 0xf, 0xa8, 0xb, 0x1f, 0x31, 0x45, 0x9c, 0xd0 }, + }, + { + .msglen = 36, + .result = { 0x85, 0x76, 0xf4, 0xfc, 0x96, 0xfb, 0x69, 0x31, 0x6, 0x5c, 0x6e, 0xd9, 0x75, 0xda, 0xf0, 0x14, 0xba, 0x4b, 0x74, 0x96, 0xf7, 0xe6, 0xd0, 0x3d, 0x36, 0x9b, 0x94, 0x8c, 0x1a, 0xb9, 0x7a, 0x88 }, + }, + { + .msglen = 37, + .result = { 0x8b, 0xc7, 0xad, 0xb8, 0xce, 0xc6, 0xd7, 0x8e, 0xd6, 0xfa, 0xa5, 0xd3, 0x59, 0x3d, 0x39, 0xdc, 0x74, 0x56, 0x3c, 0xd9, 0xc8, 0x0, 0xd2, 0xb0, 0x21, 0x7b, 0x93, 0xcb, 0x18, 0xec, 0x5f, 0xdd }, + }, + { + .msglen = 38, + .result = { 0x95, 0x7a, 0xf3, 0x9c, 0x5b, 0x40, 0x86, 0xdf, 0xa6, 0xf7, 0x34, 0x40, 0xb0, 0x7a, 0x34, 0x6c, 0xd5, 0x3d, 0x6, 0x9d, 0xc7, 0x9f, 0x11, 0x32, 0x98, 0x78, 0xee, 0xed, 0xb6, 0xb4, 0x1f, 0x34 }, + }, + { + .msglen = 39, + .result = { 0xf3, 0x50, 0x40, 0xd2, 0xbb, 0x54, 0xb3, 0xcf, 0x37, 0x55, 0xff, 0xc8, 0x41, 0x30, 0xde, 0x33, 0x2f, 0x4, 0xe3, 0xe7, 0x42, 0x31, 0x68, 0xe6, 0x6d, 0x5d, 0xdc, 0x14, 0x5a, 0x58, 0xf4, 0x46 }, + }, + { + .msglen = 40, + .result = { 0xda, 0x9d, 0xeb, 0xf7, 0xa7, 0xa1, 0x4, 0xd1, 0xfb, 0xe3, 0xd8, 0x11, 0x8d, 0x54, 0x88, 0x65, 0x42, 0x6e, 0x78, 0x7a, 0x8f, 0x1b, 0xc5, 0x13, 0x98, 0x53, 0x38, 0x26, 0xf3, 0x3d, 0xd2, 0xff }, + }, + { + .msglen = 41, + .result = { 0x9c, 0x23, 0x67, 0xa3, 0xeb, 0xed, 0xca, 0x21, 0x4b, 0x4c, 0x68, 0x95, 0xaf, 0xfb, 0x9b, 0x17, 0xf0, 0x2a, 0x5c, 0x78, 0x58, 0x65, 0xf1, 0x20, 0xfd, 0x3c, 0xd9, 0x66, 0x94, 0x66, 0x4d, 0xcc }, + }, + { + .msglen = 42, + .result = { 0xfa, 0x61, 0xf5, 0xd7, 0x58, 0xd2, 0x32, 0xb0, 0xb, 0x95, 0x88, 0xfc, 0x8a, 0x79, 0x15, 0x61, 0x1e, 0xa7, 0xf7, 0xf2, 0xf1, 0x91, 0xe7, 0xb3, 0x55, 0xa0, 0x65, 0x3c, 0xca, 0xf6, 0xac, 0x19 }, + }, + { + .msglen = 43, + .result = { 0xae, 0xc1, 0xb4, 0xa9, 0x88, 0xf3, 0x6d, 0xfe, 0xc2, 0x48, 0x19, 0x2a, 0x68, 0x41, 0x5e, 0x3f, 0xbe, 0x32, 0x20, 0xc7, 0x90, 0x6f, 0x23, 0x6d, 0x42, 0xaa, 0x38, 0xbb, 0xd5, 0x34, 0x7e, 0x21 }, + }, + { + .msglen = 44, + .result = { 0x12, 0xb0, 0xb, 0x1, 0xcf, 0xc9, 0x20, 0x8d, 0x59, 0xc1, 0xb7, 0xe9, 0x23, 0x53, 0x12, 0xd4, 0x41, 0x99, 0x7f, 0xb9, 0x57, 0x11, 0x5d, 0x9c, 0x60, 0xa8, 0x0, 0x3, 0x68, 0x9, 0x4d, 0x1d }, + }, + { + .msglen = 45, + .result = { 0xee, 0x85, 0x2, 0xed, 0xa1, 0x41, 0x71, 0xd4, 0x32, 0x2, 0x33, 0xec, 0x26, 0x31, 0x7b, 0xb8, 0xd0, 0xb0, 0xd6, 0xb0, 0x60, 0x52, 0xe1, 0xd9, 0xd7, 0x33, 0x72, 0x5c, 0xb9, 0xc3, 0x6c, 0x9f }, + }, + { + .msglen = 46, + .result = { 0x90, 0x3e, 0x7, 0x17, 0xa2, 0x18, 0xd, 0xa1, 0x71, 0xfe, 0x4b, 0x6d, 0x24, 0x40, 0x5e, 0xe2, 0xd1, 0x45, 0xd6, 0x18, 0xe8, 0xa3, 0x2d, 0x12, 0xe8, 0x11, 0xae, 0x1, 0xc4, 0x77, 0xa9, 0xab }, + }, + { + .msglen = 47, + .result = { 0x4a, 0x4f, 0x5a, 0xd1, 0xd0, 0xfb, 0xf7, 0x60, 0x9c, 0xbf, 0x23, 0x99, 0x95, 0xea, 0x51, 0xdb, 0x70, 0xc4, 0xa, 0xaf, 0x41, 0x13, 0x7d, 0x3d, 0xd1, 0x50, 0xa7, 0x13, 0x4f, 0xa0, 0xbf, 0xf4 }, + }, + { + .msglen = 48, + .result = { 0x63, 0x50, 0x7a, 0x54, 0xd8, 0xa5, 0xf, 0x96, 0x45, 0x3a, 0x85, 0x8e, 0x8e, 0xc6, 0x5d, 0xe0, 0xe8, 0xfd, 0xce, 0xa8, 0x3f, 0x59, 0x19, 0x81, 0x13, 0xd1, 0xf7, 0xd, 0x45, 0xe3, 0xf3, 0x31 }, + }, + { + .msglen = 49, + .result = { 0x3c, 0x7a, 0x1, 0xdd, 0x3a, 0x96, 0xae, 0x2, 0x2e, 0x6a, 0x7f, 0xd, 0x1e, 0x2f, 0x32, 0xfd, 0x5, 0x33, 0xae, 0x54, 0xa2, 0xa6, 0x89, 0x32, 0x9a, 0x7, 0xb7, 0xe9, 0x66, 0xaf, 0xf8, 0xc }, + }, + { + .msglen = 50, + .result = { 0x57, 0xd8, 0xed, 0xc4, 0xec, 0x23, 0xf, 0xf9, 0x55, 0xc1, 0x36, 0xde, 0xc3, 0xbd, 0x54, 0x53, 0x2f, 0xfa, 0xd1, 0xb3, 0xe1, 0x87, 0xc2, 0x39, 0x54, 0x59, 0xa9, 0xb9, 0xac, 0xed, 0xa0, 0x49 }, + }, + { + .msglen = 51, + .result = { 0xdf, 0xd5, 0x2e, 0xd2, 0xd2, 0xb0, 0x90, 0x12, 0x71, 0x37, 0x51, 0xba, 0x79, 0xd4, 0x43, 0xc7, 0x74, 0x12, 0xf3, 0x71, 0x74, 0x63, 0xc, 0x4d, 0x59, 0x2e, 0x5, 0xb5, 0xa2, 0x17, 0xe, 0xe9 }, + }, + { + .msglen = 52, + .result = { 0xbd, 0xa3, 0x12, 0x94, 0xea, 0xa7, 0xc4, 0xd3, 0x1f, 0x99, 0xcb, 0xbc, 0x53, 0x80, 0x45, 0xfd, 0x17, 0x13, 0xd7, 0x2b, 0x26, 0x5b, 0x23, 0x3d, 0x2d, 0xd8, 0x7f, 0x9, 0xcc, 0x9c, 0xa7, 0xfd }, + }, + { + .msglen = 53, + .result = { 0x66, 0x3a, 0xc1, 0x3b, 0x1f, 0x7d, 0x0, 0xf5, 0x9a, 0x5e, 0x92, 0x61, 0x16, 0xad, 0x2b, 0x15, 0x2f, 0x65, 0x89, 0xd2, 0xa3, 0xbd, 0x33, 0x71, 0x31, 0xe8, 0x37, 0x3c, 0xb0, 0x6d, 0x13, 0xc9 }, + }, + { + .msglen = 54, + .result = { 0xff, 0x17, 0xef, 0x42, 0x67, 0xba, 0xcf, 0xe7, 0xfe, 0xf5, 0x76, 0x96, 0x9e, 0xf0, 0x61, 0xe5, 0xd, 0xc3, 0xbb, 0x63, 0xd3, 0xcd, 0x4a, 0x10, 0x63, 0xa3, 0x3c, 0xe, 0xf2, 0xfc, 0xa, 0x33 }, + }, + { + .msglen = 55, + .result = { 0x78, 0xa8, 0xe5, 0x15, 0x18, 0x49, 0x4, 0xba, 0x34, 0xb6, 0xb3, 0x96, 0x3a, 0x6, 0xaa, 0x93, 0xad, 0x82, 0x5b, 0x87, 0x0, 0x3f, 0x5, 0x1, 0xe7, 0xe1, 0x22, 0x16, 0x3d, 0xb5, 0x5b, 0xb8 }, + }, + { + .msglen = 56, + .result = { 0x0, 0xad, 0xbf, 0x7d, 0x51, 0xc4, 0xed, 0x5, 0x6c, 0x81, 0x15, 0x5c, 0xa5, 0xe3, 0x6b, 0x39, 0x59, 0x10, 0x8e, 0xbc, 0x3f, 0xb8, 0x21, 0xbc, 0xd9, 0x9e, 0x35, 0x7d, 0x23, 0x48, 0x5, 0x8a }, + }, + { + .msglen = 57, + .result = { 0xf7, 0x5e, 0xa3, 0x88, 0x1f, 0x82, 0xf0, 0xc4, 0x39, 0x7e, 0xed, 0x22, 0x78, 0xd6, 0x65, 0x94, 0x4f, 0x8, 0x2e, 0x96, 0x7e, 0x44, 0x8f, 0x0, 0x3b, 0x92, 0xf9, 0xea, 0x83, 0x72, 0xc7, 0xe2 }, + }, + { + .msglen = 58, + .result = { 0x84, 0xa5, 0x85, 0x95, 0x0, 0x7e, 0xc4, 0x98, 0x36, 0xc9, 0xe5, 0xd4, 0xda, 0x59, 0xab, 0x22, 0x2f, 0xa8, 0xb7, 0x46, 0x55, 0x91, 0x2, 0xc, 0x5b, 0x64, 0x5c, 0x5b, 0x42, 0x8b, 0x7e, 0xa }, + }, + { + .msglen = 59, + .result = { 0x4e, 0x1c, 0x16, 0x99, 0xd8, 0x4, 0xb, 0x6, 0x91, 0x98, 0x87, 0xb0, 0xa3, 0x63, 0x9, 0xdf, 0xfb, 0xa6, 0xd6, 0xe4, 0x58, 0x27, 0xf5, 0x73, 0x9, 0x81, 0x4f, 0x5d, 0x88, 0x2c, 0xb8, 0x7 }, + }, + { + .msglen = 60, + .result = { 0x2f, 0x97, 0xbf, 0x70, 0x70, 0x4b, 0xfe, 0x5a, 0x2f, 0x91, 0x8f, 0x28, 0x8b, 0xee, 0xf6, 0xee, 0x41, 0x7d, 0x36, 0x14, 0x86, 0x69, 0x42, 0x9c, 0x4d, 0x5, 0xcc, 0x53, 0x71, 0x61, 0x78, 0xe }, + }, + { + .msglen = 61, + .result = { 0xe6, 0xba, 0x7f, 0x8, 0xb3, 0xdc, 0x7b, 0x95, 0xcb, 0xd1, 0x33, 0x64, 0x25, 0x5a, 0xa3, 0x70, 0x10, 0x4a, 0xe6, 0x2c, 0x54, 0x25, 0xfa, 0x7e, 0xd0, 0x47, 0x65, 0x8d, 0xa1, 0xa8, 0x80, 0x5 }, + }, + { + .msglen = 62, + .result = { 0x9b, 0x48, 0x8d, 0x79, 0x16, 0xe8, 0x32, 0x63, 0x89, 0xaa, 0x4b, 0x7d, 0xdb, 0x46, 0xcd, 0x80, 0x40, 0x9d, 0x8c, 0x6, 0xa5, 0xed, 0xb4, 0xe1, 0xdd, 0x87, 0x6b, 0xb3, 0x90, 0x2b, 0x77, 0xc8 }, + }, + { + .msglen = 63, + .result = { 0x72, 0xfb, 0x8c, 0xf1, 0xb9, 0xb3, 0x50, 0x55, 0x5c, 0xac, 0x93, 0x38, 0x73, 0x1c, 0xd0, 0x93, 0x6, 0x5e, 0xcd, 0x0, 0x24, 0x83, 0x4b, 0xef, 0xdc, 0xfd, 0x27, 0x58, 0xfc, 0xa1, 0x4a, 0x32 }, + }, + { + .msglen = 64, + .result = { 0x19, 0x5b, 0x88, 0x8d, 0x75, 0x97, 0x8a, 0x8c, 0x5d, 0xd4, 0xe7, 0xe4, 0xa, 0x4d, 0x5e, 0xcd, 0xe7, 0x88, 0xab, 0xb9, 0x6b, 0xd8, 0xd3, 0x80, 0x25, 0x3e, 0xa4, 0xfd, 0xc1, 0x83, 0x6e, 0x74 }, + }, + { + .msglen = 65, + .result = { 0x14, 0x3, 0xcc, 0x1f, 0xa5, 0xed, 0x5e, 0x3c, 0x45, 0x2d, 0x66, 0x9a, 0x36, 0xb7, 0x9a, 0xb, 0x1c, 0x83, 0x4d, 0xbe, 0xc9, 0x41, 0x7e, 0x7, 0x54, 0x97, 0x76, 0x25, 0x96, 0x76, 0xce, 0xd4 }, + }, + { + .msglen = 66, + .result = { 0x44, 0x62, 0x56, 0x7e, 0x68, 0x10, 0xed, 0xd9, 0x35, 0x8a, 0xe3, 0xd, 0x20, 0xf, 0xe6, 0x45, 0x89, 0x6c, 0x8c, 0x18, 0x13, 0xe5, 0xef, 0x28, 0x2d, 0xc1, 0x6a, 0x95, 0x9e, 0x3d, 0x81, 0x51 }, + }, + { + .msglen = 67, + .result = { 0x94, 0xac, 0xc2, 0xe0, 0x8, 0xb7, 0xe5, 0xe2, 0x18, 0xf0, 0x59, 0x47, 0xda, 0xf4, 0xb4, 0xb1, 0xfe, 0x11, 0xe4, 0x3c, 0x2c, 0xa8, 0x1, 0x30, 0x5e, 0x8e, 0x89, 0x4, 0xff, 0xf2, 0xc1, 0x88 }, + }, + { + .msglen = 68, + .result = { 0xa2, 0x73, 0x97, 0x2, 0xd7, 0xc4, 0x9b, 0x39, 0x20, 0xdc, 0xac, 0x6d, 0xca, 0x81, 0xdd, 0x83, 0xac, 0xd4, 0xf, 0x89, 0x94, 0x10, 0x8b, 0xf6, 0xb9, 0x10, 0xab, 0x24, 0xd3, 0xf9, 0xc8, 0x4f }, + }, + { + .msglen = 69, + .result = { 0x68, 0xa9, 0x9b, 0xc2, 0xb6, 0x1e, 0x4c, 0xe3, 0xc6, 0x89, 0xc7, 0x40, 0x2f, 0xee, 0x8f, 0x50, 0xf4, 0x9d, 0x56, 0x5, 0xba, 0x0, 0x30, 0xaa, 0xd6, 0xa6, 0x4d, 0x94, 0x46, 0xc, 0x3c, 0x3 }, + }, + { + .msglen = 70, + .result = { 0x4f, 0x71, 0x4e, 0x2f, 0x89, 0xce, 0x84, 0x3b, 0x9a, 0xab, 0x6c, 0x93, 0xac, 0xa8, 0x51, 0xf7, 0x72, 0x91, 0xd5, 0xad, 0xf7, 0x91, 0x5a, 0x3a, 0xa6, 0x16, 0x61, 0x6b, 0x9f, 0xba, 0xe3, 0x51 }, + }, + { + .msglen = 71, + .result = { 0x25, 0x50, 0x50, 0x55, 0x50, 0x6a, 0x55, 0x8d, 0x54, 0x61, 0x60, 0x44, 0x5a, 0xb0, 0x4f, 0x77, 0x7, 0xbe, 0xcf, 0x49, 0xb6, 0x68, 0x9b, 0x6d, 0x79, 0xd5, 0xb9, 0xb1, 0x45, 0x29, 0xcc, 0xc1 }, + }, + { + .msglen = 72, + .result = { 0x59, 0x47, 0xf5, 0x99, 0xad, 0xac, 0x9, 0x15, 0xdc, 0x67, 0x2f, 0x4e, 0x38, 0x83, 0xab, 0x53, 0x8d, 0xc2, 0x71, 0xf5, 0xb9, 0x4e, 0x59, 0xd5, 0x32, 0x10, 0x90, 0xd8, 0x5b, 0xb6, 0x5, 0xc0 }, + }, + { + .msglen = 73, + .result = { 0x68, 0x9, 0x2a, 0x7d, 0x49, 0x8f, 0xc1, 0xd4, 0x93, 0xc9, 0xf8, 0xe9, 0xd8, 0xc4, 0xc2, 0x34, 0xc8, 0xac, 0xc9, 0xb4, 0x9, 0x5d, 0x46, 0x51, 0xd4, 0x2e, 0x4, 0xbb, 0x8f, 0x66, 0x75, 0x15 }, + }, + { + .msglen = 74, + .result = { 0xc, 0xf, 0x3c, 0x79, 0x8b, 0x80, 0x93, 0xd9, 0x7f, 0x3, 0xb4, 0x5f, 0xfe, 0x66, 0xcf, 0xbe, 0xea, 0xe1, 0xa0, 0xfd, 0xf0, 0x49, 0x3d, 0x19, 0x54, 0xdc, 0x38, 0x73, 0x11, 0xb3, 0x8, 0xa3 }, + }, + { + .msglen = 75, + .result = { 0x33, 0xae, 0x39, 0xab, 0x8, 0x54, 0x48, 0x9e, 0x2b, 0xbe, 0x89, 0x7a, 0x32, 0xdb, 0x81, 0xc5, 0xbd, 0x39, 0x19, 0xc1, 0x87, 0x6f, 0x64, 0xb3, 0x70, 0xea, 0x9, 0xd2, 0xea, 0x72, 0x53, 0x6e }, + }, + { + .msglen = 76, + .result = { 0x37, 0xae, 0xae, 0xed, 0x35, 0xd1, 0x97, 0x88, 0x78, 0x57, 0x19, 0xdd, 0xbc, 0x3c, 0xa3, 0x10, 0x79, 0x21, 0x3a, 0xf9, 0xce, 0x34, 0xf3, 0xad, 0x85, 0x4f, 0xf2, 0xac, 0xd7, 0x24, 0x7b, 0x80 }, + }, + { + .msglen = 77, + .result = { 0xc0, 0xd0, 0xb7, 0xff, 0x19, 0x7a, 0xfe, 0x6c, 0x6, 0x4b, 0xf6, 0x12, 0x4c, 0xe6, 0xe8, 0x2, 0xf3, 0x32, 0xc3, 0x77, 0xf, 0x10, 0xab, 0x89, 0xde, 0x18, 0xc5, 0xe, 0x25, 0xab, 0x23, 0xdb }, + }, + { + .msglen = 78, + .result = { 0x5e, 0xe7, 0x3b, 0xa0, 0x6, 0x8e, 0x40, 0x26, 0xaf, 0x6f, 0xba, 0xf9, 0xa6, 0x23, 0xab, 0x49, 0x89, 0x15, 0xd4, 0x15, 0xc0, 0x6c, 0x1f, 0xfc, 0x6d, 0x3e, 0x51, 0x3a, 0x6e, 0xef, 0x3d, 0x17 }, + }, + { + .msglen = 79, + .result = { 0x2, 0xfd, 0xd7, 0x48, 0x76, 0x5b, 0x25, 0x26, 0xd4, 0x87, 0x94, 0x14, 0x9b, 0x13, 0x91, 0xa4, 0x39, 0x5, 0x4c, 0x4e, 0x6a, 0xdd, 0x60, 0x66, 0x4e, 0x23, 0xeb, 0xa5, 0xfd, 0xad, 0x5a, 0xda }, + }, + { + .msglen = 80, + .result = { 0x84, 0xf3, 0x92, 0xf1, 0xc0, 0xc0, 0x5a, 0x63, 0xec, 0x16, 0xf4, 0xfc, 0x4c, 0xc6, 0xb6, 0x62, 0x1e, 0x9f, 0xdd, 0xcb, 0xd8, 0x4a, 0x12, 0xf2, 0x9, 0x11, 0x88, 0x66, 0x4e, 0x85, 0xef, 0x9f }, + }, + { + .msglen = 81, + .result = { 0x8b, 0x28, 0x66, 0x9d, 0xe2, 0x96, 0x58, 0x21, 0x3f, 0xcd, 0xd7, 0xe0, 0xce, 0x9b, 0x51, 0x32, 0x68, 0xac, 0x1c, 0x9e, 0x38, 0x7d, 0x60, 0x5a, 0x32, 0xe1, 0x14, 0x91, 0xee, 0x36, 0x39, 0xbd }, + }, + { + .msglen = 82, + .result = { 0x5c, 0x16, 0xe3, 0xff, 0x6b, 0x51, 0xc2, 0x59, 0x8a, 0x24, 0xc2, 0xba, 0xc0, 0xd7, 0xd4, 0xac, 0xd9, 0x3e, 0x38, 0x1f, 0x7f, 0x2d, 0xb7, 0x85, 0x8b, 0xf1, 0xd2, 0x42, 0x28, 0xa9, 0xd7, 0x94 }, + }, + { + .msglen = 83, + .result = { 0xde, 0x40, 0xe0, 0xde, 0xf9, 0xe4, 0x75, 0x3d, 0x61, 0x91, 0x38, 0xac, 0x31, 0xa9, 0xba, 0x31, 0x18, 0x41, 0x57, 0x2e, 0x89, 0xdf, 0x26, 0x83, 0x40, 0x71, 0xce, 0xdc, 0x18, 0x3f, 0xe7, 0xd7 }, + }, + { + .msglen = 84, + .result = { 0x85, 0xf, 0x58, 0x5f, 0x4d, 0x81, 0x5b, 0x54, 0x6a, 0xa4, 0xd4, 0xfb, 0x3, 0x4e, 0x71, 0xa7, 0xc5, 0x11, 0xf, 0x1a, 0xa8, 0x44, 0x10, 0x15, 0x2e, 0xdf, 0x1e, 0xea, 0x4d, 0x86, 0x31, 0x33 }, + }, + { + .msglen = 85, + .result = { 0x7f, 0xe2, 0x1b, 0x95, 0x7b, 0x19, 0x2f, 0x4e, 0x72, 0x1d, 0x6c, 0x2c, 0xf3, 0x74, 0x6e, 0x99, 0x2b, 0x10, 0x76, 0x55, 0x25, 0xe4, 0x89, 0x19, 0x98, 0xb4, 0xdc, 0xea, 0xfa, 0x68, 0xec, 0x3 }, + }, + { + .msglen = 86, + .result = { 0x5c, 0x95, 0x3d, 0xcc, 0x6, 0x58, 0x9b, 0xc4, 0x71, 0x61, 0xc2, 0x5a, 0xac, 0xaf, 0x54, 0xbf, 0xcc, 0x93, 0x3d, 0x2e, 0xdf, 0x99, 0x74, 0xc8, 0xc8, 0x36, 0xe9, 0x44, 0x7e, 0x6d, 0x3d, 0xe7 }, + }, + { + .msglen = 87, + .result = { 0xf2, 0x33, 0xbc, 0x61, 0xc6, 0x2c, 0x19, 0x26, 0x80, 0x9e, 0x1e, 0x76, 0x8e, 0x9, 0x61, 0x6, 0xfb, 0xc3, 0xc8, 0xcb, 0x35, 0x9d, 0xaa, 0x73, 0xa8, 0xe6, 0xd2, 0x89, 0xc5, 0x5d, 0xee, 0xa4 }, + }, + { + .msglen = 88, + .result = { 0x3f, 0x13, 0xf7, 0x63, 0x67, 0x8d, 0x65, 0xcd, 0xa8, 0x5b, 0xcd, 0xc4, 0xb7, 0x25, 0x35, 0xbe, 0xd3, 0xc1, 0x6d, 0x36, 0xb9, 0x8c, 0x8c, 0x6a, 0x79, 0xd1, 0x12, 0xe8, 0xdc, 0x6c, 0xe3, 0x6d }, + }, + { + .msglen = 89, + .result = { 0x8f, 0x21, 0x5a, 0x7a, 0x84, 0x79, 0x7d, 0x33, 0xa, 0x7e, 0x7a, 0x7, 0x2a, 0xa9, 0xa6, 0x58, 0x33, 0xdf, 0xec, 0x40, 0x88, 0xf2, 0x9f, 0x8d, 0x12, 0xb5, 0x5e, 0xb2, 0x88, 0x2d, 0xc1, 0x7c }, + }, + { + .msglen = 90, + .result = { 0x73, 0xfc, 0xc6, 0x9, 0x5f, 0xc2, 0xab, 0x2d, 0xd5, 0x84, 0x6c, 0xdd, 0x1f, 0x70, 0x9e, 0x5c, 0x30, 0x36, 0xb4, 0xe7, 0x86, 0xab, 0x89, 0xc6, 0xc9, 0xed, 0x7d, 0x2e, 0x26, 0x13, 0x37, 0x4a }, + }, + { + .msglen = 91, + .result = { 0x3e, 0x41, 0x8a, 0x37, 0xbd, 0xec, 0x53, 0x52, 0x47, 0xd2, 0x71, 0xa4, 0x5b, 0xc7, 0x11, 0x8e, 0x8c, 0xb8, 0x2c, 0x36, 0xc9, 0xa7, 0x15, 0x21, 0x15, 0xde, 0x7f, 0x54, 0xc7, 0xb3, 0x8d, 0x34 }, + }, + { + .msglen = 92, + .result = { 0xca, 0x1a, 0xf9, 0xfd, 0xf4, 0xb9, 0xd, 0xdd, 0x91, 0xd8, 0x7b, 0x7c, 0xf4, 0x82, 0xe7, 0x57, 0xc0, 0xb9, 0xfe, 0x2f, 0x3c, 0xc7, 0x5a, 0x3d, 0xb, 0x79, 0xb3, 0x7a, 0x7e, 0xfd, 0x25, 0x20 }, + }, + { + .msglen = 93, + .result = { 0xf6, 0x54, 0xd6, 0x3a, 0x93, 0xe3, 0x7b, 0x42, 0x11, 0xa8, 0xda, 0xa4, 0x2f, 0xbf, 0xcb, 0xd0, 0x58, 0x59, 0xf8, 0xda, 0x8c, 0x5e, 0xdc, 0x1e, 0xb0, 0x64, 0x15, 0x31, 0x92, 0xe6, 0xcc, 0xc8 }, + }, + { + .msglen = 94, + .result = { 0x7b, 0x8f, 0x93, 0xa3, 0x55, 0x11, 0x1e, 0x18, 0x77, 0xd9, 0x12, 0x7c, 0x54, 0x4e, 0x3f, 0x36, 0x18, 0x2f, 0xc7, 0xba, 0xd3, 0xe7, 0xc, 0xa3, 0xb2, 0xb1, 0x66, 0x7a, 0xfe, 0x30, 0x1b, 0x4e }, + }, + { + .msglen = 95, + .result = { 0x16, 0xea, 0xe9, 0xae, 0x5d, 0x2f, 0x88, 0x87, 0x41, 0x43, 0x3d, 0xfc, 0x35, 0x7f, 0x2c, 0x4c, 0x63, 0x36, 0xf3, 0x36, 0x51, 0x84, 0xb1, 0x64, 0xc5, 0x19, 0xc0, 0xd6, 0x57, 0xef, 0x2a, 0xa4 }, + }, + { + .msglen = 96, + .result = { 0xc9, 0x79, 0x20, 0xa1, 0x14, 0xba, 0xbe, 0x88, 0x7d, 0x6f, 0x4, 0xe3, 0xfd, 0x2d, 0xfd, 0xc3, 0x8a, 0x1, 0xea, 0x12, 0x9d, 0x4c, 0x14, 0xc3, 0x82, 0x7f, 0xb6, 0x1e, 0x8d, 0xcc, 0x11, 0x84 }, + }, + { + .msglen = 97, + .result = { 0x20, 0xa9, 0xb7, 0x5a, 0x5b, 0x76, 0xaa, 0x7b, 0xed, 0x70, 0x16, 0xfb, 0xea, 0x93, 0x55, 0xd1, 0x9f, 0x95, 0xa, 0xe0, 0x79, 0x51, 0x12, 0x2c, 0xfd, 0x7d, 0x6c, 0x94, 0x4f, 0xb6, 0x5f, 0x14 }, + }, + { + .msglen = 98, + .result = { 0xfc, 0xf4, 0x1, 0xcc, 0x9f, 0xce, 0xc2, 0x50, 0x0, 0x1f, 0xf8, 0x3f, 0xe4, 0x87, 0x2e, 0x79, 0x94, 0xdb, 0x86, 0x85, 0x8a, 0x7d, 0xb4, 0x6a, 0x84, 0xb8, 0x6c, 0x32, 0xad, 0x8c, 0x20, 0x63 }, + }, + { + .msglen = 99, + .result = { 0x17, 0xa1, 0xf5, 0x6, 0xaa, 0xb0, 0xe3, 0x82, 0x2e, 0x9c, 0xf2, 0xb9, 0x75, 0x75, 0xe9, 0x36, 0x90, 0xa9, 0xb2, 0xb9, 0x97, 0xb0, 0x10, 0xbb, 0xdd, 0x65, 0xd0, 0xa8, 0xbf, 0x69, 0x1d, 0x43 }, + }, + { + .msglen = 100, + .result = { 0xb5, 0x6c, 0xca, 0xca, 0xe1, 0xc5, 0x74, 0x19, 0xb0, 0x89, 0x58, 0x5e, 0x2e, 0x61, 0xcb, 0xa1, 0x23, 0xd0, 0x25, 0x37, 0x47, 0xe3, 0xac, 0x3e, 0x9a, 0xf6, 0x5d, 0x0, 0x77, 0xc2, 0xdc, 0x47 }, + }, + { + .msglen = 101, + .result = { 0x8, 0xa4, 0x3b, 0xe7, 0x1e, 0xeb, 0x4c, 0x3a, 0x82, 0xf1, 0xe4, 0x9d, 0xb1, 0xcc, 0xbc, 0x30, 0xb7, 0xa6, 0xfe, 0x47, 0x43, 0x86, 0xb8, 0x10, 0x33, 0xef, 0x8e, 0x35, 0x34, 0xf1, 0x52, 0xae }, + }, + { + .msglen = 102, + .result = { 0x0, 0xdb, 0x9b, 0xb7, 0xfc, 0x8a, 0x55, 0x81, 0x49, 0x94, 0x5c, 0xc2, 0x63, 0xd2, 0x56, 0x85, 0xab, 0x5a, 0xa1, 0x89, 0x66, 0xa1, 0x4d, 0x39, 0x1b, 0xe2, 0x12, 0x9a, 0x51, 0x79, 0xc0, 0x1c }, + }, + { + .msglen = 103, + .result = { 0x4c, 0xeb, 0xaa, 0xec, 0xb8, 0x31, 0xef, 0xb6, 0x89, 0x8e, 0x42, 0xdf, 0x9d, 0x57, 0x42, 0xf7, 0x53, 0x5d, 0x11, 0xc0, 0x29, 0xf7, 0x64, 0x30, 0x42, 0x32, 0x23, 0xda, 0x19, 0xe, 0x8d, 0xf3 }, + }, + { + .msglen = 104, + .result = { 0x32, 0xf5, 0x6, 0x53, 0xf8, 0x18, 0x94, 0x3d, 0xaa, 0x5e, 0xb9, 0x9e, 0x95, 0x8, 0x4, 0x29, 0xea, 0x76, 0xa1, 0xe5, 0x60, 0xa, 0x29, 0xd0, 0x78, 0x7e, 0x0, 0x27, 0x4e, 0x63, 0xc3, 0x69 }, + }, + { + .msglen = 105, + .result = { 0xa9, 0xf1, 0x2b, 0xaa, 0x5e, 0xb3, 0xc9, 0xf3, 0x25, 0x6e, 0x6f, 0x8, 0xc3, 0xb4, 0xab, 0xd1, 0x20, 0x3c, 0xb1, 0x82, 0x6b, 0xfa, 0x8, 0x62, 0xaf, 0x7a, 0xa9, 0x0, 0x79, 0x9a, 0x2b, 0x12 }, + }, + { + .msglen = 106, + .result = { 0xc2, 0x5e, 0x53, 0x66, 0x14, 0x5, 0x26, 0x6a, 0xf1, 0x70, 0x50, 0xb3, 0x9b, 0x40, 0x99, 0x7a, 0x73, 0xe2, 0xed, 0x3d, 0x4c, 0xcc, 0xf9, 0xf6, 0x1b, 0x4c, 0x6, 0xdc, 0x9, 0x7a, 0xc2, 0x4a }, + }, + { + .msglen = 107, + .result = { 0x68, 0xeb, 0x96, 0xb6, 0x9, 0x7b, 0xe2, 0x4a, 0x18, 0x3a, 0xe8, 0xf8, 0xe8, 0xc7, 0x4e, 0x27, 0x8c, 0x18, 0x8a, 0xa6, 0x23, 0xfe, 0xc2, 0xb, 0xbd, 0x72, 0x1, 0x56, 0x21, 0x6b, 0x6c, 0x56 }, + }, + { + .msglen = 108, + .result = { 0xe1, 0x7, 0xeb, 0xc3, 0x3a, 0x5e, 0x28, 0x65, 0x14, 0xcb, 0x73, 0x19, 0xef, 0x32, 0x78, 0x96, 0xf3, 0xda, 0x1e, 0x5a, 0x89, 0xf4, 0x29, 0x7c, 0xa0, 0xfd, 0x3b, 0xe8, 0xb, 0xf0, 0x72, 0xf1 }, + }, + { + .msglen = 109, + .result = { 0x88, 0xac, 0xe5, 0xe7, 0xdb, 0x26, 0xa5, 0xa5, 0xef, 0x66, 0x92, 0xb4, 0xab, 0x6b, 0xed, 0x4b, 0x1a, 0x9e, 0x19, 0xb0, 0xb6, 0xd6, 0x11, 0xb1, 0x33, 0x40, 0x50, 0x69, 0x48, 0x75, 0x4, 0xe5 }, + }, + { + .msglen = 110, + .result = { 0x7d, 0x25, 0x12, 0x5, 0x37, 0x8c, 0x89, 0x8a, 0x43, 0xd9, 0x97, 0x26, 0xb8, 0xaf, 0xb3, 0x21, 0x4d, 0xde, 0x24, 0x58, 0x4f, 0xc8, 0xd, 0x31, 0x22, 0xb2, 0xdf, 0x34, 0xd5, 0xb, 0x25, 0xb9 }, + }, + { + .msglen = 111, + .result = { 0x4e, 0xfa, 0x3f, 0x64, 0x15, 0xf8, 0xe2, 0xb9, 0x10, 0x70, 0xeb, 0x6a, 0xf6, 0xf2, 0x14, 0x33, 0x0, 0xd1, 0x19, 0xf2, 0x8c, 0x50, 0x57, 0x17, 0xf0, 0xc5, 0x5d, 0xa1, 0xe, 0x22, 0xa0, 0x53 }, + }, + { + .msglen = 112, + .result = { 0x12, 0xac, 0x71, 0xa0, 0x72, 0x7a, 0x45, 0x74, 0x82, 0xf6, 0xde, 0x75, 0xe, 0xb9, 0xb2, 0x65, 0x76, 0x86, 0x13, 0x77, 0x4a, 0x30, 0xbe, 0xfa, 0x1, 0x38, 0x74, 0x49, 0xc9, 0x7f, 0x43, 0x9a }, + }, + { + .msglen = 113, + .result = { 0xfe, 0x25, 0x6b, 0xbf, 0x17, 0x61, 0x29, 0xce, 0x9e, 0xc2, 0x42, 0x9a, 0xb8, 0x29, 0xdb, 0x88, 0xef, 0x75, 0x3b, 0xad, 0xba, 0x9c, 0xd5, 0x9, 0x40, 0x2f, 0x49, 0xbd, 0x3, 0x43, 0xa7, 0x3 }, + }, + { + .msglen = 114, + .result = { 0xe5, 0x36, 0x48, 0xb5, 0x9e, 0xb3, 0x3c, 0x5f, 0x86, 0xab, 0x5, 0xe4, 0xc0, 0xe3, 0x94, 0xe4, 0x4c, 0x90, 0xcd, 0xa1, 0x97, 0x12, 0xdf, 0x33, 0x7a, 0x1a, 0x1e, 0xcd, 0xd4, 0x61, 0xa8, 0x3c }, + }, + { + .msglen = 115, + .result = { 0x52, 0xbd, 0xc6, 0x84, 0x65, 0x32, 0x88, 0x1, 0x85, 0x64, 0xfd, 0xc9, 0x98, 0x18, 0x27, 0x52, 0xe9, 0x30, 0xa2, 0x9e, 0xc2, 0xcf, 0xa9, 0x98, 0xbc, 0x47, 0x3a, 0xc7, 0xd5, 0xb1, 0x81, 0x78 }, + }, + { + .msglen = 116, + .result = { 0xab, 0xb1, 0xb3, 0xa5, 0x23, 0xea, 0x45, 0xe8, 0xe0, 0xa9, 0x3d, 0xe9, 0xe9, 0x86, 0x15, 0x10, 0x90, 0xca, 0xf7, 0xcc, 0x92, 0x64, 0x10, 0x3d, 0x63, 0x2f, 0x17, 0xec, 0x54, 0x9e, 0xbd, 0x3b }, + }, + { + .msglen = 117, + .result = { 0x82, 0xf8, 0x45, 0xcd, 0x8b, 0xfc, 0xd8, 0x81, 0x6b, 0x1f, 0x91, 0x30, 0x6d, 0xbb, 0x91, 0x70, 0x8b, 0xfe, 0x8d, 0x33, 0x35, 0x4f, 0x62, 0x7f, 0xba, 0xb6, 0x99, 0x3b, 0x79, 0xe6, 0x8f, 0x58 }, + }, + { + .msglen = 118, + .result = { 0xa6, 0x59, 0x67, 0x5e, 0x49, 0xe2, 0x95, 0x28, 0xa3, 0x4b, 0x4a, 0x10, 0x20, 0xd1, 0xd6, 0x7b, 0x86, 0x8a, 0x5c, 0x81, 0x31, 0x68, 0xea, 0xb7, 0x61, 0xbb, 0xb6, 0x3a, 0x6d, 0x78, 0xaa, 0x37 }, + }, + { + .msglen = 119, + .result = { 0x64, 0x9, 0xaf, 0x42, 0xff, 0xb1, 0xc7, 0xe6, 0xbf, 0x6f, 0xa1, 0xbb, 0x5a, 0x6, 0xea, 0xd, 0x57, 0x7d, 0x24, 0x41, 0x2b, 0xf9, 0x63, 0x82, 0x1f, 0x9, 0xa5, 0xa7, 0x58, 0xc, 0x4, 0x55 }, + }, + { + .msglen = 120, + .result = { 0x43, 0x33, 0x90, 0x81, 0xb6, 0x23, 0x50, 0xdf, 0xa2, 0x7e, 0x41, 0xa2, 0x40, 0x40, 0xa9, 0x34, 0xd6, 0x5, 0x6c, 0x44, 0x8, 0x3f, 0x2b, 0xaa, 0xff, 0x3, 0xc3, 0x49, 0x1b, 0x15, 0x5e, 0x7c }, + }, + { + .msglen = 121, + .result = { 0xe, 0xd7, 0x6d, 0x29, 0xdd, 0x8, 0xee, 0x2f, 0x1d, 0x5a, 0xb2, 0x70, 0x90, 0x8d, 0xa9, 0xf2, 0x5c, 0x5b, 0xc5, 0xe1, 0x7c, 0xec, 0x49, 0x8f, 0x46, 0x94, 0xe1, 0xc8, 0xd4, 0x68, 0xa2, 0x34 }, + }, + { + .msglen = 122, + .result = { 0x4f, 0x25, 0x61, 0xb1, 0x29, 0xb7, 0x41, 0x50, 0xc7, 0xfa, 0xab, 0x6c, 0x92, 0xff, 0x4, 0xc, 0xa3, 0xa1, 0x10, 0xf6, 0xa6, 0xa4, 0x5a, 0xbf, 0xe, 0x9a, 0x61, 0xa8, 0x24, 0xa3, 0x93, 0x1e }, + }, + { + .msglen = 123, + .result = { 0x7c, 0x8c, 0xf4, 0x5d, 0x45, 0xcf, 0x61, 0x22, 0xc9, 0x8e, 0x3a, 0xeb, 0x85, 0x55, 0x66, 0x2e, 0x1e, 0x33, 0x88, 0xab, 0x74, 0xf2, 0x66, 0x4f, 0x43, 0xfa, 0x3e, 0x25, 0xcc, 0xd2, 0x0, 0x71 }, + }, + { + .msglen = 124, + .result = { 0x8b, 0x51, 0x99, 0x90, 0x84, 0xda, 0x7a, 0xb3, 0xb1, 0x31, 0x1b, 0x1a, 0x66, 0xe2, 0x53, 0xac, 0x45, 0x94, 0x5c, 0xa6, 0x8c, 0x44, 0x45, 0x4, 0x58, 0x13, 0xcb, 0x44, 0x9e, 0x6c, 0x6a, 0x10 }, + }, + { + .msglen = 125, + .result = { 0xc5, 0xb0, 0x36, 0x55, 0x4d, 0x15, 0xf0, 0x67, 0xf8, 0x26, 0x45, 0x48, 0xa7, 0x65, 0xcc, 0xa8, 0x14, 0x1e, 0x63, 0x22, 0x36, 0xc3, 0xf3, 0x99, 0x5b, 0x77, 0xb2, 0xa8, 0xc3, 0x62, 0xb4, 0xdd }, + }, + { + .msglen = 126, + .result = { 0x38, 0xcb, 0x97, 0x81, 0x62, 0xde, 0x32, 0x5f, 0xc5, 0x27, 0x39, 0x82, 0x36, 0x77, 0x5a, 0xc4, 0xbf, 0x45, 0xf4, 0xe8, 0x17, 0xa9, 0x17, 0xfc, 0x34, 0xb, 0xa1, 0x11, 0x79, 0xf5, 0xc, 0x79 }, + }, + { + .msglen = 127, + .result = { 0x2e, 0x16, 0xab, 0xf4, 0x56, 0xea, 0x6a, 0x7e, 0x97, 0x25, 0xf9, 0x9a, 0x0, 0x5d, 0xe3, 0x70, 0x76, 0xa9, 0x2a, 0xab, 0xae, 0x32, 0xe5, 0xe8, 0xb6, 0xe1, 0x22, 0xc8, 0x74, 0xe1, 0x1f, 0x22 }, + }, + { + .msglen = 128, + .result = { 0x6e, 0x54, 0xeb, 0x50, 0x85, 0x7b, 0xd2, 0x64, 0x32, 0x2c, 0xb0, 0xd0, 0xc2, 0x3, 0x31, 0x95, 0xa8, 0x6a, 0x50, 0x49, 0xf4, 0x77, 0x27, 0x1a, 0x89, 0x10, 0x3e, 0x98, 0x45, 0x1e, 0xe7, 0xeb }, + }, + { + .msglen = 129, + .result = { 0x7, 0x2e, 0xdf, 0xe9, 0x2e, 0x73, 0xf4, 0x1e, 0x65, 0x31, 0x64, 0x25, 0xc1, 0x59, 0x46, 0xd7, 0xf9, 0x12, 0xfe, 0xc7, 0x9f, 0x24, 0xa, 0xd9, 0xfb, 0x8, 0xcb, 0x5f, 0xf2, 0x77, 0x11, 0xce }, + }, + { + .msglen = 130, + .result = { 0x6, 0x46, 0xc7, 0x42, 0xc2, 0xc3, 0xf2, 0x4c, 0x82, 0x7d, 0x1c, 0x2c, 0x68, 0xfd, 0x29, 0x6d, 0xc2, 0xac, 0x4f, 0xbc, 0x8d, 0xb2, 0xf7, 0x78, 0xb7, 0x8f, 0x4, 0x3f, 0x49, 0xb5, 0xc5, 0xd }, + }, + { + .msglen = 131, + .result = { 0x9c, 0x1f, 0xdb, 0x89, 0x3b, 0x8b, 0x5c, 0x3d, 0x1e, 0xd2, 0x9f, 0x74, 0x63, 0xb, 0x4f, 0x59, 0x72, 0x13, 0x4f, 0x40, 0x59, 0x35, 0xc6, 0x64, 0x5a, 0xb5, 0x43, 0xaf, 0x43, 0x7a, 0x13, 0xb0 }, + }, + { + .msglen = 132, + .result = { 0x25, 0xa9, 0x97, 0x9e, 0x4f, 0x52, 0xe6, 0xe7, 0xf, 0x38, 0xc6, 0xfb, 0x9e, 0x77, 0xe7, 0x1c, 0xb9, 0x8a, 0xf3, 0x4d, 0x76, 0xb3, 0x58, 0x8e, 0xab, 0x7d, 0xd6, 0xbb, 0x78, 0x26, 0xb1, 0x7f }, + }, + { + .msglen = 133, + .result = { 0x2b, 0x8, 0xfa, 0x23, 0x7d, 0xb2, 0xa1, 0x16, 0x85, 0x7b, 0x3c, 0xa4, 0xde, 0x19, 0xf7, 0x81, 0xb6, 0xaf, 0xbc, 0x11, 0x31, 0x10, 0x6f, 0x14, 0x4a, 0x62, 0x48, 0x1e, 0x43, 0x95, 0xa4, 0xb4 }, + }, + { + .msglen = 134, + .result = { 0x9c, 0x93, 0x30, 0x3f, 0x4c, 0x8f, 0xa7, 0x56, 0xd1, 0x6c, 0x9a, 0x28, 0xa1, 0x21, 0x7d, 0x5b, 0x12, 0x6b, 0x5a, 0xd4, 0xb9, 0x62, 0x5, 0xe2, 0xd5, 0xc8, 0x2a, 0xd1, 0xb0, 0x46, 0x2a, 0x2c }, + }, + { + .msglen = 135, + .result = { 0xd7, 0x17, 0xd, 0xc0, 0x46, 0x24, 0x9e, 0x14, 0x21, 0xac, 0xf3, 0xd0, 0xda, 0xf4, 0xd9, 0xf1, 0xf2, 0x96, 0xbd, 0x55, 0xff, 0x3c, 0x8d, 0x90, 0xc8, 0x2f, 0x1e, 0x87, 0xad, 0xd7, 0x8a, 0x8a }, + }, + { + .msglen = 136, + .result = { 0x90, 0xd6, 0xa4, 0x46, 0x75, 0x8c, 0xc3, 0xda, 0x26, 0x8a, 0xe1, 0xb7, 0xa4, 0xe, 0xef, 0x33, 0x65, 0x41, 0xa3, 0x60, 0x6a, 0xce, 0xfb, 0xc4, 0x1c, 0xa4, 0x95, 0x6d, 0x43, 0x49, 0x69, 0xd5 }, + }, + { + .msglen = 137, + .result = { 0xd6, 0xf5, 0xfe, 0xb0, 0x9a, 0xca, 0xec, 0xeb, 0xbe, 0x4b, 0xbd, 0x96, 0x65, 0xfe, 0x65, 0x31, 0xef, 0x36, 0x3a, 0xfc, 0x3a, 0x8, 0x3, 0xb0, 0xbf, 0xeb, 0xd, 0x2c, 0xd9, 0x27, 0x14, 0x4f }, + }, + { + .msglen = 138, + .result = { 0x97, 0x4f, 0x86, 0x11, 0xf9, 0x61, 0xad, 0xc, 0xba, 0x2d, 0xfa, 0xa4, 0x6f, 0x19, 0xb3, 0x66, 0xf8, 0xcc, 0x74, 0x2c, 0x76, 0x29, 0xdd, 0x6b, 0x5, 0xa3, 0x3a, 0x3b, 0xa6, 0xec, 0x81, 0xc0 }, + }, + { + .msglen = 139, + .result = { 0x9a, 0xe3, 0xc, 0x22, 0x5d, 0xb3, 0x71, 0x5d, 0x30, 0xcf, 0x6, 0xc1, 0x86, 0xf6, 0x84, 0xac, 0x25, 0x45, 0xb2, 0xa0, 0xd2, 0x93, 0x8b, 0x9e, 0x77, 0x55, 0x16, 0x51, 0x61, 0x4a, 0x91, 0xcd }, + }, + { + .msglen = 140, + .result = { 0xf1, 0x30, 0xf4, 0xc7, 0x6c, 0xe3, 0x8d, 0x63, 0x41, 0x62, 0x64, 0xe1, 0xc3, 0x97, 0xf0, 0xd6, 0xf3, 0xfd, 0x17, 0xe, 0xca, 0xd8, 0x9e, 0x6d, 0xa0, 0xa1, 0x27, 0x60, 0xff, 0xf, 0x7a, 0xca }, + }, + { + .msglen = 141, + .result = { 0x5, 0xab, 0x87, 0x58, 0xa8, 0x5e, 0x7d, 0xec, 0x23, 0x90, 0xd8, 0xfa, 0x87, 0x1, 0x4b, 0x32, 0xe9, 0x0, 0x7b, 0x92, 0x3b, 0x51, 0x44, 0x86, 0xa2, 0x55, 0xf0, 0xb7, 0x13, 0x3b, 0x58, 0x70 }, + }, + { + .msglen = 142, + .result = { 0xff, 0x4e, 0x8a, 0xca, 0xce, 0xe0, 0x84, 0x2a, 0x70, 0x82, 0x52, 0x1e, 0x67, 0xc, 0x67, 0x36, 0x76, 0x74, 0xed, 0x49, 0x21, 0x44, 0x0, 0x1a, 0x75, 0xcd, 0x4f, 0x17, 0xb8, 0xa9, 0xdf, 0xb9 }, + }, + { + .msglen = 143, + .result = { 0xf2, 0x36, 0x6f, 0xf3, 0x8e, 0xf3, 0xbd, 0x51, 0xec, 0xc4, 0x96, 0xc1, 0x88, 0xfe, 0x68, 0x5e, 0x1b, 0xdf, 0x71, 0x6b, 0xf3, 0x78, 0x84, 0x16, 0x11, 0xac, 0x37, 0x4d, 0x8f, 0x6e, 0x7b, 0x40 }, + }, + { + .msglen = 144, + .result = { 0x24, 0x20, 0x1d, 0x2, 0x16, 0x1, 0xc4, 0xe5, 0xdf, 0x81, 0xca, 0xa9, 0xf2, 0x4d, 0xe2, 0x77, 0x11, 0xf6, 0x43, 0xd3, 0x36, 0x36, 0x1c, 0xe6, 0x6c, 0x96, 0xc9, 0x74, 0x8e, 0x39, 0x1c, 0xb1 }, + }, + { + .msglen = 145, + .result = { 0xfc, 0x13, 0x13, 0x5c, 0x87, 0x9a, 0x95, 0xcd, 0x66, 0xac, 0x85, 0xda, 0x8c, 0x28, 0x38, 0x3f, 0x43, 0xe1, 0x40, 0x8e, 0x8f, 0x49, 0x17, 0xda, 0x75, 0xd0, 0xc4, 0xf5, 0x9e, 0x3, 0xf0, 0x62 }, + }, + { + .msglen = 146, + .result = { 0xcc, 0x3e, 0x74, 0x6a, 0x82, 0xb0, 0x67, 0x77, 0xcf, 0x6e, 0x93, 0x40, 0x84, 0xc7, 0xa1, 0x85, 0xa5, 0x38, 0x23, 0xa5, 0x4f, 0x9e, 0xee, 0x3d, 0xa7, 0xab, 0x88, 0x3b, 0x3, 0x1d, 0xdb, 0xbd }, + }, + { + .msglen = 147, + .result = { 0xaa, 0x4f, 0x52, 0xf0, 0xe8, 0x49, 0x80, 0x5e, 0xe4, 0xd4, 0x8f, 0xc1, 0x5c, 0x7d, 0x36, 0x2, 0xdb, 0xda, 0x45, 0xab, 0x6e, 0x90, 0xc1, 0x55, 0x4f, 0x8, 0xaf, 0x55, 0x4d, 0x45, 0x6b, 0x91 }, + }, + { + .msglen = 148, + .result = { 0xfb, 0x92, 0xef, 0x68, 0xc4, 0xa, 0xd9, 0xd8, 0x86, 0xb5, 0x63, 0x34, 0xa7, 0x42, 0x5a, 0xef, 0x13, 0xc0, 0xc9, 0x44, 0x8f, 0x9e, 0x40, 0x51, 0x1b, 0xcf, 0xbb, 0x8c, 0xb0, 0x2c, 0x56, 0xc }, + }, + { + .msglen = 149, + .result = { 0x88, 0xdb, 0x71, 0x51, 0x85, 0x63, 0xb6, 0xb4, 0xeb, 0x7c, 0x11, 0xaa, 0x96, 0x8, 0x9e, 0x60, 0x70, 0xa5, 0x19, 0xa4, 0x2, 0xf1, 0xa0, 0x4f, 0x16, 0xde, 0xd6, 0x8d, 0xd3, 0xc5, 0xc, 0x6c }, + }, + { + .msglen = 150, + .result = { 0x4a, 0xad, 0x96, 0xea, 0x90, 0xb7, 0x76, 0x9d, 0x92, 0x60, 0x35, 0x59, 0x1c, 0x89, 0x67, 0x54, 0xfd, 0x50, 0x20, 0x97, 0xc8, 0x16, 0xc8, 0xc2, 0x50, 0x40, 0x63, 0xba, 0xfb, 0xbc, 0x5e, 0xcd }, + }, + { + .msglen = 151, + .result = { 0xca, 0x4c, 0x3d, 0x26, 0x75, 0x82, 0x48, 0x5b, 0xa4, 0xd3, 0x28, 0x9, 0x8d, 0xe0, 0x67, 0x6d, 0xe1, 0x5, 0x8a, 0xbf, 0x17, 0xbb, 0x6e, 0x48, 0x2e, 0xd, 0xcd, 0x90, 0x7c, 0x4e, 0xa4, 0x94 }, + }, + { + .msglen = 152, + .result = { 0x6d, 0x27, 0x5e, 0x91, 0xeb, 0xc7, 0x1a, 0x31, 0x42, 0xfa, 0x2c, 0x91, 0xdc, 0x6a, 0xdc, 0x1b, 0x2b, 0x66, 0xf2, 0x9a, 0xf6, 0x11, 0x36, 0x96, 0x2a, 0xfc, 0x73, 0x89, 0x7e, 0xd4, 0x55, 0x3d }, + }, + { + .msglen = 153, + .result = { 0x76, 0xba, 0x1d, 0x4b, 0xc1, 0xa2, 0x1b, 0x56, 0xbe, 0x5, 0x38, 0x90, 0x47, 0xe9, 0x9, 0xc2, 0xd1, 0x2, 0x6d, 0x44, 0x81, 0xf7, 0x6e, 0x28, 0x88, 0x79, 0xb5, 0x10, 0x75, 0xfb, 0xc6, 0xe7 }, + }, + { + .msglen = 154, + .result = { 0x6d, 0xbc, 0x90, 0xa6, 0x2f, 0xb5, 0x45, 0x5f, 0x4a, 0xcb, 0x85, 0x32, 0x90, 0x57, 0x86, 0x75, 0x51, 0xa5, 0x7e, 0x4b, 0x6b, 0xb3, 0xeb, 0xfe, 0xba, 0x75, 0xfc, 0x55, 0x1a, 0x85, 0x3, 0x54 }, + }, + { + .msglen = 155, + .result = { 0x7d, 0x59, 0x19, 0xb6, 0xf2, 0x7f, 0x7, 0x7a, 0xaa, 0xf7, 0xdf, 0x2e, 0x2d, 0xfb, 0x57, 0x14, 0xd6, 0x9f, 0x9c, 0xcc, 0x56, 0x88, 0xe, 0x85, 0xcc, 0x30, 0x6, 0x32, 0x1f, 0x70, 0x47, 0x59 }, + }, + { + .msglen = 156, + .result = { 0xea, 0xfa, 0x44, 0x81, 0x83, 0xec, 0x2d, 0x63, 0xa6, 0xea, 0xf0, 0x6, 0x5d, 0x15, 0x32, 0x89, 0xed, 0x52, 0xf, 0x23, 0x66, 0x8b, 0x1c, 0x7c, 0x13, 0xd0, 0x35, 0xc1, 0x7d, 0x27, 0xfe, 0x80 }, + }, + { + .msglen = 157, + .result = { 0xab, 0x31, 0xe1, 0x44, 0x3d, 0x3a, 0xf5, 0x6a, 0x8b, 0x5d, 0xa6, 0xd5, 0x63, 0x23, 0x7e, 0x17, 0x24, 0xc9, 0x41, 0x53, 0x86, 0x90, 0xb7, 0x6f, 0xbc, 0x39, 0x5d, 0x1b, 0x19, 0xd9, 0xef, 0x9c }, + }, + { + .msglen = 158, + .result = { 0x3e, 0x34, 0xec, 0xd9, 0x26, 0xe7, 0x27, 0x3b, 0xc5, 0xc3, 0x8e, 0x11, 0xba, 0x58, 0xcf, 0x2b, 0x29, 0xc4, 0x49, 0xfc, 0xf6, 0x9d, 0xcc, 0x2a, 0x0, 0xff, 0xe6, 0xbc, 0x7d, 0x2a, 0x48, 0x22 }, + }, + { + .msglen = 159, + .result = { 0xc8, 0x59, 0x27, 0xa2, 0x58, 0x9e, 0xfe, 0x8c, 0x5a, 0x7f, 0x99, 0xd0, 0x58, 0xd4, 0x8c, 0xae, 0xa9, 0x4, 0x24, 0x50, 0x34, 0x23, 0x45, 0xfe, 0x87, 0xa7, 0x53, 0x5a, 0x27, 0x9d, 0x1b, 0x4f }, + }, + { + .msglen = 160, + .result = { 0xd7, 0x76, 0xaa, 0x3b, 0x97, 0x5e, 0xac, 0xbe, 0x46, 0x45, 0x80, 0x8e, 0x2c, 0xa2, 0xe1, 0xd4, 0x75, 0xb5, 0xe0, 0xd2, 0x4c, 0x59, 0xf0, 0xc3, 0xe8, 0x8c, 0x96, 0xbd, 0x85, 0x23, 0x8b, 0x40 }, + }, + { + .msglen = 161, + .result = { 0x40, 0x8e, 0xa5, 0xbd, 0x32, 0x7, 0x19, 0xc8, 0x31, 0x22, 0x32, 0xdf, 0xe0, 0xf5, 0xe2, 0x5f, 0x91, 0xf4, 0x95, 0x7a, 0xa7, 0x91, 0x9d, 0xed, 0x35, 0x2f, 0x0, 0x4, 0x62, 0x63, 0x4, 0x80 }, + }, + { + .msglen = 162, + .result = { 0xa6, 0x1b, 0x63, 0x3, 0xbf, 0x2, 0xbd, 0xbb, 0x69, 0x1b, 0xac, 0x54, 0x99, 0xee, 0x8b, 0xe, 0xb, 0x41, 0x78, 0xda, 0x8f, 0x72, 0x97, 0xdf, 0x9, 0xfa, 0x35, 0xe1, 0x8a, 0xb3, 0x80, 0xc3 }, + }, + { + .msglen = 163, + .result = { 0x7d, 0xd3, 0x5e, 0x1a, 0x9, 0x94, 0x6e, 0x30, 0xc6, 0xbb, 0xda, 0xe7, 0x92, 0x49, 0xf6, 0x37, 0xe, 0xb3, 0x30, 0x96, 0xb2, 0xaf, 0x57, 0x22, 0xe4, 0x8d, 0x9f, 0x83, 0x51, 0xbf, 0x98, 0xb0 }, + }, + { + .msglen = 164, + .result = { 0x3e, 0x10, 0xe4, 0x81, 0xa2, 0x1d, 0x92, 0x7a, 0x1a, 0x73, 0xfe, 0xd4, 0x8b, 0x28, 0x4c, 0x85, 0xcc, 0xfe, 0xe0, 0x4f, 0x55, 0xfd, 0x47, 0x95, 0x1f, 0x1b, 0x60, 0x38, 0x7, 0xe9, 0xc9, 0x4f }, + }, + { + .msglen = 165, + .result = { 0x75, 0x68, 0x14, 0xf8, 0x3c, 0x94, 0x2b, 0xe9, 0x6c, 0x49, 0xfc, 0x77, 0xa8, 0x6a, 0x5d, 0xf6, 0x4e, 0x45, 0xa0, 0x45, 0x2c, 0xfc, 0xec, 0xb1, 0xaf, 0xf5, 0x77, 0x6d, 0xbf, 0x96, 0x2b, 0x88 }, + }, + { + .msglen = 166, + .result = { 0x81, 0x1e, 0x33, 0x1c, 0xeb, 0xcf, 0x34, 0x58, 0x18, 0xa7, 0x2c, 0x60, 0x9, 0x36, 0x6e, 0xba, 0x46, 0x27, 0xee, 0x25, 0x60, 0xa9, 0x9f, 0x90, 0x4, 0x65, 0xa6, 0x92, 0x48, 0x4a, 0xf7, 0x1b }, + }, + { + .msglen = 167, + .result = { 0xdc, 0x3d, 0x6, 0x9e, 0x2c, 0x8c, 0x2d, 0x84, 0xf7, 0x97, 0xa, 0xeb, 0xe3, 0x68, 0xa7, 0x59, 0x3d, 0xa, 0xba, 0x6f, 0xfb, 0x11, 0x5a, 0xf8, 0x99, 0xae, 0x84, 0x1f, 0x43, 0xf8, 0xfd, 0xac }, + }, + { + .msglen = 168, + .result = { 0x4e, 0xd7, 0x72, 0x7d, 0xfe, 0x4d, 0x8a, 0x9a, 0xfa, 0x39, 0xb7, 0x74, 0x83, 0x61, 0xd5, 0xb6, 0xd1, 0x56, 0x88, 0xe7, 0x85, 0x15, 0xcf, 0x2d, 0x91, 0x73, 0xa4, 0xc9, 0xad, 0x76, 0x47, 0x2f }, + }, + { + .msglen = 169, + .result = { 0x33, 0x25, 0x94, 0xbc, 0xa4, 0xd, 0x39, 0x84, 0x4a, 0xe5, 0x30, 0x1f, 0x70, 0x41, 0xf0, 0xa7, 0x6d, 0x52, 0x3f, 0xa9, 0x17, 0x83, 0x46, 0xe, 0x26, 0x77, 0xe9, 0xfd, 0xe, 0x46, 0x21, 0xee }, + }, + { + .msglen = 170, + .result = { 0x84, 0xb8, 0x3c, 0x8d, 0x89, 0xd6, 0x55, 0x75, 0xbd, 0x5d, 0xcb, 0x76, 0xfe, 0x42, 0x98, 0xf9, 0xff, 0x8b, 0x4d, 0xe6, 0xe8, 0xd6, 0x1f, 0x37, 0xa6, 0xe0, 0xa8, 0x37, 0x28, 0xed, 0xf4, 0x38 }, + }, + { + .msglen = 171, + .result = { 0xf, 0x48, 0x6c, 0x1f, 0x99, 0x6d, 0x3c, 0x11, 0xd9, 0x7a, 0x33, 0xa, 0xdf, 0xb1, 0xa3, 0x59, 0x3f, 0xe3, 0xf0, 0x3, 0xab, 0x5e, 0x3f, 0x68, 0xe5, 0xa5, 0xd1, 0xbb, 0x8, 0x85, 0x50, 0x45 }, + }, + { + .msglen = 172, + .result = { 0x58, 0x25, 0xc1, 0x9e, 0x9d, 0x79, 0xa9, 0x71, 0xe7, 0xc5, 0x6, 0x8d, 0x23, 0x65, 0xf4, 0xbc, 0x9e, 0xa8, 0xab, 0xcc, 0x2f, 0x93, 0xac, 0x64, 0xb5, 0x6d, 0x28, 0x34, 0xe, 0x78, 0x9a, 0xfa }, + }, + { + .msglen = 173, + .result = { 0x10, 0xc6, 0xca, 0x3a, 0xc9, 0xe3, 0x82, 0x6e, 0x76, 0x5b, 0x8d, 0x42, 0x56, 0x4c, 0xc5, 0xf2, 0x2c, 0xaa, 0x95, 0x4, 0xc4, 0xef, 0x5f, 0xda, 0x10, 0xd3, 0x77, 0x9b, 0xc5, 0x95, 0x72, 0x14 }, + }, + { + .msglen = 174, + .result = { 0x7b, 0x64, 0xa, 0x83, 0xbf, 0x35, 0x85, 0xbf, 0xc2, 0xee, 0xdd, 0x95, 0xca, 0x5c, 0xa0, 0xee, 0xca, 0xa2, 0xb8, 0x33, 0xc1, 0x7d, 0xf3, 0x4d, 0x35, 0x2e, 0x27, 0xb8, 0x56, 0x5, 0x7a, 0x73 }, + }, + { + .msglen = 175, + .result = { 0xdb, 0x32, 0x29, 0x7c, 0xfd, 0xa5, 0x91, 0xae, 0x9b, 0xb0, 0xbd, 0xb4, 0x34, 0x4f, 0x60, 0x98, 0x65, 0x35, 0xe4, 0x60, 0xf8, 0x8b, 0x57, 0x47, 0x55, 0x14, 0xa4, 0x5e, 0xcc, 0xa6, 0xbd, 0xf4 }, + }, + { + .msglen = 176, + .result = { 0x7c, 0x6f, 0xd4, 0x3f, 0xd0, 0xa7, 0x7d, 0xd5, 0x34, 0xe0, 0x8d, 0x91, 0x5d, 0xbe, 0x92, 0xb8, 0x67, 0xbe, 0xf5, 0x80, 0xa4, 0xd5, 0x1b, 0x86, 0x12, 0xa7, 0x6, 0x43, 0x1c, 0x61, 0xa3, 0xd5 }, + }, + { + .msglen = 177, + .result = { 0x39, 0x4e, 0x86, 0xdf, 0xbd, 0x7f, 0x6a, 0x8d, 0xe7, 0x55, 0xce, 0x4b, 0x69, 0x90, 0xbc, 0x20, 0xf7, 0xd1, 0xba, 0x93, 0x2b, 0x57, 0x16, 0x5d, 0xc3, 0x16, 0xa, 0xf3, 0x62, 0x7, 0x66, 0xac }, + }, + { + .msglen = 178, + .result = { 0x5f, 0xfd, 0x40, 0x99, 0xa8, 0xdc, 0xe5, 0x2, 0x9e, 0x36, 0xf, 0x5d, 0x47, 0x53, 0xe4, 0x48, 0xcf, 0xd5, 0x5f, 0xd5, 0x29, 0x95, 0x5d, 0x92, 0x6d, 0x41, 0x22, 0x7d, 0x10, 0x8a, 0xc9, 0x88 }, + }, + { + .msglen = 179, + .result = { 0x58, 0x91, 0x6b, 0x40, 0x4d, 0x99, 0xf7, 0x78, 0xa5, 0xc7, 0x62, 0x49, 0x6c, 0x37, 0xd5, 0x90, 0x93, 0x3c, 0x59, 0x34, 0x36, 0xd1, 0x97, 0xcd, 0x85, 0x7d, 0x7a, 0x6d, 0x65, 0xce, 0x7f, 0xdb }, + }, + { + .msglen = 180, + .result = { 0x86, 0xc3, 0xa0, 0xa4, 0x46, 0x8a, 0xa8, 0x69, 0x8e, 0x6d, 0x5e, 0x79, 0x9f, 0xca, 0x9c, 0x2a, 0x94, 0xb0, 0xf8, 0x3f, 0xad, 0xa0, 0xfc, 0x50, 0x68, 0x39, 0x6c, 0xb5, 0xfc, 0x31, 0xaf, 0x74 }, + }, + { + .msglen = 181, + .result = { 0xce, 0x7, 0x9, 0x65, 0x72, 0xf3, 0x8c, 0x51, 0x6b, 0xf7, 0x2d, 0x46, 0xfc, 0xbc, 0xa6, 0xdd, 0x75, 0xe4, 0xd9, 0x54, 0x70, 0xcd, 0xa5, 0x5c, 0xa1, 0xb6, 0xd4, 0x3a, 0xe5, 0x4c, 0x18, 0x9e }, + }, + { + .msglen = 182, + .result = { 0x96, 0xbc, 0xcc, 0xbd, 0xb5, 0xf8, 0xd7, 0xef, 0xc7, 0x85, 0x44, 0x89, 0x6b, 0xd5, 0xbf, 0x78, 0xb7, 0x9d, 0xde, 0xf8, 0x72, 0xd1, 0xd9, 0xb3, 0xb0, 0xfd, 0x7f, 0x4e, 0x2a, 0xaa, 0x3d, 0x7c }, + }, + { + .msglen = 183, + .result = { 0x0, 0xdf, 0xb9, 0xd2, 0x99, 0x8e, 0x5c, 0xed, 0x85, 0x8b, 0x3d, 0x35, 0xdf, 0x35, 0x8c, 0x82, 0x3a, 0x20, 0x36, 0x60, 0x48, 0x7e, 0x9e, 0x8b, 0x60, 0xf9, 0x88, 0xb1, 0x8d, 0x5c, 0x41, 0xef }, + }, + { + .msglen = 184, + .result = { 0x99, 0xdf, 0xe5, 0xf6, 0xdf, 0xb3, 0x88, 0x88, 0x45, 0x34, 0x4a, 0x61, 0xc8, 0x87, 0x49, 0x20, 0xdf, 0xe0, 0x84, 0x5b, 0x35, 0xfe, 0x8c, 0xf8, 0x4a, 0x9c, 0xb1, 0x2d, 0x30, 0x5f, 0xfe, 0x3c }, + }, + { + .msglen = 185, + .result = { 0xfc, 0x53, 0x78, 0x1f, 0x4d, 0x43, 0xf4, 0xe9, 0xdc, 0x74, 0x8, 0xc3, 0xb5, 0xfc, 0x82, 0x88, 0x53, 0x25, 0xc, 0x81, 0x14, 0xa7, 0xff, 0xff, 0x9f, 0xda, 0xc8, 0x45, 0x38, 0x71, 0xdc, 0xd9 }, + }, + { + .msglen = 186, + .result = { 0xa5, 0x3f, 0x40, 0x24, 0x78, 0x12, 0xfc, 0xa7, 0x5b, 0x8a, 0xea, 0x5f, 0x83, 0xf9, 0x42, 0xc6, 0x21, 0xd, 0xa1, 0x46, 0x3, 0x3a, 0x62, 0xb9, 0x39, 0x39, 0xad, 0x6d, 0x70, 0x8e, 0xa2, 0x97 }, + }, + { + .msglen = 187, + .result = { 0x52, 0x23, 0x8a, 0xe, 0x32, 0xd5, 0x99, 0xd2, 0x7e, 0x77, 0x89, 0x70, 0x75, 0xdf, 0xf1, 0x90, 0x92, 0x1d, 0x14, 0xf7, 0xea, 0xa9, 0xdf, 0x5, 0x72, 0xf5, 0x8a, 0xd0, 0xdc, 0xee, 0x40, 0xd0 }, + }, + { + .msglen = 188, + .result = { 0x56, 0x86, 0xee, 0xbb, 0xde, 0xcc, 0x9d, 0xb2, 0x26, 0xa7, 0xb4, 0xef, 0x3d, 0x3f, 0x3e, 0x7d, 0xe3, 0x27, 0xea, 0x79, 0xd5, 0x82, 0x8f, 0x2f, 0x44, 0xa0, 0xe1, 0x4c, 0x67, 0xa6, 0x6b, 0x8f }, + }, + { + .msglen = 189, + .result = { 0xc0, 0x4c, 0xf2, 0x5c, 0x93, 0x4b, 0x36, 0xcb, 0xff, 0xc2, 0x15, 0x9, 0x77, 0x2f, 0xc1, 0xb0, 0x9, 0x98, 0x2b, 0x48, 0x3e, 0xcf, 0x6f, 0x4f, 0xe, 0x7d, 0xd9, 0xae, 0xdb, 0xeb, 0xd8, 0xe1 }, + }, + { + .msglen = 190, + .result = { 0x1f, 0xf1, 0x1c, 0x2c, 0x4e, 0xd0, 0x9c, 0x5e, 0x8e, 0xb4, 0x71, 0x88, 0xc8, 0xcc, 0xd8, 0x4b, 0x25, 0x6d, 0xad, 0xe7, 0x6d, 0x8d, 0x3b, 0x4d, 0x3a, 0xe9, 0xd, 0xa7, 0x69, 0xa8, 0x98, 0xde }, + }, + { + .msglen = 191, + .result = { 0x27, 0x4, 0x31, 0x8, 0x73, 0xf1, 0x5f, 0x15, 0x61, 0x2c, 0x62, 0x49, 0xa9, 0xe8, 0x11, 0xf3, 0xac, 0x54, 0x48, 0x98, 0x62, 0xf2, 0x7d, 0xd6, 0x12, 0xcf, 0x4, 0x1, 0x4e, 0xa9, 0x24, 0xc8 }, + }, + { + .msglen = 192, + .result = { 0xe4, 0x39, 0x59, 0x7e, 0x60, 0x5a, 0x45, 0x4b, 0x89, 0xa8, 0x97, 0x74, 0xfe, 0xb7, 0xeb, 0xd5, 0x6, 0xdb, 0xdc, 0x4d, 0x85, 0x3a, 0x38, 0x4c, 0x5e, 0x74, 0x86, 0xeb, 0xf0, 0xc4, 0x5, 0x32 }, + }, + { + .msglen = 193, + .result = { 0x9a, 0x14, 0xf6, 0x6f, 0xce, 0x82, 0xa0, 0xbb, 0xde, 0xb8, 0x24, 0x2b, 0xaf, 0xae, 0x18, 0xd4, 0xbb, 0x45, 0x9e, 0xe4, 0x87, 0x3b, 0x35, 0xca, 0xeb, 0x37, 0xd1, 0x52, 0x6, 0x6e, 0x84, 0x3b }, + }, + { + .msglen = 194, + .result = { 0x64, 0x9f, 0xab, 0x84, 0xaf, 0x83, 0xa6, 0xcb, 0x23, 0x0, 0xd5, 0x4c, 0xd3, 0x76, 0x4b, 0x57, 0x76, 0x70, 0xdb, 0xea, 0x3a, 0xcb, 0xb7, 0x9c, 0x16, 0x80, 0xbf, 0x66, 0x2b, 0x56, 0xc, 0x2c }, + }, + { + .msglen = 195, + .result = { 0xab, 0xa8, 0x11, 0x2b, 0x2, 0x99, 0xb0, 0x15, 0x36, 0x4d, 0x5b, 0x5d, 0x55, 0xc3, 0xa5, 0xbc, 0x70, 0x9, 0x36, 0xd9, 0x9f, 0xfe, 0x49, 0x3d, 0x5a, 0x2b, 0x8d, 0x69, 0xe2, 0x6, 0x1a, 0x6f }, + }, + { + .msglen = 196, + .result = { 0xd7, 0x6b, 0x15, 0x6c, 0xc1, 0x21, 0x84, 0x78, 0x7c, 0x5e, 0xbe, 0x16, 0x70, 0xe2, 0x83, 0x7f, 0x2c, 0x3, 0x5f, 0xb9, 0x2f, 0x17, 0x46, 0xb0, 0x5a, 0xaf, 0xac, 0x2b, 0x80, 0xcf, 0xa5, 0x9c }, + }, + { + .msglen = 197, + .result = { 0x15, 0x9c, 0x70, 0x75, 0x5a, 0x4e, 0xd2, 0x94, 0x7b, 0x6, 0xe8, 0xdd, 0x55, 0x21, 0xe9, 0x1b, 0x97, 0xe, 0x95, 0x5b, 0x18, 0xa7, 0x26, 0xc0, 0x0, 0xed, 0xe7, 0x55, 0xc8, 0x3d, 0xf3, 0xe7 }, + }, + { + .msglen = 198, + .result = { 0x2c, 0xdf, 0x2e, 0x88, 0xf, 0xee, 0xcf, 0x19, 0x1e, 0x72, 0x8b, 0x15, 0x7d, 0x18, 0xa1, 0xcf, 0x6, 0xa6, 0xc2, 0xec, 0x35, 0xe5, 0x2a, 0x0, 0x7f, 0x75, 0x9b, 0x63, 0x99, 0x9e, 0x2f, 0x66 }, + }, + { + .msglen = 199, + .result = { 0x28, 0xeb, 0xc7, 0x79, 0x5d, 0x7c, 0x29, 0xb9, 0x8a, 0xe8, 0x7b, 0xe4, 0x74, 0x3d, 0x3a, 0x74, 0xab, 0x2e, 0x67, 0xde, 0xe4, 0x28, 0x1b, 0xd0, 0xe3, 0x1b, 0xc9, 0xd0, 0xc0, 0x6c, 0xda, 0xba }, + }, + { + .msglen = 200, + .result = { 0x72, 0x17, 0x1e, 0xca, 0x67, 0xed, 0x83, 0xe9, 0x8d, 0x9b, 0x44, 0xe, 0xd4, 0x27, 0x2c, 0x6b, 0x7d, 0xe2, 0x22, 0x54, 0xf3, 0x72, 0xd1, 0x2, 0xaf, 0x47, 0x20, 0xc0, 0x47, 0x8a, 0x5, 0x9c }, + }, + { + .msglen = 201, + .result = { 0xb8, 0x2c, 0xea, 0xd9, 0xc4, 0x17, 0x66, 0xa6, 0x5a, 0xc1, 0xb8, 0x24, 0xf5, 0x5e, 0x1a, 0x2c, 0x85, 0xf0, 0xa3, 0xcd, 0xd3, 0x7e, 0xfa, 0x23, 0xd2, 0x90, 0x4f, 0xf3, 0x55, 0xfa, 0x17, 0x5c }, + }, + { + .msglen = 202, + .result = { 0x9d, 0x7f, 0x23, 0x8c, 0x92, 0xe5, 0x37, 0xb, 0xc7, 0x97, 0xa4, 0x68, 0xe5, 0xc, 0xd8, 0xfe, 0xb0, 0x4d, 0xc7, 0x79, 0x25, 0xd, 0xe6, 0xa6, 0xe6, 0x4, 0xc5, 0xfd, 0x2d, 0x25, 0x3f, 0xd2 }, + }, + { + .msglen = 203, + .result = { 0xdf, 0xdf, 0x13, 0xc0, 0x82, 0x73, 0x7b, 0xec, 0x2a, 0x4d, 0x9e, 0x62, 0xfc, 0x88, 0xa9, 0x47, 0xfd, 0x47, 0x59, 0xf2, 0x58, 0x5, 0xf9, 0x2e, 0xce, 0x5b, 0x1, 0xae, 0x37, 0x9e, 0xa8, 0x3f }, + }, + { + .msglen = 204, + .result = { 0x60, 0x10, 0x29, 0xc3, 0x82, 0x91, 0x8b, 0x74, 0xa5, 0x6a, 0x3f, 0x6a, 0x76, 0xaf, 0x50, 0x9e, 0xf1, 0x38, 0xf5, 0xd2, 0xdc, 0xe5, 0x5a, 0x3d, 0xa9, 0x8a, 0x56, 0xca, 0xeb, 0x57, 0x79, 0x5a }, + }, + { + .msglen = 205, + .result = { 0xd2, 0x71, 0x22, 0xe1, 0x91, 0x69, 0x5d, 0x9f, 0x6, 0xff, 0x51, 0xea, 0x7e, 0x8a, 0x5d, 0xb2, 0xae, 0x66, 0xf5, 0x22, 0x65, 0xa7, 0xfe, 0xf0, 0xce, 0xf5, 0x2c, 0xbf, 0x4e, 0x41, 0x19, 0x72 }, + }, + { + .msglen = 206, + .result = { 0x66, 0x41, 0x4d, 0xd9, 0xff, 0x1, 0x27, 0xda, 0xae, 0xee, 0x41, 0x34, 0x41, 0xd1, 0xb9, 0xac, 0x11, 0xf3, 0x5b, 0xc4, 0xa2, 0xd5, 0x3, 0x47, 0x87, 0xf4, 0x88, 0xee, 0x61, 0x22, 0x1, 0x6a }, + }, + { + .msglen = 207, + .result = { 0x59, 0xaf, 0xa5, 0x9a, 0xac, 0x1, 0x0, 0x73, 0x57, 0xa4, 0xdb, 0x22, 0x9, 0x3b, 0x3a, 0x66, 0x19, 0xd6, 0xe4, 0xf7, 0x1d, 0x2a, 0x37, 0x5f, 0x71, 0xc5, 0x54, 0x8e, 0xb, 0x73, 0xd5, 0x3c }, + }, + { + .msglen = 208, + .result = { 0xd1, 0xa7, 0x61, 0x34, 0xc5, 0x65, 0xb8, 0xa4, 0x8e, 0x3a, 0x9f, 0x5b, 0x11, 0x8b, 0x21, 0x5e, 0x7c, 0x9c, 0xfb, 0xd3, 0xe2, 0xe5, 0x92, 0x41, 0x6f, 0x4, 0x61, 0x30, 0x79, 0xf2, 0x8, 0xc4 }, + }, + { + .msglen = 209, + .result = { 0x84, 0x79, 0x2, 0x39, 0x2d, 0x2a, 0x11, 0xa5, 0xff, 0xa1, 0x3a, 0xfd, 0x70, 0x90, 0xb4, 0xa5, 0x85, 0xda, 0xd5, 0x4c, 0x8d, 0xaa, 0x97, 0x5e, 0x3b, 0x45, 0x89, 0xd0, 0xfd, 0x85, 0x57, 0xf3 }, + }, + { + .msglen = 210, + .result = { 0xc6, 0x3b, 0x4b, 0xbd, 0x70, 0x65, 0x2, 0x2f, 0xfc, 0xc2, 0x42, 0x4e, 0x77, 0xa0, 0xc8, 0x4d, 0x3d, 0x65, 0x4a, 0xb3, 0x47, 0xf5, 0x21, 0x39, 0xb0, 0x61, 0x8a, 0xae, 0x58, 0x18, 0x7e, 0xbe }, + }, + { + .msglen = 211, + .result = { 0x3c, 0x50, 0xdb, 0xa6, 0x45, 0x69, 0x8b, 0x58, 0x22, 0x1f, 0x3c, 0xa3, 0x1a, 0x79, 0x90, 0xef, 0xd4, 0x21, 0xf6, 0x9e, 0xfd, 0xe5, 0xb9, 0xb2, 0xbb, 0xef, 0x27, 0x36, 0x35, 0xd8, 0x6f, 0x69 }, + }, + { + .msglen = 212, + .result = { 0xd1, 0x5b, 0x4f, 0x10, 0xc6, 0x1, 0x2b, 0xe5, 0x4b, 0x8f, 0xba, 0x55, 0x36, 0x60, 0x26, 0xf3, 0x93, 0x40, 0xb7, 0xd, 0xbd, 0xf6, 0x80, 0x51, 0xbe, 0x52, 0x9, 0xdd, 0x78, 0x30, 0x47, 0xbd }, + }, + { + .msglen = 213, + .result = { 0xe6, 0x2e, 0x97, 0xbc, 0x93, 0xaf, 0x61, 0xb8, 0x40, 0x9d, 0x70, 0x90, 0xdc, 0x34, 0xb0, 0x7e, 0xad, 0x1d, 0x50, 0x55, 0x9e, 0x42, 0x92, 0x92, 0xaf, 0x54, 0x5c, 0x57, 0xa, 0x49, 0x39, 0xd }, + }, + { + .msglen = 214, + .result = { 0x6d, 0x72, 0xde, 0xd8, 0x72, 0x65, 0xc9, 0xaf, 0x36, 0x3b, 0x75, 0xf6, 0xf7, 0x71, 0x15, 0xa6, 0xad, 0x73, 0xa2, 0x9b, 0x1c, 0x86, 0xf3, 0xc1, 0xc1, 0x7a, 0x85, 0x87, 0x70, 0x44, 0x83, 0xe8 }, + }, + { + .msglen = 215, + .result = { 0x6c, 0xfb, 0xa2, 0xb9, 0xc1, 0xf0, 0xbf, 0xef, 0x33, 0x60, 0x55, 0x30, 0x5b, 0x2b, 0x4, 0x7b, 0xfb, 0x8f, 0xe0, 0x5d, 0x11, 0x90, 0x3c, 0x28, 0xcf, 0xd4, 0x5, 0x70, 0x88, 0x1a, 0x53, 0xa }, + }, + { + .msglen = 216, + .result = { 0xe6, 0x2a, 0x80, 0x77, 0xb, 0x8d, 0xc8, 0x79, 0x72, 0x32, 0xf9, 0xd, 0x41, 0xcc, 0x6e, 0x77, 0xe5, 0x5f, 0x22, 0xd2, 0xdb, 0x1, 0xf9, 0x96, 0xce, 0x13, 0x95, 0x51, 0x6, 0x95, 0x51, 0x24 }, + }, + { + .msglen = 217, + .result = { 0xf1, 0x79, 0x81, 0xb2, 0x3b, 0xb7, 0xc1, 0x12, 0x24, 0x6e, 0x97, 0xed, 0xe4, 0x87, 0xf4, 0xcf, 0x62, 0xf8, 0xb8, 0xa9, 0xb8, 0x9d, 0xf4, 0x5d, 0x17, 0xc7, 0x27, 0xe7, 0x84, 0x7, 0xb9, 0x56 }, + }, + { + .msglen = 218, + .result = { 0x6c, 0xe2, 0x55, 0x53, 0x36, 0x41, 0xe2, 0x99, 0xac, 0xb2, 0x67, 0xc1, 0xfe, 0x63, 0xb4, 0x93, 0x26, 0x50, 0x2e, 0xe, 0xac, 0xf7, 0x66, 0x20, 0x6, 0xb7, 0xb9, 0x98, 0x20, 0x17, 0xfa, 0x2d }, + }, + { + .msglen = 219, + .result = { 0xef, 0x47, 0xb1, 0x44, 0x60, 0xf2, 0x1a, 0xa5, 0x99, 0x8d, 0xd8, 0x7c, 0x80, 0x22, 0x2a, 0xac, 0x9, 0x27, 0xf, 0xc9, 0xb8, 0xa8, 0xfb, 0xec, 0x41, 0x23, 0x2b, 0x9b, 0x20, 0xed, 0xef, 0x5e }, + }, + { + .msglen = 220, + .result = { 0xea, 0x10, 0xab, 0xd, 0x8a, 0x2f, 0xff, 0xe2, 0x21, 0xb7, 0x8b, 0xff, 0x13, 0xa0, 0xa9, 0x4c, 0x78, 0x85, 0x35, 0xdf, 0x8c, 0xb8, 0x82, 0x57, 0x98, 0x5e, 0xc8, 0xe5, 0x95, 0x43, 0x14, 0x7e }, + }, + { + .msglen = 221, + .result = { 0xb6, 0x3b, 0x58, 0x81, 0xab, 0x62, 0xa9, 0xf3, 0x19, 0x1f, 0x3c, 0xe1, 0x21, 0x2f, 0x2, 0xc9, 0xdb, 0x8d, 0xd4, 0x7f, 0x38, 0x11, 0x1b, 0x18, 0x5c, 0xb, 0xa3, 0xa8, 0x38, 0xe4, 0xc4, 0x55 }, + }, + { + .msglen = 222, + .result = { 0xb, 0xc3, 0x3f, 0xaa, 0x9c, 0xff, 0x53, 0xb8, 0xe1, 0xa6, 0xd3, 0x43, 0x8e, 0xa6, 0x48, 0x7b, 0x5b, 0x4, 0x31, 0xc1, 0xad, 0x9d, 0x8, 0x39, 0xac, 0xee, 0x1, 0x87, 0xd3, 0x91, 0x7e, 0x7b }, + }, + { + .msglen = 223, + .result = { 0xb3, 0xd0, 0x23, 0x54, 0xc2, 0x1d, 0xd6, 0x23, 0x70, 0xe0, 0xc2, 0x61, 0x52, 0xa2, 0xbc, 0x3b, 0x6, 0x11, 0x80, 0xb2, 0xfa, 0x17, 0x26, 0x74, 0x90, 0x61, 0x46, 0x35, 0x66, 0x1a, 0xe9, 0x51 }, + }, + { + .msglen = 224, + .result = { 0x0, 0xab, 0x82, 0xf2, 0xaf, 0x44, 0x95, 0x58, 0x31, 0x2a, 0x20, 0x4c, 0x2c, 0xdc, 0x80, 0xfd, 0x71, 0x7a, 0xf4, 0x34, 0xe6, 0x7e, 0xe2, 0xff, 0x6e, 0xc2, 0xf, 0x82, 0x65, 0x1e, 0x6d, 0xe6 }, + }, + { + .msglen = 225, + .result = { 0x6, 0x67, 0x32, 0x34, 0x96, 0xb5, 0x7a, 0x86, 0xda, 0x89, 0xd6, 0x9b, 0x1e, 0x23, 0x40, 0xfb, 0xd, 0xdf, 0xce, 0xdf, 0x83, 0x14, 0xb3, 0xe2, 0x2c, 0xd, 0x70, 0x18, 0xde, 0x87, 0xc6, 0x65 }, + }, + { + .msglen = 226, + .result = { 0x7b, 0x2a, 0x1c, 0xc5, 0xc6, 0x2e, 0xb4, 0xed, 0x19, 0x75, 0x50, 0x8d, 0xe5, 0x74, 0xe9, 0x31, 0x32, 0x88, 0x36, 0x6a, 0x61, 0x10, 0x6c, 0xad, 0x25, 0xb5, 0x72, 0x8a, 0x4a, 0x9, 0x18, 0x7c }, + }, + { + .msglen = 227, + .result = { 0xa6, 0x34, 0x75, 0xcb, 0x1a, 0xbb, 0x6d, 0x4a, 0xfb, 0x81, 0x67, 0xd1, 0x46, 0xac, 0x59, 0xd, 0x86, 0x5b, 0xd5, 0x71, 0xb6, 0x52, 0xd2, 0xca, 0xdb, 0x31, 0x45, 0x97, 0x61, 0x5f, 0x77, 0x62 }, + }, + { + .msglen = 228, + .result = { 0x4, 0x7d, 0x3a, 0x50, 0x35, 0x1f, 0x7e, 0x94, 0x18, 0xe0, 0xeb, 0xc, 0xe7, 0x27, 0x85, 0x54, 0x4c, 0x33, 0x51, 0xf5, 0x51, 0x2e, 0x40, 0x88, 0x67, 0x36, 0x6b, 0x5d, 0x7c, 0xb1, 0x6, 0xc7 }, + }, + { + .msglen = 229, + .result = { 0x59, 0x7f, 0x6c, 0x70, 0x8c, 0x79, 0xf8, 0x9f, 0xb2, 0xb1, 0x5e, 0xc4, 0xe9, 0x26, 0x8c, 0xae, 0xc0, 0xfc, 0x48, 0x18, 0xe0, 0xa5, 0xab, 0xb4, 0x68, 0x23, 0x2c, 0x11, 0xf9, 0x1e, 0x11, 0x62 }, + }, + { + .msglen = 230, + .result = { 0x16, 0xe9, 0x5, 0x1c, 0xfd, 0x35, 0x95, 0xda, 0xad, 0xb4, 0xbd, 0xdc, 0x7b, 0xdb, 0xc3, 0x19, 0x56, 0x88, 0x42, 0x38, 0x58, 0x2f, 0x63, 0x5b, 0x73, 0x6e, 0xfd, 0x68, 0x24, 0x27, 0xce, 0xa3 }, + }, + { + .msglen = 231, + .result = { 0x7b, 0xba, 0x9e, 0x1a, 0xdb, 0xbb, 0x9b, 0x17, 0xe, 0x7, 0xbc, 0x8b, 0xbd, 0xdf, 0xab, 0x8b, 0xe7, 0xea, 0x39, 0xba, 0x20, 0xce, 0xd5, 0x83, 0x89, 0xe3, 0x27, 0xa3, 0xbe, 0x25, 0xb0, 0x4 }, + }, + { + .msglen = 232, + .result = { 0x11, 0x4a, 0xc5, 0xc9, 0x7f, 0x98, 0xeb, 0x92, 0xd3, 0x76, 0x4f, 0xc0, 0xd8, 0x8c, 0xfd, 0xe7, 0xf3, 0x1d, 0xfd, 0xbd, 0x36, 0x88, 0x48, 0xd6, 0xc7, 0x8c, 0x9f, 0x2c, 0xb2, 0x72, 0x14, 0xb9 }, + }, + { + .msglen = 233, + .result = { 0xb0, 0x67, 0xf9, 0x62, 0xb9, 0xa1, 0xc0, 0xe5, 0xb, 0x22, 0x4b, 0xe7, 0x84, 0x6b, 0x8c, 0xa9, 0xa, 0xfa, 0xd7, 0xe7, 0x5b, 0x7b, 0xc, 0xe0, 0x6e, 0x47, 0x24, 0xf8, 0xc7, 0xf5, 0x6b, 0x14 }, + }, + { + .msglen = 234, + .result = { 0x77, 0x25, 0x61, 0xfd, 0xc8, 0x39, 0x3a, 0x72, 0x74, 0x9, 0x8b, 0x49, 0x7d, 0xa3, 0x42, 0x66, 0xb, 0x5a, 0xa5, 0x53, 0x70, 0xbe, 0x69, 0x96, 0x69, 0xbb, 0x7a, 0x8a, 0x12, 0xa, 0x7, 0x14 }, + }, + { + .msglen = 235, + .result = { 0x10, 0x16, 0xbb, 0x95, 0x96, 0xb3, 0x87, 0xf6, 0x12, 0x5d, 0xcc, 0x9, 0xd3, 0xcd, 0xf8, 0x44, 0x2, 0x62, 0x96, 0xde, 0x7c, 0xa2, 0x66, 0x12, 0x4e, 0x86, 0x32, 0x11, 0xf1, 0x18, 0x38, 0x79 }, + }, + { + .msglen = 236, + .result = { 0x42, 0x91, 0x46, 0x5c, 0xa6, 0xae, 0x5c, 0x68, 0xc8, 0xb9, 0xa8, 0x38, 0xea, 0x18, 0x71, 0x63, 0xae, 0x9c, 0xc6, 0xd9, 0x22, 0xe4, 0xfa, 0x85, 0x9c, 0x94, 0xd4, 0xb8, 0xab, 0x98, 0xe, 0xf0 }, + }, + { + .msglen = 237, + .result = { 0x2b, 0x6b, 0xc, 0x10, 0x13, 0x80, 0x8e, 0xc3, 0x8a, 0xcd, 0xe7, 0xf0, 0x21, 0x1c, 0x1c, 0x7e, 0x61, 0x5e, 0x5, 0x37, 0xde, 0x5e, 0x9f, 0x2f, 0x8a, 0xe4, 0x31, 0x0, 0x63, 0x90, 0xc8, 0xa3 }, + }, + { + .msglen = 238, + .result = { 0xf5, 0x12, 0xb6, 0x60, 0xfe, 0x6c, 0xe5, 0xd2, 0x8b, 0x2e, 0xc9, 0x37, 0x66, 0xf8, 0xd5, 0x52, 0x28, 0x76, 0x35, 0xba, 0x4b, 0xf0, 0x2c, 0xbd, 0x47, 0x14, 0x3, 0x6b, 0x47, 0x58, 0xf8, 0x16 }, + }, + { + .msglen = 239, + .result = { 0xfa, 0x6c, 0x94, 0x22, 0xb, 0x98, 0x3b, 0x74, 0x18, 0xfa, 0xb8, 0xda, 0x55, 0x6c, 0xa2, 0xf5, 0x5b, 0xe4, 0x8, 0x99, 0xfa, 0xf7, 0xb4, 0x57, 0xfa, 0x7d, 0x8a, 0xc, 0x6a, 0xe1, 0xca, 0xc2 }, + }, + { + .msglen = 240, + .result = { 0x2b, 0x59, 0x71, 0x1e, 0x37, 0x8b, 0x24, 0x39, 0x98, 0x50, 0x79, 0x3b, 0xde, 0x2c, 0xce, 0xc6, 0xd, 0xf7, 0x53, 0xb6, 0x12, 0x2d, 0x70, 0x53, 0xdf, 0xbe, 0x57, 0x56, 0x87, 0xee, 0x9f, 0x12 }, + }, + { + .msglen = 241, + .result = { 0x38, 0xf6, 0x60, 0x9d, 0x7, 0x23, 0x85, 0xcc, 0x8e, 0x4a, 0xe5, 0xf1, 0xaf, 0x31, 0x9b, 0x97, 0xda, 0x34, 0x80, 0x6c, 0x23, 0x79, 0x69, 0x33, 0x87, 0xa6, 0x2d, 0x8d, 0xd4, 0x8e, 0x66, 0x2e }, + }, + { + .msglen = 242, + .result = { 0x88, 0x5d, 0xc8, 0x2, 0xf4, 0x76, 0xe4, 0x4e, 0xae, 0xcc, 0x9, 0x49, 0xc, 0x56, 0x7, 0x22, 0xd, 0x8f, 0xb0, 0xb4, 0x68, 0x1d, 0xb5, 0xaf, 0x89, 0xb0, 0xab, 0x3b, 0x37, 0x39, 0x88, 0x37 }, + }, + { + .msglen = 243, + .result = { 0x10, 0xb1, 0x44, 0x4a, 0xe2, 0xfc, 0x17, 0xc0, 0x7d, 0x39, 0x62, 0xb3, 0x45, 0x9b, 0xbe, 0xf8, 0x79, 0x2e, 0xe2, 0xfd, 0x59, 0x8e, 0xb5, 0x6c, 0x1d, 0xf5, 0x8b, 0x50, 0xad, 0x28, 0x93, 0xf }, + }, + { + .msglen = 244, + .result = { 0xf6, 0x5d, 0xce, 0x54, 0x13, 0x2, 0x3f, 0x5b, 0x4e, 0x72, 0xc8, 0xe1, 0x42, 0x83, 0xe7, 0x52, 0xde, 0x6f, 0xe6, 0x93, 0x15, 0xab, 0xe8, 0x1f, 0x53, 0x1d, 0xc5, 0xcd, 0xf3, 0x98, 0xf0, 0x9e }, + }, + { + .msglen = 245, + .result = { 0x56, 0xf1, 0x6f, 0xe1, 0xd7, 0x0, 0x33, 0x65, 0xe1, 0x61, 0x79, 0x15, 0x78, 0x5f, 0x98, 0x32, 0x4d, 0x11, 0x99, 0xf1, 0x14, 0xf2, 0xdc, 0x10, 0x7, 0x0, 0xaf, 0xea, 0x4, 0xd, 0x99, 0x33 }, + }, + { + .msglen = 246, + .result = { 0xfc, 0xcc, 0x27, 0x84, 0xc0, 0xbf, 0xf4, 0x52, 0xf2, 0x39, 0x1f, 0xb5, 0x5e, 0x8a, 0x17, 0xd2, 0x53, 0xff, 0x3c, 0x9b, 0x53, 0x25, 0x14, 0xed, 0xca, 0x1c, 0x88, 0xa9, 0x86, 0x5c, 0x50, 0xfe }, + }, + { + .msglen = 247, + .result = { 0xf3, 0x9f, 0x18, 0x4a, 0x35, 0xf4, 0xb3, 0x6, 0xac, 0xc4, 0x8c, 0x8e, 0xe7, 0x87, 0x0, 0x11, 0x63, 0xea, 0xba, 0x6a, 0x3f, 0x12, 0xa1, 0x4b, 0xf5, 0x6d, 0xbd, 0xeb, 0xcf, 0xfe, 0x6, 0x6d }, + }, + { + .msglen = 248, + .result = { 0x78, 0x69, 0xfc, 0x51, 0x5e, 0x48, 0xda, 0xb3, 0x81, 0xcb, 0x88, 0xf1, 0xc, 0x7, 0xeb, 0x16, 0x18, 0x2e, 0x6d, 0x85, 0x9d, 0xc0, 0x80, 0xea, 0xab, 0x39, 0xd3, 0x6a, 0xa8, 0x10, 0xe3, 0x26 }, + }, + { + .msglen = 249, + .result = { 0xee, 0xfb, 0xd, 0x72, 0x20, 0x48, 0x71, 0x10, 0x46, 0xc2, 0xb0, 0x5c, 0x11, 0xcf, 0x82, 0x2e, 0x6e, 0x3e, 0x3f, 0x16, 0xfa, 0x71, 0x80, 0x5f, 0x51, 0x50, 0x3e, 0xa2, 0x5d, 0xa1, 0x66, 0xbe }, + }, + { + .msglen = 250, + .result = { 0x72, 0x9c, 0x3, 0xe9, 0x25, 0xda, 0xaf, 0x7b, 0x40, 0x10, 0xe2, 0x85, 0xe0, 0x5b, 0xce, 0x55, 0x72, 0x1f, 0xfa, 0x54, 0x1c, 0x96, 0x48, 0xb, 0x55, 0x26, 0x53, 0x7d, 0xa9, 0xc5, 0x27, 0xd0 }, + }, + { + .msglen = 251, + .result = { 0x6f, 0x40, 0xd5, 0x72, 0x3b, 0x1f, 0x99, 0x9e, 0x7, 0x57, 0xbb, 0x57, 0x6c, 0x7e, 0x47, 0xb2, 0x76, 0x37, 0x5e, 0x64, 0x21, 0x51, 0x3c, 0xe8, 0x16, 0xda, 0x5f, 0x9f, 0xc9, 0x5b, 0xc3, 0x70 }, + }, + { + .msglen = 252, + .result = { 0x77, 0x3b, 0x47, 0x74, 0x0, 0xfd, 0x74, 0x95, 0xe, 0x59, 0xf6, 0xf, 0xcf, 0x9a, 0xb3, 0xbc, 0x9f, 0xd9, 0x3c, 0x3a, 0x30, 0x1c, 0x1f, 0x4d, 0x53, 0xbe, 0xce, 0x4c, 0xa1, 0x8b, 0xc1, 0x22 }, + }, + { + .msglen = 253, + .result = { 0xd0, 0xbe, 0x9, 0xb3, 0xa9, 0xa4, 0xb2, 0x46, 0x99, 0x40, 0x40, 0x6b, 0x52, 0x54, 0x3b, 0xfe, 0x94, 0x37, 0xf9, 0xc, 0xc2, 0xc2, 0x66, 0x3, 0xa5, 0x8c, 0x42, 0xae, 0x9d, 0xf8, 0x47, 0x87 }, + }, + { + .msglen = 254, + .result = { 0x85, 0x78, 0x21, 0xf4, 0xa, 0xee, 0xa3, 0x59, 0xe0, 0xb2, 0xd7, 0x7, 0x34, 0x5e, 0x57, 0xdc, 0xdd, 0x9a, 0xfa, 0x2c, 0xfd, 0xb6, 0xee, 0xa9, 0x14, 0xc0, 0x17, 0x86, 0xbf, 0x7b, 0xfe, 0x4b }, + }, + { + .msglen = 255, + .result = { 0x59, 0x52, 0x50, 0x4, 0xb6, 0x28, 0xf9, 0x28, 0x7f, 0x6c, 0x37, 0xba, 0xfb, 0xb2, 0x58, 0xe7, 0xa, 0xac, 0x6c, 0x4a, 0xef, 0x66, 0x6, 0x7b, 0x1, 0x1f, 0x4c, 0xa4, 0xe5, 0xe5, 0x29, 0x5d }, + }, + { + .msglen = 256, + .result = { 0x52, 0x1a, 0x14, 0xc3, 0xb4, 0x85, 0xf0, 0xb5, 0x82, 0xe9, 0x40, 0xc2, 0xc, 0x6d, 0x59, 0x64, 0x86, 0x7d, 0xa, 0x3b, 0x7f, 0x85, 0x78, 0xea, 0xea, 0x66, 0x48, 0xfa, 0x4a, 0xde, 0x5c, 0xd3 }, + }, +}; diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c index 932f77f7ee..6a7629d80c 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_ds.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_ds.c @@ -184,7 +184,7 @@ TEST_CASE("Digital Signature start HMAC key out of range", "[hw_crypto] [ds]") esp_ds_context_t *ctx; const char *message = "test"; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY5 + 1, &ctx)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY_MAX, &ctx)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_start_sign(message, &ds_data, HMAC_KEY0 - 1, &ctx)); } @@ -255,7 +255,7 @@ TEST_CASE("Digital Signature Blocking HMAC key out of range", "[hw_crypto] [ds]" const char *message = "test"; uint8_t signature_data [128 * 4]; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY5 + 1, signature_data)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY_MAX, signature_data)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_ds_sign(message, &ds_data, HMAC_KEY0 - 1, signature_data)); } diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c index 8f8ccf39ef..dc18cec22a 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_hmac.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,22 +9,12 @@ #include "esp_efuse_table.h" #include "esp_log.h" #include "esp_hmac.h" +#include "hmac_test_cases.h" #if CONFIG_ESP_SECURITY_ENABLE_FPGA_TESTS -/* Allow testing varying message lengths (truncating the same message) - for various results */ -typedef struct { - int msglen; - uint8_t result[32]; -} hmac_result; - static void setup_keyblock(esp_efuse_block_t key_block, esp_efuse_purpose_t purpose) { - const uint8_t key_data[32] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32 - }; esp_err_t status = esp_efuse_write_key(key_block, purpose, key_data, sizeof(key_data)); if (status == ESP_OK) { @@ -42,16 +32,6 @@ TEST_CASE("HMAC 'downstream' JTAG Enable mode", "[hw_crypto]") setup_keyblock(EFUSE_BLK_KEY4, ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG); - // Results calculated with Python: - // - // import hmac, hashlib, binascii - // key = b"".join([chr(x).encode() for x in range(1,33)]) - // ", ".join("0x%x" % x for x in hmac.HMAC(key, b"\x00" * 32, hashlib.sha256).digest() ) - const uint8_t token_data[32] = { - 0xb2, 0xa4, 0x9b, 0x1c, 0xce, 0x1b, 0xe9, 0x22, 0xbb, 0x7e, 0x43, 0x12, 0x77, 0x41, 0x3e, 0x3e, - 0x8e, 0x6c, 0x3e, 0x8e, 0x6e, 0x17, 0x62, 0x5c, 0x50, 0xac, 0x66, 0xa9, 0xa8, 0x57, 0x94, 0x9b - }; - TEST_ASSERT_MESSAGE(ESP_OK == esp_efuse_batch_write_begin(), "Error programming security efuse.\n"); @@ -80,135 +60,6 @@ TEST_CASE("HMAC 'upstream' MAC generation with zeroes", "[hw_crypto]") setup_keyblock(EFUSE_BLK_KEY5, ESP_EFUSE_KEY_PURPOSE_HMAC_UP); const uint8_t zeroes[128] = { }; - // Produce the HMAC of various numbers of zeroes - // - // Results calculated with Python: - // - // import hmac, hashlib, binascii - // key = b"".join([chr(x).encode() for x in range(1,33)]) - // ", ".join("0x%x" % x for x in hmac.HMAC(key, b"\x00" * 128, hashlib.sha256).digest() ) - - static const hmac_result zero_results[] = { - { - .msglen = 64, - .result = { - 0x4f, 0x34, 0x31, 0x8a, 0x45, 0x74, 0x4d, 0x71, 0x53, 0xb7, 0x18, 0xf4, 0x78, 0x1c, 0xbb, 0x10, - 0x19, 0x60, 0xba, 0x9c, 0x8c, 0xe2, 0x3b, 0xc1, 0x1d, 0x79, 0xb6, 0x3c, 0xae, 0x0f, 0x30, 0xc8, - }, - }, - { - .msglen = 128, - .result = { - 0x40, 0xd5, 0xb9, 0xe6, 0x25, 0x8f, 0x3c, 0xd0, 0x3f, 0xb9, 0x6c, 0xa3, 0xa7, 0x2b, 0x84, 0xe3, - 0x1d, 0x4b, 0x4e, 0x65, 0xf8, 0x7b, 0x3e, 0x3, 0x26, 0x2, 0xcd, 0x49, 0x73, 0xf0, 0xac, 0x25 - }, - }, - { - .msglen = 48, - .result = { - 0x84, 0x4e, 0x45, 0xcd, 0xb3, 0x8f, 0xf8, 0x96, 0xe7, 0xe7, 0x80, 0x48, 0x31, 0x89, 0x79, 0xa7, - 0x5d, 0x80, 0xd1, 0xbf, 0x3, 0xca, 0x9b, 0x78, 0x4f, 0x3b, 0x42, 0x80, 0xb9, 0x6, 0x19, 0x7d - }, - }, - { - .msglen = 32, - .result = { - 0xb2, 0xa4, 0x9b, 0x1c, 0xce, 0x1b, 0xe9, 0x22, 0xbb, 0x7e, 0x43, 0x12, 0x77, 0x41, 0x3e, 0x3e, - 0x8e, 0x6c, 0x3e, 0x8e, 0x6e, 0x17, 0x62, 0x5c, 0x50, 0xac, 0x66, 0xa9, 0xa8, 0x57, 0x94, 0x9b - }, - }, - { - .msglen = 33, - .result = { - 0x98, 0xd7, 0x44, 0xab, 0xbb, 0x89, 0xca, 0x51, 0x3e, 0x2, 0x8e, 0x5c, 0xa1, 0x61, 0x25, 0xd2, - 0x93, 0x3e, 0x85, 0x4b, 0x9f, 0x73, 0x63, 0x57, 0xab, 0xbc, 0x7a, 0x66, 0x51, 0xd2, 0x39, 0xb9 - }, - }, - { - .msglen = 1, - .result = { - 0xab, 0x7d, 0x90, 0x85, 0x8, 0xb3, 0xf3, 0x7, 0x45, 0x6c, 0x85, 0x40, 0xbf, 0xcd, 0xb4, 0x52, - 0x54, 0x2c, 0x2, 0xe0, 0x53, 0xdc, 0x16, 0x12, 0x90, 0xf1, 0x5b, 0x5b, 0xf8, 0x71, 0x65, 0x44 - }, - }, - { - .msglen = 127, - .result = { - 0x19, 0x38, 0x88, 0xb, 0x30, 0xac, 0xef, 0x4e, 0xd, 0x38, 0x7d, 0x7e, 0x42, 0x5c, 0x90, 0xc4, - 0x9b, 0xc1, 0xbd, 0x9e, 0x30, 0xc6, 0x16, 0x1f, 0x36, 0x7e, 0x46, 0xcd, 0xb2, 0xd7, 0x37, 0x70 - }, - }, - { - .msglen = 126, - .result = { - 0xf, 0xa4, 0xb5, 0x16, 0x3b, 0xf5, 0xe8, 0x6e, 0xaf, 0x38, 0xc6, 0x27, 0x9a, 0xc, 0x88, 0xaf, - 0xb5, 0x10, 0x75, 0x3d, 0x4a, 0x85, 0x10, 0x4e, 0x60, 0xe4, 0x61, 0x30, 0x8, 0x46, 0x98, 0xc7 - }, - }, - { - .msglen = 125, - .result = { - 0x3f, 0x1a, 0x90, 0x47, 0xeb, 0x44, 0xcc, 0x27, 0xfa, 0x22, 0xb3, 0x5d, 0xa2, 0x22, 0x30, 0x54, - 0x61, 0x15, 0xe5, 0x54, 0x55, 0x13, 0x7c, 0xb8, 0xc7, 0xc0, 0x28, 0xa4, 0xd4, 0xbc, 0x1c, 0xad - }, - }, - { - .msglen = 124, - .result = { - 0x14, 0xdf, 0x13, 0xa2, 0xe4, 0xfd, 0xa3, 0xa8, 0x9b, 0x71, 0x78, 0x2e, 0x24, 0xb6, 0x61, 0x13, - 0xff, 0x6c, 0x6d, 0xe8, 0x95, 0xf9, 0x68, 0xb4, 0x92, 0x7c, 0xc9, 0xf7, 0x5e, 0x14, 0x44, 0x8 - }, - }, - { - .msglen = 123, - .result = { - 0x6, 0xd0, 0xe, 0xbe, 0x90, 0x3b, 0x52, 0x85, 0xd4, 0x25, 0x7e, 0xbe, 0x71, 0x92, 0xd0, 0xf0, - 0x6a, 0x99, 0x93, 0x64, 0xe6, 0x9a, 0x27, 0xfa, 0x57, 0xcb, 0x6f, 0x9f, 0x44, 0x30, 0xf5, 0xcc - }, - }, - { - .msglen = 122, - .result = { - 0x76, 0x7a, 0x86, 0x80, 0x1e, 0x54, 0x11, 0xef, 0x2f, 0x4e, 0xf9, 0x7, 0xda, 0x42, 0xd6, 0x71, - 0x3b, 0xb9, 0x92, 0xfb, 0x8, 0x1d, 0xf2, 0x41, 0x96, 0x5f, 0x28, 0x10, 0x20, 0x1a, 0x7b, 0xef - }, - }, - { - .msglen = 121, - .result = { - 0x59, 0xb0, 0xdb, 0x73, 0xee, 0x43, 0xb9, 0x63, 0x82, 0x36, 0x11, 0x5a, 0x6b, 0x46, 0x8, 0xbb, - 0x18, 0xdd, 0x74, 0x82, 0x8f, 0xf3, 0xb3, 0x5d, 0xd1, 0xad, 0xe, 0x8e, 0x77, 0x90, 0xde, 0x70 - }, - }, - { - .msglen = 120, - .result = { - 0xe0, 0x24, 0xc5, 0x2, 0x6b, 0xe, 0xe3, 0x9b, 0x1, 0x95, 0x6, 0x21, 0xc6, 0xad, 0x0, 0x72, - 0x36, 0x9, 0x75, 0xcd, 0x10, 0xa3, 0xf, 0xa2, 0xe5, 0xcd, 0x27, 0x6b, 0x95, 0x23, 0x6, 0x72 - }, - }, - { - .msglen = 119, - .result = { - 0x70, 0x4, 0x2c, 0x78, 0xc5, 0x40, 0x3f, 0xfb, 0x71, 0xfb, 0x3e, 0xbd, 0x9f, 0x4e, 0x2f, 0xf8, - 0x3c, 0x9b, 0xd1, 0xad, 0xee, 0xc8, 0x4f, 0x40, 0xec, 0x29, 0x5a, 0xb9, 0x9a, 0xa7, 0xe9, 0x51 - }, - }, - { - .msglen = 118, - .result = { - 0x1a, 0x4b, 0x49, 0xd3, 0x6, 0x1, 0x75, 0xca, 0x3, 0x12, 0x2e, 0x9a, 0xd4, 0xda, 0xb8, 0x23, - 0xf9, 0xa0, 0xa6, 0xbc, 0xbc, 0xcc, 0xa1, 0x6f, 0xd8, 0x3b, 0x2a, 0x37, 0xd3, 0xc3, 0xca, 0x5f - }, - }, - { - .msglen = 0, - .result = { - 0x46, 0x24, 0x76, 0xa8, 0x97, 0xdd, 0xfd, 0xbd, 0x40, 0xd1, 0x42, 0xe, 0x8, 0xa5, 0xbc, 0xfe, - 0xeb, 0x25, 0xc3, 0xe2, 0xad, 0xe6, 0xa0, 0xa9, 0x8, 0x3b, 0x32, 0x7b, 0x9e, 0xf9, 0xfc, 0xa1 - }, - }, - }; const size_t num_zero_results = sizeof(zero_results) / sizeof(hmac_result); @@ -224,1047 +75,6 @@ TEST_CASE("HMAC 'upstream' MAC generation from data", "[hw_crypto]") setup_keyblock(EFUSE_BLK_KEY5, ESP_EFUSE_KEY_PURPOSE_HMAC_UP); - // 257 characters of pseudo-Latin from lipsum.com (not Copyright) - const char *message = "Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. Sunt architecto iure aspernatur soluta ut recusandae. Ut quibusdam occaecati ut qui sit dignissimos eaque.."; - - // 256 different HMAC results for different length portions of the above. Generated as follows: - // - // import hmac, hashlib, binascii - // key = b"".join([chr(x).encode() for x in range(1,33)]) - // assert len(message) == 257 - // for l in range(1, len(message)): - // print(" // %d" % l) - // mac = hmac.HMAC(key, message[:l], hashlib.sha256).digest() - // print("{ " + ", ".join("0x%x" % ord(x) for x in mac) + " }, ") - // - // (Note: the zero length case is handled in the other unit test.) - static const hmac_result results[] = { - { - .msglen = 1, - .result = { 0xf2, 0x1a, 0x8e, 0x60, 0xea, 0xd9, 0x36, 0xd1, 0xc2, 0x74, 0x24, 0xae, 0x6, 0x2d, 0x81, 0x28, 0x16, 0xa6, 0x33, 0xca, 0x9d, 0x55, 0xc0, 0x82, 0x28, 0xd9, 0x79, 0x8f, 0x5a, 0xaa, 0xfd, 0x25 }, - }, - { - .msglen = 2, - .result = { 0x1f, 0x6, 0xfc, 0x68, 0x5c, 0xa8, 0xbf, 0x3e, 0x57, 0x6d, 0x2, 0x56, 0x4a, 0x35, 0x31, 0xbd, 0xeb, 0xf4, 0x5d, 0xd5, 0x71, 0xf9, 0x65, 0x7d, 0xa9, 0x32, 0x1d, 0x68, 0x21, 0xd2, 0x9b, 0xaf }, - }, - { - .msglen = 3, - .result = { 0x2b, 0xb4, 0x4e, 0x80, 0x6e, 0xd2, 0xcb, 0xee, 0x4b, 0x40, 0xfb, 0xf9, 0x61, 0x76, 0x78, 0x2a, 0xb1, 0xc8, 0xea, 0xa3, 0x3e, 0xf7, 0x24, 0x86, 0xa0, 0x73, 0xda, 0xe, 0xaf, 0x98, 0xb, 0xf0 }, - }, - { - .msglen = 4, - .result = { 0xf, 0x39, 0xd1, 0x1a, 0x3a, 0xe9, 0xa9, 0xf8, 0xe9, 0x39, 0xed, 0x1b, 0x32, 0x3, 0xbc, 0x24, 0x32, 0xe8, 0x12, 0xd7, 0xc4, 0xed, 0x2a, 0x8a, 0xed, 0x46, 0xbf, 0xa7, 0x21, 0x31, 0x37, 0xb5 }, - }, - { - .msglen = 5, - .result = { 0x6c, 0xfc, 0xf8, 0x9a, 0x56, 0xce, 0xe6, 0x1, 0x36, 0xca, 0x36, 0x37, 0xa8, 0xb9, 0xca, 0x99, 0x3b, 0xb1, 0xf8, 0x24, 0xa5, 0xf6, 0x20, 0x4d, 0xff, 0x8c, 0x60, 0xd3, 0x9, 0x92, 0xef, 0xb3 }, - }, - { - .msglen = 6, - .result = { 0x86, 0x99, 0x7, 0xd7, 0x5b, 0xb3, 0x93, 0x95, 0x3a, 0x9e, 0xf5, 0x95, 0x9d, 0x5e, 0x7b, 0xaf, 0x9b, 0x4b, 0x19, 0x35, 0x31, 0x34, 0xba, 0x29, 0xa, 0x56, 0xb, 0xe4, 0xa4, 0xbf, 0xb8, 0x9f }, - }, - { - .msglen = 7, - .result = { 0xa9, 0x9, 0x85, 0x26, 0x7b, 0x92, 0x23, 0xe7, 0x3d, 0x44, 0xa1, 0xcc, 0xba, 0x5c, 0xda, 0xdb, 0x5a, 0xe2, 0x76, 0x78, 0xd7, 0x42, 0x77, 0x4a, 0x8e, 0x2b, 0x79, 0x73, 0x4c, 0x29, 0x6, 0x1c }, - }, - { - .msglen = 8, - .result = { 0x26, 0x15, 0x1f, 0xe3, 0x53, 0xd9, 0x8, 0xc5, 0xf0, 0x11, 0x7, 0x7, 0x5f, 0x8c, 0xf6, 0x61, 0xd2, 0x21, 0x16, 0xe4, 0xb9, 0x61, 0x29, 0x1c, 0x4d, 0x2b, 0x6d, 0x9a, 0x88, 0x8c, 0xdc, 0xa9 }, - }, - { - .msglen = 9, - .result = { 0x2, 0xf2, 0xe6, 0xc8, 0x9c, 0xdc, 0x1b, 0x64, 0xd6, 0x32, 0xc2, 0x48, 0x62, 0x51, 0x9c, 0x0, 0x90, 0xf4, 0xf1, 0x2a, 0x0, 0x2, 0xce, 0x32, 0xbb, 0x8f, 0x38, 0x9c, 0x8b, 0xaa, 0xdd, 0x5d }, - }, - { - .msglen = 10, - .result = { 0x44, 0x76, 0x8a, 0x53, 0xcf, 0xbb, 0xc1, 0xd0, 0x36, 0x96, 0xb5, 0xe9, 0xe, 0xfb, 0xce, 0xb3, 0x47, 0x21, 0xaa, 0xea, 0xac, 0x76, 0x54, 0x91, 0xc1, 0xcb, 0x88, 0x32, 0xb1, 0xea, 0xd5, 0x4c }, - }, - { - .msglen = 11, - .result = { 0x95, 0xf9, 0x78, 0x12, 0xe5, 0x7a, 0xf4, 0xc5, 0xee, 0x5e, 0x27, 0xe7, 0x5e, 0x8, 0x56, 0x60, 0x97, 0xc1, 0xee, 0xf, 0xf5, 0x24, 0x5c, 0x20, 0xbe, 0x95, 0x3c, 0xa2, 0xf5, 0x68, 0x69, 0x6f }, - }, - { - .msglen = 12, - .result = { 0x8e, 0x71, 0xa8, 0x23, 0x7a, 0x8, 0x6a, 0xf4, 0x2e, 0xab, 0x58, 0x56, 0x37, 0x55, 0x26, 0x57, 0x13, 0xc, 0x6b, 0x6b, 0x65, 0xb6, 0x4f, 0xec, 0xde, 0xc2, 0xe6, 0xb0, 0x34, 0xc0, 0x4a, 0xba }, - }, - { - .msglen = 13, - .result = { 0x75, 0xc8, 0x29, 0x60, 0x89, 0xb7, 0xba, 0xc7, 0x40, 0x18, 0x73, 0x8a, 0xa3, 0x92, 0xb2, 0x2c, 0x79, 0x74, 0x1c, 0xdc, 0xc0, 0x97, 0x14, 0xdb, 0x26, 0xcc, 0xad, 0x7f, 0x9d, 0x2f, 0xd, 0x5 }, - }, - { - .msglen = 14, - .result = { 0xe9, 0xf2, 0x97, 0x12, 0x4d, 0xc3, 0x22, 0xca, 0x7, 0xc, 0xac, 0xae, 0xcb, 0x63, 0xe2, 0x88, 0xa2, 0xf8, 0xb0, 0x94, 0xfc, 0x21, 0xf4, 0x69, 0x8e, 0xa0, 0x95, 0x3, 0x54, 0xa1, 0x61, 0xed }, - }, - { - .msglen = 15, - .result = { 0x34, 0xd4, 0x3e, 0xcd, 0xcc, 0xa, 0x5f, 0xaf, 0xf5, 0x3d, 0xb8, 0xaa, 0x18, 0x4a, 0x18, 0xef, 0x22, 0x75, 0x29, 0x17, 0x1b, 0x33, 0xf2, 0x50, 0x4e, 0x90, 0xd5, 0xa3, 0x10, 0xff, 0x79, 0xbc }, - }, - { - .msglen = 16, - .result = { 0xcf, 0x6, 0x59, 0x8d, 0x2d, 0x7b, 0xb, 0x3d, 0x1a, 0xa3, 0x9c, 0xfa, 0xa2, 0xf1, 0x88, 0x6, 0xd2, 0xb4, 0xb5, 0x2d, 0x4c, 0x56, 0x7, 0xf5, 0x20, 0xce, 0x9a, 0x79, 0x3a, 0x2e, 0x11, 0xfa }, - }, - { - .msglen = 17, - .result = { 0x55, 0x5f, 0x37, 0xd9, 0x7, 0x3a, 0x3a, 0x6b, 0x22, 0xf8, 0x1c, 0x8f, 0xd8, 0xf6, 0xf7, 0x18, 0x77, 0xf3, 0x52, 0x32, 0xc6, 0x9b, 0xe0, 0xc7, 0xa6, 0xf0, 0x6b, 0xb0, 0x6a, 0xad, 0xb2, 0x7e }, - }, - { - .msglen = 18, - .result = { 0xa0, 0x60, 0x25, 0x34, 0xd7, 0xe1, 0x66, 0x7e, 0xdd, 0xec, 0x8, 0x95, 0xb5, 0xd9, 0x2d, 0x4e, 0x29, 0x89, 0x39, 0xb9, 0xc1, 0xe4, 0xc1, 0x86, 0x10, 0x16, 0x5, 0x17, 0xd0, 0x6, 0x91, 0x2d }, - }, - { - .msglen = 19, - .result = { 0xb4, 0x45, 0xbc, 0xae, 0xb3, 0x5b, 0x61, 0xd3, 0x50, 0x8c, 0x38, 0x7a, 0x4c, 0x4c, 0xbc, 0x38, 0x89, 0x98, 0x75, 0x23, 0xa9, 0x92, 0xa4, 0xea, 0xfe, 0xe6, 0x88, 0x61, 0xb0, 0xf0, 0x8, 0x7b }, - }, - { - .msglen = 20, - .result = { 0x1d, 0x2e, 0x5c, 0x69, 0x7b, 0x2a, 0xa0, 0x9d, 0xe6, 0x5b, 0xc, 0x3, 0x53, 0x9, 0x66, 0x74, 0xd8, 0xf6, 0xe8, 0x87, 0x5d, 0xc7, 0x1, 0xf0, 0xce, 0xaf, 0xb1, 0x15, 0x34, 0x22, 0x8e, 0x83 }, - }, - { - .msglen = 21, - .result = { 0x8e, 0xd9, 0xb1, 0xc7, 0x99, 0x91, 0x1, 0x9a, 0xe, 0xfa, 0xd2, 0xed, 0xc4, 0xae, 0x47, 0xf2, 0xa2, 0x48, 0x53, 0xa8, 0x92, 0xff, 0xe4, 0xcc, 0x95, 0x5e, 0x25, 0x1a, 0x2a, 0x49, 0x6c, 0xfd }, - }, - { - .msglen = 22, - .result = { 0x14, 0xba, 0x32, 0xbe, 0x21, 0x6, 0x6e, 0x6a, 0x28, 0x2b, 0x4e, 0xfc, 0x97, 0xa5, 0x6, 0x32, 0x62, 0x7, 0xf3, 0x61, 0x41, 0x43, 0x5e, 0x34, 0x93, 0x0, 0xa8, 0xb3, 0x9, 0x55, 0x37, 0x3f }, - }, - { - .msglen = 23, - .result = { 0xa1, 0xf0, 0xe6, 0xf1, 0x9d, 0x5d, 0x30, 0x10, 0x17, 0xce, 0x39, 0x5e, 0x93, 0x2b, 0xe6, 0xeb, 0x6b, 0x5b, 0x64, 0x47, 0x65, 0xe8, 0x93, 0x2e, 0x39, 0x74, 0x6a, 0x71, 0xf3, 0xdb, 0xb6, 0x8d }, - }, - { - .msglen = 24, - .result = { 0xab, 0xf4, 0xe1, 0x78, 0xc1, 0x63, 0x95, 0xf2, 0x6c, 0x54, 0xc, 0xac, 0xce, 0x88, 0x17, 0xf6, 0x1c, 0x84, 0x5b, 0x26, 0xa3, 0x5c, 0xea, 0xf7, 0x66, 0xcb, 0x84, 0xed, 0xbe, 0x52, 0xd, 0x25 }, - }, - { - .msglen = 25, - .result = { 0xd8, 0x94, 0x77, 0xa7, 0x6c, 0x51, 0x30, 0x3c, 0xd7, 0x4f, 0xc4, 0x6e, 0x1a, 0x25, 0xf8, 0x87, 0x93, 0x49, 0x28, 0x6b, 0x1b, 0x3, 0x79, 0x5, 0x14, 0x15, 0xd1, 0xee, 0x51, 0x7b, 0x9f, 0x94 }, - }, - { - .msglen = 26, - .result = { 0xbb, 0x8a, 0x5f, 0x73, 0x8d, 0x4e, 0x8a, 0x11, 0x95, 0x5d, 0xf5, 0xcf, 0x25, 0xea, 0x79, 0x38, 0xc4, 0x4b, 0xb4, 0x6f, 0xa3, 0x1f, 0x18, 0x23, 0x73, 0x1e, 0x46, 0xcb, 0x5d, 0x97, 0xcf, 0x6c }, - }, - { - .msglen = 27, - .result = { 0xe2, 0xad, 0x4b, 0x4e, 0x43, 0xf1, 0x6d, 0x62, 0x1a, 0xb4, 0x65, 0xbb, 0xb3, 0x34, 0x8, 0xf7, 0x14, 0x14, 0xd2, 0x6f, 0x41, 0x8f, 0xa7, 0x6f, 0xab, 0x6e, 0x61, 0xe2, 0x5, 0x5b, 0x2a, 0xe6 }, - }, - { - .msglen = 28, - .result = { 0xd9, 0xea, 0x5, 0x72, 0x59, 0x12, 0xff, 0xb, 0x33, 0x87, 0x17, 0x9d, 0xb2, 0x9, 0x4f, 0xfc, 0xba, 0xd7, 0xc, 0x45, 0x3b, 0xbe, 0x6a, 0x12, 0x59, 0x38, 0x40, 0x30, 0x8c, 0xa4, 0xf, 0x7d }, - }, - { - .msglen = 29, - .result = { 0x29, 0xe, 0x6d, 0x59, 0x2a, 0xaf, 0x5f, 0x93, 0xc7, 0x97, 0xbb, 0x29, 0x92, 0x2c, 0xba, 0x6b, 0xa5, 0xcb, 0x7e, 0x88, 0x5b, 0xcd, 0xd4, 0xfe, 0xb4, 0xc7, 0x65, 0xae, 0x6b, 0x7f, 0x78, 0xb6 }, - }, - { - .msglen = 30, - .result = { 0x5e, 0xea, 0x58, 0xb5, 0x93, 0x4b, 0xb7, 0x32, 0x50, 0xcb, 0xc6, 0x6c, 0x63, 0x9d, 0x5d, 0xa9, 0x3f, 0x80, 0xc4, 0x91, 0xbc, 0xe3, 0x2a, 0xd6, 0x20, 0xfb, 0xf9, 0x43, 0x59, 0xcf, 0x86, 0x1d }, - }, - { - .msglen = 31, - .result = { 0x46, 0xee, 0x3a, 0x2a, 0x1, 0xf6, 0x43, 0xe, 0xbb, 0xc6, 0x90, 0x4f, 0x66, 0xa5, 0xe9, 0xd7, 0xa8, 0x29, 0x7e, 0x16, 0x4, 0x57, 0xee, 0x5c, 0xf4, 0x6c, 0xc8, 0x4a, 0x92, 0x27, 0x83, 0x42 }, - }, - { - .msglen = 32, - .result = { 0x82, 0x36, 0xe6, 0xf, 0xa, 0x37, 0x2d, 0x7b, 0x2, 0x75, 0xc4, 0x48, 0x36, 0xbf, 0xdf, 0x79, 0x35, 0xdf, 0xcb, 0x65, 0x25, 0xae, 0x11, 0x2c, 0xfa, 0x54, 0x4a, 0x99, 0xfe, 0x2a, 0x63, 0xbd }, - }, - { - .msglen = 33, - .result = { 0x9e, 0x35, 0xc8, 0x6c, 0xa7, 0xe8, 0x8b, 0xb2, 0x0, 0x4c, 0x41, 0x51, 0x5b, 0xd2, 0x4b, 0x9f, 0x10, 0xea, 0xfe, 0xd7, 0xc1, 0xd1, 0x36, 0xfb, 0x52, 0xd6, 0xe3, 0xe2, 0x23, 0xc9, 0x53, 0x33 }, - }, - { - .msglen = 34, - .result = { 0x52, 0xe9, 0x15, 0x90, 0x65, 0xb, 0x75, 0x89, 0xb3, 0xed, 0x7a, 0xb6, 0x12, 0xe6, 0xe, 0xeb, 0x7c, 0x25, 0xb4, 0xf3, 0x2a, 0xf6, 0xfe, 0x6a, 0x3c, 0xd9, 0xf0, 0x2a, 0xaf, 0xc7, 0x1b, 0xbc }, - }, - { - .msglen = 35, - .result = { 0xfc, 0xa5, 0xf1, 0x9a, 0xa0, 0xfa, 0x42, 0x7b, 0x49, 0xf, 0xd7, 0x76, 0xe0, 0xf9, 0x31, 0x17, 0x87, 0x70, 0x19, 0x90, 0x26, 0x96, 0xcd, 0xd6, 0xf, 0xa8, 0xb, 0x1f, 0x31, 0x45, 0x9c, 0xd0 }, - }, - { - .msglen = 36, - .result = { 0x85, 0x76, 0xf4, 0xfc, 0x96, 0xfb, 0x69, 0x31, 0x6, 0x5c, 0x6e, 0xd9, 0x75, 0xda, 0xf0, 0x14, 0xba, 0x4b, 0x74, 0x96, 0xf7, 0xe6, 0xd0, 0x3d, 0x36, 0x9b, 0x94, 0x8c, 0x1a, 0xb9, 0x7a, 0x88 }, - }, - { - .msglen = 37, - .result = { 0x8b, 0xc7, 0xad, 0xb8, 0xce, 0xc6, 0xd7, 0x8e, 0xd6, 0xfa, 0xa5, 0xd3, 0x59, 0x3d, 0x39, 0xdc, 0x74, 0x56, 0x3c, 0xd9, 0xc8, 0x0, 0xd2, 0xb0, 0x21, 0x7b, 0x93, 0xcb, 0x18, 0xec, 0x5f, 0xdd }, - }, - { - .msglen = 38, - .result = { 0x95, 0x7a, 0xf3, 0x9c, 0x5b, 0x40, 0x86, 0xdf, 0xa6, 0xf7, 0x34, 0x40, 0xb0, 0x7a, 0x34, 0x6c, 0xd5, 0x3d, 0x6, 0x9d, 0xc7, 0x9f, 0x11, 0x32, 0x98, 0x78, 0xee, 0xed, 0xb6, 0xb4, 0x1f, 0x34 }, - }, - { - .msglen = 39, - .result = { 0xf3, 0x50, 0x40, 0xd2, 0xbb, 0x54, 0xb3, 0xcf, 0x37, 0x55, 0xff, 0xc8, 0x41, 0x30, 0xde, 0x33, 0x2f, 0x4, 0xe3, 0xe7, 0x42, 0x31, 0x68, 0xe6, 0x6d, 0x5d, 0xdc, 0x14, 0x5a, 0x58, 0xf4, 0x46 }, - }, - { - .msglen = 40, - .result = { 0xda, 0x9d, 0xeb, 0xf7, 0xa7, 0xa1, 0x4, 0xd1, 0xfb, 0xe3, 0xd8, 0x11, 0x8d, 0x54, 0x88, 0x65, 0x42, 0x6e, 0x78, 0x7a, 0x8f, 0x1b, 0xc5, 0x13, 0x98, 0x53, 0x38, 0x26, 0xf3, 0x3d, 0xd2, 0xff }, - }, - { - .msglen = 41, - .result = { 0x9c, 0x23, 0x67, 0xa3, 0xeb, 0xed, 0xca, 0x21, 0x4b, 0x4c, 0x68, 0x95, 0xaf, 0xfb, 0x9b, 0x17, 0xf0, 0x2a, 0x5c, 0x78, 0x58, 0x65, 0xf1, 0x20, 0xfd, 0x3c, 0xd9, 0x66, 0x94, 0x66, 0x4d, 0xcc }, - }, - { - .msglen = 42, - .result = { 0xfa, 0x61, 0xf5, 0xd7, 0x58, 0xd2, 0x32, 0xb0, 0xb, 0x95, 0x88, 0xfc, 0x8a, 0x79, 0x15, 0x61, 0x1e, 0xa7, 0xf7, 0xf2, 0xf1, 0x91, 0xe7, 0xb3, 0x55, 0xa0, 0x65, 0x3c, 0xca, 0xf6, 0xac, 0x19 }, - }, - { - .msglen = 43, - .result = { 0xae, 0xc1, 0xb4, 0xa9, 0x88, 0xf3, 0x6d, 0xfe, 0xc2, 0x48, 0x19, 0x2a, 0x68, 0x41, 0x5e, 0x3f, 0xbe, 0x32, 0x20, 0xc7, 0x90, 0x6f, 0x23, 0x6d, 0x42, 0xaa, 0x38, 0xbb, 0xd5, 0x34, 0x7e, 0x21 }, - }, - { - .msglen = 44, - .result = { 0x12, 0xb0, 0xb, 0x1, 0xcf, 0xc9, 0x20, 0x8d, 0x59, 0xc1, 0xb7, 0xe9, 0x23, 0x53, 0x12, 0xd4, 0x41, 0x99, 0x7f, 0xb9, 0x57, 0x11, 0x5d, 0x9c, 0x60, 0xa8, 0x0, 0x3, 0x68, 0x9, 0x4d, 0x1d }, - }, - { - .msglen = 45, - .result = { 0xee, 0x85, 0x2, 0xed, 0xa1, 0x41, 0x71, 0xd4, 0x32, 0x2, 0x33, 0xec, 0x26, 0x31, 0x7b, 0xb8, 0xd0, 0xb0, 0xd6, 0xb0, 0x60, 0x52, 0xe1, 0xd9, 0xd7, 0x33, 0x72, 0x5c, 0xb9, 0xc3, 0x6c, 0x9f }, - }, - { - .msglen = 46, - .result = { 0x90, 0x3e, 0x7, 0x17, 0xa2, 0x18, 0xd, 0xa1, 0x71, 0xfe, 0x4b, 0x6d, 0x24, 0x40, 0x5e, 0xe2, 0xd1, 0x45, 0xd6, 0x18, 0xe8, 0xa3, 0x2d, 0x12, 0xe8, 0x11, 0xae, 0x1, 0xc4, 0x77, 0xa9, 0xab }, - }, - { - .msglen = 47, - .result = { 0x4a, 0x4f, 0x5a, 0xd1, 0xd0, 0xfb, 0xf7, 0x60, 0x9c, 0xbf, 0x23, 0x99, 0x95, 0xea, 0x51, 0xdb, 0x70, 0xc4, 0xa, 0xaf, 0x41, 0x13, 0x7d, 0x3d, 0xd1, 0x50, 0xa7, 0x13, 0x4f, 0xa0, 0xbf, 0xf4 }, - }, - { - .msglen = 48, - .result = { 0x63, 0x50, 0x7a, 0x54, 0xd8, 0xa5, 0xf, 0x96, 0x45, 0x3a, 0x85, 0x8e, 0x8e, 0xc6, 0x5d, 0xe0, 0xe8, 0xfd, 0xce, 0xa8, 0x3f, 0x59, 0x19, 0x81, 0x13, 0xd1, 0xf7, 0xd, 0x45, 0xe3, 0xf3, 0x31 }, - }, - { - .msglen = 49, - .result = { 0x3c, 0x7a, 0x1, 0xdd, 0x3a, 0x96, 0xae, 0x2, 0x2e, 0x6a, 0x7f, 0xd, 0x1e, 0x2f, 0x32, 0xfd, 0x5, 0x33, 0xae, 0x54, 0xa2, 0xa6, 0x89, 0x32, 0x9a, 0x7, 0xb7, 0xe9, 0x66, 0xaf, 0xf8, 0xc }, - }, - { - .msglen = 50, - .result = { 0x57, 0xd8, 0xed, 0xc4, 0xec, 0x23, 0xf, 0xf9, 0x55, 0xc1, 0x36, 0xde, 0xc3, 0xbd, 0x54, 0x53, 0x2f, 0xfa, 0xd1, 0xb3, 0xe1, 0x87, 0xc2, 0x39, 0x54, 0x59, 0xa9, 0xb9, 0xac, 0xed, 0xa0, 0x49 }, - }, - { - .msglen = 51, - .result = { 0xdf, 0xd5, 0x2e, 0xd2, 0xd2, 0xb0, 0x90, 0x12, 0x71, 0x37, 0x51, 0xba, 0x79, 0xd4, 0x43, 0xc7, 0x74, 0x12, 0xf3, 0x71, 0x74, 0x63, 0xc, 0x4d, 0x59, 0x2e, 0x5, 0xb5, 0xa2, 0x17, 0xe, 0xe9 }, - }, - { - .msglen = 52, - .result = { 0xbd, 0xa3, 0x12, 0x94, 0xea, 0xa7, 0xc4, 0xd3, 0x1f, 0x99, 0xcb, 0xbc, 0x53, 0x80, 0x45, 0xfd, 0x17, 0x13, 0xd7, 0x2b, 0x26, 0x5b, 0x23, 0x3d, 0x2d, 0xd8, 0x7f, 0x9, 0xcc, 0x9c, 0xa7, 0xfd }, - }, - { - .msglen = 53, - .result = { 0x66, 0x3a, 0xc1, 0x3b, 0x1f, 0x7d, 0x0, 0xf5, 0x9a, 0x5e, 0x92, 0x61, 0x16, 0xad, 0x2b, 0x15, 0x2f, 0x65, 0x89, 0xd2, 0xa3, 0xbd, 0x33, 0x71, 0x31, 0xe8, 0x37, 0x3c, 0xb0, 0x6d, 0x13, 0xc9 }, - }, - { - .msglen = 54, - .result = { 0xff, 0x17, 0xef, 0x42, 0x67, 0xba, 0xcf, 0xe7, 0xfe, 0xf5, 0x76, 0x96, 0x9e, 0xf0, 0x61, 0xe5, 0xd, 0xc3, 0xbb, 0x63, 0xd3, 0xcd, 0x4a, 0x10, 0x63, 0xa3, 0x3c, 0xe, 0xf2, 0xfc, 0xa, 0x33 }, - }, - { - .msglen = 55, - .result = { 0x78, 0xa8, 0xe5, 0x15, 0x18, 0x49, 0x4, 0xba, 0x34, 0xb6, 0xb3, 0x96, 0x3a, 0x6, 0xaa, 0x93, 0xad, 0x82, 0x5b, 0x87, 0x0, 0x3f, 0x5, 0x1, 0xe7, 0xe1, 0x22, 0x16, 0x3d, 0xb5, 0x5b, 0xb8 }, - }, - { - .msglen = 56, - .result = { 0x0, 0xad, 0xbf, 0x7d, 0x51, 0xc4, 0xed, 0x5, 0x6c, 0x81, 0x15, 0x5c, 0xa5, 0xe3, 0x6b, 0x39, 0x59, 0x10, 0x8e, 0xbc, 0x3f, 0xb8, 0x21, 0xbc, 0xd9, 0x9e, 0x35, 0x7d, 0x23, 0x48, 0x5, 0x8a }, - }, - { - .msglen = 57, - .result = { 0xf7, 0x5e, 0xa3, 0x88, 0x1f, 0x82, 0xf0, 0xc4, 0x39, 0x7e, 0xed, 0x22, 0x78, 0xd6, 0x65, 0x94, 0x4f, 0x8, 0x2e, 0x96, 0x7e, 0x44, 0x8f, 0x0, 0x3b, 0x92, 0xf9, 0xea, 0x83, 0x72, 0xc7, 0xe2 }, - }, - { - .msglen = 58, - .result = { 0x84, 0xa5, 0x85, 0x95, 0x0, 0x7e, 0xc4, 0x98, 0x36, 0xc9, 0xe5, 0xd4, 0xda, 0x59, 0xab, 0x22, 0x2f, 0xa8, 0xb7, 0x46, 0x55, 0x91, 0x2, 0xc, 0x5b, 0x64, 0x5c, 0x5b, 0x42, 0x8b, 0x7e, 0xa }, - }, - { - .msglen = 59, - .result = { 0x4e, 0x1c, 0x16, 0x99, 0xd8, 0x4, 0xb, 0x6, 0x91, 0x98, 0x87, 0xb0, 0xa3, 0x63, 0x9, 0xdf, 0xfb, 0xa6, 0xd6, 0xe4, 0x58, 0x27, 0xf5, 0x73, 0x9, 0x81, 0x4f, 0x5d, 0x88, 0x2c, 0xb8, 0x7 }, - }, - { - .msglen = 60, - .result = { 0x2f, 0x97, 0xbf, 0x70, 0x70, 0x4b, 0xfe, 0x5a, 0x2f, 0x91, 0x8f, 0x28, 0x8b, 0xee, 0xf6, 0xee, 0x41, 0x7d, 0x36, 0x14, 0x86, 0x69, 0x42, 0x9c, 0x4d, 0x5, 0xcc, 0x53, 0x71, 0x61, 0x78, 0xe }, - }, - { - .msglen = 61, - .result = { 0xe6, 0xba, 0x7f, 0x8, 0xb3, 0xdc, 0x7b, 0x95, 0xcb, 0xd1, 0x33, 0x64, 0x25, 0x5a, 0xa3, 0x70, 0x10, 0x4a, 0xe6, 0x2c, 0x54, 0x25, 0xfa, 0x7e, 0xd0, 0x47, 0x65, 0x8d, 0xa1, 0xa8, 0x80, 0x5 }, - }, - { - .msglen = 62, - .result = { 0x9b, 0x48, 0x8d, 0x79, 0x16, 0xe8, 0x32, 0x63, 0x89, 0xaa, 0x4b, 0x7d, 0xdb, 0x46, 0xcd, 0x80, 0x40, 0x9d, 0x8c, 0x6, 0xa5, 0xed, 0xb4, 0xe1, 0xdd, 0x87, 0x6b, 0xb3, 0x90, 0x2b, 0x77, 0xc8 }, - }, - { - .msglen = 63, - .result = { 0x72, 0xfb, 0x8c, 0xf1, 0xb9, 0xb3, 0x50, 0x55, 0x5c, 0xac, 0x93, 0x38, 0x73, 0x1c, 0xd0, 0x93, 0x6, 0x5e, 0xcd, 0x0, 0x24, 0x83, 0x4b, 0xef, 0xdc, 0xfd, 0x27, 0x58, 0xfc, 0xa1, 0x4a, 0x32 }, - }, - { - .msglen = 64, - .result = { 0x19, 0x5b, 0x88, 0x8d, 0x75, 0x97, 0x8a, 0x8c, 0x5d, 0xd4, 0xe7, 0xe4, 0xa, 0x4d, 0x5e, 0xcd, 0xe7, 0x88, 0xab, 0xb9, 0x6b, 0xd8, 0xd3, 0x80, 0x25, 0x3e, 0xa4, 0xfd, 0xc1, 0x83, 0x6e, 0x74 }, - }, - { - .msglen = 65, - .result = { 0x14, 0x3, 0xcc, 0x1f, 0xa5, 0xed, 0x5e, 0x3c, 0x45, 0x2d, 0x66, 0x9a, 0x36, 0xb7, 0x9a, 0xb, 0x1c, 0x83, 0x4d, 0xbe, 0xc9, 0x41, 0x7e, 0x7, 0x54, 0x97, 0x76, 0x25, 0x96, 0x76, 0xce, 0xd4 }, - }, - { - .msglen = 66, - .result = { 0x44, 0x62, 0x56, 0x7e, 0x68, 0x10, 0xed, 0xd9, 0x35, 0x8a, 0xe3, 0xd, 0x20, 0xf, 0xe6, 0x45, 0x89, 0x6c, 0x8c, 0x18, 0x13, 0xe5, 0xef, 0x28, 0x2d, 0xc1, 0x6a, 0x95, 0x9e, 0x3d, 0x81, 0x51 }, - }, - { - .msglen = 67, - .result = { 0x94, 0xac, 0xc2, 0xe0, 0x8, 0xb7, 0xe5, 0xe2, 0x18, 0xf0, 0x59, 0x47, 0xda, 0xf4, 0xb4, 0xb1, 0xfe, 0x11, 0xe4, 0x3c, 0x2c, 0xa8, 0x1, 0x30, 0x5e, 0x8e, 0x89, 0x4, 0xff, 0xf2, 0xc1, 0x88 }, - }, - { - .msglen = 68, - .result = { 0xa2, 0x73, 0x97, 0x2, 0xd7, 0xc4, 0x9b, 0x39, 0x20, 0xdc, 0xac, 0x6d, 0xca, 0x81, 0xdd, 0x83, 0xac, 0xd4, 0xf, 0x89, 0x94, 0x10, 0x8b, 0xf6, 0xb9, 0x10, 0xab, 0x24, 0xd3, 0xf9, 0xc8, 0x4f }, - }, - { - .msglen = 69, - .result = { 0x68, 0xa9, 0x9b, 0xc2, 0xb6, 0x1e, 0x4c, 0xe3, 0xc6, 0x89, 0xc7, 0x40, 0x2f, 0xee, 0x8f, 0x50, 0xf4, 0x9d, 0x56, 0x5, 0xba, 0x0, 0x30, 0xaa, 0xd6, 0xa6, 0x4d, 0x94, 0x46, 0xc, 0x3c, 0x3 }, - }, - { - .msglen = 70, - .result = { 0x4f, 0x71, 0x4e, 0x2f, 0x89, 0xce, 0x84, 0x3b, 0x9a, 0xab, 0x6c, 0x93, 0xac, 0xa8, 0x51, 0xf7, 0x72, 0x91, 0xd5, 0xad, 0xf7, 0x91, 0x5a, 0x3a, 0xa6, 0x16, 0x61, 0x6b, 0x9f, 0xba, 0xe3, 0x51 }, - }, - { - .msglen = 71, - .result = { 0x25, 0x50, 0x50, 0x55, 0x50, 0x6a, 0x55, 0x8d, 0x54, 0x61, 0x60, 0x44, 0x5a, 0xb0, 0x4f, 0x77, 0x7, 0xbe, 0xcf, 0x49, 0xb6, 0x68, 0x9b, 0x6d, 0x79, 0xd5, 0xb9, 0xb1, 0x45, 0x29, 0xcc, 0xc1 }, - }, - { - .msglen = 72, - .result = { 0x59, 0x47, 0xf5, 0x99, 0xad, 0xac, 0x9, 0x15, 0xdc, 0x67, 0x2f, 0x4e, 0x38, 0x83, 0xab, 0x53, 0x8d, 0xc2, 0x71, 0xf5, 0xb9, 0x4e, 0x59, 0xd5, 0x32, 0x10, 0x90, 0xd8, 0x5b, 0xb6, 0x5, 0xc0 }, - }, - { - .msglen = 73, - .result = { 0x68, 0x9, 0x2a, 0x7d, 0x49, 0x8f, 0xc1, 0xd4, 0x93, 0xc9, 0xf8, 0xe9, 0xd8, 0xc4, 0xc2, 0x34, 0xc8, 0xac, 0xc9, 0xb4, 0x9, 0x5d, 0x46, 0x51, 0xd4, 0x2e, 0x4, 0xbb, 0x8f, 0x66, 0x75, 0x15 }, - }, - { - .msglen = 74, - .result = { 0xc, 0xf, 0x3c, 0x79, 0x8b, 0x80, 0x93, 0xd9, 0x7f, 0x3, 0xb4, 0x5f, 0xfe, 0x66, 0xcf, 0xbe, 0xea, 0xe1, 0xa0, 0xfd, 0xf0, 0x49, 0x3d, 0x19, 0x54, 0xdc, 0x38, 0x73, 0x11, 0xb3, 0x8, 0xa3 }, - }, - { - .msglen = 75, - .result = { 0x33, 0xae, 0x39, 0xab, 0x8, 0x54, 0x48, 0x9e, 0x2b, 0xbe, 0x89, 0x7a, 0x32, 0xdb, 0x81, 0xc5, 0xbd, 0x39, 0x19, 0xc1, 0x87, 0x6f, 0x64, 0xb3, 0x70, 0xea, 0x9, 0xd2, 0xea, 0x72, 0x53, 0x6e }, - }, - { - .msglen = 76, - .result = { 0x37, 0xae, 0xae, 0xed, 0x35, 0xd1, 0x97, 0x88, 0x78, 0x57, 0x19, 0xdd, 0xbc, 0x3c, 0xa3, 0x10, 0x79, 0x21, 0x3a, 0xf9, 0xce, 0x34, 0xf3, 0xad, 0x85, 0x4f, 0xf2, 0xac, 0xd7, 0x24, 0x7b, 0x80 }, - }, - { - .msglen = 77, - .result = { 0xc0, 0xd0, 0xb7, 0xff, 0x19, 0x7a, 0xfe, 0x6c, 0x6, 0x4b, 0xf6, 0x12, 0x4c, 0xe6, 0xe8, 0x2, 0xf3, 0x32, 0xc3, 0x77, 0xf, 0x10, 0xab, 0x89, 0xde, 0x18, 0xc5, 0xe, 0x25, 0xab, 0x23, 0xdb }, - }, - { - .msglen = 78, - .result = { 0x5e, 0xe7, 0x3b, 0xa0, 0x6, 0x8e, 0x40, 0x26, 0xaf, 0x6f, 0xba, 0xf9, 0xa6, 0x23, 0xab, 0x49, 0x89, 0x15, 0xd4, 0x15, 0xc0, 0x6c, 0x1f, 0xfc, 0x6d, 0x3e, 0x51, 0x3a, 0x6e, 0xef, 0x3d, 0x17 }, - }, - { - .msglen = 79, - .result = { 0x2, 0xfd, 0xd7, 0x48, 0x76, 0x5b, 0x25, 0x26, 0xd4, 0x87, 0x94, 0x14, 0x9b, 0x13, 0x91, 0xa4, 0x39, 0x5, 0x4c, 0x4e, 0x6a, 0xdd, 0x60, 0x66, 0x4e, 0x23, 0xeb, 0xa5, 0xfd, 0xad, 0x5a, 0xda }, - }, - { - .msglen = 80, - .result = { 0x84, 0xf3, 0x92, 0xf1, 0xc0, 0xc0, 0x5a, 0x63, 0xec, 0x16, 0xf4, 0xfc, 0x4c, 0xc6, 0xb6, 0x62, 0x1e, 0x9f, 0xdd, 0xcb, 0xd8, 0x4a, 0x12, 0xf2, 0x9, 0x11, 0x88, 0x66, 0x4e, 0x85, 0xef, 0x9f }, - }, - { - .msglen = 81, - .result = { 0x8b, 0x28, 0x66, 0x9d, 0xe2, 0x96, 0x58, 0x21, 0x3f, 0xcd, 0xd7, 0xe0, 0xce, 0x9b, 0x51, 0x32, 0x68, 0xac, 0x1c, 0x9e, 0x38, 0x7d, 0x60, 0x5a, 0x32, 0xe1, 0x14, 0x91, 0xee, 0x36, 0x39, 0xbd }, - }, - { - .msglen = 82, - .result = { 0x5c, 0x16, 0xe3, 0xff, 0x6b, 0x51, 0xc2, 0x59, 0x8a, 0x24, 0xc2, 0xba, 0xc0, 0xd7, 0xd4, 0xac, 0xd9, 0x3e, 0x38, 0x1f, 0x7f, 0x2d, 0xb7, 0x85, 0x8b, 0xf1, 0xd2, 0x42, 0x28, 0xa9, 0xd7, 0x94 }, - }, - { - .msglen = 83, - .result = { 0xde, 0x40, 0xe0, 0xde, 0xf9, 0xe4, 0x75, 0x3d, 0x61, 0x91, 0x38, 0xac, 0x31, 0xa9, 0xba, 0x31, 0x18, 0x41, 0x57, 0x2e, 0x89, 0xdf, 0x26, 0x83, 0x40, 0x71, 0xce, 0xdc, 0x18, 0x3f, 0xe7, 0xd7 }, - }, - { - .msglen = 84, - .result = { 0x85, 0xf, 0x58, 0x5f, 0x4d, 0x81, 0x5b, 0x54, 0x6a, 0xa4, 0xd4, 0xfb, 0x3, 0x4e, 0x71, 0xa7, 0xc5, 0x11, 0xf, 0x1a, 0xa8, 0x44, 0x10, 0x15, 0x2e, 0xdf, 0x1e, 0xea, 0x4d, 0x86, 0x31, 0x33 }, - }, - { - .msglen = 85, - .result = { 0x7f, 0xe2, 0x1b, 0x95, 0x7b, 0x19, 0x2f, 0x4e, 0x72, 0x1d, 0x6c, 0x2c, 0xf3, 0x74, 0x6e, 0x99, 0x2b, 0x10, 0x76, 0x55, 0x25, 0xe4, 0x89, 0x19, 0x98, 0xb4, 0xdc, 0xea, 0xfa, 0x68, 0xec, 0x3 }, - }, - { - .msglen = 86, - .result = { 0x5c, 0x95, 0x3d, 0xcc, 0x6, 0x58, 0x9b, 0xc4, 0x71, 0x61, 0xc2, 0x5a, 0xac, 0xaf, 0x54, 0xbf, 0xcc, 0x93, 0x3d, 0x2e, 0xdf, 0x99, 0x74, 0xc8, 0xc8, 0x36, 0xe9, 0x44, 0x7e, 0x6d, 0x3d, 0xe7 }, - }, - { - .msglen = 87, - .result = { 0xf2, 0x33, 0xbc, 0x61, 0xc6, 0x2c, 0x19, 0x26, 0x80, 0x9e, 0x1e, 0x76, 0x8e, 0x9, 0x61, 0x6, 0xfb, 0xc3, 0xc8, 0xcb, 0x35, 0x9d, 0xaa, 0x73, 0xa8, 0xe6, 0xd2, 0x89, 0xc5, 0x5d, 0xee, 0xa4 }, - }, - { - .msglen = 88, - .result = { 0x3f, 0x13, 0xf7, 0x63, 0x67, 0x8d, 0x65, 0xcd, 0xa8, 0x5b, 0xcd, 0xc4, 0xb7, 0x25, 0x35, 0xbe, 0xd3, 0xc1, 0x6d, 0x36, 0xb9, 0x8c, 0x8c, 0x6a, 0x79, 0xd1, 0x12, 0xe8, 0xdc, 0x6c, 0xe3, 0x6d }, - }, - { - .msglen = 89, - .result = { 0x8f, 0x21, 0x5a, 0x7a, 0x84, 0x79, 0x7d, 0x33, 0xa, 0x7e, 0x7a, 0x7, 0x2a, 0xa9, 0xa6, 0x58, 0x33, 0xdf, 0xec, 0x40, 0x88, 0xf2, 0x9f, 0x8d, 0x12, 0xb5, 0x5e, 0xb2, 0x88, 0x2d, 0xc1, 0x7c }, - }, - { - .msglen = 90, - .result = { 0x73, 0xfc, 0xc6, 0x9, 0x5f, 0xc2, 0xab, 0x2d, 0xd5, 0x84, 0x6c, 0xdd, 0x1f, 0x70, 0x9e, 0x5c, 0x30, 0x36, 0xb4, 0xe7, 0x86, 0xab, 0x89, 0xc6, 0xc9, 0xed, 0x7d, 0x2e, 0x26, 0x13, 0x37, 0x4a }, - }, - { - .msglen = 91, - .result = { 0x3e, 0x41, 0x8a, 0x37, 0xbd, 0xec, 0x53, 0x52, 0x47, 0xd2, 0x71, 0xa4, 0x5b, 0xc7, 0x11, 0x8e, 0x8c, 0xb8, 0x2c, 0x36, 0xc9, 0xa7, 0x15, 0x21, 0x15, 0xde, 0x7f, 0x54, 0xc7, 0xb3, 0x8d, 0x34 }, - }, - { - .msglen = 92, - .result = { 0xca, 0x1a, 0xf9, 0xfd, 0xf4, 0xb9, 0xd, 0xdd, 0x91, 0xd8, 0x7b, 0x7c, 0xf4, 0x82, 0xe7, 0x57, 0xc0, 0xb9, 0xfe, 0x2f, 0x3c, 0xc7, 0x5a, 0x3d, 0xb, 0x79, 0xb3, 0x7a, 0x7e, 0xfd, 0x25, 0x20 }, - }, - { - .msglen = 93, - .result = { 0xf6, 0x54, 0xd6, 0x3a, 0x93, 0xe3, 0x7b, 0x42, 0x11, 0xa8, 0xda, 0xa4, 0x2f, 0xbf, 0xcb, 0xd0, 0x58, 0x59, 0xf8, 0xda, 0x8c, 0x5e, 0xdc, 0x1e, 0xb0, 0x64, 0x15, 0x31, 0x92, 0xe6, 0xcc, 0xc8 }, - }, - { - .msglen = 94, - .result = { 0x7b, 0x8f, 0x93, 0xa3, 0x55, 0x11, 0x1e, 0x18, 0x77, 0xd9, 0x12, 0x7c, 0x54, 0x4e, 0x3f, 0x36, 0x18, 0x2f, 0xc7, 0xba, 0xd3, 0xe7, 0xc, 0xa3, 0xb2, 0xb1, 0x66, 0x7a, 0xfe, 0x30, 0x1b, 0x4e }, - }, - { - .msglen = 95, - .result = { 0x16, 0xea, 0xe9, 0xae, 0x5d, 0x2f, 0x88, 0x87, 0x41, 0x43, 0x3d, 0xfc, 0x35, 0x7f, 0x2c, 0x4c, 0x63, 0x36, 0xf3, 0x36, 0x51, 0x84, 0xb1, 0x64, 0xc5, 0x19, 0xc0, 0xd6, 0x57, 0xef, 0x2a, 0xa4 }, - }, - { - .msglen = 96, - .result = { 0xc9, 0x79, 0x20, 0xa1, 0x14, 0xba, 0xbe, 0x88, 0x7d, 0x6f, 0x4, 0xe3, 0xfd, 0x2d, 0xfd, 0xc3, 0x8a, 0x1, 0xea, 0x12, 0x9d, 0x4c, 0x14, 0xc3, 0x82, 0x7f, 0xb6, 0x1e, 0x8d, 0xcc, 0x11, 0x84 }, - }, - { - .msglen = 97, - .result = { 0x20, 0xa9, 0xb7, 0x5a, 0x5b, 0x76, 0xaa, 0x7b, 0xed, 0x70, 0x16, 0xfb, 0xea, 0x93, 0x55, 0xd1, 0x9f, 0x95, 0xa, 0xe0, 0x79, 0x51, 0x12, 0x2c, 0xfd, 0x7d, 0x6c, 0x94, 0x4f, 0xb6, 0x5f, 0x14 }, - }, - { - .msglen = 98, - .result = { 0xfc, 0xf4, 0x1, 0xcc, 0x9f, 0xce, 0xc2, 0x50, 0x0, 0x1f, 0xf8, 0x3f, 0xe4, 0x87, 0x2e, 0x79, 0x94, 0xdb, 0x86, 0x85, 0x8a, 0x7d, 0xb4, 0x6a, 0x84, 0xb8, 0x6c, 0x32, 0xad, 0x8c, 0x20, 0x63 }, - }, - { - .msglen = 99, - .result = { 0x17, 0xa1, 0xf5, 0x6, 0xaa, 0xb0, 0xe3, 0x82, 0x2e, 0x9c, 0xf2, 0xb9, 0x75, 0x75, 0xe9, 0x36, 0x90, 0xa9, 0xb2, 0xb9, 0x97, 0xb0, 0x10, 0xbb, 0xdd, 0x65, 0xd0, 0xa8, 0xbf, 0x69, 0x1d, 0x43 }, - }, - { - .msglen = 100, - .result = { 0xb5, 0x6c, 0xca, 0xca, 0xe1, 0xc5, 0x74, 0x19, 0xb0, 0x89, 0x58, 0x5e, 0x2e, 0x61, 0xcb, 0xa1, 0x23, 0xd0, 0x25, 0x37, 0x47, 0xe3, 0xac, 0x3e, 0x9a, 0xf6, 0x5d, 0x0, 0x77, 0xc2, 0xdc, 0x47 }, - }, - { - .msglen = 101, - .result = { 0x8, 0xa4, 0x3b, 0xe7, 0x1e, 0xeb, 0x4c, 0x3a, 0x82, 0xf1, 0xe4, 0x9d, 0xb1, 0xcc, 0xbc, 0x30, 0xb7, 0xa6, 0xfe, 0x47, 0x43, 0x86, 0xb8, 0x10, 0x33, 0xef, 0x8e, 0x35, 0x34, 0xf1, 0x52, 0xae }, - }, - { - .msglen = 102, - .result = { 0x0, 0xdb, 0x9b, 0xb7, 0xfc, 0x8a, 0x55, 0x81, 0x49, 0x94, 0x5c, 0xc2, 0x63, 0xd2, 0x56, 0x85, 0xab, 0x5a, 0xa1, 0x89, 0x66, 0xa1, 0x4d, 0x39, 0x1b, 0xe2, 0x12, 0x9a, 0x51, 0x79, 0xc0, 0x1c }, - }, - { - .msglen = 103, - .result = { 0x4c, 0xeb, 0xaa, 0xec, 0xb8, 0x31, 0xef, 0xb6, 0x89, 0x8e, 0x42, 0xdf, 0x9d, 0x57, 0x42, 0xf7, 0x53, 0x5d, 0x11, 0xc0, 0x29, 0xf7, 0x64, 0x30, 0x42, 0x32, 0x23, 0xda, 0x19, 0xe, 0x8d, 0xf3 }, - }, - { - .msglen = 104, - .result = { 0x32, 0xf5, 0x6, 0x53, 0xf8, 0x18, 0x94, 0x3d, 0xaa, 0x5e, 0xb9, 0x9e, 0x95, 0x8, 0x4, 0x29, 0xea, 0x76, 0xa1, 0xe5, 0x60, 0xa, 0x29, 0xd0, 0x78, 0x7e, 0x0, 0x27, 0x4e, 0x63, 0xc3, 0x69 }, - }, - { - .msglen = 105, - .result = { 0xa9, 0xf1, 0x2b, 0xaa, 0x5e, 0xb3, 0xc9, 0xf3, 0x25, 0x6e, 0x6f, 0x8, 0xc3, 0xb4, 0xab, 0xd1, 0x20, 0x3c, 0xb1, 0x82, 0x6b, 0xfa, 0x8, 0x62, 0xaf, 0x7a, 0xa9, 0x0, 0x79, 0x9a, 0x2b, 0x12 }, - }, - { - .msglen = 106, - .result = { 0xc2, 0x5e, 0x53, 0x66, 0x14, 0x5, 0x26, 0x6a, 0xf1, 0x70, 0x50, 0xb3, 0x9b, 0x40, 0x99, 0x7a, 0x73, 0xe2, 0xed, 0x3d, 0x4c, 0xcc, 0xf9, 0xf6, 0x1b, 0x4c, 0x6, 0xdc, 0x9, 0x7a, 0xc2, 0x4a }, - }, - { - .msglen = 107, - .result = { 0x68, 0xeb, 0x96, 0xb6, 0x9, 0x7b, 0xe2, 0x4a, 0x18, 0x3a, 0xe8, 0xf8, 0xe8, 0xc7, 0x4e, 0x27, 0x8c, 0x18, 0x8a, 0xa6, 0x23, 0xfe, 0xc2, 0xb, 0xbd, 0x72, 0x1, 0x56, 0x21, 0x6b, 0x6c, 0x56 }, - }, - { - .msglen = 108, - .result = { 0xe1, 0x7, 0xeb, 0xc3, 0x3a, 0x5e, 0x28, 0x65, 0x14, 0xcb, 0x73, 0x19, 0xef, 0x32, 0x78, 0x96, 0xf3, 0xda, 0x1e, 0x5a, 0x89, 0xf4, 0x29, 0x7c, 0xa0, 0xfd, 0x3b, 0xe8, 0xb, 0xf0, 0x72, 0xf1 }, - }, - { - .msglen = 109, - .result = { 0x88, 0xac, 0xe5, 0xe7, 0xdb, 0x26, 0xa5, 0xa5, 0xef, 0x66, 0x92, 0xb4, 0xab, 0x6b, 0xed, 0x4b, 0x1a, 0x9e, 0x19, 0xb0, 0xb6, 0xd6, 0x11, 0xb1, 0x33, 0x40, 0x50, 0x69, 0x48, 0x75, 0x4, 0xe5 }, - }, - { - .msglen = 110, - .result = { 0x7d, 0x25, 0x12, 0x5, 0x37, 0x8c, 0x89, 0x8a, 0x43, 0xd9, 0x97, 0x26, 0xb8, 0xaf, 0xb3, 0x21, 0x4d, 0xde, 0x24, 0x58, 0x4f, 0xc8, 0xd, 0x31, 0x22, 0xb2, 0xdf, 0x34, 0xd5, 0xb, 0x25, 0xb9 }, - }, - { - .msglen = 111, - .result = { 0x4e, 0xfa, 0x3f, 0x64, 0x15, 0xf8, 0xe2, 0xb9, 0x10, 0x70, 0xeb, 0x6a, 0xf6, 0xf2, 0x14, 0x33, 0x0, 0xd1, 0x19, 0xf2, 0x8c, 0x50, 0x57, 0x17, 0xf0, 0xc5, 0x5d, 0xa1, 0xe, 0x22, 0xa0, 0x53 }, - }, - { - .msglen = 112, - .result = { 0x12, 0xac, 0x71, 0xa0, 0x72, 0x7a, 0x45, 0x74, 0x82, 0xf6, 0xde, 0x75, 0xe, 0xb9, 0xb2, 0x65, 0x76, 0x86, 0x13, 0x77, 0x4a, 0x30, 0xbe, 0xfa, 0x1, 0x38, 0x74, 0x49, 0xc9, 0x7f, 0x43, 0x9a }, - }, - { - .msglen = 113, - .result = { 0xfe, 0x25, 0x6b, 0xbf, 0x17, 0x61, 0x29, 0xce, 0x9e, 0xc2, 0x42, 0x9a, 0xb8, 0x29, 0xdb, 0x88, 0xef, 0x75, 0x3b, 0xad, 0xba, 0x9c, 0xd5, 0x9, 0x40, 0x2f, 0x49, 0xbd, 0x3, 0x43, 0xa7, 0x3 }, - }, - { - .msglen = 114, - .result = { 0xe5, 0x36, 0x48, 0xb5, 0x9e, 0xb3, 0x3c, 0x5f, 0x86, 0xab, 0x5, 0xe4, 0xc0, 0xe3, 0x94, 0xe4, 0x4c, 0x90, 0xcd, 0xa1, 0x97, 0x12, 0xdf, 0x33, 0x7a, 0x1a, 0x1e, 0xcd, 0xd4, 0x61, 0xa8, 0x3c }, - }, - { - .msglen = 115, - .result = { 0x52, 0xbd, 0xc6, 0x84, 0x65, 0x32, 0x88, 0x1, 0x85, 0x64, 0xfd, 0xc9, 0x98, 0x18, 0x27, 0x52, 0xe9, 0x30, 0xa2, 0x9e, 0xc2, 0xcf, 0xa9, 0x98, 0xbc, 0x47, 0x3a, 0xc7, 0xd5, 0xb1, 0x81, 0x78 }, - }, - { - .msglen = 116, - .result = { 0xab, 0xb1, 0xb3, 0xa5, 0x23, 0xea, 0x45, 0xe8, 0xe0, 0xa9, 0x3d, 0xe9, 0xe9, 0x86, 0x15, 0x10, 0x90, 0xca, 0xf7, 0xcc, 0x92, 0x64, 0x10, 0x3d, 0x63, 0x2f, 0x17, 0xec, 0x54, 0x9e, 0xbd, 0x3b }, - }, - { - .msglen = 117, - .result = { 0x82, 0xf8, 0x45, 0xcd, 0x8b, 0xfc, 0xd8, 0x81, 0x6b, 0x1f, 0x91, 0x30, 0x6d, 0xbb, 0x91, 0x70, 0x8b, 0xfe, 0x8d, 0x33, 0x35, 0x4f, 0x62, 0x7f, 0xba, 0xb6, 0x99, 0x3b, 0x79, 0xe6, 0x8f, 0x58 }, - }, - { - .msglen = 118, - .result = { 0xa6, 0x59, 0x67, 0x5e, 0x49, 0xe2, 0x95, 0x28, 0xa3, 0x4b, 0x4a, 0x10, 0x20, 0xd1, 0xd6, 0x7b, 0x86, 0x8a, 0x5c, 0x81, 0x31, 0x68, 0xea, 0xb7, 0x61, 0xbb, 0xb6, 0x3a, 0x6d, 0x78, 0xaa, 0x37 }, - }, - { - .msglen = 119, - .result = { 0x64, 0x9, 0xaf, 0x42, 0xff, 0xb1, 0xc7, 0xe6, 0xbf, 0x6f, 0xa1, 0xbb, 0x5a, 0x6, 0xea, 0xd, 0x57, 0x7d, 0x24, 0x41, 0x2b, 0xf9, 0x63, 0x82, 0x1f, 0x9, 0xa5, 0xa7, 0x58, 0xc, 0x4, 0x55 }, - }, - { - .msglen = 120, - .result = { 0x43, 0x33, 0x90, 0x81, 0xb6, 0x23, 0x50, 0xdf, 0xa2, 0x7e, 0x41, 0xa2, 0x40, 0x40, 0xa9, 0x34, 0xd6, 0x5, 0x6c, 0x44, 0x8, 0x3f, 0x2b, 0xaa, 0xff, 0x3, 0xc3, 0x49, 0x1b, 0x15, 0x5e, 0x7c }, - }, - { - .msglen = 121, - .result = { 0xe, 0xd7, 0x6d, 0x29, 0xdd, 0x8, 0xee, 0x2f, 0x1d, 0x5a, 0xb2, 0x70, 0x90, 0x8d, 0xa9, 0xf2, 0x5c, 0x5b, 0xc5, 0xe1, 0x7c, 0xec, 0x49, 0x8f, 0x46, 0x94, 0xe1, 0xc8, 0xd4, 0x68, 0xa2, 0x34 }, - }, - { - .msglen = 122, - .result = { 0x4f, 0x25, 0x61, 0xb1, 0x29, 0xb7, 0x41, 0x50, 0xc7, 0xfa, 0xab, 0x6c, 0x92, 0xff, 0x4, 0xc, 0xa3, 0xa1, 0x10, 0xf6, 0xa6, 0xa4, 0x5a, 0xbf, 0xe, 0x9a, 0x61, 0xa8, 0x24, 0xa3, 0x93, 0x1e }, - }, - { - .msglen = 123, - .result = { 0x7c, 0x8c, 0xf4, 0x5d, 0x45, 0xcf, 0x61, 0x22, 0xc9, 0x8e, 0x3a, 0xeb, 0x85, 0x55, 0x66, 0x2e, 0x1e, 0x33, 0x88, 0xab, 0x74, 0xf2, 0x66, 0x4f, 0x43, 0xfa, 0x3e, 0x25, 0xcc, 0xd2, 0x0, 0x71 }, - }, - { - .msglen = 124, - .result = { 0x8b, 0x51, 0x99, 0x90, 0x84, 0xda, 0x7a, 0xb3, 0xb1, 0x31, 0x1b, 0x1a, 0x66, 0xe2, 0x53, 0xac, 0x45, 0x94, 0x5c, 0xa6, 0x8c, 0x44, 0x45, 0x4, 0x58, 0x13, 0xcb, 0x44, 0x9e, 0x6c, 0x6a, 0x10 }, - }, - { - .msglen = 125, - .result = { 0xc5, 0xb0, 0x36, 0x55, 0x4d, 0x15, 0xf0, 0x67, 0xf8, 0x26, 0x45, 0x48, 0xa7, 0x65, 0xcc, 0xa8, 0x14, 0x1e, 0x63, 0x22, 0x36, 0xc3, 0xf3, 0x99, 0x5b, 0x77, 0xb2, 0xa8, 0xc3, 0x62, 0xb4, 0xdd }, - }, - { - .msglen = 126, - .result = { 0x38, 0xcb, 0x97, 0x81, 0x62, 0xde, 0x32, 0x5f, 0xc5, 0x27, 0x39, 0x82, 0x36, 0x77, 0x5a, 0xc4, 0xbf, 0x45, 0xf4, 0xe8, 0x17, 0xa9, 0x17, 0xfc, 0x34, 0xb, 0xa1, 0x11, 0x79, 0xf5, 0xc, 0x79 }, - }, - { - .msglen = 127, - .result = { 0x2e, 0x16, 0xab, 0xf4, 0x56, 0xea, 0x6a, 0x7e, 0x97, 0x25, 0xf9, 0x9a, 0x0, 0x5d, 0xe3, 0x70, 0x76, 0xa9, 0x2a, 0xab, 0xae, 0x32, 0xe5, 0xe8, 0xb6, 0xe1, 0x22, 0xc8, 0x74, 0xe1, 0x1f, 0x22 }, - }, - { - .msglen = 128, - .result = { 0x6e, 0x54, 0xeb, 0x50, 0x85, 0x7b, 0xd2, 0x64, 0x32, 0x2c, 0xb0, 0xd0, 0xc2, 0x3, 0x31, 0x95, 0xa8, 0x6a, 0x50, 0x49, 0xf4, 0x77, 0x27, 0x1a, 0x89, 0x10, 0x3e, 0x98, 0x45, 0x1e, 0xe7, 0xeb }, - }, - { - .msglen = 129, - .result = { 0x7, 0x2e, 0xdf, 0xe9, 0x2e, 0x73, 0xf4, 0x1e, 0x65, 0x31, 0x64, 0x25, 0xc1, 0x59, 0x46, 0xd7, 0xf9, 0x12, 0xfe, 0xc7, 0x9f, 0x24, 0xa, 0xd9, 0xfb, 0x8, 0xcb, 0x5f, 0xf2, 0x77, 0x11, 0xce }, - }, - { - .msglen = 130, - .result = { 0x6, 0x46, 0xc7, 0x42, 0xc2, 0xc3, 0xf2, 0x4c, 0x82, 0x7d, 0x1c, 0x2c, 0x68, 0xfd, 0x29, 0x6d, 0xc2, 0xac, 0x4f, 0xbc, 0x8d, 0xb2, 0xf7, 0x78, 0xb7, 0x8f, 0x4, 0x3f, 0x49, 0xb5, 0xc5, 0xd }, - }, - { - .msglen = 131, - .result = { 0x9c, 0x1f, 0xdb, 0x89, 0x3b, 0x8b, 0x5c, 0x3d, 0x1e, 0xd2, 0x9f, 0x74, 0x63, 0xb, 0x4f, 0x59, 0x72, 0x13, 0x4f, 0x40, 0x59, 0x35, 0xc6, 0x64, 0x5a, 0xb5, 0x43, 0xaf, 0x43, 0x7a, 0x13, 0xb0 }, - }, - { - .msglen = 132, - .result = { 0x25, 0xa9, 0x97, 0x9e, 0x4f, 0x52, 0xe6, 0xe7, 0xf, 0x38, 0xc6, 0xfb, 0x9e, 0x77, 0xe7, 0x1c, 0xb9, 0x8a, 0xf3, 0x4d, 0x76, 0xb3, 0x58, 0x8e, 0xab, 0x7d, 0xd6, 0xbb, 0x78, 0x26, 0xb1, 0x7f }, - }, - { - .msglen = 133, - .result = { 0x2b, 0x8, 0xfa, 0x23, 0x7d, 0xb2, 0xa1, 0x16, 0x85, 0x7b, 0x3c, 0xa4, 0xde, 0x19, 0xf7, 0x81, 0xb6, 0xaf, 0xbc, 0x11, 0x31, 0x10, 0x6f, 0x14, 0x4a, 0x62, 0x48, 0x1e, 0x43, 0x95, 0xa4, 0xb4 }, - }, - { - .msglen = 134, - .result = { 0x9c, 0x93, 0x30, 0x3f, 0x4c, 0x8f, 0xa7, 0x56, 0xd1, 0x6c, 0x9a, 0x28, 0xa1, 0x21, 0x7d, 0x5b, 0x12, 0x6b, 0x5a, 0xd4, 0xb9, 0x62, 0x5, 0xe2, 0xd5, 0xc8, 0x2a, 0xd1, 0xb0, 0x46, 0x2a, 0x2c }, - }, - { - .msglen = 135, - .result = { 0xd7, 0x17, 0xd, 0xc0, 0x46, 0x24, 0x9e, 0x14, 0x21, 0xac, 0xf3, 0xd0, 0xda, 0xf4, 0xd9, 0xf1, 0xf2, 0x96, 0xbd, 0x55, 0xff, 0x3c, 0x8d, 0x90, 0xc8, 0x2f, 0x1e, 0x87, 0xad, 0xd7, 0x8a, 0x8a }, - }, - { - .msglen = 136, - .result = { 0x90, 0xd6, 0xa4, 0x46, 0x75, 0x8c, 0xc3, 0xda, 0x26, 0x8a, 0xe1, 0xb7, 0xa4, 0xe, 0xef, 0x33, 0x65, 0x41, 0xa3, 0x60, 0x6a, 0xce, 0xfb, 0xc4, 0x1c, 0xa4, 0x95, 0x6d, 0x43, 0x49, 0x69, 0xd5 }, - }, - { - .msglen = 137, - .result = { 0xd6, 0xf5, 0xfe, 0xb0, 0x9a, 0xca, 0xec, 0xeb, 0xbe, 0x4b, 0xbd, 0x96, 0x65, 0xfe, 0x65, 0x31, 0xef, 0x36, 0x3a, 0xfc, 0x3a, 0x8, 0x3, 0xb0, 0xbf, 0xeb, 0xd, 0x2c, 0xd9, 0x27, 0x14, 0x4f }, - }, - { - .msglen = 138, - .result = { 0x97, 0x4f, 0x86, 0x11, 0xf9, 0x61, 0xad, 0xc, 0xba, 0x2d, 0xfa, 0xa4, 0x6f, 0x19, 0xb3, 0x66, 0xf8, 0xcc, 0x74, 0x2c, 0x76, 0x29, 0xdd, 0x6b, 0x5, 0xa3, 0x3a, 0x3b, 0xa6, 0xec, 0x81, 0xc0 }, - }, - { - .msglen = 139, - .result = { 0x9a, 0xe3, 0xc, 0x22, 0x5d, 0xb3, 0x71, 0x5d, 0x30, 0xcf, 0x6, 0xc1, 0x86, 0xf6, 0x84, 0xac, 0x25, 0x45, 0xb2, 0xa0, 0xd2, 0x93, 0x8b, 0x9e, 0x77, 0x55, 0x16, 0x51, 0x61, 0x4a, 0x91, 0xcd }, - }, - { - .msglen = 140, - .result = { 0xf1, 0x30, 0xf4, 0xc7, 0x6c, 0xe3, 0x8d, 0x63, 0x41, 0x62, 0x64, 0xe1, 0xc3, 0x97, 0xf0, 0xd6, 0xf3, 0xfd, 0x17, 0xe, 0xca, 0xd8, 0x9e, 0x6d, 0xa0, 0xa1, 0x27, 0x60, 0xff, 0xf, 0x7a, 0xca }, - }, - { - .msglen = 141, - .result = { 0x5, 0xab, 0x87, 0x58, 0xa8, 0x5e, 0x7d, 0xec, 0x23, 0x90, 0xd8, 0xfa, 0x87, 0x1, 0x4b, 0x32, 0xe9, 0x0, 0x7b, 0x92, 0x3b, 0x51, 0x44, 0x86, 0xa2, 0x55, 0xf0, 0xb7, 0x13, 0x3b, 0x58, 0x70 }, - }, - { - .msglen = 142, - .result = { 0xff, 0x4e, 0x8a, 0xca, 0xce, 0xe0, 0x84, 0x2a, 0x70, 0x82, 0x52, 0x1e, 0x67, 0xc, 0x67, 0x36, 0x76, 0x74, 0xed, 0x49, 0x21, 0x44, 0x0, 0x1a, 0x75, 0xcd, 0x4f, 0x17, 0xb8, 0xa9, 0xdf, 0xb9 }, - }, - { - .msglen = 143, - .result = { 0xf2, 0x36, 0x6f, 0xf3, 0x8e, 0xf3, 0xbd, 0x51, 0xec, 0xc4, 0x96, 0xc1, 0x88, 0xfe, 0x68, 0x5e, 0x1b, 0xdf, 0x71, 0x6b, 0xf3, 0x78, 0x84, 0x16, 0x11, 0xac, 0x37, 0x4d, 0x8f, 0x6e, 0x7b, 0x40 }, - }, - { - .msglen = 144, - .result = { 0x24, 0x20, 0x1d, 0x2, 0x16, 0x1, 0xc4, 0xe5, 0xdf, 0x81, 0xca, 0xa9, 0xf2, 0x4d, 0xe2, 0x77, 0x11, 0xf6, 0x43, 0xd3, 0x36, 0x36, 0x1c, 0xe6, 0x6c, 0x96, 0xc9, 0x74, 0x8e, 0x39, 0x1c, 0xb1 }, - }, - { - .msglen = 145, - .result = { 0xfc, 0x13, 0x13, 0x5c, 0x87, 0x9a, 0x95, 0xcd, 0x66, 0xac, 0x85, 0xda, 0x8c, 0x28, 0x38, 0x3f, 0x43, 0xe1, 0x40, 0x8e, 0x8f, 0x49, 0x17, 0xda, 0x75, 0xd0, 0xc4, 0xf5, 0x9e, 0x3, 0xf0, 0x62 }, - }, - { - .msglen = 146, - .result = { 0xcc, 0x3e, 0x74, 0x6a, 0x82, 0xb0, 0x67, 0x77, 0xcf, 0x6e, 0x93, 0x40, 0x84, 0xc7, 0xa1, 0x85, 0xa5, 0x38, 0x23, 0xa5, 0x4f, 0x9e, 0xee, 0x3d, 0xa7, 0xab, 0x88, 0x3b, 0x3, 0x1d, 0xdb, 0xbd }, - }, - { - .msglen = 147, - .result = { 0xaa, 0x4f, 0x52, 0xf0, 0xe8, 0x49, 0x80, 0x5e, 0xe4, 0xd4, 0x8f, 0xc1, 0x5c, 0x7d, 0x36, 0x2, 0xdb, 0xda, 0x45, 0xab, 0x6e, 0x90, 0xc1, 0x55, 0x4f, 0x8, 0xaf, 0x55, 0x4d, 0x45, 0x6b, 0x91 }, - }, - { - .msglen = 148, - .result = { 0xfb, 0x92, 0xef, 0x68, 0xc4, 0xa, 0xd9, 0xd8, 0x86, 0xb5, 0x63, 0x34, 0xa7, 0x42, 0x5a, 0xef, 0x13, 0xc0, 0xc9, 0x44, 0x8f, 0x9e, 0x40, 0x51, 0x1b, 0xcf, 0xbb, 0x8c, 0xb0, 0x2c, 0x56, 0xc }, - }, - { - .msglen = 149, - .result = { 0x88, 0xdb, 0x71, 0x51, 0x85, 0x63, 0xb6, 0xb4, 0xeb, 0x7c, 0x11, 0xaa, 0x96, 0x8, 0x9e, 0x60, 0x70, 0xa5, 0x19, 0xa4, 0x2, 0xf1, 0xa0, 0x4f, 0x16, 0xde, 0xd6, 0x8d, 0xd3, 0xc5, 0xc, 0x6c }, - }, - { - .msglen = 150, - .result = { 0x4a, 0xad, 0x96, 0xea, 0x90, 0xb7, 0x76, 0x9d, 0x92, 0x60, 0x35, 0x59, 0x1c, 0x89, 0x67, 0x54, 0xfd, 0x50, 0x20, 0x97, 0xc8, 0x16, 0xc8, 0xc2, 0x50, 0x40, 0x63, 0xba, 0xfb, 0xbc, 0x5e, 0xcd }, - }, - { - .msglen = 151, - .result = { 0xca, 0x4c, 0x3d, 0x26, 0x75, 0x82, 0x48, 0x5b, 0xa4, 0xd3, 0x28, 0x9, 0x8d, 0xe0, 0x67, 0x6d, 0xe1, 0x5, 0x8a, 0xbf, 0x17, 0xbb, 0x6e, 0x48, 0x2e, 0xd, 0xcd, 0x90, 0x7c, 0x4e, 0xa4, 0x94 }, - }, - { - .msglen = 152, - .result = { 0x6d, 0x27, 0x5e, 0x91, 0xeb, 0xc7, 0x1a, 0x31, 0x42, 0xfa, 0x2c, 0x91, 0xdc, 0x6a, 0xdc, 0x1b, 0x2b, 0x66, 0xf2, 0x9a, 0xf6, 0x11, 0x36, 0x96, 0x2a, 0xfc, 0x73, 0x89, 0x7e, 0xd4, 0x55, 0x3d }, - }, - { - .msglen = 153, - .result = { 0x76, 0xba, 0x1d, 0x4b, 0xc1, 0xa2, 0x1b, 0x56, 0xbe, 0x5, 0x38, 0x90, 0x47, 0xe9, 0x9, 0xc2, 0xd1, 0x2, 0x6d, 0x44, 0x81, 0xf7, 0x6e, 0x28, 0x88, 0x79, 0xb5, 0x10, 0x75, 0xfb, 0xc6, 0xe7 }, - }, - { - .msglen = 154, - .result = { 0x6d, 0xbc, 0x90, 0xa6, 0x2f, 0xb5, 0x45, 0x5f, 0x4a, 0xcb, 0x85, 0x32, 0x90, 0x57, 0x86, 0x75, 0x51, 0xa5, 0x7e, 0x4b, 0x6b, 0xb3, 0xeb, 0xfe, 0xba, 0x75, 0xfc, 0x55, 0x1a, 0x85, 0x3, 0x54 }, - }, - { - .msglen = 155, - .result = { 0x7d, 0x59, 0x19, 0xb6, 0xf2, 0x7f, 0x7, 0x7a, 0xaa, 0xf7, 0xdf, 0x2e, 0x2d, 0xfb, 0x57, 0x14, 0xd6, 0x9f, 0x9c, 0xcc, 0x56, 0x88, 0xe, 0x85, 0xcc, 0x30, 0x6, 0x32, 0x1f, 0x70, 0x47, 0x59 }, - }, - { - .msglen = 156, - .result = { 0xea, 0xfa, 0x44, 0x81, 0x83, 0xec, 0x2d, 0x63, 0xa6, 0xea, 0xf0, 0x6, 0x5d, 0x15, 0x32, 0x89, 0xed, 0x52, 0xf, 0x23, 0x66, 0x8b, 0x1c, 0x7c, 0x13, 0xd0, 0x35, 0xc1, 0x7d, 0x27, 0xfe, 0x80 }, - }, - { - .msglen = 157, - .result = { 0xab, 0x31, 0xe1, 0x44, 0x3d, 0x3a, 0xf5, 0x6a, 0x8b, 0x5d, 0xa6, 0xd5, 0x63, 0x23, 0x7e, 0x17, 0x24, 0xc9, 0x41, 0x53, 0x86, 0x90, 0xb7, 0x6f, 0xbc, 0x39, 0x5d, 0x1b, 0x19, 0xd9, 0xef, 0x9c }, - }, - { - .msglen = 158, - .result = { 0x3e, 0x34, 0xec, 0xd9, 0x26, 0xe7, 0x27, 0x3b, 0xc5, 0xc3, 0x8e, 0x11, 0xba, 0x58, 0xcf, 0x2b, 0x29, 0xc4, 0x49, 0xfc, 0xf6, 0x9d, 0xcc, 0x2a, 0x0, 0xff, 0xe6, 0xbc, 0x7d, 0x2a, 0x48, 0x22 }, - }, - { - .msglen = 159, - .result = { 0xc8, 0x59, 0x27, 0xa2, 0x58, 0x9e, 0xfe, 0x8c, 0x5a, 0x7f, 0x99, 0xd0, 0x58, 0xd4, 0x8c, 0xae, 0xa9, 0x4, 0x24, 0x50, 0x34, 0x23, 0x45, 0xfe, 0x87, 0xa7, 0x53, 0x5a, 0x27, 0x9d, 0x1b, 0x4f }, - }, - { - .msglen = 160, - .result = { 0xd7, 0x76, 0xaa, 0x3b, 0x97, 0x5e, 0xac, 0xbe, 0x46, 0x45, 0x80, 0x8e, 0x2c, 0xa2, 0xe1, 0xd4, 0x75, 0xb5, 0xe0, 0xd2, 0x4c, 0x59, 0xf0, 0xc3, 0xe8, 0x8c, 0x96, 0xbd, 0x85, 0x23, 0x8b, 0x40 }, - }, - { - .msglen = 161, - .result = { 0x40, 0x8e, 0xa5, 0xbd, 0x32, 0x7, 0x19, 0xc8, 0x31, 0x22, 0x32, 0xdf, 0xe0, 0xf5, 0xe2, 0x5f, 0x91, 0xf4, 0x95, 0x7a, 0xa7, 0x91, 0x9d, 0xed, 0x35, 0x2f, 0x0, 0x4, 0x62, 0x63, 0x4, 0x80 }, - }, - { - .msglen = 162, - .result = { 0xa6, 0x1b, 0x63, 0x3, 0xbf, 0x2, 0xbd, 0xbb, 0x69, 0x1b, 0xac, 0x54, 0x99, 0xee, 0x8b, 0xe, 0xb, 0x41, 0x78, 0xda, 0x8f, 0x72, 0x97, 0xdf, 0x9, 0xfa, 0x35, 0xe1, 0x8a, 0xb3, 0x80, 0xc3 }, - }, - { - .msglen = 163, - .result = { 0x7d, 0xd3, 0x5e, 0x1a, 0x9, 0x94, 0x6e, 0x30, 0xc6, 0xbb, 0xda, 0xe7, 0x92, 0x49, 0xf6, 0x37, 0xe, 0xb3, 0x30, 0x96, 0xb2, 0xaf, 0x57, 0x22, 0xe4, 0x8d, 0x9f, 0x83, 0x51, 0xbf, 0x98, 0xb0 }, - }, - { - .msglen = 164, - .result = { 0x3e, 0x10, 0xe4, 0x81, 0xa2, 0x1d, 0x92, 0x7a, 0x1a, 0x73, 0xfe, 0xd4, 0x8b, 0x28, 0x4c, 0x85, 0xcc, 0xfe, 0xe0, 0x4f, 0x55, 0xfd, 0x47, 0x95, 0x1f, 0x1b, 0x60, 0x38, 0x7, 0xe9, 0xc9, 0x4f }, - }, - { - .msglen = 165, - .result = { 0x75, 0x68, 0x14, 0xf8, 0x3c, 0x94, 0x2b, 0xe9, 0x6c, 0x49, 0xfc, 0x77, 0xa8, 0x6a, 0x5d, 0xf6, 0x4e, 0x45, 0xa0, 0x45, 0x2c, 0xfc, 0xec, 0xb1, 0xaf, 0xf5, 0x77, 0x6d, 0xbf, 0x96, 0x2b, 0x88 }, - }, - { - .msglen = 166, - .result = { 0x81, 0x1e, 0x33, 0x1c, 0xeb, 0xcf, 0x34, 0x58, 0x18, 0xa7, 0x2c, 0x60, 0x9, 0x36, 0x6e, 0xba, 0x46, 0x27, 0xee, 0x25, 0x60, 0xa9, 0x9f, 0x90, 0x4, 0x65, 0xa6, 0x92, 0x48, 0x4a, 0xf7, 0x1b }, - }, - { - .msglen = 167, - .result = { 0xdc, 0x3d, 0x6, 0x9e, 0x2c, 0x8c, 0x2d, 0x84, 0xf7, 0x97, 0xa, 0xeb, 0xe3, 0x68, 0xa7, 0x59, 0x3d, 0xa, 0xba, 0x6f, 0xfb, 0x11, 0x5a, 0xf8, 0x99, 0xae, 0x84, 0x1f, 0x43, 0xf8, 0xfd, 0xac }, - }, - { - .msglen = 168, - .result = { 0x4e, 0xd7, 0x72, 0x7d, 0xfe, 0x4d, 0x8a, 0x9a, 0xfa, 0x39, 0xb7, 0x74, 0x83, 0x61, 0xd5, 0xb6, 0xd1, 0x56, 0x88, 0xe7, 0x85, 0x15, 0xcf, 0x2d, 0x91, 0x73, 0xa4, 0xc9, 0xad, 0x76, 0x47, 0x2f }, - }, - { - .msglen = 169, - .result = { 0x33, 0x25, 0x94, 0xbc, 0xa4, 0xd, 0x39, 0x84, 0x4a, 0xe5, 0x30, 0x1f, 0x70, 0x41, 0xf0, 0xa7, 0x6d, 0x52, 0x3f, 0xa9, 0x17, 0x83, 0x46, 0xe, 0x26, 0x77, 0xe9, 0xfd, 0xe, 0x46, 0x21, 0xee }, - }, - { - .msglen = 170, - .result = { 0x84, 0xb8, 0x3c, 0x8d, 0x89, 0xd6, 0x55, 0x75, 0xbd, 0x5d, 0xcb, 0x76, 0xfe, 0x42, 0x98, 0xf9, 0xff, 0x8b, 0x4d, 0xe6, 0xe8, 0xd6, 0x1f, 0x37, 0xa6, 0xe0, 0xa8, 0x37, 0x28, 0xed, 0xf4, 0x38 }, - }, - { - .msglen = 171, - .result = { 0xf, 0x48, 0x6c, 0x1f, 0x99, 0x6d, 0x3c, 0x11, 0xd9, 0x7a, 0x33, 0xa, 0xdf, 0xb1, 0xa3, 0x59, 0x3f, 0xe3, 0xf0, 0x3, 0xab, 0x5e, 0x3f, 0x68, 0xe5, 0xa5, 0xd1, 0xbb, 0x8, 0x85, 0x50, 0x45 }, - }, - { - .msglen = 172, - .result = { 0x58, 0x25, 0xc1, 0x9e, 0x9d, 0x79, 0xa9, 0x71, 0xe7, 0xc5, 0x6, 0x8d, 0x23, 0x65, 0xf4, 0xbc, 0x9e, 0xa8, 0xab, 0xcc, 0x2f, 0x93, 0xac, 0x64, 0xb5, 0x6d, 0x28, 0x34, 0xe, 0x78, 0x9a, 0xfa }, - }, - { - .msglen = 173, - .result = { 0x10, 0xc6, 0xca, 0x3a, 0xc9, 0xe3, 0x82, 0x6e, 0x76, 0x5b, 0x8d, 0x42, 0x56, 0x4c, 0xc5, 0xf2, 0x2c, 0xaa, 0x95, 0x4, 0xc4, 0xef, 0x5f, 0xda, 0x10, 0xd3, 0x77, 0x9b, 0xc5, 0x95, 0x72, 0x14 }, - }, - { - .msglen = 174, - .result = { 0x7b, 0x64, 0xa, 0x83, 0xbf, 0x35, 0x85, 0xbf, 0xc2, 0xee, 0xdd, 0x95, 0xca, 0x5c, 0xa0, 0xee, 0xca, 0xa2, 0xb8, 0x33, 0xc1, 0x7d, 0xf3, 0x4d, 0x35, 0x2e, 0x27, 0xb8, 0x56, 0x5, 0x7a, 0x73 }, - }, - { - .msglen = 175, - .result = { 0xdb, 0x32, 0x29, 0x7c, 0xfd, 0xa5, 0x91, 0xae, 0x9b, 0xb0, 0xbd, 0xb4, 0x34, 0x4f, 0x60, 0x98, 0x65, 0x35, 0xe4, 0x60, 0xf8, 0x8b, 0x57, 0x47, 0x55, 0x14, 0xa4, 0x5e, 0xcc, 0xa6, 0xbd, 0xf4 }, - }, - { - .msglen = 176, - .result = { 0x7c, 0x6f, 0xd4, 0x3f, 0xd0, 0xa7, 0x7d, 0xd5, 0x34, 0xe0, 0x8d, 0x91, 0x5d, 0xbe, 0x92, 0xb8, 0x67, 0xbe, 0xf5, 0x80, 0xa4, 0xd5, 0x1b, 0x86, 0x12, 0xa7, 0x6, 0x43, 0x1c, 0x61, 0xa3, 0xd5 }, - }, - { - .msglen = 177, - .result = { 0x39, 0x4e, 0x86, 0xdf, 0xbd, 0x7f, 0x6a, 0x8d, 0xe7, 0x55, 0xce, 0x4b, 0x69, 0x90, 0xbc, 0x20, 0xf7, 0xd1, 0xba, 0x93, 0x2b, 0x57, 0x16, 0x5d, 0xc3, 0x16, 0xa, 0xf3, 0x62, 0x7, 0x66, 0xac }, - }, - { - .msglen = 178, - .result = { 0x5f, 0xfd, 0x40, 0x99, 0xa8, 0xdc, 0xe5, 0x2, 0x9e, 0x36, 0xf, 0x5d, 0x47, 0x53, 0xe4, 0x48, 0xcf, 0xd5, 0x5f, 0xd5, 0x29, 0x95, 0x5d, 0x92, 0x6d, 0x41, 0x22, 0x7d, 0x10, 0x8a, 0xc9, 0x88 }, - }, - { - .msglen = 179, - .result = { 0x58, 0x91, 0x6b, 0x40, 0x4d, 0x99, 0xf7, 0x78, 0xa5, 0xc7, 0x62, 0x49, 0x6c, 0x37, 0xd5, 0x90, 0x93, 0x3c, 0x59, 0x34, 0x36, 0xd1, 0x97, 0xcd, 0x85, 0x7d, 0x7a, 0x6d, 0x65, 0xce, 0x7f, 0xdb }, - }, - { - .msglen = 180, - .result = { 0x86, 0xc3, 0xa0, 0xa4, 0x46, 0x8a, 0xa8, 0x69, 0x8e, 0x6d, 0x5e, 0x79, 0x9f, 0xca, 0x9c, 0x2a, 0x94, 0xb0, 0xf8, 0x3f, 0xad, 0xa0, 0xfc, 0x50, 0x68, 0x39, 0x6c, 0xb5, 0xfc, 0x31, 0xaf, 0x74 }, - }, - { - .msglen = 181, - .result = { 0xce, 0x7, 0x9, 0x65, 0x72, 0xf3, 0x8c, 0x51, 0x6b, 0xf7, 0x2d, 0x46, 0xfc, 0xbc, 0xa6, 0xdd, 0x75, 0xe4, 0xd9, 0x54, 0x70, 0xcd, 0xa5, 0x5c, 0xa1, 0xb6, 0xd4, 0x3a, 0xe5, 0x4c, 0x18, 0x9e }, - }, - { - .msglen = 182, - .result = { 0x96, 0xbc, 0xcc, 0xbd, 0xb5, 0xf8, 0xd7, 0xef, 0xc7, 0x85, 0x44, 0x89, 0x6b, 0xd5, 0xbf, 0x78, 0xb7, 0x9d, 0xde, 0xf8, 0x72, 0xd1, 0xd9, 0xb3, 0xb0, 0xfd, 0x7f, 0x4e, 0x2a, 0xaa, 0x3d, 0x7c }, - }, - { - .msglen = 183, - .result = { 0x0, 0xdf, 0xb9, 0xd2, 0x99, 0x8e, 0x5c, 0xed, 0x85, 0x8b, 0x3d, 0x35, 0xdf, 0x35, 0x8c, 0x82, 0x3a, 0x20, 0x36, 0x60, 0x48, 0x7e, 0x9e, 0x8b, 0x60, 0xf9, 0x88, 0xb1, 0x8d, 0x5c, 0x41, 0xef }, - }, - { - .msglen = 184, - .result = { 0x99, 0xdf, 0xe5, 0xf6, 0xdf, 0xb3, 0x88, 0x88, 0x45, 0x34, 0x4a, 0x61, 0xc8, 0x87, 0x49, 0x20, 0xdf, 0xe0, 0x84, 0x5b, 0x35, 0xfe, 0x8c, 0xf8, 0x4a, 0x9c, 0xb1, 0x2d, 0x30, 0x5f, 0xfe, 0x3c }, - }, - { - .msglen = 185, - .result = { 0xfc, 0x53, 0x78, 0x1f, 0x4d, 0x43, 0xf4, 0xe9, 0xdc, 0x74, 0x8, 0xc3, 0xb5, 0xfc, 0x82, 0x88, 0x53, 0x25, 0xc, 0x81, 0x14, 0xa7, 0xff, 0xff, 0x9f, 0xda, 0xc8, 0x45, 0x38, 0x71, 0xdc, 0xd9 }, - }, - { - .msglen = 186, - .result = { 0xa5, 0x3f, 0x40, 0x24, 0x78, 0x12, 0xfc, 0xa7, 0x5b, 0x8a, 0xea, 0x5f, 0x83, 0xf9, 0x42, 0xc6, 0x21, 0xd, 0xa1, 0x46, 0x3, 0x3a, 0x62, 0xb9, 0x39, 0x39, 0xad, 0x6d, 0x70, 0x8e, 0xa2, 0x97 }, - }, - { - .msglen = 187, - .result = { 0x52, 0x23, 0x8a, 0xe, 0x32, 0xd5, 0x99, 0xd2, 0x7e, 0x77, 0x89, 0x70, 0x75, 0xdf, 0xf1, 0x90, 0x92, 0x1d, 0x14, 0xf7, 0xea, 0xa9, 0xdf, 0x5, 0x72, 0xf5, 0x8a, 0xd0, 0xdc, 0xee, 0x40, 0xd0 }, - }, - { - .msglen = 188, - .result = { 0x56, 0x86, 0xee, 0xbb, 0xde, 0xcc, 0x9d, 0xb2, 0x26, 0xa7, 0xb4, 0xef, 0x3d, 0x3f, 0x3e, 0x7d, 0xe3, 0x27, 0xea, 0x79, 0xd5, 0x82, 0x8f, 0x2f, 0x44, 0xa0, 0xe1, 0x4c, 0x67, 0xa6, 0x6b, 0x8f }, - }, - { - .msglen = 189, - .result = { 0xc0, 0x4c, 0xf2, 0x5c, 0x93, 0x4b, 0x36, 0xcb, 0xff, 0xc2, 0x15, 0x9, 0x77, 0x2f, 0xc1, 0xb0, 0x9, 0x98, 0x2b, 0x48, 0x3e, 0xcf, 0x6f, 0x4f, 0xe, 0x7d, 0xd9, 0xae, 0xdb, 0xeb, 0xd8, 0xe1 }, - }, - { - .msglen = 190, - .result = { 0x1f, 0xf1, 0x1c, 0x2c, 0x4e, 0xd0, 0x9c, 0x5e, 0x8e, 0xb4, 0x71, 0x88, 0xc8, 0xcc, 0xd8, 0x4b, 0x25, 0x6d, 0xad, 0xe7, 0x6d, 0x8d, 0x3b, 0x4d, 0x3a, 0xe9, 0xd, 0xa7, 0x69, 0xa8, 0x98, 0xde }, - }, - { - .msglen = 191, - .result = { 0x27, 0x4, 0x31, 0x8, 0x73, 0xf1, 0x5f, 0x15, 0x61, 0x2c, 0x62, 0x49, 0xa9, 0xe8, 0x11, 0xf3, 0xac, 0x54, 0x48, 0x98, 0x62, 0xf2, 0x7d, 0xd6, 0x12, 0xcf, 0x4, 0x1, 0x4e, 0xa9, 0x24, 0xc8 }, - }, - { - .msglen = 192, - .result = { 0xe4, 0x39, 0x59, 0x7e, 0x60, 0x5a, 0x45, 0x4b, 0x89, 0xa8, 0x97, 0x74, 0xfe, 0xb7, 0xeb, 0xd5, 0x6, 0xdb, 0xdc, 0x4d, 0x85, 0x3a, 0x38, 0x4c, 0x5e, 0x74, 0x86, 0xeb, 0xf0, 0xc4, 0x5, 0x32 }, - }, - { - .msglen = 193, - .result = { 0x9a, 0x14, 0xf6, 0x6f, 0xce, 0x82, 0xa0, 0xbb, 0xde, 0xb8, 0x24, 0x2b, 0xaf, 0xae, 0x18, 0xd4, 0xbb, 0x45, 0x9e, 0xe4, 0x87, 0x3b, 0x35, 0xca, 0xeb, 0x37, 0xd1, 0x52, 0x6, 0x6e, 0x84, 0x3b }, - }, - { - .msglen = 194, - .result = { 0x64, 0x9f, 0xab, 0x84, 0xaf, 0x83, 0xa6, 0xcb, 0x23, 0x0, 0xd5, 0x4c, 0xd3, 0x76, 0x4b, 0x57, 0x76, 0x70, 0xdb, 0xea, 0x3a, 0xcb, 0xb7, 0x9c, 0x16, 0x80, 0xbf, 0x66, 0x2b, 0x56, 0xc, 0x2c }, - }, - { - .msglen = 195, - .result = { 0xab, 0xa8, 0x11, 0x2b, 0x2, 0x99, 0xb0, 0x15, 0x36, 0x4d, 0x5b, 0x5d, 0x55, 0xc3, 0xa5, 0xbc, 0x70, 0x9, 0x36, 0xd9, 0x9f, 0xfe, 0x49, 0x3d, 0x5a, 0x2b, 0x8d, 0x69, 0xe2, 0x6, 0x1a, 0x6f }, - }, - { - .msglen = 196, - .result = { 0xd7, 0x6b, 0x15, 0x6c, 0xc1, 0x21, 0x84, 0x78, 0x7c, 0x5e, 0xbe, 0x16, 0x70, 0xe2, 0x83, 0x7f, 0x2c, 0x3, 0x5f, 0xb9, 0x2f, 0x17, 0x46, 0xb0, 0x5a, 0xaf, 0xac, 0x2b, 0x80, 0xcf, 0xa5, 0x9c }, - }, - { - .msglen = 197, - .result = { 0x15, 0x9c, 0x70, 0x75, 0x5a, 0x4e, 0xd2, 0x94, 0x7b, 0x6, 0xe8, 0xdd, 0x55, 0x21, 0xe9, 0x1b, 0x97, 0xe, 0x95, 0x5b, 0x18, 0xa7, 0x26, 0xc0, 0x0, 0xed, 0xe7, 0x55, 0xc8, 0x3d, 0xf3, 0xe7 }, - }, - { - .msglen = 198, - .result = { 0x2c, 0xdf, 0x2e, 0x88, 0xf, 0xee, 0xcf, 0x19, 0x1e, 0x72, 0x8b, 0x15, 0x7d, 0x18, 0xa1, 0xcf, 0x6, 0xa6, 0xc2, 0xec, 0x35, 0xe5, 0x2a, 0x0, 0x7f, 0x75, 0x9b, 0x63, 0x99, 0x9e, 0x2f, 0x66 }, - }, - { - .msglen = 199, - .result = { 0x28, 0xeb, 0xc7, 0x79, 0x5d, 0x7c, 0x29, 0xb9, 0x8a, 0xe8, 0x7b, 0xe4, 0x74, 0x3d, 0x3a, 0x74, 0xab, 0x2e, 0x67, 0xde, 0xe4, 0x28, 0x1b, 0xd0, 0xe3, 0x1b, 0xc9, 0xd0, 0xc0, 0x6c, 0xda, 0xba }, - }, - { - .msglen = 200, - .result = { 0x72, 0x17, 0x1e, 0xca, 0x67, 0xed, 0x83, 0xe9, 0x8d, 0x9b, 0x44, 0xe, 0xd4, 0x27, 0x2c, 0x6b, 0x7d, 0xe2, 0x22, 0x54, 0xf3, 0x72, 0xd1, 0x2, 0xaf, 0x47, 0x20, 0xc0, 0x47, 0x8a, 0x5, 0x9c }, - }, - { - .msglen = 201, - .result = { 0xb8, 0x2c, 0xea, 0xd9, 0xc4, 0x17, 0x66, 0xa6, 0x5a, 0xc1, 0xb8, 0x24, 0xf5, 0x5e, 0x1a, 0x2c, 0x85, 0xf0, 0xa3, 0xcd, 0xd3, 0x7e, 0xfa, 0x23, 0xd2, 0x90, 0x4f, 0xf3, 0x55, 0xfa, 0x17, 0x5c }, - }, - { - .msglen = 202, - .result = { 0x9d, 0x7f, 0x23, 0x8c, 0x92, 0xe5, 0x37, 0xb, 0xc7, 0x97, 0xa4, 0x68, 0xe5, 0xc, 0xd8, 0xfe, 0xb0, 0x4d, 0xc7, 0x79, 0x25, 0xd, 0xe6, 0xa6, 0xe6, 0x4, 0xc5, 0xfd, 0x2d, 0x25, 0x3f, 0xd2 }, - }, - { - .msglen = 203, - .result = { 0xdf, 0xdf, 0x13, 0xc0, 0x82, 0x73, 0x7b, 0xec, 0x2a, 0x4d, 0x9e, 0x62, 0xfc, 0x88, 0xa9, 0x47, 0xfd, 0x47, 0x59, 0xf2, 0x58, 0x5, 0xf9, 0x2e, 0xce, 0x5b, 0x1, 0xae, 0x37, 0x9e, 0xa8, 0x3f }, - }, - { - .msglen = 204, - .result = { 0x60, 0x10, 0x29, 0xc3, 0x82, 0x91, 0x8b, 0x74, 0xa5, 0x6a, 0x3f, 0x6a, 0x76, 0xaf, 0x50, 0x9e, 0xf1, 0x38, 0xf5, 0xd2, 0xdc, 0xe5, 0x5a, 0x3d, 0xa9, 0x8a, 0x56, 0xca, 0xeb, 0x57, 0x79, 0x5a }, - }, - { - .msglen = 205, - .result = { 0xd2, 0x71, 0x22, 0xe1, 0x91, 0x69, 0x5d, 0x9f, 0x6, 0xff, 0x51, 0xea, 0x7e, 0x8a, 0x5d, 0xb2, 0xae, 0x66, 0xf5, 0x22, 0x65, 0xa7, 0xfe, 0xf0, 0xce, 0xf5, 0x2c, 0xbf, 0x4e, 0x41, 0x19, 0x72 }, - }, - { - .msglen = 206, - .result = { 0x66, 0x41, 0x4d, 0xd9, 0xff, 0x1, 0x27, 0xda, 0xae, 0xee, 0x41, 0x34, 0x41, 0xd1, 0xb9, 0xac, 0x11, 0xf3, 0x5b, 0xc4, 0xa2, 0xd5, 0x3, 0x47, 0x87, 0xf4, 0x88, 0xee, 0x61, 0x22, 0x1, 0x6a }, - }, - { - .msglen = 207, - .result = { 0x59, 0xaf, 0xa5, 0x9a, 0xac, 0x1, 0x0, 0x73, 0x57, 0xa4, 0xdb, 0x22, 0x9, 0x3b, 0x3a, 0x66, 0x19, 0xd6, 0xe4, 0xf7, 0x1d, 0x2a, 0x37, 0x5f, 0x71, 0xc5, 0x54, 0x8e, 0xb, 0x73, 0xd5, 0x3c }, - }, - { - .msglen = 208, - .result = { 0xd1, 0xa7, 0x61, 0x34, 0xc5, 0x65, 0xb8, 0xa4, 0x8e, 0x3a, 0x9f, 0x5b, 0x11, 0x8b, 0x21, 0x5e, 0x7c, 0x9c, 0xfb, 0xd3, 0xe2, 0xe5, 0x92, 0x41, 0x6f, 0x4, 0x61, 0x30, 0x79, 0xf2, 0x8, 0xc4 }, - }, - { - .msglen = 209, - .result = { 0x84, 0x79, 0x2, 0x39, 0x2d, 0x2a, 0x11, 0xa5, 0xff, 0xa1, 0x3a, 0xfd, 0x70, 0x90, 0xb4, 0xa5, 0x85, 0xda, 0xd5, 0x4c, 0x8d, 0xaa, 0x97, 0x5e, 0x3b, 0x45, 0x89, 0xd0, 0xfd, 0x85, 0x57, 0xf3 }, - }, - { - .msglen = 210, - .result = { 0xc6, 0x3b, 0x4b, 0xbd, 0x70, 0x65, 0x2, 0x2f, 0xfc, 0xc2, 0x42, 0x4e, 0x77, 0xa0, 0xc8, 0x4d, 0x3d, 0x65, 0x4a, 0xb3, 0x47, 0xf5, 0x21, 0x39, 0xb0, 0x61, 0x8a, 0xae, 0x58, 0x18, 0x7e, 0xbe }, - }, - { - .msglen = 211, - .result = { 0x3c, 0x50, 0xdb, 0xa6, 0x45, 0x69, 0x8b, 0x58, 0x22, 0x1f, 0x3c, 0xa3, 0x1a, 0x79, 0x90, 0xef, 0xd4, 0x21, 0xf6, 0x9e, 0xfd, 0xe5, 0xb9, 0xb2, 0xbb, 0xef, 0x27, 0x36, 0x35, 0xd8, 0x6f, 0x69 }, - }, - { - .msglen = 212, - .result = { 0xd1, 0x5b, 0x4f, 0x10, 0xc6, 0x1, 0x2b, 0xe5, 0x4b, 0x8f, 0xba, 0x55, 0x36, 0x60, 0x26, 0xf3, 0x93, 0x40, 0xb7, 0xd, 0xbd, 0xf6, 0x80, 0x51, 0xbe, 0x52, 0x9, 0xdd, 0x78, 0x30, 0x47, 0xbd }, - }, - { - .msglen = 213, - .result = { 0xe6, 0x2e, 0x97, 0xbc, 0x93, 0xaf, 0x61, 0xb8, 0x40, 0x9d, 0x70, 0x90, 0xdc, 0x34, 0xb0, 0x7e, 0xad, 0x1d, 0x50, 0x55, 0x9e, 0x42, 0x92, 0x92, 0xaf, 0x54, 0x5c, 0x57, 0xa, 0x49, 0x39, 0xd }, - }, - { - .msglen = 214, - .result = { 0x6d, 0x72, 0xde, 0xd8, 0x72, 0x65, 0xc9, 0xaf, 0x36, 0x3b, 0x75, 0xf6, 0xf7, 0x71, 0x15, 0xa6, 0xad, 0x73, 0xa2, 0x9b, 0x1c, 0x86, 0xf3, 0xc1, 0xc1, 0x7a, 0x85, 0x87, 0x70, 0x44, 0x83, 0xe8 }, - }, - { - .msglen = 215, - .result = { 0x6c, 0xfb, 0xa2, 0xb9, 0xc1, 0xf0, 0xbf, 0xef, 0x33, 0x60, 0x55, 0x30, 0x5b, 0x2b, 0x4, 0x7b, 0xfb, 0x8f, 0xe0, 0x5d, 0x11, 0x90, 0x3c, 0x28, 0xcf, 0xd4, 0x5, 0x70, 0x88, 0x1a, 0x53, 0xa }, - }, - { - .msglen = 216, - .result = { 0xe6, 0x2a, 0x80, 0x77, 0xb, 0x8d, 0xc8, 0x79, 0x72, 0x32, 0xf9, 0xd, 0x41, 0xcc, 0x6e, 0x77, 0xe5, 0x5f, 0x22, 0xd2, 0xdb, 0x1, 0xf9, 0x96, 0xce, 0x13, 0x95, 0x51, 0x6, 0x95, 0x51, 0x24 }, - }, - { - .msglen = 217, - .result = { 0xf1, 0x79, 0x81, 0xb2, 0x3b, 0xb7, 0xc1, 0x12, 0x24, 0x6e, 0x97, 0xed, 0xe4, 0x87, 0xf4, 0xcf, 0x62, 0xf8, 0xb8, 0xa9, 0xb8, 0x9d, 0xf4, 0x5d, 0x17, 0xc7, 0x27, 0xe7, 0x84, 0x7, 0xb9, 0x56 }, - }, - { - .msglen = 218, - .result = { 0x6c, 0xe2, 0x55, 0x53, 0x36, 0x41, 0xe2, 0x99, 0xac, 0xb2, 0x67, 0xc1, 0xfe, 0x63, 0xb4, 0x93, 0x26, 0x50, 0x2e, 0xe, 0xac, 0xf7, 0x66, 0x20, 0x6, 0xb7, 0xb9, 0x98, 0x20, 0x17, 0xfa, 0x2d }, - }, - { - .msglen = 219, - .result = { 0xef, 0x47, 0xb1, 0x44, 0x60, 0xf2, 0x1a, 0xa5, 0x99, 0x8d, 0xd8, 0x7c, 0x80, 0x22, 0x2a, 0xac, 0x9, 0x27, 0xf, 0xc9, 0xb8, 0xa8, 0xfb, 0xec, 0x41, 0x23, 0x2b, 0x9b, 0x20, 0xed, 0xef, 0x5e }, - }, - { - .msglen = 220, - .result = { 0xea, 0x10, 0xab, 0xd, 0x8a, 0x2f, 0xff, 0xe2, 0x21, 0xb7, 0x8b, 0xff, 0x13, 0xa0, 0xa9, 0x4c, 0x78, 0x85, 0x35, 0xdf, 0x8c, 0xb8, 0x82, 0x57, 0x98, 0x5e, 0xc8, 0xe5, 0x95, 0x43, 0x14, 0x7e }, - }, - { - .msglen = 221, - .result = { 0xb6, 0x3b, 0x58, 0x81, 0xab, 0x62, 0xa9, 0xf3, 0x19, 0x1f, 0x3c, 0xe1, 0x21, 0x2f, 0x2, 0xc9, 0xdb, 0x8d, 0xd4, 0x7f, 0x38, 0x11, 0x1b, 0x18, 0x5c, 0xb, 0xa3, 0xa8, 0x38, 0xe4, 0xc4, 0x55 }, - }, - { - .msglen = 222, - .result = { 0xb, 0xc3, 0x3f, 0xaa, 0x9c, 0xff, 0x53, 0xb8, 0xe1, 0xa6, 0xd3, 0x43, 0x8e, 0xa6, 0x48, 0x7b, 0x5b, 0x4, 0x31, 0xc1, 0xad, 0x9d, 0x8, 0x39, 0xac, 0xee, 0x1, 0x87, 0xd3, 0x91, 0x7e, 0x7b }, - }, - { - .msglen = 223, - .result = { 0xb3, 0xd0, 0x23, 0x54, 0xc2, 0x1d, 0xd6, 0x23, 0x70, 0xe0, 0xc2, 0x61, 0x52, 0xa2, 0xbc, 0x3b, 0x6, 0x11, 0x80, 0xb2, 0xfa, 0x17, 0x26, 0x74, 0x90, 0x61, 0x46, 0x35, 0x66, 0x1a, 0xe9, 0x51 }, - }, - { - .msglen = 224, - .result = { 0x0, 0xab, 0x82, 0xf2, 0xaf, 0x44, 0x95, 0x58, 0x31, 0x2a, 0x20, 0x4c, 0x2c, 0xdc, 0x80, 0xfd, 0x71, 0x7a, 0xf4, 0x34, 0xe6, 0x7e, 0xe2, 0xff, 0x6e, 0xc2, 0xf, 0x82, 0x65, 0x1e, 0x6d, 0xe6 }, - }, - { - .msglen = 225, - .result = { 0x6, 0x67, 0x32, 0x34, 0x96, 0xb5, 0x7a, 0x86, 0xda, 0x89, 0xd6, 0x9b, 0x1e, 0x23, 0x40, 0xfb, 0xd, 0xdf, 0xce, 0xdf, 0x83, 0x14, 0xb3, 0xe2, 0x2c, 0xd, 0x70, 0x18, 0xde, 0x87, 0xc6, 0x65 }, - }, - { - .msglen = 226, - .result = { 0x7b, 0x2a, 0x1c, 0xc5, 0xc6, 0x2e, 0xb4, 0xed, 0x19, 0x75, 0x50, 0x8d, 0xe5, 0x74, 0xe9, 0x31, 0x32, 0x88, 0x36, 0x6a, 0x61, 0x10, 0x6c, 0xad, 0x25, 0xb5, 0x72, 0x8a, 0x4a, 0x9, 0x18, 0x7c }, - }, - { - .msglen = 227, - .result = { 0xa6, 0x34, 0x75, 0xcb, 0x1a, 0xbb, 0x6d, 0x4a, 0xfb, 0x81, 0x67, 0xd1, 0x46, 0xac, 0x59, 0xd, 0x86, 0x5b, 0xd5, 0x71, 0xb6, 0x52, 0xd2, 0xca, 0xdb, 0x31, 0x45, 0x97, 0x61, 0x5f, 0x77, 0x62 }, - }, - { - .msglen = 228, - .result = { 0x4, 0x7d, 0x3a, 0x50, 0x35, 0x1f, 0x7e, 0x94, 0x18, 0xe0, 0xeb, 0xc, 0xe7, 0x27, 0x85, 0x54, 0x4c, 0x33, 0x51, 0xf5, 0x51, 0x2e, 0x40, 0x88, 0x67, 0x36, 0x6b, 0x5d, 0x7c, 0xb1, 0x6, 0xc7 }, - }, - { - .msglen = 229, - .result = { 0x59, 0x7f, 0x6c, 0x70, 0x8c, 0x79, 0xf8, 0x9f, 0xb2, 0xb1, 0x5e, 0xc4, 0xe9, 0x26, 0x8c, 0xae, 0xc0, 0xfc, 0x48, 0x18, 0xe0, 0xa5, 0xab, 0xb4, 0x68, 0x23, 0x2c, 0x11, 0xf9, 0x1e, 0x11, 0x62 }, - }, - { - .msglen = 230, - .result = { 0x16, 0xe9, 0x5, 0x1c, 0xfd, 0x35, 0x95, 0xda, 0xad, 0xb4, 0xbd, 0xdc, 0x7b, 0xdb, 0xc3, 0x19, 0x56, 0x88, 0x42, 0x38, 0x58, 0x2f, 0x63, 0x5b, 0x73, 0x6e, 0xfd, 0x68, 0x24, 0x27, 0xce, 0xa3 }, - }, - { - .msglen = 231, - .result = { 0x7b, 0xba, 0x9e, 0x1a, 0xdb, 0xbb, 0x9b, 0x17, 0xe, 0x7, 0xbc, 0x8b, 0xbd, 0xdf, 0xab, 0x8b, 0xe7, 0xea, 0x39, 0xba, 0x20, 0xce, 0xd5, 0x83, 0x89, 0xe3, 0x27, 0xa3, 0xbe, 0x25, 0xb0, 0x4 }, - }, - { - .msglen = 232, - .result = { 0x11, 0x4a, 0xc5, 0xc9, 0x7f, 0x98, 0xeb, 0x92, 0xd3, 0x76, 0x4f, 0xc0, 0xd8, 0x8c, 0xfd, 0xe7, 0xf3, 0x1d, 0xfd, 0xbd, 0x36, 0x88, 0x48, 0xd6, 0xc7, 0x8c, 0x9f, 0x2c, 0xb2, 0x72, 0x14, 0xb9 }, - }, - { - .msglen = 233, - .result = { 0xb0, 0x67, 0xf9, 0x62, 0xb9, 0xa1, 0xc0, 0xe5, 0xb, 0x22, 0x4b, 0xe7, 0x84, 0x6b, 0x8c, 0xa9, 0xa, 0xfa, 0xd7, 0xe7, 0x5b, 0x7b, 0xc, 0xe0, 0x6e, 0x47, 0x24, 0xf8, 0xc7, 0xf5, 0x6b, 0x14 }, - }, - { - .msglen = 234, - .result = { 0x77, 0x25, 0x61, 0xfd, 0xc8, 0x39, 0x3a, 0x72, 0x74, 0x9, 0x8b, 0x49, 0x7d, 0xa3, 0x42, 0x66, 0xb, 0x5a, 0xa5, 0x53, 0x70, 0xbe, 0x69, 0x96, 0x69, 0xbb, 0x7a, 0x8a, 0x12, 0xa, 0x7, 0x14 }, - }, - { - .msglen = 235, - .result = { 0x10, 0x16, 0xbb, 0x95, 0x96, 0xb3, 0x87, 0xf6, 0x12, 0x5d, 0xcc, 0x9, 0xd3, 0xcd, 0xf8, 0x44, 0x2, 0x62, 0x96, 0xde, 0x7c, 0xa2, 0x66, 0x12, 0x4e, 0x86, 0x32, 0x11, 0xf1, 0x18, 0x38, 0x79 }, - }, - { - .msglen = 236, - .result = { 0x42, 0x91, 0x46, 0x5c, 0xa6, 0xae, 0x5c, 0x68, 0xc8, 0xb9, 0xa8, 0x38, 0xea, 0x18, 0x71, 0x63, 0xae, 0x9c, 0xc6, 0xd9, 0x22, 0xe4, 0xfa, 0x85, 0x9c, 0x94, 0xd4, 0xb8, 0xab, 0x98, 0xe, 0xf0 }, - }, - { - .msglen = 237, - .result = { 0x2b, 0x6b, 0xc, 0x10, 0x13, 0x80, 0x8e, 0xc3, 0x8a, 0xcd, 0xe7, 0xf0, 0x21, 0x1c, 0x1c, 0x7e, 0x61, 0x5e, 0x5, 0x37, 0xde, 0x5e, 0x9f, 0x2f, 0x8a, 0xe4, 0x31, 0x0, 0x63, 0x90, 0xc8, 0xa3 }, - }, - { - .msglen = 238, - .result = { 0xf5, 0x12, 0xb6, 0x60, 0xfe, 0x6c, 0xe5, 0xd2, 0x8b, 0x2e, 0xc9, 0x37, 0x66, 0xf8, 0xd5, 0x52, 0x28, 0x76, 0x35, 0xba, 0x4b, 0xf0, 0x2c, 0xbd, 0x47, 0x14, 0x3, 0x6b, 0x47, 0x58, 0xf8, 0x16 }, - }, - { - .msglen = 239, - .result = { 0xfa, 0x6c, 0x94, 0x22, 0xb, 0x98, 0x3b, 0x74, 0x18, 0xfa, 0xb8, 0xda, 0x55, 0x6c, 0xa2, 0xf5, 0x5b, 0xe4, 0x8, 0x99, 0xfa, 0xf7, 0xb4, 0x57, 0xfa, 0x7d, 0x8a, 0xc, 0x6a, 0xe1, 0xca, 0xc2 }, - }, - { - .msglen = 240, - .result = { 0x2b, 0x59, 0x71, 0x1e, 0x37, 0x8b, 0x24, 0x39, 0x98, 0x50, 0x79, 0x3b, 0xde, 0x2c, 0xce, 0xc6, 0xd, 0xf7, 0x53, 0xb6, 0x12, 0x2d, 0x70, 0x53, 0xdf, 0xbe, 0x57, 0x56, 0x87, 0xee, 0x9f, 0x12 }, - }, - { - .msglen = 241, - .result = { 0x38, 0xf6, 0x60, 0x9d, 0x7, 0x23, 0x85, 0xcc, 0x8e, 0x4a, 0xe5, 0xf1, 0xaf, 0x31, 0x9b, 0x97, 0xda, 0x34, 0x80, 0x6c, 0x23, 0x79, 0x69, 0x33, 0x87, 0xa6, 0x2d, 0x8d, 0xd4, 0x8e, 0x66, 0x2e }, - }, - { - .msglen = 242, - .result = { 0x88, 0x5d, 0xc8, 0x2, 0xf4, 0x76, 0xe4, 0x4e, 0xae, 0xcc, 0x9, 0x49, 0xc, 0x56, 0x7, 0x22, 0xd, 0x8f, 0xb0, 0xb4, 0x68, 0x1d, 0xb5, 0xaf, 0x89, 0xb0, 0xab, 0x3b, 0x37, 0x39, 0x88, 0x37 }, - }, - { - .msglen = 243, - .result = { 0x10, 0xb1, 0x44, 0x4a, 0xe2, 0xfc, 0x17, 0xc0, 0x7d, 0x39, 0x62, 0xb3, 0x45, 0x9b, 0xbe, 0xf8, 0x79, 0x2e, 0xe2, 0xfd, 0x59, 0x8e, 0xb5, 0x6c, 0x1d, 0xf5, 0x8b, 0x50, 0xad, 0x28, 0x93, 0xf }, - }, - { - .msglen = 244, - .result = { 0xf6, 0x5d, 0xce, 0x54, 0x13, 0x2, 0x3f, 0x5b, 0x4e, 0x72, 0xc8, 0xe1, 0x42, 0x83, 0xe7, 0x52, 0xde, 0x6f, 0xe6, 0x93, 0x15, 0xab, 0xe8, 0x1f, 0x53, 0x1d, 0xc5, 0xcd, 0xf3, 0x98, 0xf0, 0x9e }, - }, - { - .msglen = 245, - .result = { 0x56, 0xf1, 0x6f, 0xe1, 0xd7, 0x0, 0x33, 0x65, 0xe1, 0x61, 0x79, 0x15, 0x78, 0x5f, 0x98, 0x32, 0x4d, 0x11, 0x99, 0xf1, 0x14, 0xf2, 0xdc, 0x10, 0x7, 0x0, 0xaf, 0xea, 0x4, 0xd, 0x99, 0x33 }, - }, - { - .msglen = 246, - .result = { 0xfc, 0xcc, 0x27, 0x84, 0xc0, 0xbf, 0xf4, 0x52, 0xf2, 0x39, 0x1f, 0xb5, 0x5e, 0x8a, 0x17, 0xd2, 0x53, 0xff, 0x3c, 0x9b, 0x53, 0x25, 0x14, 0xed, 0xca, 0x1c, 0x88, 0xa9, 0x86, 0x5c, 0x50, 0xfe }, - }, - { - .msglen = 247, - .result = { 0xf3, 0x9f, 0x18, 0x4a, 0x35, 0xf4, 0xb3, 0x6, 0xac, 0xc4, 0x8c, 0x8e, 0xe7, 0x87, 0x0, 0x11, 0x63, 0xea, 0xba, 0x6a, 0x3f, 0x12, 0xa1, 0x4b, 0xf5, 0x6d, 0xbd, 0xeb, 0xcf, 0xfe, 0x6, 0x6d }, - }, - { - .msglen = 248, - .result = { 0x78, 0x69, 0xfc, 0x51, 0x5e, 0x48, 0xda, 0xb3, 0x81, 0xcb, 0x88, 0xf1, 0xc, 0x7, 0xeb, 0x16, 0x18, 0x2e, 0x6d, 0x85, 0x9d, 0xc0, 0x80, 0xea, 0xab, 0x39, 0xd3, 0x6a, 0xa8, 0x10, 0xe3, 0x26 }, - }, - { - .msglen = 249, - .result = { 0xee, 0xfb, 0xd, 0x72, 0x20, 0x48, 0x71, 0x10, 0x46, 0xc2, 0xb0, 0x5c, 0x11, 0xcf, 0x82, 0x2e, 0x6e, 0x3e, 0x3f, 0x16, 0xfa, 0x71, 0x80, 0x5f, 0x51, 0x50, 0x3e, 0xa2, 0x5d, 0xa1, 0x66, 0xbe }, - }, - { - .msglen = 250, - .result = { 0x72, 0x9c, 0x3, 0xe9, 0x25, 0xda, 0xaf, 0x7b, 0x40, 0x10, 0xe2, 0x85, 0xe0, 0x5b, 0xce, 0x55, 0x72, 0x1f, 0xfa, 0x54, 0x1c, 0x96, 0x48, 0xb, 0x55, 0x26, 0x53, 0x7d, 0xa9, 0xc5, 0x27, 0xd0 }, - }, - { - .msglen = 251, - .result = { 0x6f, 0x40, 0xd5, 0x72, 0x3b, 0x1f, 0x99, 0x9e, 0x7, 0x57, 0xbb, 0x57, 0x6c, 0x7e, 0x47, 0xb2, 0x76, 0x37, 0x5e, 0x64, 0x21, 0x51, 0x3c, 0xe8, 0x16, 0xda, 0x5f, 0x9f, 0xc9, 0x5b, 0xc3, 0x70 }, - }, - { - .msglen = 252, - .result = { 0x77, 0x3b, 0x47, 0x74, 0x0, 0xfd, 0x74, 0x95, 0xe, 0x59, 0xf6, 0xf, 0xcf, 0x9a, 0xb3, 0xbc, 0x9f, 0xd9, 0x3c, 0x3a, 0x30, 0x1c, 0x1f, 0x4d, 0x53, 0xbe, 0xce, 0x4c, 0xa1, 0x8b, 0xc1, 0x22 }, - }, - { - .msglen = 253, - .result = { 0xd0, 0xbe, 0x9, 0xb3, 0xa9, 0xa4, 0xb2, 0x46, 0x99, 0x40, 0x40, 0x6b, 0x52, 0x54, 0x3b, 0xfe, 0x94, 0x37, 0xf9, 0xc, 0xc2, 0xc2, 0x66, 0x3, 0xa5, 0x8c, 0x42, 0xae, 0x9d, 0xf8, 0x47, 0x87 }, - }, - { - .msglen = 254, - .result = { 0x85, 0x78, 0x21, 0xf4, 0xa, 0xee, 0xa3, 0x59, 0xe0, 0xb2, 0xd7, 0x7, 0x34, 0x5e, 0x57, 0xdc, 0xdd, 0x9a, 0xfa, 0x2c, 0xfd, 0xb6, 0xee, 0xa9, 0x14, 0xc0, 0x17, 0x86, 0xbf, 0x7b, 0xfe, 0x4b }, - }, - { - .msglen = 255, - .result = { 0x59, 0x52, 0x50, 0x4, 0xb6, 0x28, 0xf9, 0x28, 0x7f, 0x6c, 0x37, 0xba, 0xfb, 0xb2, 0x58, 0xe7, 0xa, 0xac, 0x6c, 0x4a, 0xef, 0x66, 0x6, 0x7b, 0x1, 0x1f, 0x4c, 0xa4, 0xe5, 0xe5, 0x29, 0x5d }, - }, - { - .msglen = 256, - .result = { 0x52, 0x1a, 0x14, 0xc3, 0xb4, 0x85, 0xf0, 0xb5, 0x82, 0xe9, 0x40, 0xc2, 0xc, 0x6d, 0x59, 0x64, 0x86, 0x7d, 0xa, 0x3b, 0x7f, 0x85, 0x78, 0xea, 0xea, 0x66, 0x48, 0xfa, 0x4a, 0xde, 0x5c, 0xd3 }, - }, - }; - for (int i = 0; i < sizeof(results) / sizeof(hmac_result); i++) { TEST_ESP_OK(esp_hmac_calculate(HMAC_KEY5, message, results[i].msglen, hmac)); TEST_ASSERT_EQUAL_HEX8_ARRAY(results[i].result, hmac, sizeof(hmac)); @@ -1275,22 +85,8 @@ TEST_CASE("HMAC 'upstream' wait lock", "[hw_crypto]") { uint8_t hmac[32]; - // 257 characters of pseudo-Latin from lipsum.com (not Copyright) - const char *message = "Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. Sunt architecto iure aspernatur soluta ut recusandae. Ut quibusdam occaecati ut qui sit dignissimos eaque.."; - setup_keyblock(EFUSE_BLK_KEY5, ESP_EFUSE_KEY_PURPOSE_HMAC_UP); - static const hmac_result results[] = { - { - .msglen = 255, - .result = { 0x59, 0x52, 0x50, 0x4, 0xb6, 0x28, 0xf9, 0x28, 0x7f, 0x6c, 0x37, 0xba, 0xfb, 0xb2, 0x58, 0xe7, 0xa, 0xac, 0x6c, 0x4a, 0xef, 0x66, 0x6, 0x7b, 0x1, 0x1f, 0x4c, 0xa4, 0xe5, 0xe5, 0x29, 0x5d }, - }, - { - .msglen = 256, - .result = { 0x52, 0x1a, 0x14, 0xc3, 0xb4, 0x85, 0xf0, 0xb5, 0x82, 0xe9, 0x40, 0xc2, 0xc, 0x6d, 0x59, 0x64, 0x86, 0x7d, 0xa, 0x3b, 0x7f, 0x85, 0x78, 0xea, 0xea, 0x66, 0x48, 0xfa, 0x4a, 0xde, 0x5c, 0xd3 }, - }, - }; - for (int i = 0; i < sizeof(results) / sizeof(hmac_result); i++) { TEST_ESP_OK(esp_hmac_calculate(HMAC_KEY5, message, results[i].msglen, hmac)); TEST_ASSERT_EQUAL_HEX8_ARRAY(results[i].result, hmac, sizeof(hmac)); @@ -1307,9 +103,6 @@ TEST_CASE("HMAC key out of range", "[hw_crypto]") { uint8_t hmac[32]; - // 257 characters of pseudo-Latin from lipsum.com (not Copyright) - const char *message = "Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis."; - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY0 - 1, message, 47, hmac)); - TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY5 + 1, message, 47, hmac)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_hmac_calculate(HMAC_KEY_MAX, message, 47, hmac)); } diff --git a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c index 1fdb5b28f1..1b2a25a4b6 100644 --- a/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c +++ b/components/esp_security/test_apps/crypto_drivers/main/test_key_mgr.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -18,6 +18,31 @@ #include "esp_key_mgr.h" #include "esp_system.h" #include "unity_test_utils_memory.h" + +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY +#include "esp_hmac.h" +#include "hmac_test_cases.h" +#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +#include "esp_ds.h" + +#define NUM_RESULTS 10 +typedef struct { + uint8_t iv[ESP_DS_IV_LEN]; + esp_ds_p_data_t p_data; + uint8_t expected_c[ESP_DS_C_LEN]; + uint8_t hmac_key_idx; + uint32_t expected_results[NUM_RESULTS][SOC_RSA_MAX_BIT_LEN / 32]; +} encrypt_testcase_t; + +#if SOC_RSA_MAX_BIT_LEN == 4096 +#include "digital_signature_test_cases_4096.h" +#elif SOC_RSA_MAX_BIT_LEN == 3072 +#include "digital_signature_test_cases_3072.h" +#endif +#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */ + static const char *TAG = "key_mgr_test"; #define ENCRYPTED_DATA_SIZE 128 @@ -33,41 +58,55 @@ static const uint8_t plaintext_data[ENCRYPTED_DATA_SIZE] = { }; static const uint8_t expected_ciphertext[ENCRYPTED_DATA_SIZE] = { - 0x1f, 0x41, 0xa4, 0xec, 0x0f, 0xd3, 0xaf, 0xe1, 0xb5, 0xc0, 0x56, 0x41, 0xcb, 0x28, 0x97, 0x1c, - 0x45, 0x02, 0x23, 0xcd, 0x45, 0x06, 0x19, 0xd8, 0xf9, 0x40, 0x8d, 0xdf, 0xb8, 0x71, 0xa7, 0x79, - 0xdf, 0xbb, 0x2d, 0x6a, 0xdd, 0x16, 0x18, 0x32, 0xe4, 0xa6, 0xfe, 0x23, 0xc9, 0x70, 0xa0, 0xfa, - 0xec, 0x74, 0xf4, 0x62, 0xea, 0x31, 0xc7, 0x1e, 0xfe, 0x94, 0xda, 0xe1, 0x70, 0xf8, 0x9f, 0xa3, - 0x03, 0xdf, 0x89, 0x77, 0x0a, 0x41, 0x7d, 0xc5, 0xe6, 0xc8, 0xb1, 0x10, 0xc8, 0x12, 0xa6, 0x3f, - 0xea, 0xf0, 0xfa, 0x7a, 0x5d, 0x33, 0xb3, 0xe6, 0xc2, 0x27, 0x07, 0x1e, 0x71, 0x22, 0x87, 0x73, - 0xc4, 0x2a, 0xbd, 0x59, 0x8f, 0xc6, 0xfb, 0x28, 0x2e, 0xec, 0xa2, 0x1f, 0x42, 0x7c, 0x54, 0xec, - 0x1e, 0x0f, 0x9f, 0xf2, 0x6e, 0x3f, 0xb8, 0x7d, 0xbf, 0xee, 0xf9, 0x7c, 0x93, 0xb2, 0x79, 0x98 + 0xf9, 0xb6, 0x08, 0x0f, 0xfb, 0x37, 0x46, 0xe4, 0x99, 0x3c, 0xf9, 0x29, 0xab, 0x90, 0xd5, 0x3f, + 0xc8, 0x70, 0x45, 0xae, 0x28, 0x16, 0xbd, 0x83, 0x66, 0x16, 0x83, 0x86, 0x01, 0xc9, 0xa2, 0x97, + 0xa4, 0xf6, 0xf0, 0x40, 0xb5, 0xfd, 0xb7, 0x13, 0x60, 0xc3, 0x39, 0xf2, 0x32, 0x5a, 0xa3, 0x89, + 0xfd, 0x77, 0x9c, 0x6b, 0x0e, 0x98, 0xdf, 0x8f, 0xf7, 0xcc, 0x2a, 0x1e, 0xce, 0xdc, 0xef, 0x41, + 0xac, 0x0f, 0x48, 0x97, 0xa1, 0x1a, 0xc0, 0x82, 0x42, 0x7e, 0x1a, 0x35, 0xcd, 0xcb, 0x2b, 0x1d, + 0x72, 0xc6, 0x78, 0xab, 0x35, 0x58, 0xd1, 0xe3, 0xb1, 0x61, 0x8d, 0x11, 0x70, 0x91, 0x62, 0xb4, + 0x5f, 0xdd, 0x75, 0x2f, 0x78, 0xc4, 0x95, 0x67, 0x3a, 0xd3, 0x87, 0x02, 0x35, 0x78, 0x48, 0xef, + 0xf2, 0xde, 0xdb, 0x59, 0xda, 0x33, 0xa6, 0x27, 0xdd, 0x33, 0x18, 0x0c, 0x57, 0x24, 0x95, 0x38, }; /* Big endian */ -uint8_t init_key[] = { - 0x4d, 0x21, 0x64, 0x21, 0x8f, 0xa2, 0xe3, 0xa0, 0xab, 0x74, 0xb5, 0xab, 0x17, 0x9a, 0x5d, 0x08, - 0x58, 0xf4, 0x22, 0x03, 0xbd, 0x52, 0xe7, 0x88, 0x3c, 0x22, 0x0f, 0x95, 0x89, 0x70, 0xe1, 0x93 +static const uint8_t init_key[] = { + 0xee, 0x89, 0x95, 0xda, 0x3c, 0x8a, 0x43, 0x83, 0xa9, 0x4b, 0x25, 0x5b, 0x04, 0x7e, 0xf1, 0x57, + 0xb8, 0xe8, 0x06, 0x45, 0x87, 0x76, 0xee, 0x1b, 0x4e, 0x2e, 0x55, 0xa7, 0x1f, 0x25, 0xe1, 0x94, }; /* Big endian */ -uint8_t k2_info[] = { - 0xd8, 0xcd, 0x04, 0x45, 0xb4, 0x45, 0xc4, 0x15, 0xf6, 0x40, 0x1c, 0x7d, 0x90, 0x1b, 0x99, 0xa4, - 0x79, 0x6b, 0xfb, 0x5b, 0x2a, 0x40, 0x60, 0xe1, 0xc1, 0xe1, 0x48, 0xcd, 0x46, 0x6b, 0x9b, 0x48, - 0xda, 0x7a, 0x70, 0x0a, 0x78, 0x0b, 0x9d, 0xf9, 0x0e, 0xed, 0x91, 0xfc, 0xa5, 0xc2, 0x96, 0x05, - 0x91, 0x76, 0xdb, 0x68, 0x84, 0x5d, 0x5e, 0x5b, 0xa6, 0xe9, 0x6b, 0x3b, 0x12, 0x50, 0x05, 0xc3 +static const uint8_t k2_info[] = { + 0x8f, 0x96, 0x33, 0x47, 0xe1, 0xa5, 0x57, 0xe9, 0x2a, 0x51, 0xa9, 0xbe, 0x48, 0x84, 0x25, 0x4e, + 0x6f, 0x50, 0x1c, 0x45, 0xdb, 0xb6, 0xfa, 0xeb, 0x35, 0xd2, 0x27, 0x91, 0x3f, 0x67, 0x57, 0xd9, + 0xcb, 0x55, 0xe4, 0x2b, 0x18, 0x16, 0xe7, 0xce, 0x6c, 0xf2, 0x58, 0x71, 0x17, 0x76, 0x2a, 0x86, + 0x05, 0xe7, 0x37, 0x45, 0x71, 0x34, 0xca, 0xaf, 0x60, 0x07, 0xdf, 0xf4, 0xd2, 0xee, 0x3d, 0x4b, }; /* Big endian */ -uint8_t k1_ecdsa_encrypt[] = { - 0xeb, 0x83, 0x24, 0x7d, 0xf8, 0x40, 0xc9, 0x88, 0x5f, 0x5e, 0x58, 0x57, 0x25, 0xa9, 0x23, 0x4a, - 0xa4, 0xc4, 0x12, 0x17, 0xf3, 0x9e, 0x1f, 0xa0, 0xa0, 0xfa, 0xd5, 0xbf, 0xb6, 0x6c, 0xb5, 0x48 +static const uint8_t k1_encrypt[] = { + 0xe0, 0xe8, 0x41, 0xe3, 0xd0, 0x92, 0x71, 0x84, 0x4b, 0x02, 0x1e, 0xec, 0x14, 0xdd, 0xaf, 0xf8, + 0x39, 0xf9, 0x6a, 0x8d, 0x1b, 0xd7, 0x64, 0x3b, 0x7b, 0xa6, 0x05, 0x42, 0x01, 0xfb, 0xab, 0xe1, }; -uint8_t k1_xts_encrypt[] = { - 0xeb, 0x83, 0x24, 0x7d, 0xf8, 0x40, 0xc9, 0x88, 0x5f, 0x5e, 0x58, 0x57, 0x25, 0xa9, 0x23, 0x4a, - 0xa4, 0xc4, 0x12, 0x17, 0xf3, 0x9e, 0x1f, 0xa0, 0xa0, 0xfa, 0xd5, 0xbf, 0xb6, 0x6c, 0xb5, 0x48 +static const uint8_t k1_hmac_encrypt[] = { + 0x9e, 0xd8, 0x62, 0x4f, 0x27, 0xe1, 0x13, 0xfc, 0x50, 0x4b, 0x7f, 0x68, 0x70, 0x7b, 0xa1, 0xb2, + 0xb1, 0x75, 0x21, 0x43, 0x88, 0x7d, 0xed, 0x4b, 0x58, 0x27, 0xb4, 0x15, 0x57, 0xc2, 0x46, 0x78, }; +// Note: generated using the hmac_key_idx = 0 of digital_signature_test_cases_3072 +static const uint8_t k1_ds_encrypt[] = { + 0xa9, 0xf7, 0xd1, 0xd9, 0xaa, 0x80, 0xfa, 0x6f, 0xfa, 0x34, 0xf6, 0x66, 0xbf, 0xba, 0x7b, 0xc9, + 0xa9, 0xf4, 0xeb, 0xba, 0x43, 0x61, 0x59, 0x32, 0x5d, 0xa0, 0xda, 0xd9, 0x0d, 0xc7, 0xde, 0xb2, +}; + +static const uint8_t k1_G[] = { + 0x25, 0x8c, 0x48, 0x4d, 0x0b, 0x4d, 0x3f, 0xbf, 0xde, 0xcf, 0x00, 0xc9, 0x4b, 0x0b, 0xf1, 0x14, + 0xb4, 0x31, 0x97, 0x79, 0x5a, 0xd3, 0x48, 0x72, 0x44, 0x2d, 0xab, 0x76, 0x29, 0xb9, 0x8b, 0x05, + 0xf5, 0x6b, 0xfb, 0xb4, 0xe4, 0xde, 0x81, 0x83, 0xa7, 0x0a, 0x90, 0xe4, 0x33, 0x41, 0x92, 0xaa, + 0xc5, 0xed, 0x93, 0xe0, 0x76, 0x2b, 0xe2, 0x4b, 0xdd, 0xa2, 0x8e, 0xe1, 0xc9, 0xe2, 0x94, 0x50, +}; + +#if SOC_KEY_MANAGER_FE_KEY_DEPLOY const esp_partition_t *get_test_storage_partition(void) { /* This finds "storage" partition defined partition table */ @@ -81,7 +120,7 @@ const esp_partition_t *get_test_storage_partition(void) return result; } -static esp_err_t test_xts_aes_key(void) +static esp_err_t test_xts_aes_key(bool verify) { const esp_partition_t *partition = get_test_storage_partition(); ESP_ERROR_CHECK(esp_partition_erase_range(partition, 0, partition->size)); @@ -90,55 +129,268 @@ static esp_err_t test_xts_aes_key(void) ESP_ERROR_CHECK(esp_flash_write_encrypted(NULL, address, plaintext_data, sizeof(plaintext_data))); uint8_t read_data[ENCRYPTED_DATA_SIZE]; ESP_ERROR_CHECK(esp_flash_read(NULL, read_data, address, sizeof(read_data))); - if (memcmp(read_data, expected_ciphertext, sizeof(expected_ciphertext)) != 0) { - ESP_LOGE(TAG, "Encrypted data does not match expected data"); - return ESP_FAIL; + if (verify) { + TEST_ASSERT_EQUAL_HEX8_ARRAY(expected_ciphertext, read_data, sizeof(expected_ciphertext)); } return ESP_OK; } -extern void set_leak_threshold(int threshold); -TEST_CASE("Key Manager AES mode: XTS-AES key deployment", "[hw_crypto] [key_mgr]") +TEST_CASE("Key Manager AES mode: XTS-AES-128 key deployment", "[hw_crypto] [key_mgr]") { - static esp_key_mgr_aes_key_config_t key_config; - memcpy(key_config.k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); - memcpy(key_config.k1_encrypted, (uint8_t*) k1_xts_encrypt, KEY_MGR_K1_ENCRYPTED_SIZE); - memcpy(key_config.sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); - key_config.use_pre_generated_sw_init_key = 1; - key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + esp_key_mgr_aes_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_aes_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); - static esp_key_mgr_key_recovery_info_t key_info; - esp_err_t esp_ret = ESP_FAIL; - esp_ret = esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_info); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); - esp_ret = esp_key_mgr_activate_key(&key_info); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); - esp_ret = test_xts_aes_key(); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); - esp_ret = esp_key_mgr_deactivate_key(key_info.key_type); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); + memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config->k1_encrypted, (uint8_t*) k1_encrypt, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); + key_config->use_pre_generated_sw_init_key = 1; + key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_xts_aes_key(true)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); } -TEST_CASE("Key Manager random mode: XTS_AES_128 key deployment", "[hw_crypto] [key_mgr]") +TEST_CASE("Key Manager ECDH0 mode: XTS-AES-128 key deployment", "[hw_crypto] [key_mgr]") { - ESP_LOGI(TAG, "Key Manager Example Start"); - static esp_key_mgr_random_key_config_t key_config; + esp_key_mgr_ecdh0_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_ecdh0_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); - key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + memcpy(key_config->k1_G, (uint8_t*) k1_G, KEY_MGR_ECDH0_INFO_SIZE); + key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY; - static esp_key_mgr_key_recovery_info_t key_info; - esp_err_t esp_ret = ESP_FAIL; - esp_ret = esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_info); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + esp_key_mgr_ecdh0_info_t *ecdh0_info = calloc(1, sizeof(esp_key_mgr_ecdh0_info_t)); + TEST_ASSERT_NOT_NULL(ecdh0_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(key_config, key_recovery_info, ecdh0_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_xts_aes_key(false)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); + free(ecdh0_info); } +TEST_CASE("Key Manager Random mode: XTS-AES-128 key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + key_config->key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_xts_aes_key(false)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); +} +#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY TEST_CASE("Key Manager random mode: ECDSA key deployment", "[hw_crypto] [key_mgr]") { - static esp_key_mgr_random_key_config_t key_config; - static esp_key_mgr_key_recovery_info_t key_info; - esp_err_t esp_ret = ESP_FAIL; - key_config.key_type = ESP_KEY_MGR_ECDSA_KEY; - esp_ret = esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_info); - TEST_ASSERT_EQUAL(ESP_OK, esp_ret); + esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + key_config->key_type = ESP_KEY_MGR_ECDSA_256_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(key_config, key_recovery_info)); + + free(key_config); + free(key_recovery_info); } +#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY +static esp_err_t test_hmac_key(bool verify) +{ + uint8_t hmac[32]; + for (int i = 0; i < sizeof(results) / sizeof(hmac_result); i++) { + TEST_ESP_OK(esp_hmac_calculate(HMAC_KEY_KM, message, results[i].msglen, hmac)); + if (verify) { + TEST_ASSERT_EQUAL_HEX8_ARRAY(results[i].result, hmac, sizeof(hmac)); + } + } + return ESP_OK; +} + +TEST_CASE("Key Manager AES mode: HMAC key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_aes_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_aes_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config->k1_encrypted, (uint8_t*) k1_hmac_encrypt, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); + key_config->use_pre_generated_sw_init_key = 1; + key_config->key_type = ESP_KEY_MGR_HMAC_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_hmac_key(true)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); +} + +TEST_CASE("Key Manager ECDH0 mode: HMAC key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_ecdh0_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_ecdh0_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + memcpy(key_config->k1_G, (uint8_t*) k1_G, KEY_MGR_ECDH0_INFO_SIZE); + key_config->key_type = ESP_KEY_MGR_HMAC_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + esp_key_mgr_ecdh0_info_t *ecdh0_info = calloc(1, sizeof(esp_key_mgr_ecdh0_info_t)); + TEST_ASSERT_NOT_NULL(ecdh0_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(key_config, key_recovery_info, ecdh0_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_hmac_key(false)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); + free(ecdh0_info); +} + +TEST_CASE("Key Manager random mode: HMAC key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + key_config->key_type = ESP_KEY_MGR_HMAC_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_hmac_key(false)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); +} +#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +static esp_err_t test_ds_key(void) +{ + esp_ds_data_t ds_data = { }; + uint8_t signature[ESP_DS_SIGNATURE_MAX_BIT_LEN / 8] = { 0 }; + esp_err_t ds_r = ESP_FAIL; + + for (int i = 0; i < NUM_MESSAGES; i++) { + printf("Running test case %d...\n", i); + const encrypt_testcase_t *t = &test_cases[0]; + assert(t->hmac_key_idx == 0); // as the key deployed using Key Manager is the HMAC key ID 0 + + // copy encrypt parameter test case into ds_data structure + memcpy(ds_data.iv, t->iv, ESP_DS_IV_LEN); + memcpy(ds_data.c, t->expected_c, ESP_DS_C_LEN); + ds_data.rsa_length = t->p_data.length; + + ds_r = esp_ds_sign(test_messages[i], + &ds_data, + HMAC_KEY_KM, + signature); + + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->expected_results[i], signature, sizeof(signature)); + } + return ESP_OK; +} + +TEST_CASE("Key Manager AES mode: DS key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_aes_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_aes_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config->k1_encrypted, (uint8_t*) k1_ds_encrypt, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); + key_config->use_pre_generated_sw_init_key = 1; + key_config->key_type = ESP_KEY_MGR_DS_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, test_ds_key()); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); +} + +TEST_CASE("Key Manager ECDH0 mode: DS key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_ecdh0_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_ecdh0_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + memcpy(key_config->k1_G, (uint8_t*) k1_G, KEY_MGR_ECDH0_INFO_SIZE); + key_config->key_type = ESP_KEY_MGR_DS_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + esp_key_mgr_ecdh0_info_t *ecdh0_info = calloc(1, sizeof(esp_key_mgr_ecdh0_info_t)); + TEST_ASSERT_NOT_NULL(ecdh0_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(key_config, key_recovery_info, ecdh0_info)); + // Generate the deployed DS key and use ds_encrypt_params to generate encrypted input params + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); + free(ecdh0_info); +} + +TEST_CASE("Key Manager random mode: DS key deployment", "[hw_crypto] [key_mgr]") +{ + esp_key_mgr_random_key_config_t *key_config = calloc(1, sizeof(esp_key_mgr_random_key_config_t)); + TEST_ASSERT_NOT_NULL(key_config); + + key_config->key_type = ESP_KEY_MGR_DS_KEY; + + esp_key_mgr_key_recovery_info_t *key_recovery_info = calloc(1, sizeof(esp_key_mgr_key_recovery_info_t)); + TEST_ASSERT_NOT_NULL(key_recovery_info); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(key_config, key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(key_recovery_info)); + // No way to generate encrypted input params when DS key deployed in random mode + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info->key_type)); + + free(key_config); + free(key_recovery_info); +} +#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */ diff --git a/components/esp_security/test_apps/crypto_drivers/sdkconfig.defaults.esp32c5 b/components/esp_security/test_apps/crypto_drivers/sdkconfig.defaults.esp32c5 new file mode 100644 index 0000000000..8ff365b198 --- /dev/null +++ b/components/esp_security/test_apps/crypto_drivers/sdkconfig.defaults.esp32c5 @@ -0,0 +1,3 @@ +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions.csv" diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 5af3d7bbbc..d37e809fd3 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -707,6 +707,9 @@ void IRAM_ATTR call_start_cpu0(void) trax_start_trace(TRAX_DOWNCOUNT_WORDS); #endif // CONFIG_ESP32_TRAX || CONFIG_ESP32S2_TRAX || CONFIG_ESP32S3_TRAX +#if SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED + esp_clk_tree_initialize(); +#endif esp_clk_init(); esp_perip_clk_init(); diff --git a/components/esp_system/port/soc/esp32c5/clk.c b/components/esp_system/port/soc/esp32c5/clk.c index 836286748c..2c14e538b7 100644 --- a/components/esp_system/port/soc/esp32c5/clk.c +++ b/components/esp_system/port/soc/esp32c5/clk.c @@ -27,6 +27,38 @@ #if SOC_MODEM_CLOCK_SUPPORTED #include "hal/modem_lpcon_ll.h" #endif +#include "hal/adc_ll.h" +#include "hal/aes_ll.h" +#include "hal/assist_debug_ll.h" +#include "hal/apm_ll.h" +#include "hal/clk_gate_ll.h" +#include "hal/clk_tree_ll.h" +#include "hal/ds_ll.h" +#include "hal/ecc_ll.h" +#include "hal/etm_ll.h" +#include "hal/gdma_ll.h" +#include "hal/hmac_ll.h" +#include "hal/i2c_ll.h" +#include "hal/i2s_ll.h" +#include "hal/ledc_ll.h" +#include "hal/lp_core_ll.h" +#include "hal/lp_clkrst_ll.h" +#include "hal/mcpwm_ll.h" +#include "hal/mpi_ll.h" +#include "hal/mspi_ll.h" +#include "hal/parlio_ll.h" +#include "hal/pau_ll.h" +#include "hal/pcnt_ll.h" +#include "hal/rmt_ll.h" +#include "hal/rtc_io_ll.h" +#include "hal/sha_ll.h" +#include "hal/spi_ll.h" +#include "hal/temperature_sensor_ll.h" +#include "hal/timer_ll.h" +#include "hal/twaifd_ll.h" +#include "hal/uart_ll.h" +#include "hal/uhci_ll.h" +#include "hal/usb_serial_jtag_ll.h" #include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_modem_clock.h" #include "esp_private/periph_ctrl.h" @@ -200,16 +232,14 @@ void rtc_clk_select_rtc_slow_clk(void) */ __attribute__((weak)) void esp_perip_clk_init(void) { -// TODO: [ESP32C5] IDF-8844 -#if SOC_MODEM_CLOCK_SUPPORTED - // modem_clock_domain_pmu_state_icg_map_init(); /* During system initialization, the low-power clock source of the modem * (WiFi, BLE or Coexist) follows the configuration of the slow clock source * of the system. If the WiFi, BLE or Coexist module needs a higher * precision sleep clock (for example, the BLE needs to use the main XTAL * oscillator (40 MHz) to provide the clock during the sleep process in some * scenarios), the module needs to switch to the required clock source by - * itself. */ //TODO - WIFI-5233 + * itself. */ +#if CONFIG_ESP_WIFI_ENABLED soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) ? MODEM_CLOCK_LPCLK_SRC_XTAL32K @@ -225,102 +255,100 @@ __attribute__((weak)) void esp_perip_clk_init(void) * to IDF-11064. */ clk_ll_soc_root_clk_auto_gating_bypass(true); - ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet"); -#if 0 // TODO: [ESP32C5] IDF-8844 - uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0; - uint32_t common_perip_clk1 = 0; - soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW || - rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) { - common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG); - wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG); - } else { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | + if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) \ + && (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) \ + && (rst_reason != RESET_REASON_CPU0_JTAG) && (rst_reason != RESET_REASON_CPU0_LOCKUP)) { #if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | + uart_ll_enable_bus_clock(UART_NUM_0, false); + uart_ll_sclk_disable(&UART0); +#elif CONFIG_ESP_CONSOLE_UART_NUM != 1 + uart_ll_sclk_disable(&UART1); + uart_ll_enable_bus_clock(UART_NUM_1, false); #endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | + i2c_ll_enable_bus_clock(0, false); + i2c_ll_enable_controller_clock(&I2C0, false); + rmt_ll_enable_bus_clock(0, false); + rmt_ll_enable_group_clock(0, false); + ledc_ll_enable_clock(&LEDC, false); + ledc_ll_enable_bus_clock(false); + clk_ll_enable_timergroup_rtc_calibration_clock(false); + timer_ll_enable_clock(0, 0, false); + timer_ll_enable_clock(1, 0, false); + _timer_ll_enable_bus_clock(0, false); + _timer_ll_enable_bus_clock(1, false); + twaifd_ll_enable_clock(0, false); + twaifd_ll_enable_bus_clock(0, false); + twaifd_ll_enable_clock(1, false); + twaifd_ll_enable_bus_clock(1, false); + i2s_ll_enable_bus_clock(0, false); + i2s_ll_tx_disable_clock(&I2S0); + i2s_ll_rx_disable_clock(&I2S0); + adc_ll_enable_bus_clock(false); + pcnt_ll_enable_bus_clock(0, false); + etm_ll_enable_bus_clock(0, false); + mcpwm_ll_enable_bus_clock(0, false); + mcpwm_ll_group_enable_clock(0, false); + parlio_ll_rx_enable_clock(&PARL_IO, false); + parlio_ll_tx_enable_clock(&PARL_IO, false); + parlio_ll_enable_bus_clock(0, false); + ahb_dma_ll_force_enable_reg_clock(&AHB_DMA, false); + _gdma_ll_enable_bus_clock(0, false); +#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP + mspi_timing_ll_enable_core_clock(0, false); #endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_I2S0_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; + spi_ll_enable_bus_clock(SPI2_HOST, false); + temperature_sensor_ll_bus_clk_enable(false); + pau_ll_enable_bus_clock(false); +#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD + /* Disable ASSIST Debug module clock if PC recoreding function is not used, + * if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */ + assist_debug_ll_enable_bus_clock(false); +#endif + mpi_ll_enable_bus_clock(false); + aes_ll_enable_bus_clock(false); + sha_ll_enable_bus_clock(false); + ecc_ll_enable_bus_clock(false); + hmac_ll_enable_bus_clock(false); + ds_ll_enable_bus_clock(false); + apm_ll_hp_tee_enable_clk_gating(true); + apm_ll_lp_tee_enable_clk_gating(true); + uhci_ll_enable_bus_clock(0, false); + apm_ll_hp_apm_enable_ctrl_clk_gating(true); + apm_ll_cpu_apm_enable_ctrl_clk_gating(true); - common_perip_clk1 = 0; - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | - SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_UNUSED_BIT5 | - SYSTEM_WIFI_CLK_UNUSED_BIT12; + // TODO: Replace with hal implementation + REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN); + REG_CLR_BIT(PCR_TCM_MEM_MONITOR_CONF_REG, PCR_TCM_MEM_MONITOR_CLK_EN); + REG_CLR_BIT(PCR_PSRAM_MEM_MONITOR_CONF_REG, PCR_PSRAM_MEM_MONITOR_CLK_EN); + REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN); + REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN); + WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0); + +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + // Disable USB-Serial-JTAG clock and it's pad if not used + usb_serial_jtag_ll_phy_enable_pad(false); + usb_serial_jtag_ll_enable_bus_clock(false); + usb_serial_jtag_ll_enable_mem_clock(false); + usb_serial_jtag_ll_set_mem_pd(true); +#endif } - //Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state. - common_perip_clk |= SYSTEM_I2S0_CLK_EN | -#if CONFIG_ESP_CONSOLE_UART_NUM != 0 - SYSTEM_UART_CLK_EN | -#endif -#if CONFIG_ESP_CONSOLE_UART_NUM != 1 - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S0_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; - common_perip_clk1 = 0; + if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \ + || (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \ + || (rst_reason == RESET_REASON_CORE_PWR_GLITCH)) { + _lp_i2c_ll_enable_bus_clock(0, false); + lp_uart_ll_sclk_disable(0); + _lp_uart_ll_enable_bus_clock(0, false); + _lp_core_ll_enable_bus_clock(false); + _rtcio_ll_enable_io_clock(false); + _lp_clkrst_ll_enable_rng_clock(false); + _lp_clkrst_ll_enable_otp_dbg_clock(false); + _lp_clkrst_ll_enable_lp_ana_i2c_clock(false); + _lp_clkrst_ll_enable_lp_ext_i2c_clock(false); - /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock, - * the current is not reduced when disable I2S clock. - */ - // TOCK(check replacement) - // REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - // REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL); - - /* Disable some peripheral clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk); - - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1); - - /* Disable hardware crypto clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk); - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk); - - /* Disable WiFi/BT/SDIO clocks. */ - CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk); - SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN); - - /* Set WiFi light sleep clock source to RTC slow clock */ - REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); - CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M); - SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW); - - /* Enable RNG clock. */ - periph_module_enable(PERIPH_RNG_MODULE); -#endif + apm_ll_lp_apm_enable_ctrl_clk_gating(true); + apm_ll_lp_apm0_enable_ctrl_clk_gating(true); + WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0); + } } diff --git a/components/esp_system/port/soc/esp32c6/clk.c b/components/esp_system/port/soc/esp32c6/clk.c index 1c2997c419..121621c577 100644 --- a/components/esp_system/port/soc/esp32c6/clk.c +++ b/components/esp_system/port/soc/esp32c6/clk.c @@ -224,7 +224,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) * precision sleep clock (for example, the BLE needs to use the main XTAL * oscillator (40 MHz) to provide the clock during the sleep process in some * scenarios), the module needs to switch to the required clock source by - * itself. */ //TODO - WIFI-5233 + * itself. */ soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)(\ (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW \ diff --git a/components/esp_system/port/soc/esp32c61/clk.c b/components/esp_system/port/soc/esp32c61/clk.c index 0e51476772..00942220af 100644 --- a/components/esp_system/port/soc/esp32c61/clk.c +++ b/components/esp_system/port/soc/esp32c61/clk.c @@ -188,7 +188,7 @@ __attribute__((weak)) void esp_perip_clk_init(void) * precision sleep clock (for example, the BLE needs to use the main XTAL * oscillator (40 MHz) to provide the clock during the sleep process in some * scenarios), the module needs to switch to the required clock source by - * itself. */ //TODO - WIFI-5233 + * itself. */ soc_rtc_slow_clk_src_t rtc_slow_clk_src = rtc_clk_slow_src_get(); modem_clock_lpclk_src_t modem_lpclk_src = (modem_clock_lpclk_src_t)( (rtc_slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? MODEM_CLOCK_LPCLK_SRC_RC_SLOW diff --git a/components/esp_system/startup_funcs.c b/components/esp_system/startup_funcs.c index 2c1279a87b..204108f128 100644 --- a/components/esp_system/startup_funcs.c +++ b/components/esp_system/startup_funcs.c @@ -163,6 +163,17 @@ ESP_SYSTEM_INIT_FN(init_coexist, SECONDARY, BIT(0), 204) } #endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED +ESP_SYSTEM_INIT_FN(init_bootloader_offset, SECONDARY, BIT(0), 205) +{ + // The bootloader offset variable in ROM is stored in a memory that will be reclaimed by heap component. + // Reading it before the heap is initialized helps to preserve the value. + volatile int bootloader_offset = esp_rom_get_bootloader_offset(); + (void)bootloader_offset; + return ESP_OK; +} +#endif // SOC_RECOVERY_BOOTLOADER_SUPPORTED + #ifndef CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE ESP_SYSTEM_INIT_FN(init_disable_rtc_wdt, SECONDARY, BIT(0), 999) { diff --git a/components/esp_system/system_init_fn.txt b/components/esp_system/system_init_fn.txt index 7f4b2d06fd..0d68cf299d 100644 --- a/components/esp_system/system_init_fn.txt +++ b/components/esp_system/system_init_fn.txt @@ -88,7 +88,6 @@ SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/p SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/lowpower/port/esp32p4/sleep_clock.c on BIT(0) SECONDARY: 107: sleep_sys_periph_startup_init in components/esp_hw_support/sleep_system_peripheral.c on BIT(0) SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c5/sleep_mmu.c on BIT(0) -SECONDARY: 108: sleep_mmu_startup_init in components/esp_hw_support/lowpower/port/esp32c61/sleep_mmu.c on BIT(0) # app_trace has to be initialized before systemview SECONDARY: 115: esp_apptrace_init in components/app_trace/app_trace.c on ESP_SYSTEM_INIT_ALL_CORES @@ -109,6 +108,7 @@ SECONDARY: 151: nvs_sec_provider_register_hmac_scheme in components/nvs_sec_prov SECONDARY: 201: init_pm in components/esp_system/startup_funcs.c on BIT(0) SECONDARY: 203: init_apb_dma in components/esp_system/startup_funcs.c on BIT(0) SECONDARY: 204: init_coexist in components/esp_system/startup_funcs.c on BIT(0) +SECONDARY: 205: init_bootloader_offset in components/esp_system/startup_funcs.c on BIT(0) # usb_console needs to create an esp_timer at startup. # This can be done only after esp_timer initialization (esp_timer_init_os). diff --git a/components/esp_tee/subproject/main/common/panic/esp_tee_panic.c b/components/esp_tee/subproject/main/common/panic/esp_tee_panic.c index 4e060f2a57..4db95e4768 100644 --- a/components/esp_tee/subproject/main/common/panic/esp_tee_panic.c +++ b/components/esp_tee/subproject/main/common/panic/esp_tee_panic.c @@ -106,23 +106,18 @@ void tee_apm_violation_isr(void *arg) intptr_t exc_sp = RV_READ_CSR(mscratch); RvExcFrame *frame = (RvExcFrame *)exc_sp; - apm_ctrl_path_t *apm_excp_type = (apm_ctrl_path_t *)arg; - apm_ctrl_exception_info_t excp_info = { - .apm_path = { - .apm_ctrl = apm_excp_type->apm_ctrl, - .apm_m_path = apm_excp_type->apm_m_path, - } - }; + apm_hal_ctrl_info_t *ctrl_info = (apm_hal_ctrl_info_t *)arg; + apm_ctrl_exception_info_t excp_info = {}; - apm_hal_apm_ctrl_get_exception_info(&excp_info); - apm_hal_apm_ctrl_exception_clear(apm_excp_type); + apm_hal_get_exception_info(ctrl_info, &excp_info); + apm_hal_clear_exception_status(ctrl_info); int fault_core = esp_cpu_get_core_id(); - panic_print_rsn((const void *)frame, fault_core, esp_tee_apm_excp_type_to_str(excp_info.excp_type)); + panic_print_rsn((const void *)frame, fault_core, esp_tee_apm_excp_type_to_str(excp_info.type)); - tee_panic_print("Access addr: 0x%x | Mode: %s\n", excp_info.excp_addr, esp_tee_apm_excp_mode_to_str(excp_info.excp_mode)); - tee_panic_print("Module: %s | Path: %d\n", esp_tee_apm_excp_ctrl_to_str(excp_info.apm_path.apm_ctrl), excp_info.apm_path.apm_m_path); - tee_panic_print("Master: %s | Region: %d\n", esp_tee_apm_excp_mid_to_str(excp_info.excp_id), (excp_info.excp_regn == 0) ? 0 : (__builtin_ffs(excp_info.excp_regn) - 1)); + tee_panic_print("Access addr: 0x%x | Mode: %s\n", excp_info.addr, esp_tee_apm_excp_mode_to_str(excp_info.mode)); + tee_panic_print("Module: %s | Path: %d\n", esp_tee_apm_excp_ctrl_to_str(ctrl_info->ctrl_mod), ctrl_info->path); + tee_panic_print("Master: %s | Region: %d\n", esp_tee_apm_excp_mid_to_str(excp_info.id), (excp_info.regn == 0) ? 0 : (__builtin_ffs(excp_info.regn) - 1)); panic_print_info((const void *)frame, fault_core); ESP_INFINITE_LOOP(); diff --git a/components/esp_tee/subproject/main/core/esp_secure_services_iram.c b/components/esp_tee/subproject/main/core/esp_secure_services_iram.c index ffa5110662..17b2bc2e61 100644 --- a/components/esp_tee/subproject/main/core/esp_secure_services_iram.c +++ b/components/esp_tee/subproject/main/core/esp_secure_services_iram.c @@ -212,6 +212,11 @@ uint32_t _ss_spi_flash_hal_check_status(spi_flash_host_inst_t *host) esp_err_t _ss_spi_flash_hal_common_command(spi_flash_host_inst_t *host, spi_flash_trans_t *trans) { + bool paddr_chk = esp_tee_flash_check_paddr_in_tee_region(trans->address); + if (paddr_chk) { + ESP_LOGD(TAG, "[%s] Illegal flash access at 0x%08x", __func__, trans->address); + return ESP_FAIL; + } return spi_flash_hal_common_command(host, trans); } diff --git a/components/esp_tee/subproject/main/soc/common/esp_tee_apm_intr.c b/components/esp_tee/subproject/main/soc/common/esp_tee_apm_intr.c index d6c4dea1db..744e5dd2d9 100644 --- a/components/esp_tee/subproject/main/soc/common/esp_tee_apm_intr.c +++ b/components/esp_tee/subproject/main/soc/common/esp_tee_apm_intr.c @@ -6,26 +6,42 @@ #include #include "soc/soc_caps.h" +#include "hal/apm_types.h" #include "esp_bit_defs.h" -#include "hal/apm_hal.h" -#include "hal/apm_ll.h" +#include "esp_tee.h" +#include "esp_tee_apm_intr.h" static const char *const excp_mid_strs[] = { - [APM_LL_MASTER_HPCORE] = "HPCORE", - [APM_LL_MASTER_LPCORE] = "LPCORE", - [APM_LL_MASTER_REGDMA] = "REGDMA", - [APM_LL_MASTER_SDIOSLV] = "SDIOSLV", - [APM_LL_MASTER_MODEM] = "MODEM", - [APM_LL_MASTER_MEM_MONITOR] = "MEM_MONITOR", - [APM_LL_MASTER_TRACE] = "TRACE", - [APM_LL_MASTER_GDMA_SPI2] = "GDMA_SPI2", - [APM_LL_MASTER_GDMA_UHCI0] = "GDMA_UHCI0", - [APM_LL_MASTER_GDMA_I2S0] = "GDMA_I2S0", - [APM_LL_MASTER_GDMA_AES] = "GDMA_AES", - [APM_LL_MASTER_GDMA_SHA] = "GDMA_SHA", - [APM_LL_MASTER_GDMA_ADC] = "GDMA_ADC", - [APM_LL_MASTER_GDMA_PARLIO] = "GDMA_PARLIO", + [APM_MASTER_HPCORE] = "HPCORE", +#if SOC_LP_CORE_SUPPORTED + [APM_MASTER_LPCORE] = "LPCORE", +#endif /* SOC_LP_CORE_SUPPORTED */ + [APM_MASTER_REGDMA] = "REGDMA", +#if SOC_SDIO_SLAVE_SUPPORTED + [APM_MASTER_SDIOSLV] = "SDIOSLV", +#endif /* SOC_SDIO_SLAVE_SUPPORTED */ + [APM_MASTER_MODEM] = "MODEM", + [APM_MASTER_MEM_MON] = "MEM_MONITOR", + [APM_MASTER_TRACE] = "TRACE", +#if SOC_SPIRAM_SUPPORTED + [APM_MASTER_PSRAM_MEM_MON] = "PSRAM_MEM_MONITOR", +#endif /* SOC_SPIRAM_SUPPORTED */ +#if SOC_GPSPI_SUPPORTED + [APM_MASTER_GDMA_GPSPI] = "GDMA_GPSPI", +#endif /* SOC_GPSPI_SUPPORTED */ +#if SOC_UHCI_SUPPORTED + [APM_MASTER_GDMA_UHCI] = "GDMA_UHCI", +#endif /* SOC_UHCI_SUPPORTED */ + [APM_MASTER_GDMA_I2S] = "GDMA_I2S", +#if SOC_AES_SUPPORTED + [APM_MASTER_GDMA_AES] = "GDMA_AES", +#endif /* SOC_AES_SUPPORTED */ + [APM_MASTER_GDMA_SHA] = "GDMA_SHA", + [APM_MASTER_GDMA_ADC] = "GDMA_ADC", +#if SOC_PARLIO_SUPPORTED + [APM_MASTER_GDMA_PARLIO] = "GDMA_PARLIO", +#endif /* SOC_PARLIO_SUPPORTED */ }; const char *esp_tee_apm_excp_mid_to_str(uint8_t mid) @@ -49,22 +65,27 @@ const char *esp_tee_apm_excp_type_to_str(uint8_t type) return excp_type; } -const char *esp_tee_apm_excp_ctrl_to_str(apm_ll_apm_ctrl_t apm_ctrl) +const char *esp_tee_apm_excp_ctrl_to_str(apm_ctrl_module_t ctrl_mod) { char *excp_ctrl = NULL; - switch (apm_ctrl) { + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + excp_ctrl = "HP_APM"; + break; + case APM_CTRL_LP_APM: + excp_ctrl = "LP_APM"; + break; #if SOC_APM_LP_APM0_SUPPORTED - case LP_APM0_CTRL: + case APM_CTRL_LP_APM0: excp_ctrl = "LP_APM0"; break; #endif - case HP_APM_CTRL: - excp_ctrl = "HP_APM"; - break; - case LP_APM_CTRL: - excp_ctrl = "LP_APM"; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + excp_ctrl = "CPU_APM"; break; +#endif default: excp_ctrl = "Unknown"; break; @@ -78,14 +99,14 @@ const char *esp_tee_apm_excp_mode_to_str(uint8_t mode) char *excp_mode = NULL; switch (mode) { - case APM_LL_SECURE_MODE_TEE: - case APM_LL_SECURE_MODE_REE0: + case APM_SEC_MODE_TEE: + case APM_SEC_MODE_REE0: excp_mode = "REE0"; break; - case APM_LL_SECURE_MODE_REE1: + case APM_SEC_MODE_REE1: excp_mode = "REE1"; break; - case APM_LL_SECURE_MODE_REE2: + case APM_SEC_MODE_REE2: excp_mode = "REE2"; break; default: diff --git a/components/esp_tee/subproject/main/soc/common/include/esp_tee_apm_intr.h b/components/esp_tee/subproject/main/soc/common/include/esp_tee_apm_intr.h index 6019df64b3..23f4b88025 100644 --- a/components/esp_tee/subproject/main/soc/common/include/esp_tee_apm_intr.h +++ b/components/esp_tee/subproject/main/soc/common/include/esp_tee_apm_intr.h @@ -5,7 +5,7 @@ */ #pragma once -#include "hal/apm_hal.h" +#include "hal/apm_types.h" #ifdef __cplusplus extern "C" { @@ -15,7 +15,7 @@ const char *esp_tee_apm_excp_mid_to_str(uint8_t mid); const char *esp_tee_apm_excp_type_to_str(uint8_t type); -const char *esp_tee_apm_excp_ctrl_to_str(apm_ll_apm_ctrl_t apm_ctrl); +const char *esp_tee_apm_excp_ctrl_to_str(apm_ctrl_module_t apm_ctrl); const char *esp_tee_apm_excp_mode_to_str(uint8_t mode); diff --git a/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c b/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c index 352375467f..4dedbc6c17 100644 --- a/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c +++ b/components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c @@ -3,16 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_log.h" -#include "esp_tee.h" -#include "esp_tee_intr.h" +#include -#include "hal/apm_hal.h" #include "soc/soc.h" +#include "soc/soc_caps.h" #include "soc/spi_mem_reg.h" #include "soc/efuse_reg.h" #include "soc/pcr_reg.h" +#include "soc/apm_defs.h" +#include "hal/apm_types.h" +#include "hal/apm_hal.h" + +#include "esp_log.h" +#include "esp_tee.h" +#include "esp_tee_intr.h" + extern void tee_apm_violation_isr(void *arg); static const char *TAG = "esp_tee_apm_prot_cfg"; @@ -44,125 +50,6 @@ static const char *TAG = "esp_tee_apm_prot_cfg"; #define HP_APM_SPI1_REG_END HP_APM_SPI1_REG_START #endif -/*----------------------- HP APM range and filter configuration -----------------------*/ - -/* HP_APM: TEE mode accessible regions */ -apm_ctrl_region_config_data_t hp_apm_pms_data_tee[] = { - /* Region 0: Entire memory region (RWX)*/ - { - .regn_num = 0, - .regn_start_addr = 0x0, - .regn_end_addr = ~0x0, - .regn_pms = 0x7, - .filter_enable = 1, - }, -}; - -/* HP_APM: REE0 mode accessible regions */ -apm_ctrl_region_config_data_t hp_apm_pms_data[] = { - /* NOTE: Without this entry, the REE SRAM region becomes inaccessible to - * the MODEM master, resulting in an APM violation during Wi-Fi initialization. - */ - /* Region 1: REE SRAM region (RW) */ - { - .regn_num = 1, - .regn_start_addr = SOC_NS_IRAM_START, - .regn_end_addr = SOC_IRAM_HIGH, - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 2: RTC memory (RWX) */ - { - .regn_num = 2, - .regn_start_addr = SOC_RTC_IRAM_LOW, - .regn_end_addr = SOC_RTC_IRAM_HIGH, - .regn_pms = 0x7, - .filter_enable = 1, - }, - /* Region 3: Peripherals [Start - MMU] (RW) */ - /* Protected: MMU */ - { - .regn_num = 3, - .regn_start_addr = SOC_PERIPHERAL_LOW, - .regn_end_addr = (SPI_MEM_MMU_ITEM_CONTENT_REG(0) - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 4: Peripherals [MMU - SPI1] (RW) */ - /* Protected: SPI1 */ - { - .regn_num = 4, - .regn_start_addr = SPI_MEM_MMU_POWER_CTRL_REG(0), - .regn_end_addr = (HP_APM_SPI1_REG_START - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 5: Peripherals [SPI1 - Interrupt Matrix] (RW) */ - /* Protected: Interrupt Matrix */ - { - .regn_num = 5, - .regn_start_addr = HP_APM_SPI1_REG_END, - .regn_end_addr = (DR_REG_INTMTX_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 6/7: Peripherals [H/W Lock - HMAC] (RW) */ - /* Protected: AES, SHA, ECC, DS, HMAC */ - { - .regn_num = 6, - .regn_start_addr = DR_REG_ATOMIC_BASE, - .regn_end_addr = (DR_REG_AES_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 7, - .regn_start_addr = DR_REG_RSA_BASE, - .regn_end_addr = (DR_REG_ECC_MULT_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 8/9/10: Peripherals [IO_MUX - TEE Controller & APM] (RW) */ - /* Protected: AES, SHA, ECC, DS and HMAC PCRs, APM, TEE Controller */ - { - .regn_num = 8, - .regn_start_addr = DR_REG_IO_MUX_BASE, - .regn_end_addr = (PCR_AES_CONF_REG - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 9, - .regn_start_addr = PCR_RSA_CONF_REG, - .regn_end_addr = (PCR_ECC_CONF_REG - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 10, - .regn_start_addr = PCR_IOMUX_CONF_REG, - .regn_end_addr = (DR_REG_TEE_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 11: Peripherals [Miscellaneous - PMU] (RW) */ - { - .regn_num = 11, - .regn_start_addr = DR_REG_MISC_BASE, - .regn_end_addr = (DR_REG_PMU_BASE - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 12: Peripherals [DEBUG - PWDET] (RW) */ - { - .regn_num = 12, - .regn_start_addr = DR_REG_OPT_DEBUG_BASE, - .regn_end_addr = 0x600D0000, - .regn_pms = 0x6, - .filter_enable = 1, - }, -}; - /* NOTE: Following are the master IDs for setting the security mode and access through APM: * +---------+-------------+ * | Bit | Source | @@ -189,177 +76,176 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = { * +---------+-------------+ */ -/* HP_APM: TEE mode masters' configuration */ -apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data_tee = { - .apm_ctrl = HP_APM_CTRL, - .apm_m_cnt = HP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_TEE, - /* Crypto DMA (AES/SHA) and HP_CPU */ - .master_ids = 0xC00001, - .pms_data = hp_apm_pms_data_tee, +#define APM_MASTERS_ALL (0xFFFFFFFFU) +#define APM_MASTERS_HP_CPU (BIT(APM_MASTER_HPCORE)) +#define APM_MASTERS_LP_CPU (BIT(APM_MASTER_LPCORE)) +#define APM_MASTERS_GDMA_CRYPTO (BIT(APM_MASTER_GDMA_AES) | BIT(APM_MASTER_GDMA_SHA)) +#define APM_MASTERS_TEE (APM_MASTERS_HP_CPU | APM_MASTERS_GDMA_CRYPTO) +#define APM_MASTERS_REE (APM_MASTERS_ALL & ~(APM_MASTERS_TEE)) + +/*----------------------- TEE mode configuration -----------------------*/ + +/** + * NOTE: Fixes APM filter behavior to allow unrestricted access for TEE mode. + * + * By default, TEE mode should have unrestricted access to the entire CPU address space. + * However, it has been observed that when APM filters are enabled, TEE mode + * accesses are incorrectly being filtered based on the region configurations and + * access attributes set for REE[0..2] modes. + */ +static void enable_tee_mode_access(void) +{ + uint32_t regn_num = 0; + uint32_t regn_start_addr = 0x00; + uint32_t regn_end_addr = UINT32_MAX; + + /* HP_APM */ + apm_ll_hp_apm_set_region_start_addr(regn_num, regn_start_addr); + apm_ll_hp_apm_set_region_end_addr(regn_num, regn_end_addr); + apm_ll_hp_apm_enable_region_filter(regn_num, true); + /* LP_APM */ + apm_ll_lp_apm_set_region_start_addr(regn_num, regn_start_addr); + apm_ll_lp_apm_set_region_end_addr(regn_num, regn_end_addr); + apm_ll_lp_apm_enable_region_filter(regn_num, true); + /* LP_APM0 */ + apm_ll_lp_apm0_set_region_start_addr(regn_num, regn_start_addr); + apm_ll_lp_apm0_set_region_end_addr(regn_num, regn_end_addr); + apm_ll_lp_apm0_enable_region_filter(regn_num, true); +} + +/*----------------------- REE0 mode configuration -----------------------*/ + +/*----------------------- HP_APM configuration -----------------------*/ + +/* HP_APM: REE0 mode accessible regions */ +static apm_hal_ctrl_region_cfg_t hp_apm_regn_cfg_ree0[] = { + /* Region 1: CPU peripherals (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 1, DR_REG_TRACE_BASE, 0x600D0000, APM_PERM_R | APM_PERM_W), + + /* NOTE: Without this entry, the REE SRAM region becomes inaccessible to + * the MODEM master, resulting in an APM violation during Wi-Fi initialization. + */ + /* Region 2: REE SRAM region (RW) - for all other masters except LP_CORE */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M1, 2, SOC_NS_IRAM_START, SOC_IRAM_HIGH, APM_PERM_R | APM_PERM_W), + /* Region 2: REE SRAM region (RW) - for all LP_CORE */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M2, 2, SOC_NS_IRAM_START, SOC_IRAM_HIGH, APM_PERM_R | APM_PERM_W), + + /* Region 3: Peripherals [Start - MMU] (RW) */ + /* Protected: MMU */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 3, SOC_PERIPHERAL_LOW, SPI_MEM_MMU_ITEM_CONTENT_REG(0), APM_PERM_R | APM_PERM_W), + + /* Region 4: Peripherals [MMU - SPI1] (RW) */ + /* Protected: SPI1 */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 4, SPI_MEM_MMU_POWER_CTRL_REG(0), HP_APM_SPI1_REG_START, APM_PERM_R | APM_PERM_W), + + /* Region 5: Peripherals [SPI1 - Interrupt Matrix] (RW) */ + /* Protected: Interrupt Matrix */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 5, HP_APM_SPI1_REG_END, DR_REG_INTMTX_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 6/7: Peripherals [H/W Lock - HMAC] (RW) */ + /* Protected: AES, SHA, ECC, DS, HMAC */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 6, DR_REG_ATOMIC_BASE, DR_REG_AES_BASE, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 7, DR_REG_RSA_BASE, DR_REG_ECC_MULT_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 8/9/10: Peripherals [IO_MUX - TEE Controller & APM] (RW) */ + /* Protected: AES, SHA, ECC, DS and HMAC PCRs, APM, TEE Controller */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 8, DR_REG_IO_MUX_BASE, PCR_AES_CONF_REG, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 9, PCR_RSA_CONF_REG, PCR_ECC_CONF_REG, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 10, PCR_IOMUX_CONF_REG, DR_REG_TEE_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 11: Peripherals [Miscellaneous - PMU] (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 11, DR_REG_MISC_BASE, DR_REG_PMU_BASE, APM_PERM_R | APM_PERM_W), }; /* HP_APM: REE0 mode masters' configuration */ -apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data = { - .apm_ctrl = HP_APM_CTRL, - .apm_m_cnt = HP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_REE0, - /* All masters except crypto DMA (AES/SHA) and HP CPU */ - .master_ids = 0xFF3FFFFE, - .pms_data = hp_apm_pms_data, -}; +static apm_hal_ctrl_sec_mode_cfg_t hp_apm_ctrl_sec_mode_cfg_ree0 = + APM_HAL_SEC_MODE_CFG(APM_CTRL_HP_APM, APM_SEC_MODE_REE0, hp_apm_regn_cfg_ree0); -/*----------------------- LP_APM0 range and filter configuration -----------------------*/ +/*----------------------- LP_APM configuration -----------------------*/ -/* LP_APM0: REE0 mode accessible regions */ -apm_ctrl_region_config_data_t lp_apm0_pms_data[] = { - /* Region 0: RTC memory (RWX) */ - { - .regn_num = 0, - .regn_start_addr = SOC_RTC_IRAM_LOW, - .regn_end_addr = SOC_RTC_IRAM_HIGH, - .regn_pms = 0x7, - .filter_enable = 1, - }, -}; - -/* LP_APM0: REE0 mode masters' configuration */ -apm_ctrl_secure_mode_config_t lp_apm0_sec_mode_data = { - .apm_ctrl = LP_APM0_CTRL, - .apm_m_cnt = LP_APM0_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_REE0, - /* LP_CPU */ - .master_ids = 0x2, - .pms_data = lp_apm0_pms_data, -}; - -/*----------------------- LP_APM range and filter configuration -----------------------*/ - -/* LP_APM: TEE mode accessible regions */ -apm_ctrl_region_config_data_t lp_apm_pms_data_tee[] = { - /* Region 0: Entire memory region (RWX) */ - { - .regn_num = 0, - .regn_start_addr = 0x0, - .regn_end_addr = ~0x0, - .regn_pms = 0x7, - .filter_enable = 1, - }, -}; - -/* LP_APM: REE0 mode accessible regions */ -apm_ctrl_region_config_data_t lp_apm_pms_data[] = { +static apm_hal_ctrl_region_cfg_t lp_apm_regn_cfg_ree0[] = { /* Region 1: RTC memory (RWX) */ - { - .regn_num = 1, - .regn_start_addr = SOC_RTC_IRAM_LOW, - .regn_end_addr = SOC_RTC_IRAM_HIGH, - .regn_pms = 0x7, - .filter_enable = 1, - }, + /* NOTE: LP_MEM gets automatically remapped to an offset of 0x20000000 + * when accessed in low-speed mode */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 1, SOC_RTC_IRAM_LOW + 0x20000000, SOC_RTC_IRAM_HIGH + 0x20000000, APM_PERM_ALL), + /* Region 2: LP Peripherals [PMU - eFuse BLK x] (RW) */ /* Protected: eFuse BLK x */ - { - .regn_num = 2, - .regn_start_addr = DR_REG_PMU_BASE, - .regn_end_addr = (LP_APM_EFUSE_REG_START - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 3: LP Peripherals [eFuse - END] (RW) */ - { - .regn_num = 3, - .regn_start_addr = LP_APM_EFUSE_REG_END, - .regn_end_addr = (DR_REG_TRACE_BASE - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, -}; + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M1, 2, DR_REG_PMU_BASE, LP_APM_EFUSE_REG_START, APM_PERM_R | APM_PERM_W), -/* LP_APM0: TEE mode masters' configuration */ -apm_ctrl_secure_mode_config_t lp_apm_sec_mode_data_tee = { - .apm_ctrl = LP_APM_CTRL, - .apm_m_cnt = LP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_TEE, - /* HP_CPU and LP_CPU */ - .master_ids = 0x3, - .pms_data = lp_apm_pms_data_tee, + /* Region 3: LP Peripherals [eFuse - END] (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M1, 3, LP_APM_EFUSE_REG_END, DR_REG_TRACE_BASE, APM_PERM_R | APM_PERM_W), }; /* LP_APM: REE0 mode masters' configuration */ -apm_ctrl_secure_mode_config_t lp_apm_sec_mode_data = { - .apm_ctrl = LP_APM_CTRL, - .apm_m_cnt = LP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_REE0, - /* HP_CPU and LP_CPU */ - .master_ids = 0x3, - .pms_data = lp_apm_pms_data, +static apm_hal_ctrl_sec_mode_cfg_t lp_apm_ctrl_sec_mode_cfg_ree0 = + APM_HAL_SEC_MODE_CFG(APM_CTRL_LP_APM, APM_SEC_MODE_REE0, lp_apm_regn_cfg_ree0); + +/*----------------------- LP_APM0 configuration -----------------------*/ + +/* LP_APM0: REE0 mode accessible regions */ +static apm_hal_ctrl_region_cfg_t lp_apm0_regn_cfg_ree0[] = { + /* Region 0: RTC memory (RWX) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 1, SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH, APM_PERM_ALL), }; +/* LP_APM0: REE0 mode masters' configuration */ +static apm_hal_ctrl_sec_mode_cfg_t lp_apm0_ctrl_sec_mode_cfg_ree0 = + APM_HAL_SEC_MODE_CFG(APM_CTRL_LP_APM0, APM_SEC_MODE_REE0, lp_apm0_regn_cfg_ree0); + /*---------------- TEE APM API-----------------------*/ -void esp_tee_apm_int_enable(apm_ctrl_secure_mode_config_t *sec_mode_data) +static void enable_apm_intr(apm_ctrl_module_t ctrl_mod, uint32_t path_count) { - for (int i = 0; i < sec_mode_data->apm_m_cnt; i++) { - apm_ctrl_path_t *apm_excp_data = calloc(1, sizeof(apm_ctrl_path_t)); - assert(apm_excp_data != NULL); + for (uint32_t i = 0; i < path_count; i++) { + apm_hal_ctrl_info_t *ctrl_info = calloc(1, sizeof(apm_hal_ctrl_info_t)); + assert(ctrl_info != NULL); - apm_excp_data->apm_ctrl = sec_mode_data->apm_ctrl; - apm_excp_data->apm_m_path = i; + ctrl_info->ctrl_mod = ctrl_mod; + ctrl_info->path = i; - int intr_src_num = apm_hal_apm_ctrl_get_int_src_num(apm_excp_data); + int intr_src_num = apm_hal_get_intr_src_num(ctrl_info); struct vector_desc_t apm_vd = {0}; apm_vd.source = intr_src_num; apm_vd.isr = tee_apm_violation_isr; - apm_vd.arg = (void *)apm_excp_data; + apm_vd.arg = (void *)ctrl_info; /* Register interrupt handler with TEE. */ esp_tee_intr_register((void *)&apm_vd); - /* Enable APM Ctrl intewrrupt for access path(M[0:n]) */ - apm_hal_apm_ctrl_exception_clear(apm_excp_data); - apm_hal_apm_ctrl_interrupt_enable(apm_excp_data, true); + /* Enable APM Ctrl interrupt for access path(M[0:n]) */ + apm_hal_clear_exception_status(ctrl_info); + apm_hal_enable_intr(ctrl_info, true); } } void esp_tee_configure_apm_protection(void) { /* Disable all control filter first to have full access of address rage. */ - apm_hal_apm_ctrl_filter_enable_all(false); + apm_hal_enable_ctrl_filter_all(false); - /* Switch HP_CPU to TEE mode */ - apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_TEE); + /* Enable TEE mode access for all APM modules */ + enable_tee_mode_access(); - /* LP APM0 configuration. */ - lp_apm0_sec_mode_data.regn_count = sizeof(lp_apm0_pms_data) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm0_sec_mode_data); + /* HP_APM REE0 configuration. */ + apm_hal_set_ctrl_sec_mode_cfg(&hp_apm_ctrl_sec_mode_cfg_ree0); + /* HP_APM interrupt configuration. */ + enable_apm_intr(APM_CTRL_HP_APM, APM_CTRL_HP_APM_PATH_NUM); + ESP_LOGD(TAG, "[HP_APM] Configured for REE0"); - /* LP APM0 interrupt configuration. */ - esp_tee_apm_int_enable(&lp_apm0_sec_mode_data); - ESP_LOGD(TAG, "[REE0] LP_APM0 configured"); + /* LP_APM REE0 configuration. */ + apm_hal_set_ctrl_sec_mode_cfg(&lp_apm_ctrl_sec_mode_cfg_ree0); + /* LP_APM interrupt configuration. */ + enable_apm_intr(APM_CTRL_LP_APM, APM_CTRL_LP_APM_PATH_NUM); + ESP_LOGD(TAG, "[LP_APM] Configured for REE0"); - /* LP APM TEE configuration. */ - lp_apm_sec_mode_data_tee.regn_count = sizeof(lp_apm_pms_data_tee) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm_sec_mode_data_tee); - ESP_LOGD(TAG, "[TEE] LP_APM configured"); + /* LP_APM0 REE0 configuration. */ + apm_hal_set_ctrl_sec_mode_cfg(&lp_apm0_ctrl_sec_mode_cfg_ree0); + enable_apm_intr(APM_CTRL_LP_APM0, APM_CTRL_LP_APM0_PATH_NUM); + ESP_LOGD(TAG, "[LP_APM0] Configured for REE0"); - /* LP APM configuration. */ - lp_apm_sec_mode_data.regn_count = sizeof(lp_apm_pms_data) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm_sec_mode_data); - /* LP APM interrupt configuration. */ - esp_tee_apm_int_enable(&lp_apm_sec_mode_data); - ESP_LOGD(TAG, "[REE0] LP_APM configured"); - - /* HP APM TEE configuration. */ - hp_apm_sec_mode_data_tee.regn_count = sizeof(hp_apm_pms_data_tee) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&hp_apm_sec_mode_data_tee); - ESP_LOGD(TAG, "[TEE] HP_APM configured"); - - /* HP APM configuration. */ - hp_apm_sec_mode_data.regn_count = sizeof(hp_apm_pms_data) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&hp_apm_sec_mode_data); - /* HP APM interrupt configuration. */ - esp_tee_apm_int_enable(&hp_apm_sec_mode_data); - ESP_LOGD(TAG, "[REE0] HP_APM configured"); + /* Switch HP_CPU to TEE mode and rest of the masters to REE0 mode */ + apm_hal_set_master_sec_mode(APM_MASTERS_TEE, APM_SEC_MODE_TEE); + apm_hal_set_master_sec_mode(APM_MASTERS_REE, APM_SEC_MODE_REE0); } diff --git a/components/esp_tee/subproject/main/soc/esp32h2/esp_tee_apm_prot_cfg.c b/components/esp_tee/subproject/main/soc/esp32h2/esp_tee_apm_prot_cfg.c index af5472b4b5..582cb4700d 100644 --- a/components/esp_tee/subproject/main/soc/esp32h2/esp_tee_apm_prot_cfg.c +++ b/components/esp_tee/subproject/main/soc/esp32h2/esp_tee_apm_prot_cfg.c @@ -3,16 +3,22 @@ * * SPDX-License-Identifier: Apache-2.0 */ -#include "esp_log.h" -#include "esp_tee.h" -#include "esp_tee_intr.h" +#include -#include "hal/apm_hal.h" #include "soc/soc.h" +#include "soc/soc_caps.h" #include "soc/spi_mem_reg.h" #include "soc/efuse_reg.h" #include "soc/pcr_reg.h" +#include "soc/apm_defs.h" +#include "hal/apm_types.h" +#include "hal/apm_hal.h" + +#include "esp_log.h" +#include "esp_tee.h" +#include "esp_tee_intr.h" + extern void tee_apm_violation_isr(void *arg); static const char *TAG = "esp_tee_apm_prot_cfg"; @@ -44,125 +50,6 @@ static const char *TAG = "esp_tee_apm_prot_cfg"; #define HP_APM_SPI1_REG_END HP_APM_SPI1_REG_START #endif -/*----------------------- HP APM range and filter configuration -----------------------*/ - -/* HP_APM: TEE mode accessible regions */ -apm_ctrl_region_config_data_t hp_apm_pms_data_tee[] = { - /* Region 0: Entire memory region (RWX)*/ - { - .regn_num = 0, - .regn_start_addr = 0x0, - .regn_end_addr = ~0x0, - .regn_pms = 0x7, - .filter_enable = 1, - }, -}; - -/* HP_APM: REE0 mode accessible regions */ -apm_ctrl_region_config_data_t hp_apm_pms_data[] = { - /* NOTE: Without this entry, the REE SRAM region becomes inaccessible to - * the MODEM master, resulting in an APM violation during Wi-Fi initialization. - */ - /* Region 1: REE SRAM region (RW) */ - { - .regn_num = 1, - .regn_start_addr = SOC_NS_IRAM_START, - .regn_end_addr = SOC_IRAM_HIGH, - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 2: RTC memory (RWX) */ - { - .regn_num = 2, - .regn_start_addr = SOC_RTC_IRAM_LOW, - .regn_end_addr = SOC_RTC_IRAM_HIGH, - .regn_pms = 0x7, - .filter_enable = 1, - }, - /* Region 3: Peripherals [Start - MMU] (RW) */ - /* Protected: MMU */ - { - .regn_num = 3, - .regn_start_addr = SOC_PERIPHERAL_LOW, - .regn_end_addr = (SPI_MEM_MMU_ITEM_CONTENT_REG(0) - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 4: Peripherals [MMU - SPI1] (RW) */ - /* Protected: SPI1 */ - { - .regn_num = 4, - .regn_start_addr = SPI_MEM_MMU_POWER_CTRL_REG(0), - .regn_end_addr = (HP_APM_SPI1_REG_START - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 5: Peripherals [SPI1 - Interrupt Matrix] (RW) */ - /* Protected: Interrupt Matrix */ - { - .regn_num = 5, - .regn_start_addr = HP_APM_SPI1_REG_END, - .regn_end_addr = (DR_REG_INTMTX_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 6/7: Peripherals [H/W Lock - HMAC] (RW) */ - /* Protected: AES, SHA, ECC, DS, HMAC */ - { - .regn_num = 6, - .regn_start_addr = DR_REG_PCNT_BASE, - .regn_end_addr = (DR_REG_AES_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 7, - .regn_start_addr = DR_REG_RSA_BASE, - .regn_end_addr = (DR_REG_ECC_MULT_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 8/9/10: Peripherals [IO_MUX - TEE Controller & APM] (RW) */ - /* Protected: AES, SHA, ECC, DS and HMAC PCRs, APM, TEE Controller */ - { - .regn_num = 8, - .regn_start_addr = DR_REG_ECDSA_BASE, - .regn_end_addr = (PCR_AES_CONF_REG - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 9, - .regn_start_addr = PCR_RSA_CONF_REG, - .regn_end_addr = (PCR_ECC_CONF_REG - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - { - .regn_num = 10, - .regn_start_addr = PCR_ECDSA_CONF_REG, - .regn_end_addr = (DR_REG_TEE_BASE - 0x4), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 11: Peripherals [Miscellaneous - PMU] (RW) */ - { - .regn_num = 11, - .regn_start_addr = DR_REG_MISC_BASE, - .regn_end_addr = (DR_REG_PMU_BASE - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 12: Peripherals [DEBUG - PWDET] (RW) */ - { - .regn_num = 12, - .regn_start_addr = DR_REG_TRACE_BASE, - .regn_end_addr = 0x600D0000, - .regn_pms = 0x6, - .filter_enable = 1, - }, -}; - /* NOTE: Following are the master IDs for setting the security mode and access through APM: * +---------+-------------+ * | Bit | Source | @@ -189,115 +76,154 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = { * +---------+-------------+ */ -/* HP_APM: TEE mode masters' configuration */ -apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data_tee = { - .apm_ctrl = HP_APM_CTRL, - .apm_m_cnt = HP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_TEE, - /* Crypto DMA (AES/SHA) and HP_CPU */ - .master_ids = 0xC00001, - .pms_data = hp_apm_pms_data_tee, +#define APM_MASTERS_ALL (0xFFFFFFFFU) +#define APM_MASTERS_HP_CPU (BIT(APM_MASTER_HPCORE)) +#define APM_MASTERS_LP_CPU (BIT(APM_MASTER_LPCORE)) +#define APM_MASTERS_GDMA_CRYPTO (BIT(APM_MASTER_GDMA_AES) | BIT(APM_MASTER_GDMA_SHA)) +#define APM_MASTERS_TEE (APM_MASTERS_HP_CPU | APM_MASTERS_GDMA_CRYPTO) +#define APM_MASTERS_REE (APM_MASTERS_ALL & ~(APM_MASTERS_TEE)) + +/*----------------------- TEE mode configuration -----------------------*/ + +/** + * NOTE: Fixes APM filter behavior to allow unrestricted access for TEE mode. + * + * By default, TEE mode should have unrestricted access to the entire CPU address space. + * However, it has been observed that when APM filters are enabled, TEE mode + * accesses are incorrectly being filtered based on the region configurations and + * access attributes set for REE[0..2] modes. + */ +static void enable_tee_mode_access(void) +{ + uint32_t regn_num = 0; + uint32_t regn_start_addr = 0x00; + uint32_t regn_end_addr = UINT32_MAX; + + /* HP_APM */ + apm_ll_hp_apm_set_region_start_addr(regn_num, regn_start_addr); + apm_ll_hp_apm_set_region_end_addr(regn_num, regn_end_addr); + apm_ll_hp_apm_enable_region_filter(regn_num, true); +} + +/*----------------------- REE0 mode configuration -----------------------*/ + +/*----------------------- HP_APM configuration -----------------------*/ + +/* HP_APM: REE0 mode accessible regions */ +static apm_hal_ctrl_region_cfg_t hp_apm_regn_cfg_ree0[] = { + /* Region 1: CPU peripherals (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 1, DR_REG_TRACE_BASE, 0x600D0000, APM_PERM_R | APM_PERM_W), + + /* Region 2: RTC memory (RWX) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M1, 2, SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH, APM_PERM_ALL), + + /* NOTE: Without this entry, the REE SRAM region becomes inaccessible to + * the MODEM master, resulting in an APM violation during Wi-Fi initialization. + */ + /* Region 3: REE SRAM region (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M2, 3, SOC_NS_IRAM_START, SOC_IRAM_HIGH, APM_PERM_R | APM_PERM_W), + + /* Region 4: Peripherals [Start - MMU] (RW) */ + /* Protected: MMU */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 4, SOC_PERIPHERAL_LOW, SPI_MEM_MMU_ITEM_CONTENT_REG(0), APM_PERM_R | APM_PERM_W), + + /* Region 5: Peripherals [MMU - SPI1] (RW) */ + /* Protected: SPI1 */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 5, SPI_MEM_MMU_POWER_CTRL_REG(0), HP_APM_SPI1_REG_START, APM_PERM_R | APM_PERM_W), + + /* Region 6: Peripherals [SPI1 - Interrupt Matrix] (RW) */ + /* Protected: Interrupt Matrix */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 6, HP_APM_SPI1_REG_END, DR_REG_INTMTX_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 7/8: Peripherals [PCNT - HMAC] (RW) */ + /* Protected: AES, SHA, ECC, DS, HMAC */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 7, DR_REG_PCNT_BASE, DR_REG_AES_BASE, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 8, DR_REG_RSA_BASE, DR_REG_ECC_MULT_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 8/9/10: Peripherals [ECDSA - TEE Controller & APM] (RW) */ + /* Protected: AES, SHA, ECC, DS and HMAC PCRs, APM, TEE Controller */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 9, DR_REG_ECDSA_BASE, PCR_AES_CONF_REG, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 10, PCR_RSA_CONF_REG, PCR_ECC_CONF_REG, APM_PERM_R | APM_PERM_W), + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 11, PCR_ECDSA_CONF_REG, DR_REG_TEE_BASE, APM_PERM_R | APM_PERM_W), + + /* Region 11: Peripherals [Miscellaneous - PMU] (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M3, 12, DR_REG_MISC_BASE, DR_REG_PMU_BASE, APM_PERM_R | APM_PERM_W), }; /* HP_APM: REE0 mode masters' configuration */ -apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data = { - .apm_ctrl = HP_APM_CTRL, - .apm_m_cnt = HP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_REE0, - /* All masters except crypto DMA (AES/SHA) and HP CPU */ - .master_ids = 0xFF3FFFFE, - .pms_data = hp_apm_pms_data, -}; +static apm_hal_ctrl_sec_mode_cfg_t hp_apm_ctrl_sec_mode_cfg_ree0 = + APM_HAL_SEC_MODE_CFG(APM_CTRL_HP_APM, APM_SEC_MODE_REE0, hp_apm_regn_cfg_ree0); -/*----------------------- LP_APM range and filter configuration -----------------------*/ +/*----------------------- LP_APM configuration -----------------------*/ /* NOTE: Due to ESP32-H2's limited LP_APM module regions, neither TEE nor REE can directly * access the protected eFuse region. However, since the HMAC peripheral can access the * key stored in eFuse for TEE secure storage, this access restriction does not impact * functionality. */ -/* LP_APM: REE0 mode accessible regions */ -apm_ctrl_region_config_data_t lp_apm_pms_data[] = { +static apm_hal_ctrl_region_cfg_t lp_apm_regn_cfg_ree0[] = { /* Region 0: LP Peripherals [PMU - eFuse BLK x] (RW) */ /* Protected: eFuse BLK x */ - { - .regn_num = 0, - .regn_start_addr = DR_REG_PMU_BASE, - .regn_end_addr = (LP_APM_EFUSE_REG_START - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, - /* Region 1: LP Peripherals [eFuse - END] (RW) */ - { - .regn_num = 1, - .regn_start_addr = LP_APM_EFUSE_REG_END, - .regn_end_addr = (DR_REG_TRACE_BASE - 0x04), - .regn_pms = 0x6, - .filter_enable = 1, - }, -}; + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 0, DR_REG_PMU_BASE, LP_APM_EFUSE_REG_START, APM_PERM_R | APM_PERM_W), -/* LP_APM: REE0 mode masters' configuration */ -apm_ctrl_secure_mode_config_t lp_apm_sec_mode_data = { - .apm_ctrl = LP_APM_CTRL, - .apm_m_cnt = LP_APM_MAX_ACCESS_PATH, - .sec_mode = APM_LL_SECURE_MODE_REE0, - /* HP_CPU */ - .master_ids = 0x1, - .pms_data = lp_apm_pms_data, + /* Region 1: LP Peripherals [eFuse - END] (RW) */ + APM_HAL_REGION_ENTRY(APM_CTRL_ACCESS_PATH_M0, 1, LP_APM_EFUSE_REG_END, DR_REG_TRACE_BASE, APM_PERM_R | APM_PERM_W), }; /*---------------- TEE APM API-----------------------*/ -void esp_tee_apm_int_enable(apm_ctrl_secure_mode_config_t *sec_mode_data) +static void enable_apm_intr(apm_ctrl_module_t ctrl_mod, uint32_t path_count) { - for (int i = 0; i < sec_mode_data->apm_m_cnt; i++) { - apm_ctrl_path_t *apm_excp_data = calloc(1, sizeof(apm_ctrl_path_t)); - assert(apm_excp_data != NULL); + for (uint32_t i = 0; i < path_count; i++) { + apm_hal_ctrl_info_t *ctrl_info = calloc(1, sizeof(apm_hal_ctrl_info_t)); + assert(ctrl_info != NULL); - apm_excp_data->apm_ctrl = sec_mode_data->apm_ctrl; - apm_excp_data->apm_m_path = i; + ctrl_info->ctrl_mod = ctrl_mod; + ctrl_info->path = i; - int intr_src_num = apm_hal_apm_ctrl_get_int_src_num(apm_excp_data); + int intr_src_num = apm_hal_get_intr_src_num(ctrl_info); struct vector_desc_t apm_vd = {0}; apm_vd.source = intr_src_num; apm_vd.isr = tee_apm_violation_isr; - apm_vd.arg = (void *)apm_excp_data; + apm_vd.arg = (void *)ctrl_info; /* Register interrupt handler with TEE. */ esp_tee_intr_register((void *)&apm_vd); - /* Enable APM Ctrl intewrrupt for access path(M[0:n]) */ - apm_hal_apm_ctrl_exception_clear(apm_excp_data); - apm_hal_apm_ctrl_interrupt_enable(apm_excp_data, true); + /* Enable APM Ctrl interrupt for access path(M[0:n]) */ + apm_hal_clear_exception_status(ctrl_info); + apm_hal_enable_intr(ctrl_info, true); } } void esp_tee_configure_apm_protection(void) { /* Disable all control filter first to have full access of address rage. */ - apm_hal_apm_ctrl_filter_enable_all(false); + apm_hal_enable_ctrl_filter_all(false); - /* Switch HP_CPU to TEE mode */ - apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_TEE); + /* Enable TEE mode access for all APM modules */ + enable_tee_mode_access(); - /* LP APM TEE configuration. */ - lp_apm_sec_mode_data.regn_count = sizeof(lp_apm_pms_data) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm_sec_mode_data); - /* LP APM interrupt configuration. */ - esp_tee_apm_int_enable(&lp_apm_sec_mode_data); - ESP_LOGD(TAG, "[REE0] LP_APM configured"); + /* HP_APM REE0 configuration. */ + apm_hal_set_ctrl_sec_mode_cfg(&hp_apm_ctrl_sec_mode_cfg_ree0); + /* HP_APM interrupt configuration. */ + enable_apm_intr(APM_CTRL_HP_APM, APM_CTRL_HP_APM_PATH_NUM); + ESP_LOGD(TAG, "[HP_APM] Configured for REE0"); - /* HP APM TEE configuration. */ - hp_apm_sec_mode_data_tee.regn_count = sizeof(hp_apm_pms_data_tee) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&hp_apm_sec_mode_data_tee); - ESP_LOGD(TAG, "[TEE] HP_APM configured"); + /* LP_APM REE0 configuration. */ + size_t regn_count = sizeof(lp_apm_regn_cfg_ree0) / sizeof(lp_apm_regn_cfg_ree0[0]); + for (uint32_t regn_idx = 0; regn_idx < regn_count; regn_idx++) { + const apm_hal_ctrl_region_cfg_t *region = &lp_apm_regn_cfg_ree0[regn_idx]; + apm_hal_set_region_filter_cfg(APM_CTRL_LP_APM, APM_SEC_MODE_REE0, region); + apm_hal_enable_region_filter(APM_CTRL_LP_APM, region->regn_num, region->filter_en); + } + apm_hal_enable_ctrl_filter(APM_CTRL_LP_APM, APM_CTRL_ACCESS_PATH_M0, true); + /* LP_APM interrupt configuration. */ + enable_apm_intr(APM_CTRL_LP_APM, APM_CTRL_LP_APM_PATH_NUM); + ESP_LOGD(TAG, "[LP_APM] Configured for REE0"); - /* HP APM configuration. */ - hp_apm_sec_mode_data.regn_count = sizeof(hp_apm_pms_data) / sizeof(apm_ctrl_region_config_data_t); - apm_hal_apm_ctrl_master_sec_mode_config(&hp_apm_sec_mode_data); - /* HP APM interrupt configuration. */ - esp_tee_apm_int_enable(&hp_apm_sec_mode_data); - ESP_LOGD(TAG, "[REE0] HP_APM configured"); + /* Switch HP_CPU to TEE mode and rest of the masters to REE0 mode */ + apm_hal_set_master_sec_mode(APM_MASTERS_TEE, APM_SEC_MODE_TEE); + apm_hal_set_master_sec_mode(APM_MASTERS_REE, APM_SEC_MODE_REE0); } diff --git a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c index c6172ea3e0..7c5d3cb9b9 100644 --- a/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c +++ b/components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_flash_prot.c @@ -125,13 +125,13 @@ static void test_esp_partition_api_w(const esp_partition_t *part) TEST_ASSERT_NOT_NULL(part); uint8_t buf_w[128]; memset(buf_w, 0xA5, sizeof(buf_w)); - TEST_ESP_OK(esp_partition_write(part, 0x00, buf_w, sizeof(buf_w))); + TEST_ESP_ERR(ESP_FAIL, esp_partition_write(part, 0x00, buf_w, sizeof(buf_w))); } static void test_esp_partition_api_e(const esp_partition_t *part) { TEST_ASSERT_NOT_NULL(part); - TEST_ESP_OK(esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE)); + TEST_ESP_ERR(ESP_FAIL, esp_partition_erase_range(part, 0x00, SPI_FLASH_SEC_SIZE)); } static void test_esp_partition_api(void) @@ -229,12 +229,12 @@ static void test_esp_flash_api_w(uint32_t paddr) { uint8_t buf_w[128]; memset(buf_w, 0xA5, sizeof(buf_w)); - TEST_ESP_OK(esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w))); + TEST_ESP_ERR(ESP_FAIL, esp_flash_write(NULL, buf_w, paddr, sizeof(buf_w))); } static void test_esp_flash_api_e(uint32_t paddr) { - TEST_ESP_OK(esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE)); + TEST_ESP_ERR(ESP_FAIL, esp_flash_erase_region(NULL, paddr, SPI_FLASH_SEC_SIZE)); } static void test_esp_flash_api(void) diff --git a/components/esp_tee/test_apps/tee_test_fw/pytest_esp_tee_ut.py b/components/esp_tee/test_apps/tee_test_fw/pytest_esp_tee_ut.py index 6b4654e79e..409c0bdfc3 100644 --- a/components/esp_tee/test_apps/tee_test_fw/pytest_esp_tee_ut.py +++ b/components/esp_tee/test_apps/tee_test_fw/pytest_esp_tee_ut.py @@ -1,5 +1,6 @@ # SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Apache-2.0 +import re from enum import Enum from typing import Dict from typing import Tuple @@ -198,8 +199,18 @@ def expect_panic_rsn(dut: IdfDut, expected_rsn: str) -> None: def run_multiple_stages(dut: IdfDut, test_case_num: int, stages: int, api: TeeFlashAccessApi) -> None: expected_ops = { - TeeFlashAccessApi.ESP_PARTITION: ['read', 'program_page', 'program_page', 'erase_sector'], - TeeFlashAccessApi.ESP_FLASH: ['program_page', 'read', 'erase_sector', 'program_page'], + TeeFlashAccessApi.ESP_PARTITION: [ + 'read', + 'program_page|common_command', + 'program_page|common_command', + 'erase_sector|common_command', + ], + TeeFlashAccessApi.ESP_FLASH: [ + 'program_page|common_command', + 'read', + 'erase_sector|common_command', + 'program_page|common_command', + ], } flash_enc_enabled = dut.app.sdkconfig.get('SECURE_FLASH_ENC_ENABLED', True) @@ -225,7 +236,7 @@ def run_multiple_stages(dut: IdfDut, test_case_num: int, stages: int, api: TeeFl r'\[_ss_spi_flash_hal_(\w+)\] Illegal flash access at \s*(0x[0-9a-fA-F]+)', timeout=10 ) actual_op = match.group(1).decode() - if actual_op != curr_op: + if not re.fullmatch(curr_op, actual_op): raise RuntimeError(f'Unexpected flash operation: {actual_op} (expected: {curr_op})') elif api == TeeFlashAccessApi.ESP_ROM_SPIFLASH: expect_panic_rsn(dut, 'APM - Authority exception') diff --git a/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h b/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h index 8e86bb3bd7..f6b7309e45 100644 --- a/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h +++ b/components/esp_wifi/include/esp_private/esp_wifi_he_types_private.h @@ -235,21 +235,43 @@ typedef struct { */ uint32_t mu_bw[3]; uint32_t mu_sigb_dump; +#if CONFIG_IDF_TARGET_ESP32C5 uint32_t vht; uint32_t vht_noeb; uint32_t vht_stbc; uint32_t vht_txbf; uint32_t vht_retry; +#endif uint32_t rx_isr; uint32_t rx_nblks; uint32_t rx_ndpa; uint32_t rx_reset_rxbase_cnt; uint32_t rx_base_null_cnt; +#if CONFIG_IDF_TARGET_ESP32C5 uint32_t vht_mu[64][4]; uint32_t vht_mu_noeb; uint32_t vht_mu_stbc; uint32_t vht_mu_retry[64][4]; uint16_t vht_mu_mcs[64][4][12]; +#endif + +#if CONFIG_IDF_TARGET_ESP32C61 + int8_t min_legacy_rssi; + int8_t max_legacy_rssi; + float avg_legacy_rssi; + + int8_t min_data_rssi; + int8_t max_data_rssi; + float avg_data_rssi; + + int8_t min_mu_legacy_rssi; + int8_t max_mu_legacy_rssi; + float avg_mu_legacy_rssi; + + int8_t min_mu_data_rssi; + int8_t max_mu_data_rssi; + float avg_mu_data_rssi; +#endif } esp_test_rx_statistics_t; //140 bytes #else diff --git a/components/esp_wifi/lib b/components/esp_wifi/lib index 8a1b7bbc00..49d2500723 160000 --- a/components/esp_wifi/lib +++ b/components/esp_wifi/lib @@ -1 +1 @@ -Subproject commit 8a1b7bbc00e895d040c5c9a6fb9d1db2bbfc7958 +Subproject commit 49d2500723a1098ec574bfe8b795562b6a6ccc3b diff --git a/components/esp_wifi/test_apps/wifi_nvs_config/README.md b/components/esp_wifi/test_apps/wifi_nvs_config/README.md new file mode 100644 index 0000000000..1c35092948 --- /dev/null +++ b/components/esp_wifi/test_apps/wifi_nvs_config/README.md @@ -0,0 +1,2 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | diff --git a/components/hal/apm_hal.c b/components/hal/apm_hal.c index e82f491f5e..1591337a14 100644 --- a/components/hal/apm_hal.c +++ b/components/hal/apm_hal.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include #include "hal/assert.h" #include "hal/apm_hal.h" #include "hal/apm_ll.h" @@ -53,192 +54,471 @@ void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data) } #else -void apm_tee_hal_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode) +void apm_hal_set_master_sec_mode(uint32_t master_mask, apm_security_mode_t mode) { - apm_tee_ll_set_master_secure_mode(apm_ctrl, master_id, sec_mode); -} - -void apm_tee_hal_set_master_secure_mode_all(apm_ll_secure_mode_t sec_mode) -{ - for (int i = 0; i < APM_LL_MASTER_MAX; i++) { - apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, i, sec_mode); - } -#if SOC_LP_CORE_SUPPORTED - apm_tee_hal_set_master_secure_mode(LP_APM_CTRL, APM_LL_MASTER_LPCORE, sec_mode); -#endif -} - -void apm_tee_hal_clk_gating_enable(bool enable) -{ - apm_tee_ll_clk_gating_enable(enable); -} - -void apm_hal_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, uint32_t regn_num, bool enable) -{ - apm_ll_apm_ctrl_region_filter_enable(apm_ctrl, regn_num, enable); -} - -void apm_hal_apm_ctrl_filter_enable(apm_ctrl_path_t *apm_path, bool enable) -{ - HAL_ASSERT(apm_path || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((apm_path->apm_ctrl == LP_APM0_CTRL) && (apm_path->apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || -#endif - ((apm_path->apm_ctrl == HP_APM_CTRL) && (apm_path->apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((apm_path->apm_ctrl == LP_APM_CTRL) && (apm_path->apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - apm_ll_apm_ctrl_filter_enable(apm_path->apm_ctrl, apm_path->apm_m_path, enable); -} - -void apm_hal_apm_ctrl_filter_enable_all(bool enable) -{ - apm_ctrl_path_t apm_path; - - for (int i = 0; i < HP_APM_MAX_ACCESS_PATH; i++) { - apm_path.apm_ctrl = HP_APM_CTRL; - apm_path.apm_m_path = i; - apm_hal_apm_ctrl_filter_enable(&apm_path, enable); - } - for (int i = 0; i < LP_APM_MAX_ACCESS_PATH; i++) { - apm_path.apm_ctrl = LP_APM_CTRL; - apm_path.apm_m_path = i; - apm_hal_apm_ctrl_filter_enable(&apm_path, enable); - } -#if defined(SOC_APM_LP_APM0_SUPPORTED) - for (int i = 0; i < LP_APM0_MAX_ACCESS_PATH; i++) { - apm_path.apm_ctrl = LP_APM0_CTRL; - apm_path.apm_m_path = i; - apm_hal_apm_ctrl_filter_enable(&apm_path, enable); - } -#endif -} - -void apm_hal_apm_ctrl_region_config(const apm_ctrl_region_config_data_t *pms_data) -{ - HAL_ASSERT(pms_data || - (( -#if defined(SOC_APM_LP_APM0_SUPPORTED) - (pms_data->apm_ctrl == LP_APM0_CTRL) || -#endif - (pms_data->apm_ctrl == LP_APM_CTRL) - ) && - (pms_data->regn_num <= APM_LL_LP_MAX_REGION_NUM) - ) || - ((pms_data->apm_ctrl == HP_APM_CTRL) && (pms_data->regn_num <= APM_LL_HP_MAX_REGION_NUM)) - ); - - apm_ll_apm_ctrl_set_region_start_address(pms_data->apm_ctrl, pms_data->regn_num, pms_data->regn_start_addr); - apm_ll_apm_ctrl_set_region_end_address(pms_data->apm_ctrl, pms_data->regn_num, pms_data->regn_end_addr); - apm_ll_apm_ctrl_sec_mode_region_attr_config(pms_data->apm_ctrl, pms_data->regn_num, pms_data->sec_mode, pms_data->regn_pms); -} - -uint8_t apm_hal_apm_ctrl_exception_status(apm_ctrl_path_t *apm_path) -{ - HAL_ASSERT(apm_path || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((apm_path->apm_ctrl == LP_APM0_CTRL) && (apm_path->apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || -#endif - ((apm_path->apm_ctrl == HP_APM_CTRL) && (apm_path->apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((apm_path->apm_ctrl == LP_APM_CTRL) && (apm_path->apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - return apm_ll_apm_ctrl_exception_status(apm_path->apm_ctrl, apm_path->apm_m_path); -} - -void apm_hal_apm_ctrl_exception_clear(apm_ctrl_path_t *apm_path) -{ - HAL_ASSERT(apm_path || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((apm_path->apm_ctrl == LP_APM0_CTRL) && (apm_path->apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || -#endif - ((apm_path->apm_ctrl == HP_APM_CTRL) && (apm_path->apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((apm_path->apm_ctrl == LP_APM_CTRL) && (apm_path->apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - apm_ll_apm_ctrl_exception_clear(apm_path->apm_ctrl, apm_path->apm_m_path); -} - -void apm_hal_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info) -{ - HAL_ASSERT(excp_info || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((excp_info->apm_path.apm_ctrl == LP_APM0_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || -#endif - ((excp_info->apm_path.apm_ctrl == HP_APM_CTRL) && (excp_info->apm_path.apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((excp_info->apm_path.apm_ctrl == LP_APM_CTRL) && (excp_info->apm_path.apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - apm_ll_apm_ctrl_get_exception_info(excp_info); -} - -void apm_hal_apm_ctrl_interrupt_enable(apm_ctrl_path_t *apm_path, bool enable) -{ - HAL_ASSERT(apm_path || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((apm_path->apm_ctrl == LP_APM0_CTRL) && (apm_path->apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || -#endif - ((apm_path->apm_ctrl == HP_APM_CTRL) && (apm_path->apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((apm_path->apm_ctrl == LP_APM_CTRL) && (apm_path->apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - apm_ll_apm_ctrl_interrupt_enable(apm_path->apm_ctrl, apm_path->apm_m_path, enable); -} - -void apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) -{ - apm_ll_apm_ctrl_clk_gating_enable(apm_ctrl, enable); -} - -void apm_hal_apm_ctrl_master_sec_mode_config(apm_ctrl_secure_mode_config_t *sec_mode_data) -{ - apm_ctrl_path_t apm_path; - - /* Configure given secure mode for all specified Masters. */ - for (int i = 0; i < APM_LL_MASTER_MAX; i++) { - if (sec_mode_data->master_ids & (1 << i)) { - apm_tee_hal_set_master_secure_mode(sec_mode_data->apm_ctrl, i, sec_mode_data->sec_mode); + master_mask &= APM_MASTER_MASK_ALL; + while (master_mask) { + uint32_t master = __builtin_ctz(master_mask); + master_mask &= ~(1U << master); + apm_ll_hp_tee_set_master_sec_mode(master, mode); +#if SOC_APM_SUPPORT_LP_TEE_CTRL + if (master == APM_MASTER_LPCORE) { + apm_ll_lp_tee_set_master_sec_mode(master, mode); } - } - - /* Configure the given APM Ctrl for all Masters for the: - * - Secure mode, - * - Regions range, - * - access permissions and - * - region filter - */ - for (int i = 0; i < sec_mode_data->regn_count; i++) { - sec_mode_data->pms_data[i].sec_mode = sec_mode_data->sec_mode; - sec_mode_data->pms_data[i].apm_ctrl = sec_mode_data->apm_ctrl; - apm_hal_apm_ctrl_region_config(&sec_mode_data->pms_data[i]); - apm_hal_apm_ctrl_region_filter_enable(sec_mode_data->pms_data[i].apm_ctrl, - sec_mode_data->pms_data[i].regn_num, - sec_mode_data->pms_data[i].filter_enable); - } - - /* Configure APM Ctrl access path(M[0:n]) */ - for (int i = 0; i < sec_mode_data->apm_m_cnt; i++) { - apm_path.apm_ctrl = sec_mode_data->apm_ctrl; - apm_path.apm_m_path = i; - apm_hal_apm_ctrl_filter_enable(&apm_path, 1); - } -} - -void apm_hal_apm_ctrl_reset_event_enable(bool enable) -{ - apm_ll_apm_ctrl_reset_event_enable(enable); -} - -int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path) -{ - HAL_ASSERT(apm_path || -#if defined(SOC_APM_LP_APM0_SUPPORTED) - ((apm_path->apm_ctrl == LP_APM0_CTRL) && (apm_path->apm_m_path < LP_APM0_MAX_ACCESS_PATH)) || #endif - ((apm_path->apm_ctrl == HP_APM_CTRL) && (apm_path->apm_m_path < HP_APM_MAX_ACCESS_PATH)) || - ((apm_path->apm_ctrl == LP_APM_CTRL) && (apm_path->apm_m_path < LP_APM_MAX_ACCESS_PATH)) - ); - - return apm_ll_apm_ctrl_get_int_src_num(apm_path->apm_ctrl, apm_path->apm_m_path); + } } + +void apm_hal_set_master_sec_mode_all(apm_security_mode_t mode) +{ + apm_hal_set_master_sec_mode(APM_MASTER_MASK_ALL, mode); +} + +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK +void apm_hal_lock_master_sec_mode(uint32_t master_mask) +{ + master_mask &= APM_MASTER_MASK_ALL; + while (master_mask) { + uint32_t master = __builtin_ctz(master_mask); + master_mask &= ~(1U << master); + apm_ll_hp_tee_lock_master_sec_mode(master); +#if SOC_APM_SUPPORT_LP_TEE_CTRL + if (master == APM_MASTER_LPCORE) { + apm_ll_lp_tee_lock_master_sec_mode(master); + } +#endif + } +} + +void apm_hal_lock_master_sec_mode_all(void) +{ + apm_hal_lock_master_sec_mode(APM_MASTER_MASK_ALL); +} +#endif + +#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL +void apm_hal_tee_set_peri_access(apm_tee_ctrl_module_t ctrl_mod, uint64_t periph_mask, apm_security_mode_t mode, apm_perm_t pms) +{ + switch (ctrl_mod) { + case APM_TEE_CTRL_HP: + uint64_t hp_tee_peri_mask = periph_mask & APM_TEE_HP_PERIPH_MASK_ALL; + for (uint32_t periph = 0; periph < APM_TEE_HP_PERIPH_MAX; periph++) { + if (hp_tee_peri_mask & (1ULL << periph)) { + apm_ll_hp_tee_set_peri_access((apm_tee_hp_periph_t)periph, mode, pms); + } + } + apm_ll_hp_tee_enable_bus_err_resp(true); + break; +#if SOC_APM_SUPPORT_LP_TEE_CTRL + case APM_TEE_CTRL_LP: + uint32_t lp_tee_peri_mask = (uint32_t)periph_mask & (uint32_t)APM_TEE_LP_PERIPH_MASK_ALL; + while (lp_tee_peri_mask) { + uint32_t periph = __builtin_ctz(lp_tee_peri_mask); + apm_ll_lp_tee_set_peri_access((apm_tee_lp_periph_t)periph, mode, pms); + lp_tee_peri_mask &= ~(1U << periph); + } + apm_ll_lp_tee_enable_bus_err_resp(true); + break; +#endif + default: + break; + } +} + +void apm_hal_tee_set_peri_access_all(apm_tee_ctrl_module_t ctrl_mod, apm_security_mode_t mode, apm_perm_t pms) +{ + switch (ctrl_mod) { + case APM_TEE_CTRL_HP: + apm_hal_tee_set_peri_access(APM_TEE_CTRL_HP, (uint64_t)(APM_TEE_HP_PERIPH_MASK_ALL), mode, pms); + break; +#if SOC_APM_SUPPORT_LP_TEE_CTRL + case APM_TEE_CTRL_LP: + apm_hal_tee_set_peri_access(APM_TEE_CTRL_LP, (uint64_t)(APM_TEE_LP_PERIPH_MASK_ALL), mode, pms); + break; +#endif + default: + break; + } +} +#endif + +void apm_hal_tee_enable_clk_gating(apm_tee_ctrl_module_t ctrl_mod, bool enable) +{ + switch (ctrl_mod) { + case APM_TEE_CTRL_HP: + apm_ll_hp_tee_enable_clk_gating(enable); + break; +#if SOC_APM_SUPPORT_LP_TEE_CTRL + case APM_TEE_CTRL_LP: + apm_ll_lp_tee_enable_clk_gating(enable); + break; +#endif + default: + break; + } +} + +void apm_hal_enable_ctrl_filter(apm_ctrl_module_t ctrl_mod, apm_ctrl_access_path_t path, bool enable) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_enable_ctrl_filter(path, enable); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_enable_ctrl_filter(path, enable); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_enable_ctrl_filter(path, enable); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_enable_ctrl_filter(path, enable); + break; +#endif + default: + break; + } +} + +void apm_hal_enable_ctrl_filter_all(bool enable) +{ + apm_ll_hp_apm_enable_ctrl_filter_all(enable); +#if SOC_APM_LP_APM0_SUPPORTED + apm_ll_lp_apm0_enable_ctrl_filter_all(enable); +#endif + apm_ll_lp_apm_enable_ctrl_filter_all(enable); +#if SOC_APM_CPU_APM_SUPPORTED + apm_ll_cpu_apm_enable_ctrl_filter_all(enable); +#endif +} + +void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_enable_region_filter(regn_num, enable); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_enable_region_filter(regn_num, enable); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_enable_region_filter(regn_num, enable); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_enable_region_filter(regn_num, enable); + break; +#endif + default: + break; + } +} + +void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_set_region_start_addr(regn_num, addr); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_set_region_start_addr(regn_num, addr); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_set_region_start_addr(regn_num, addr); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_set_region_start_addr(regn_num, addr); + break; +#endif + default: + break; + } +} + +void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_set_region_end_addr(regn_num, addr); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_set_region_end_addr(regn_num, addr); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_set_region_end_addr(regn_num, addr); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_set_region_end_addr(regn_num, addr); + break; +#endif + default: + break; + } +} + +void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_set_sec_mode_region_attr(regn_num, mode, regn_pms); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms); + break; +#endif + default: + break; + } +} + +void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg) +{ + HAL_ASSERT(regn_cfg); + HAL_ASSERT(mode != APM_SEC_MODE_TEE); + + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr); + apm_ll_hp_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr); + apm_ll_hp_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr); + apm_ll_lp_apm0_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr); + apm_ll_lp_apm0_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr); + apm_ll_lp_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr); + apm_ll_lp_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr); + apm_ll_cpu_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr); + apm_ll_cpu_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms); + break; +#endif + default: + break; + } +} + +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK +void apm_hal_lock_region_filter_cfg(apm_ctrl_module_t ctrl_mod, uint32_t regn_num) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_lock_sec_mode_region_attr(regn_num); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_lock_sec_mode_region_attr(regn_num); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_lock_sec_mode_region_attr(regn_num); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_lock_sec_mode_region_attr(regn_num); + break; +#endif + default: + break; + } +} +#endif + +void apm_hal_set_ctrl_sec_mode_cfg(const apm_hal_ctrl_sec_mode_cfg_t *cfg) +{ + HAL_ASSERT(cfg); + HAL_ASSERT(cfg->regions); + + for (uint32_t regn_idx = 0; regn_idx < cfg->regn_count; regn_idx++) { + const apm_hal_ctrl_region_cfg_t *region = &cfg->regions[regn_idx]; + apm_hal_set_region_filter_cfg(cfg->ctrl_mod, cfg->mode, region); + apm_hal_enable_region_filter(cfg->ctrl_mod, region->regn_num, region->filter_en); +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK + if (region->lock_en) { + apm_hal_lock_region_filter_cfg(cfg->ctrl_mod, region->regn_num); + } +#endif + apm_hal_enable_ctrl_filter(cfg->ctrl_mod, region->path_id, true); + } +} + +uint32_t apm_hal_get_exception_type(apm_hal_ctrl_info_t *ctrl_info) +{ + HAL_ASSERT(ctrl_info); + + switch (ctrl_info->ctrl_mod) { + case APM_CTRL_HP_APM: + return apm_ll_hp_apm_get_excp_type(ctrl_info->path); +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + return apm_ll_lp_apm0_get_excp_type(ctrl_info->path); +#endif + case APM_CTRL_LP_APM: + return apm_ll_lp_apm_get_excp_type(ctrl_info->path); +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + return apm_ll_cpu_apm_get_excp_type(ctrl_info->path); +#endif + default: + return UINT8_MAX; + } +} + +void apm_hal_clear_exception_status(apm_hal_ctrl_info_t *ctrl_info) +{ + HAL_ASSERT(ctrl_info); + + switch (ctrl_info->ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_clear_ctrl_excp_status(ctrl_info->path); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_clear_ctrl_excp_status(ctrl_info->path); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_clear_ctrl_excp_status(ctrl_info->path); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_clear_ctrl_excp_status(ctrl_info->path); + break; +#endif + default: + break; + } +} + +void apm_hal_get_exception_info(apm_hal_ctrl_info_t *ctrl_info, apm_ctrl_exception_info_t *excp_info) +{ + HAL_ASSERT(ctrl_info); + HAL_ASSERT(excp_info); + + switch (ctrl_info->ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_get_excp_info(ctrl_info->path, excp_info); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_get_excp_info(ctrl_info->path, excp_info); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_get_excp_info(ctrl_info->path, excp_info); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_get_excp_info(ctrl_info->path, excp_info); + break; +#endif + default: + break; + } +} + +void apm_hal_enable_intr(apm_hal_ctrl_info_t *ctrl_info, bool enable) +{ + HAL_ASSERT(ctrl_info); + + switch (ctrl_info->ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_enable_ctrl_intr(ctrl_info->path, enable); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_enable_ctrl_intr(ctrl_info->path, enable); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_enable_ctrl_intr(ctrl_info->path, enable); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_enable_ctrl_intr(ctrl_info->path, enable); + break; +#endif + default: + break; + } +} + +int apm_hal_get_intr_src_num(apm_hal_ctrl_info_t *ctrl_info) +{ + HAL_ASSERT(ctrl_info); + + switch (ctrl_info->ctrl_mod) { + case APM_CTRL_HP_APM: + return apm_ll_hp_apm_get_ctrl_intr_src(ctrl_info->path); +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + return apm_ll_lp_apm0_get_ctrl_intr_src(ctrl_info->path); +#endif + case APM_CTRL_LP_APM: + return apm_ll_lp_apm_get_ctrl_intr_src(ctrl_info->path); +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + return apm_ll_cpu_apm_get_ctrl_intr_src(ctrl_info->path); +#endif + default: + return -1; + } +} + +void apm_hal_enable_reset_event_bypass(bool enable) +{ + apm_ll_enable_reset_event_bypass(enable); +} + +void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable) +{ + switch (ctrl_mod) { + case APM_CTRL_HP_APM: + apm_ll_hp_apm_enable_ctrl_clk_gating(enable); + break; +#if SOC_APM_LP_APM0_SUPPORTED + case APM_CTRL_LP_APM0: + apm_ll_lp_apm0_enable_ctrl_clk_gating(enable); + break; +#endif + case APM_CTRL_LP_APM: + apm_ll_lp_apm_enable_ctrl_clk_gating(enable); + break; +#if SOC_APM_CPU_APM_SUPPORTED + case APM_CTRL_CPU_APM: + apm_ll_cpu_apm_enable_ctrl_clk_gating(enable); + break; +#endif + default: + break; + } +} + #endif //CONFIG_IDF_TARGET_ESP32P4 diff --git a/components/hal/ds_hal.c b/components/hal/ds_hal.c index 53f9279456..7591eff3a8 100644 --- a/components/hal/ds_hal.c +++ b/components/hal/ds_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include "hal/systimer_hal.h" #include "hal/ds_hal.h" #include "hal/ds_ll.h" +#include "soc/soc_caps.h" void ds_hal_start(void) { @@ -23,6 +24,13 @@ void ds_hal_configure_iv(const uint32_t *iv) ds_ll_configure_iv(iv); } +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +void ds_hal_set_key_source(ds_key_source_t key_source) +{ + ds_ll_set_key_source(key_source); +} +#endif + void ds_hal_write_message(const uint8_t *msg, size_t size) { ds_ll_write_message(msg, size); diff --git a/components/hal/ecdsa_hal.c b/components/hal/ecdsa_hal.c index 98e227cb59..097ac9e53b 100644 --- a/components/hal/ecdsa_hal.c +++ b/components/hal/ecdsa_hal.c @@ -16,7 +16,7 @@ #endif #ifdef SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY -#include "hal/key_mgr_ll.h" +#include "hal/key_mgr_hal.h" #endif #define ECDSA_HAL_P192_COMPONENT_LEN 24 @@ -30,12 +30,20 @@ static void configure_ecdsa_periph(ecdsa_hal_config_t *conf) #if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY // Force Key Manager to use eFuse key for XTS-AES operation - key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); + if (conf->curve == ECDSA_CURVE_SECP192R1) { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_192_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); + } else { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_256_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); + } #endif } #if SOC_KEY_MANAGER_SUPPORTED else { - key_mgr_ll_set_key_usage(ESP_KEY_MGR_ECDSA_KEY, ESP_KEY_MGR_USE_OWN_KEY); + if (conf->curve == ECDSA_CURVE_SECP192R1) { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_192_KEY, ESP_KEY_MGR_USE_OWN_KEY); + } else { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_ECDSA_256_KEY, ESP_KEY_MGR_USE_OWN_KEY); + } } #endif diff --git a/components/hal/esp32c5/include/hal/apm_ll.h b/components/hal/esp32c5/include/hal/apm_ll.h index d735bb922a..f3176340dc 100644 --- a/components/hal/esp32c5/include/hal/apm_ll.h +++ b/components/hal/esp32c5/include/hal/apm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,396 +7,952 @@ #include #include -#include "esp_err.h" -#include "soc/pcr_reg.h" + +#include "soc/apm_defs.h" #include "soc/tee_reg.h" #include "soc/lp_tee_reg.h" -#include "soc/lp_apm0_reg.h" #include "soc/hp_apm_reg.h" +#include "soc/hp_apm_struct.h" +#include "soc/lp_apm0_reg.h" +#include "soc/lp_apm0_struct.h" #include "soc/lp_apm_reg.h" +#include "soc/lp_apm_struct.h" +#include "soc/cpu_apm_reg.h" +#include "soc/cpu_apm_struct.h" + +#include "soc/pcr_reg.h" #include "soc/interrupts.h" -#include "hal/assert.h" +#include "hal/apm_types.h" #ifdef __cplusplus extern "C" { #endif -#define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_ID_S 18 -#define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U -#define APM_LL_CTRL_EXCEPTION_MODE_S 16 -#define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U -#define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU -#define APM_LL_CTRL_EXCEPTION_REGION_S 0 -#define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU - -#define APM_LL_HP_MAX_REGION_NUM 15 -#define APM_LL_LP_MAX_REGION_NUM 3 -#define APM_LL_MASTER_MAX 32 - -#define LP_APM0_MAX_ACCESS_PATH 0x1 -#define HP_APM_MAX_ACCESS_PATH 0x5 -#define LP_APM_MAX_ACCESS_PATH 0x2 - -#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION_FILTER_EN_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION_FILTER_EN_REG) : \ - (LP_APM_REGION_FILTER_EN_REG)); \ - }) - -#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) - -#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ATTR_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_ATTR_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0)) -#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) -#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U -#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1))) - -#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_INT_EN_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_INT_EN_REG) : \ - (LP_APM_INT_EN_REG)); \ - }) - -#define APM_CTRL_CLK_EN (BIT(0)) -#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_CLOCK_GATE_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_CLOCK_GATE_REG) : \ - (LP_APM_CLOCK_GATE_REG)); \ - }) - -#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_FUNC_CTRL_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_FUNC_CTRL_REG) : \ - (LP_APM_FUNC_CTRL_REG)); \ - }) +/* Helper macros for getting APM ctrl region pms attributes field mask */ +#define APM_REGION_PMS_SHIFT(mode) (4U * ((mode) - 1)) +#define APM_REGION_PMS_MASK(mode) (0x07U << APM_REGION_PMS_SHIFT(mode)) +#define APM_REGION_PMS_FIELD(mode, pms) ((pms) << APM_REGION_PMS_SHIFT(mode)) +/* Helper macros for getting TEE ctrl periph pms attributes field mask */ +#define APM_PERI_PMS_MASK(mode) ((1U << (mode)) | (1U << ((mode) ^ 4U))) +#define APM_PERI_PMS_R_FIELD(mode, pms) ((((pms) & APM_PERM_R) >> 2U) << (mode)) +#define APM_PERI_PMS_W_FIELD(mode, pms) ((((pms) & APM_PERM_W) >> 1U) << ((mode) ^ 4U)) /** - * @brief APM Master ID - */ -typedef enum { - APM_LL_MASTER_HPCORE = 0, - APM_LL_MASTER_LPCORE = 1, - APM_LL_MASTER_REGDMA = 2, - APM_LL_MASTER_SDIOSLV = 3, - APM_LL_MASTER_MODEM = 4, - APM_LL_MASTER_MEM_MONITOR = 5, - APM_LL_MASTER_TRACE = 6, - APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID - APM_LL_MASTER_GDMA_SPI2 = 16, - APM_LL_MASTER_GDMA_UHCI0 = 18, - APM_LL_MASTER_GDMA_I2S0 = 19, - APM_LL_MASTER_GDMA_AES = 22, - APM_LL_MASTER_GDMA_SHA = 23, - APM_LL_MASTER_GDMA_ADC = 24, - APM_LL_MASTER_GDMA_PARLIO = 25, -} apm_ll_master_id_t; - -/** - * @brief APM Controller - */ -typedef enum { - LP_APM0_CTRL = 0, - HP_APM_CTRL = 1, - LP_APM_CTRL = 2, -} apm_ll_apm_ctrl_t; - -/** - * @brief APM Secure Mode - */ -typedef enum { - APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ - APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */ - APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */ - APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */ -} apm_ll_secure_mode_t; - -/** - * @brief APM Ctrl access path - */ -typedef enum { - APM_CTRL_ACCESS_PATH_M0 = 0x0, - APM_CTRL_ACCESS_PATH_M1 = 0x1, - APM_CTRL_ACCESS_PATH_M2 = 0x2, - APM_CTRL_ACCESS_PATH_M3 = 0x3, - APM_CTRL_ACCESS_PATH_M4 = 0x4, -} apm_ll_ctrl_access_path_t; - -/** - * @brief APM Ctrl path. - */ -typedef struct { - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */ - apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */ -} apm_ctrl_path_t; - -/** - * @brief APM exception information - */ -typedef struct { - apm_ctrl_path_t apm_path; - uint8_t excp_regn; - uint8_t excp_mode; - uint8_t excp_id; - uint8_t excp_type; - uint32_t excp_addr; -} apm_ctrl_exception_info_t; - -/** - * @brief Set secure mode + * @brief Set security mode for a specific master in HP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param master_id APM master ID - * @param sec_mode Secure mode + * @param id Master ID + * @param mode Security mode to set */ -static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, - apm_ll_secure_mode_t sec_mode) +static inline void apm_ll_hp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) { - if (apm_ctrl == HP_APM_CTRL) { - REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); - } else if ((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) { - REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, sec_mode); + REG_WRITE(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, mode); +} + +/** + * @brief Lock master security mode for HP-TEE + * + * @param id Master ID + */ +static inline void apm_ll_hp_tee_lock_master_sec_mode(apm_master_id_t id) +{ + REG_SET_BIT(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, APM_TEE_MODE_LOCK_BIT); +} + +/** + * @brief Set access permissions for a specific peripheral in HP-TEE + * + * @param periph Peripheral ID + * @param mode Security mode + * @param pms Access permissions + */ +static inline void apm_ll_hp_tee_set_peri_access(apm_tee_hp_periph_t periph, apm_security_mode_t mode, apm_perm_t pms) +{ + uint32_t reg = TEE_UART0_CTRL_REG + APM_TEE_PERI_CTRL_OFFSET * periph; + uint32_t val = REG_READ(reg); + val &= ~APM_PERI_PMS_MASK(mode); + val |= APM_PERI_PMS_R_FIELD(mode, pms); + val |= APM_PERI_PMS_W_FIELD(mode, pms); + REG_WRITE(reg, val); +} + +/** + * @brief Enable or disable error response from HP-TEE when access is blocked. + * + * @param enable true to enable error response, false to disable. + */ +static inline void apm_ll_hp_tee_enable_bus_err_resp(bool enable) +{ + if (enable) { + REG_SET_BIT(TEE_BUS_ERR_CONF_REG, TEE_BUS_ERR_RESP_EN); + } else { + REG_CLR_BIT(TEE_BUS_ERR_CONF_REG, TEE_BUS_ERR_RESP_EN); } } /** - * @brief TEE controller clock auto gating enable + * @brief Enable/disable clock gating for HP-TEE * - * @param enable Flag for HP clock auto gating enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_tee_ll_clk_gating_enable(bool enable) +static inline void apm_ll_hp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); - } else { REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); + } else { + REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); } } /** - * @brief enable/disable APM Ctrl Region access permission filter + * @brief Set security mode for a specific master in LP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Memory Region number - * @param enable Flag for Region access filter enable/disable + * @param id Master ID (unused) + * @param mode Security mode to set */ -static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, bool enable) +static inline void apm_ll_lp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) +{ + (void)id; + REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, mode); +} + +/** + * @brief Lock master security mode for LP-TEE + * + * @param id Master ID (unused) + */ +static inline void apm_ll_lp_tee_lock_master_sec_mode(apm_master_id_t id) +{ + (void)id; + REG_SET_BIT(LP_TEE_M0_MODE_CTRL_REG, LP_TEE_M0_LOCK); +} + +/** + * @brief Set access permissions for a specific peripheral in LP-TEE + * + * @param periph Peripheral ID + * @param mode Security mode + * @param pms Access permissions + */ +static inline void apm_ll_lp_tee_set_peri_access(apm_tee_lp_periph_t periph, apm_security_mode_t mode, apm_perm_t pms) +{ + uint32_t reg = LP_TEE_EFUSE_CTRL_REG + APM_TEE_PERI_CTRL_OFFSET * periph; + uint32_t val = REG_READ(reg); + val &= ~APM_PERI_PMS_MASK(mode); + val |= APM_PERI_PMS_R_FIELD(mode, pms); + val |= APM_PERI_PMS_W_FIELD(mode, pms); + REG_WRITE(reg, val); +} + +/** + * @brief Enable or disable error response from LP-TEE when access is blocked. + * + * @param enable true to enable error response, false to disable. + */ +static inline void apm_ll_lp_tee_enable_bus_err_resp(bool enable) { if (enable) { - REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_SET_BIT(LP_TEE_BUS_ERR_CONF_REG, LP_TEE_BUS_ERR_RESP_EN); } else { - REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_CLR_BIT(LP_TEE_BUS_ERR_CONF_REG, LP_TEE_BUS_ERR_RESP_EN); } } /** - * @brief enable/disable APM Ctrl access path(M[0:n]) + * @brief Enable/disable clock gating for LP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access path - * @param enable Flag for LP APM0 M path filter enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_lp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN); } } /** - * @brief APM Ctrl Region start address configuration + * @brief Enable/disable forced HP memory access for LP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param addr Region start address + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) -{ - REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr); -} - -/** - * @brief APM Ctrl Region end address configuration - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param addr Region end address - */ -static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) -{ - REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr); -} - -/** - * @brief HP Region pms attributes configuration - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param sec_mode Secure mode of the Master - * @param regn_pms XWR permissions for the given secure mode and Region number - */ -static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) -{ - uint32_t val = 0; - val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num)); - val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode); - val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); - REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val); -} - -/** - * @brief Get APM Ctrl access path(M[0:n]) exception status - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access path - */ -static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) -{ - return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path)); -} - -/** - * @brief Clear APM Ctrl access path(M[0:n]) exception - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param amp_m_path APM Ctrl access path - */ -static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) -{ - REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path), - APM_CTRL_M_REGION_STATUS_CLR); -} - -/** - * @brief Get APM Ctrl access path(M[0:n]) exception information - * - * @param excp_info Exception related information like addr, - * region, apm_ctrl, apm_m_path, sec_mode and master id - */ -static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info) -{ - excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_ID); - excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_MODE); - excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_REGION); - excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path); - excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path)); -} - -/** - * @brief Interrupt enable for APM Ctrl at access path(M[0:n]) - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - * @param enable Flag for access path interrupt enable/disable - */ -static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_lp_tee_enable_force_hp_mem_access(bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN); } } /** - * @brief APM Ctrl clock auto gating enable + * @brief Enable/disable controller filter for specific path in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param enable Flag for HP clock auto gating enable/disable + * @param path Access path + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } } /** - * @brief APM/TEE/HP System Reg reset event bypass enable + * @brief Enable/disable all controller filters in HP-APM * - * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, - * but also some reset events. - * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. - * Some reset events will be bypassed. - * - * @param enable Flag for event bypass enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(HP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in HP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in HP-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_hp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(HP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in HP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_hp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(HP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in HP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_hp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in HP-APM + * + * @param regn_num Region number + */ +static inline void apm_ll_hp_apm_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from HP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_hp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from HP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_hp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from HP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_hp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from HP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_hp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + hp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_hp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_hp_apm_get_excp_type(path); + info->addr = apm_ll_hp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in HP-APM + * + * @param path Access path + */ +static inline void apm_ll_hp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(HP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in HP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(HP_APM_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Get controller interrupt source number from HP-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_hp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_HP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable controller clock gating in HP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); + } else { + REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); + } +} + +/** + * @brief Enable/disable controller filter for specific path in LP-APM0 + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM0 + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM0_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM0 + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM0 + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm0_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM0_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM0 + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm0_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM0_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM0 + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm0_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM0_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in LP-APM0 + * + * @param regn_num Region number + */ +static inline void apm_ll_lp_apm0_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(LP_APM0_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM0 + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_data(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_EXCEPTION_INFO0_REG); +} + +/** + * @brief Get exception status from LP-APM0 + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_type(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_STATUS_REG); +} + +/** + * @brief Get exception address from LP-APM0 + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_addr(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_EXCEPTION_INFO1_REG); +} + +/** + * @brief Get exception information from LP-APM0 + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm0_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm0_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm0_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm0_get_excp_type(path); + info->addr = apm_ll_lp_apm0_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM0 + * + * @param path Access path + */ +static inline void apm_ll_lp_apm0_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + (void)path; + REG_SET_BIT(LP_APM0_M0_STATUS_CLR_REG, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM0 + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM0_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM0 + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm0_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + (void)path; + return ETS_LP_APM0_INTR_SOURCE; +} + +/** + * @brief Enable/disable controller clock gating in LP-APM0 + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN); + } else { + REG_SET_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN); + } + +} + +/** + * @brief Enable/disable controller filter for specific path in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in LP-APM + * + * @param regn_num Region number + */ +static inline void apm_ll_lp_apm_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from LP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from LP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from LP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm_get_excp_type(path); + info->addr = apm_ll_lp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM + * + * @param path Access path + */ +static inline void apm_ll_lp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(LP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable controller clock gating in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } else { + REG_SET_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_LP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable controller filter for specific path in CPU-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in CPU-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(CPU_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in CPU-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in CPU-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_cpu_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(CPU_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in CPU-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_cpu_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(CPU_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in CPU-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_cpu_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in CPU-APM + * + * @param regn_num Region number + */ +static inline void apm_ll_cpu_apm_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from CPU-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from CPU-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from CPU-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from CPU-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_cpu_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + cpu_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_cpu_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_cpu_apm_get_excp_type(path); + info->addr = apm_ll_cpu_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in CPU-APM + * + * @param path Access path + */ +static inline void apm_ll_cpu_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(CPU_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in CPU-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(CPU_APM_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable controller clock gating in CPU-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN); + } else { + REG_SET_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from CPU-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_cpu_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_CPU_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable APM reset event bypass + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_enable_reset_event_bypass(bool enable) { if (enable) { REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); @@ -405,26 +961,6 @@ static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) } } -/** - * @brief Return APM Ctrl interrupt source number. - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - */ -static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path) -{ - switch (apm_ctrl) { - case LP_APM0_CTRL : - return (ETS_LP_APM0_INTR_SOURCE); - case HP_APM_CTRL : - return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path); - case LP_APM_CTRL : - return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path); - } - - return -1; -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c5/include/hal/axi_icm_ll.h b/components/hal/esp32c5/include/hal/axi_icm_ll.h new file mode 100644 index 0000000000..903a49490d --- /dev/null +++ b/components/hal/esp32c5/include/hal/axi_icm_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/hp_system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set arbitration priority for GDMA master port + * + * @param priority Arbitration priority for GDMA master port + */ +static inline void axi_icm_ll_set_gdma_arbiter_prio(uint8_t priority) +{ + HAL_ASSERT(priority < 2); // Ensure priority is within valid range (0-1) + HP_SYSTEM.axi_mst_pri.dma_priority = priority; +} + +/** + * @brief Set arbitration priority for Cache master port + * + * @param priority Arbitration priority for Cache master port + */ +static inline void axi_icm_ll_set_cache_arbiter_prio(uint8_t priority) +{ + HAL_ASSERT(priority < 2); // Ensure priority is within valid range (0-1) + HP_SYSTEM.axi_mst_pri.cache_priority = priority; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/clk_gate_ll.h b/components/hal/esp32c5/include/hal/clk_gate_ll.h new file mode 100644 index 0000000000..4a1d7d2ac6 --- /dev/null +++ b/components/hal/esp32c5/include/hal/clk_gate_ll.h @@ -0,0 +1,128 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include "esp_attr.h" +#include "soc/pcr_struct.h" + +/** + * Enable or disable the clock gate for ref_12m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_12m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_12m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_12m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_12m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_20m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_20m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_20m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_20m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_20m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_40m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_40m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_40m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_40m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_40m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_48m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_48m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_48m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_48m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_48m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_60m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_60m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_60m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_60m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_60m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_80m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_80m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_80m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_80m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_120m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_120m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_120m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_120m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_160m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_160m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_160m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_160m_clk_en(__VA_ARGS__) + +/** + * Enable or disable the clock gate for ref_240m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_240m_clk_en(bool enable) +{ + PCR.pll_div_clk_en.pll_240m_clk_en = enable; +} +/// use a macro to wrap the function, force the caller to use it in a critical section +/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance +#define clk_gate_ll_ref_240m_clk_en(...) (void)__DECLARE_RCC_ATOMIC_ENV; _clk_gate_ll_ref_240m_clk_en(__VA_ARGS__) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/clk_tree_ll.h b/components/hal/esp32c5/include/hal/clk_tree_ll.h index 67c695401e..00c1057955 100644 --- a/components/hal/esp32c5/include/hal/clk_tree_ll.h +++ b/components/hal/esp32c5/include/hal/clk_tree_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -568,6 +568,15 @@ static inline __attribute__((always_inline)) void clk_ll_rc_slow_set_divider(uin HAL_ASSERT(divider == 1); } +/** + * @brief Enable the RTC clock calibration reference XTAL source on timer group0. + * @param enable enable or disable the XTAL source. + */ +static inline __attribute__((always_inline)) void clk_ll_enable_timergroup_rtc_calibration_clock(bool enable) +{ + PCR.timergroup_xtal_conf.tg0_xtal_clk_en = enable; +} + /************************** LP STORAGE REGISTER STORE/LOAD **************************/ /** * @brief Store RTC_SLOW_CLK calibration value in RTC storage register diff --git a/components/hal/esp32c5/include/hal/ds_ll.h b/components/hal/esp32c5/include/hal/ds_ll.h index 02b4e41c35..61ebbc4870 100644 --- a/components/hal/esp32c5/include/hal/ds_ll.h +++ b/components/hal/esp32c5/include/hal/ds_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -78,6 +78,14 @@ static inline ds_key_check_t ds_ll_key_error_source(void) } } +/** + * @brief Set the DS key source. + */ +static inline void ds_ll_set_key_source(ds_key_source_t key_source) +{ + REG_WRITE(DS_KEY_SOURCE_REG, key_source); +} + /** * @brief Write the initialization vector to the corresponding register field. */ diff --git a/components/hal/esp32c5/include/hal/huk_ll.h b/components/hal/esp32c5/include/hal/huk_ll.h index 37215ae35e..fb6e4e69f4 100644 --- a/components/hal/esp32c5/include/hal/huk_ll.h +++ b/components/hal/esp32c5/include/hal/huk_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -22,6 +22,8 @@ #include "hal/huk_types.h" #include "soc/huk_reg.h" #include "soc/soc_caps.h" +#include "soc/lp_aon_reg.h" +#include "esp_rom_sys.h" // HUK memory recharge workaround #ifdef __cplusplus extern "C" { @@ -103,6 +105,20 @@ static inline esp_huk_gen_status_t huk_ll_get_gen_status(void) return (esp_huk_gen_status_t) REG_GET_FIELD(HUK_STATUS_REG, HUK_STATUS); } + +static inline void __attribute__((always_inline)) huk_ll_recharge_huk_memory(void) +{ + REG_CLR_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PD); + + REG_CLR_BIT(LP_AON_PUF_MEM_SW_REG, LP_AON_PUF_MEM_SW); + REG_SET_BIT(LP_AON_PUF_MEM_DISCHARGE_REG, LP_AON_PUF_MEM_DISCHARGE); + esp_rom_delay_us(100000); + + REG_CLR_BIT(LP_AON_PUF_MEM_DISCHARGE_REG, LP_AON_PUF_MEM_DISCHARGE); + REG_SET_BIT(LP_AON_PUF_MEM_SW_REG, LP_AON_PUF_MEM_SW); + esp_rom_delay_us(100000); +} + /** * @brief Read the HUK date information */ diff --git a/components/hal/esp32c5/include/hal/key_mgr_ll.h b/components/hal/esp32c5/include/hal/key_mgr_ll.h index f46c7c2e4c..fddc6a02e1 100644 --- a/components/hal/esp32c5/include/hal/key_mgr_ll.h +++ b/components/hal/esp32c5/include/hal/key_mgr_ll.h @@ -19,6 +19,7 @@ #include "hal/key_mgr_types.h" #include "soc/keymng_reg.h" #include "soc/pcr_struct.h" +#include "soc/pcr_reg.h" #ifdef __cplusplus extern "C" { @@ -34,29 +35,38 @@ static inline esp_key_mgr_state_t key_mgr_ll_get_state(void) return (esp_key_mgr_state_t) REG_GET_FIELD(KEYMNG_STATE_REG, KEYMNG_STATE); } +static inline void key_mgr_ll_power_up(void) +{ + /* Power up the Key Manager peripheral (default state is power-down) */ + REG_CLR_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PD); + REG_SET_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PU); +} + +#define key_mgr_ll_enable_bus_clock(...) do { \ + _key_mgr_ll_enable_bus_clock(__VA_ARGS__); \ + } while(0) + +static inline void key_mgr_ll_power_down(void) +{ + /* Power down the Key Manager peripheral */ + REG_CLR_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PU); + REG_SET_BIT(PCR_KM_PD_CTRL_REG, PCR_KM_MEM_FORCE_PD); +} + /** * @brief Enable the bus clock for Key Manager peripheral - * Note: Please use key_mgr_ll_enable_bus_clock which requires the critical section - * and do not use _key_mgr_ll_enable_bus_clock + * * @param true to enable, false to disable */ static inline void _key_mgr_ll_enable_bus_clock(bool enable) { - // Set the force power down bit to 0 to enable key manager - PCR.km_pd_ctrl.km_mem_force_pd = 0; // Enable key manager clock - PCR.km_conf.km_clk_en = 1; + PCR.km_conf.km_clk_en = enable; } -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define key_mgr_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_bus_clock(__VA_ARGS__) - /** * @brief Enable the peripheral clock for Key Manager * - * Note: Please use key_mgr_ll_enable_peripheral_clock which requires the critical section - * and do not use _key_mgr_ll_enable_peripheral_clock * @param true to enable, false to disable */ static inline void _key_mgr_ll_enable_peripheral_clock(bool enable) @@ -64,12 +74,13 @@ static inline void _key_mgr_ll_enable_peripheral_clock(bool enable) ; /* Nothing to do here, Kept for compatibility with other SoC */ } -#define key_mgr_ll_enable_peripheral_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_enable_peripheral_clock(__VA_ARGS__) +#define key_mgr_ll_enable_peripheral_clock(...) do { \ + _key_mgr_ll_enable_peripheral_clock(__VA_ARGS__); \ + } while(0) /** * @brief Reset the Key Manager peripheral - * Note: Please use key_mgr_ll_reset_register which requires the critical section - * and do not use _key_mgr_ll_reset_register + * */ static inline void _key_mgr_ll_reset_register(void) { @@ -84,9 +95,9 @@ static inline void _key_mgr_ll_reset_register(void) } -/// use a macro to wrap the function, force the caller to use it in a critical section -/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define key_mgr_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _key_mgr_ll_reset_register(__VA_ARGS__) +#define key_mgr_ll_reset_register(...) do { \ + _key_mgr_ll_reset_register(__VA_ARGS__); \ + } while(0) /* @brief Start the key manager at IDLE state */ static inline void key_mgr_ll_start(void) @@ -151,13 +162,16 @@ static inline void key_mgr_ll_use_sw_init_key(void) static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: + case ESP_KEY_MGR_ECDSA_384_KEY: if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA); } else { REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA); } break; + case ESP_KEY_MGR_XTS_AES_128_KEY: case ESP_KEY_MGR_XTS_AES_256_KEY: if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { @@ -167,6 +181,30 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ } break; + case ESP_KEY_MGR_HMAC_KEY: + if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { + REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC); + } else { + REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC); + } + break; + + case ESP_KEY_MGR_DS_KEY: + if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { + REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS); + } else { + REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS); + } + break; + + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { + REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM); + } else { + REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM); + } + break; default: HAL_ASSERT(false && "Unsupported mode"); return; @@ -176,7 +214,9 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: + case ESP_KEY_MGR_ECDSA_384_KEY: return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA)); break; @@ -185,6 +225,19 @@ static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_t return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH)); break; + case ESP_KEY_MGR_HMAC_KEY: + return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC)); + break; + + case ESP_KEY_MGR_DS_KEY: + return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS)); + break; + + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM)); + break; + default: HAL_ASSERT(false && "Unsupported mode"); return ESP_KEY_MGR_USAGE_INVALID; @@ -210,13 +263,30 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void) static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type) { switch(key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: + case ESP_KEY_MGR_ECDSA_384_KEY: REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA); break; + case ESP_KEY_MGR_XTS_AES_128_KEY: case ESP_KEY_MGR_XTS_AES_256_KEY: REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH); break; + + case ESP_KEY_MGR_HMAC_KEY: + REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC); + break; + + case ESP_KEY_MGR_DS_KEY: + REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS); + break; + + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM); + break; + default: HAL_ASSERT(false && "Unsupported mode"); return; @@ -255,9 +325,12 @@ static inline bool key_mgr_ll_is_result_success(void) static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type) { switch (key_type) { - - case ESP_KEY_MGR_ECDSA_KEY: - return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_VLD); + case ESP_KEY_MGR_ECDSA_192_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD); + case ESP_KEY_MGR_ECDSA_256_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD); + case ESP_KEY_MGR_ECDSA_384_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD); break; case ESP_KEY_MGR_XTS_AES_128_KEY: @@ -265,6 +338,19 @@ static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD); break; + case ESP_KEY_MGR_HMAC_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD); + break; + + case ESP_KEY_MGR_DS_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD); + break; + + case ESP_KEY_MGR_PSRAM_128_KEY: + case ESP_KEY_MGR_PSRAM_256_KEY: + return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD); + break; + default: HAL_ASSERT(false && "Unsupported mode"); return 0; @@ -334,15 +420,23 @@ static inline bool key_mgr_ll_is_huk_valid(void) } /* @brief Set the XTS-AES (Flash Encryption) key length for the Key Manager */ -static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_xts_aes_key_len_t key_len) +static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len) { - REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len); + if (key_type == ESP_KEY_MGR_XTS_AES_128_KEY || key_type == ESP_KEY_MGR_XTS_AES_256_KEY) { + REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN, key_len); + } else if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + REG_SET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN, key_len); + } } /* @brief Get the XTS-AES (Flash Encryption) key length for the Key Manager */ -static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(void) +static inline esp_key_mgr_xts_aes_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type) { - return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN); + if (key_type == ESP_KEY_MGR_PSRAM_128_KEY || key_type == ESP_KEY_MGR_PSRAM_256_KEY) { + return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_PSRAM_KEY_LEN); + } else { + return (esp_key_mgr_xts_aes_key_len_t) REG_GET_FIELD(KEYMNG_STATIC_REG, KEYMNG_FLASH_KEY_LEN); + } } /** diff --git a/components/hal/esp32c5/include/hal/lp_clkrst_ll.h b/components/hal/esp32c5/include/hal/lp_clkrst_ll.h new file mode 100644 index 0000000000..e2d215ee45 --- /dev/null +++ b/components/hal/esp32c5/include/hal/lp_clkrst_ll.h @@ -0,0 +1,55 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +// The LL layer for ESP32-C5 LP_CLKRST & LP PERI register operations + +#pragma once + +#include +#include +#include "soc/soc.h" +#include "soc/lp_clkrst_struct.h" +#include "soc/lpperi_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +__attribute__((always_inline)) +static inline void _lp_clkrst_ll_enable_rng_clock(bool en) +{ + LPPERI.clk_en.rng_ck_en = en; +} +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__) + +__attribute__((always_inline)) +static inline void _lp_clkrst_ll_enable_otp_dbg_clock(bool en) +{ + LPPERI.clk_en.otp_dbg_ck_en = en; +} +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_clkrst_ll_enable_otp_dbg_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_otp_dbg_clock(__VA_ARGS__) + +__attribute__((always_inline)) +static inline void _lp_clkrst_ll_enable_lp_ana_i2c_clock(bool en) +{ + LPPERI.clk_en.lp_ana_i2c_ck_en = en; +} +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_clkrst_ll_enable_lp_ana_i2c_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_lp_ana_i2c_clock(__VA_ARGS__) + +__attribute__((always_inline)) +static inline void _lp_clkrst_ll_enable_lp_ext_i2c_clock(bool en) +{ + LPPERI.clk_en.lp_ext_i2c_ck_en = en; +} +/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way +#define lp_clkrst_ll_enable_lp_ext_i2c_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_lp_ext_i2c_clock(__VA_ARGS__) + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c5/include/hal/lp_core_ll.h b/components/hal/esp32c5/include/hal/lp_core_ll.h index 04de32308c..0b0cddc913 100644 --- a/components/hal/esp32c5/include/hal/lp_core_ll.h +++ b/components/hal/esp32c5/include/hal/lp_core_ll.h @@ -32,14 +32,14 @@ extern "C" { * * @param enable true to enable, false to disable */ -static inline void lp_core_ll_enable_bus_clock(bool enable) +static inline void _lp_core_ll_enable_bus_clock(bool enable) { LPPERI.clk_en.lp_cpu_ck_en = enable; } /// use a macro to wrap the function, force the caller to use it in a critical section /// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance -#define lp_core_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_core_ll_enable_bus_clock(__VA_ARGS__) +#define lp_core_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_core_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Reset the lp_core module diff --git a/components/hal/esp32c5/include/hal/rtc_io_ll.h b/components/hal/esp32c5/include/hal/rtc_io_ll.h index 8210382195..cae63b9642 100644 --- a/components/hal/esp32c5/include/hal/rtc_io_ll.h +++ b/components/hal/esp32c5/include/hal/rtc_io_ll.h @@ -60,7 +60,8 @@ static inline void rtcio_ll_iomux_func_sel(int rtcio_num, int func) static inline void _rtcio_ll_enable_io_clock(bool enable) { LPPERI.clk_en.lp_io_ck_en = enable; - while (LPPERI.clk_en.lp_io_ck_en != enable) { + LP_GPIO.clock_gate.clk_en = enable; + while ((LPPERI.clk_en.lp_io_ck_en != enable) || (LP_GPIO.clock_gate.clk_en != enable)) { ; } } diff --git a/components/hal/esp32c5/include/hal/spi_ll.h b/components/hal/esp32c5/include/hal/spi_ll.h index 6db46ddcca..f63c7defa2 100644 --- a/components/hal/esp32c5/include/hal/spi_ll.h +++ b/components/hal/esp32c5/include/hal/spi_ll.h @@ -6,12 +6,10 @@ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer for ESP32C5 SPI register operations + * It is NOT public api, don't use in application code. ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -198,6 +196,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->user.usr_miso_highpart = 0; hw->user.usr_mosi_highpart = 0; + //Disable unused error_end condition + hw->user1.mst_wfull_err_end_en = 0; + hw->user2.mst_rempty_err_end_en = 0; + //Disable unneeded ints hw->slave.val = 0; hw->user.val = 0; diff --git a/components/hal/esp32c5/include/hal/spimem_flash_ll.h b/components/hal/esp32c5/include/hal/spimem_flash_ll.h index f6f1b4e1fa..390aa8d7b6 100644 --- a/components/hal/esp32c5/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c5/include/hal/spimem_flash_ll.h @@ -216,7 +216,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 } /** - * Configure the delay after Suspend/Resume + * Configure the delay after Suspend * * @param dev Beginning address of the peripheral registers. * @param dly_val delay time @@ -224,10 +224,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val) { dev->ctrl1.cs_hold_dly_res = dly_val; - dev->sus_status.flash_per_dly_128 = 1; dev->sus_status.flash_pes_dly_128 = 1; } +/** + * Configure the delay after Resume + * + * @param dev Beginning address of the peripheral registers. + * @param dly_val delay time + */ +static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val) +{ + dev->ctrl1.cs_hold_dly_per = dly_val; + dev->sus_status.flash_per_dly_128 = 1; +} + /** * Configure the cs hold delay time(used to set the minimum CS high time tSHSL) * diff --git a/components/hal/esp32c5/include/hal/uart_ll.h b/components/hal/esp32c5/include/hal/uart_ll.h index 28c94dd106..22d5b0eb5d 100644 --- a/components/hal/esp32c5/include/hal/uart_ll.h +++ b/components/hal/esp32c5/include/hal/uart_ll.h @@ -185,14 +185,14 @@ FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, ui * @param hw_id LP UART instance ID * @param enable True to enable, False to disable */ -static inline void lp_uart_ll_enable_bus_clock(int hw_id, bool enable) +static inline void _lp_uart_ll_enable_bus_clock(int hw_id, bool enable) { (void)hw_id; LPPERI.clk_en.lp_uart_ck_en = enable; } /// LPPERI.clk_en is a shared register, so this function must be used in an atomic way -#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_enable_bus_clock(__VA_ARGS__) +#define lp_uart_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_uart_ll_enable_bus_clock(__VA_ARGS__) /** * @brief Enable the UART clock. diff --git a/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h index 6cff591138..1850a92182 100644 --- a/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c5/include/hal/usb_serial_jtag_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -329,6 +329,25 @@ FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void) return (PCR.usb_device_conf.usb_device_clk_en && !PCR.usb_device_conf.usb_device_rst_en); } +/* ---------------------------- USB MEM Control ---------------------------- */ +/** + * @brief Power down the power USJ mem. + * @param clk_en True if power down the USJ mem. + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_set_mem_pd(bool pd) +{ + USB_SERIAL_JTAG.mem_conf.usb_mem_pd = pd; +} + +/** + * @brief Enable the mem clock for USJ module + * @param clk_en True if enable the clock of USJ module mem. + */ +FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_mem_clock(bool clk_en) +{ + USB_SERIAL_JTAG.mem_conf.usb_mem_clk_en = clk_en; +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c6/include/hal/apm_ll.h b/components/hal/esp32c6/include/hal/apm_ll.h index 0288568707..6859dc7f2c 100644 --- a/components/hal/esp32c6/include/hal/apm_ll.h +++ b/components/hal/esp32c6/include/hal/apm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,394 +7,644 @@ #include #include -#include "esp_err.h" -#include "soc/pcr_reg.h" + +#include "soc/apm_defs.h" #include "soc/tee_reg.h" #include "soc/lp_tee_reg.h" -#include "soc/lp_apm0_reg.h" #include "soc/hp_apm_reg.h" +#include "soc/hp_apm_struct.h" +#include "soc/lp_apm0_reg.h" +#include "soc/lp_apm0_struct.h" #include "soc/lp_apm_reg.h" +#include "soc/lp_apm_struct.h" + +#include "soc/pcr_reg.h" #include "soc/interrupts.h" +#include "hal/apm_types.h" #ifdef __cplusplus extern "C" { #endif -#define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_ID_S 18 -#define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U -#define APM_LL_CTRL_EXCEPTION_MODE_S 16 -#define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U -#define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU -#define APM_LL_CTRL_EXCEPTION_REGION_S 0 -#define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU - -#define APM_LL_HP_MAX_REGION_NUM 15 -#define APM_LL_LP_MAX_REGION_NUM 3 -#define APM_LL_MASTER_MAX 32 - -#define LP_APM0_MAX_ACCESS_PATH 0x1 -#define HP_APM_MAX_ACCESS_PATH 0x4 -#define LP_APM_MAX_ACCESS_PATH 0x2 - -#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION_FILTER_EN_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION_FILTER_EN_REG) : \ - (LP_APM_REGION_FILTER_EN_REG)); \ - }) - -#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) - -#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \ - (LP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num))); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0)) -#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path))); \ - }) - -#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) -#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U -#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1))) - -#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_INT_EN_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_INT_EN_REG) : \ - (LP_APM_INT_EN_REG)); \ - }) - -#define APM_CTRL_CLK_EN (BIT(0)) -#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_CLOCK_GATE_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_CLOCK_GATE_REG) : \ - (LP_APM_CLOCK_GATE_REG)); \ - }) - -#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \ - ({\ - (LP_APM0_CTRL == apm_ctrl) ? (LP_APM0_FUNC_CTRL_REG) : \ - ((HP_APM_CTRL == apm_ctrl) ? (HP_APM_FUNC_CTRL_REG) : \ - (LP_APM_FUNC_CTRL_REG)); \ - }) +/* Helper macros for calculating pms attr field position for given security mode */ +#define APM_REGION_PMS_SHIFT(mode) (4U * ((mode) - 1)) +#define APM_REGION_PMS_MASK(mode) (0x07U << APM_REGION_PMS_SHIFT(mode)) +#define APM_REGION_PMS_FIELD(mode, pms) ((pms) << APM_REGION_PMS_SHIFT(mode)) /** - * @brief APM Master ID - */ -typedef enum { - APM_LL_MASTER_HPCORE = 0, - APM_LL_MASTER_LPCORE = 1, - APM_LL_MASTER_REGDMA = 2, - APM_LL_MASTER_SDIOSLV = 3, - APM_LL_MASTER_MODEM = 4, - APM_LL_MASTER_MEM_MONITOR = 5, - APM_LL_MASTER_TRACE = 6, - APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID - APM_LL_MASTER_GDMA_SPI2 = 16, - APM_LL_MASTER_GDMA_UHCI0 = 18, - APM_LL_MASTER_GDMA_I2S0 = 19, - APM_LL_MASTER_GDMA_AES = 22, - APM_LL_MASTER_GDMA_SHA = 23, - APM_LL_MASTER_GDMA_ADC = 24, - APM_LL_MASTER_GDMA_PARLIO = 25, -} apm_ll_master_id_t; - -/** - * @brief APM Controller - */ -typedef enum { - LP_APM0_CTRL = 0, - HP_APM_CTRL = 1, - LP_APM_CTRL = 2, -} apm_ll_apm_ctrl_t; - -/** - * @brief APM Secure Mode - */ -typedef enum { - APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ - APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */ - APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */ - APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */ -} apm_ll_secure_mode_t; - -/** - * @brief APM Ctrl access path - */ -typedef enum { - APM_CTRL_ACCESS_PATH_M0 = 0x0, - APM_CTRL_ACCESS_PATH_M1 = 0x1, - APM_CTRL_ACCESS_PATH_M2 = 0x2, - APM_CTRL_ACCESS_PATH_M3 = 0x3, -} apm_ll_ctrl_access_path_t; - -/** - * @brief APM Ctrl path. - */ -typedef struct { - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */ - apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */ -} apm_ctrl_path_t; - -/** - * @brief APM exception information - */ -typedef struct { - apm_ctrl_path_t apm_path; - uint8_t excp_regn; - uint8_t excp_mode; - uint8_t excp_id; - uint8_t excp_type; - uint32_t excp_addr; -} apm_ctrl_exception_info_t; - -/** - * @brief Set secure mode + * @brief Set security mode for a specific master in HP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param master_id APM master ID - * @param sec_mode Secure mode + * @param id Master ID + * @param mode Security mode to set */ -static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, - apm_ll_secure_mode_t sec_mode) +static inline void apm_ll_hp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) { - if (apm_ctrl == HP_APM_CTRL) { - REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); - } else if ((apm_ctrl == LP_APM0_CTRL) || (apm_ctrl == LP_APM_CTRL)) { - REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, sec_mode); - } + REG_WRITE(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, mode); } /** - * @brief TEE controller clock auto gating enable + * @brief Enable/disable clock gating for HP-TEE * - * @param enable Flag for HP clock auto gating enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_tee_ll_clk_gating_enable(bool enable) +static inline void apm_ll_hp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); - } else { REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); + } else { + REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); } } /** - * @brief enable/disable APM Ctrl Region access permission filter + * @brief Set security mode for a specific master in LP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Memory Region number - * @param enable Flag for Region access filter enable/disable + * @param id Master ID (unused) + * @param mode Security mode to set */ -static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, bool enable) +static inline void apm_ll_lp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) +{ + (void)id; + REG_WRITE(LP_TEE_M0_MODE_CTRL_REG, mode); +} + +/** + * @brief Enable/disable clock gating for LP-TEE + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_CLR_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN); } else { - REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_SET_BIT(LP_TEE_CLOCK_GATE_REG, LP_TEE_CLK_EN); } } /** - * @brief enable/disable APM Ctrl access path(M[0:n]) + * @brief Enable/disable forced HP memory access for LP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access path - * @param enable Flag for LP APM0 M path filter enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_lp_tee_enable_force_hp_mem_access(bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(LP_TEE_FORCE_ACC_HP_REG, LP_TEE_FORCE_ACC_HPMEM_EN); } } /** - * @brief APM Ctrl Region start address configuration + * @brief Enable/disable all controller filters in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param addr Region start address + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) +static inline void apm_ll_hp_apm_enable_ctrl_filter_all(bool enable) { - REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr); + REG_WRITE(HP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); } /** - * @brief APM Ctrl Region end address configuration + * @brief Enable/disable region filter in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param addr Region end address + * @param regn_num Region number + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) -{ - REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr); -} - -/** - * @brief HP Region pms attributes configuration - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param regn_num Region number to be configured - * @param sec_mode Secure mode of the Master - * @param regn_pms XWR permissions for the given secure mode and Region number - */ -static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) -{ - uint32_t val = 0; - val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num)); - val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode); - val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); - REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val); -} - -/** - * @brief Get APM Ctrl access path(M[0:n]) exception status - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access path - */ -static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) -{ - return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path)); -} - -/** - * @brief Clear APM Ctrl access path(M[0:n]) exception - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param amp_m_path APM Ctrl access path - */ -static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) -{ - REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path), - APM_CTRL_M_REGION_STATUS_CLR); -} - -/** - * @brief Get APM Ctrl access path(M[0:n]) exception information - * - * @param excp_info Exception related information like addr, - * region, apm_ctrl, apm_m_path, sec_mode and master id - */ -static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info) -{ - excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_ID); - excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_MODE); - excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_REGION); - excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path); - excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path)); -} - -/** - * @brief Interrupt enable for APM Ctrl at access path(M[0:n]) - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - * @param enable Flag for access path interrupt enable/disable - */ -static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_hp_apm_enable_region_filter(uint32_t regn_num, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } } /** - * @brief APM Ctrl clock auto gating enable + * @brief Set region start address in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param enable Flag for HP clock auto gating enable/disable + * @param regn_num Region number + * @param addr Start address */ -static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +static inline void apm_ll_hp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(HP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in HP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_hp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(HP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in HP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_hp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = HP_APM_REGION0_PMS_ATTR_REG + APM_REGION_PMS_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Get exception data (regn, master, security mode) from HP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_hp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from HP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_hp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from HP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_hp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from HP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_hp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + hp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_hp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_hp_apm_get_excp_type(path); + info->addr = apm_ll_hp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in HP-APM + * + * @param path Access path + */ +static inline void apm_ll_hp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(HP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in HP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_SET_BIT(HP_APM_INT_EN_REG, BIT(path)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(path)); } } /** - * @brief APM/TEE/HP System Reg reset event bypass enable + * @brief Get controller interrupt source number from HP-APM * - * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, - * but also some reset events. - * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. - * Some reset events will be bypassed. - * - * @param enable Flag for event bypass enable/disable + * @param path Access path + * @return Interrupt source number */ -static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) +static inline int apm_ll_hp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_HP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable controller clock gating in HP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); + } else { + REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); + } +} + +/** + * @brief Enable/disable controller filter for specific path in LP-APM0 + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM0_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM0 + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM0_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM0 + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM0_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM0 + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm0_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM0_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM0 + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm0_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM0_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM0 + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm0_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM0_REGION0_PMS_ATTR_REG + APM_REGION_PMS_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM0 + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_data(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_EXCEPTION_INFO0_REG); +} + +/** + * @brief Get exception status from LP-APM0 + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_type(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_STATUS_REG); +} + +/** + * @brief Get exception address from LP-APM0 + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm0_get_excp_addr(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM0_M0_EXCEPTION_INFO1_REG); +} + +/** + * @brief Get exception information from LP-APM0 + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm0_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm0_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm0_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm0_get_excp_type(path); + info->addr = apm_ll_lp_apm0_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM0 + * + * @param path Access path + */ +static inline void apm_ll_lp_apm0_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + (void)path; + REG_SET_BIT(LP_APM0_M0_STATUS_CLR_REG, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM0 + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM0_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM0_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM0 + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm0_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + (void)path; + return ETS_LP_APM0_INTR_SOURCE; +} + +/** + * @brief Enable/disable controller clock gating in LP-APM0 + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm0_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN); + } else { + REG_SET_BIT(LP_APM0_CLOCK_GATE_REG, LP_APM0_CLK_EN); + } + +} + +/** + * @brief Enable/disable controller filter for specific path in HP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable controller filter for specific path in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM_REGION0_PMS_ATTR_REG + APM_REGION_PMS_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from LP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from LP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(LP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from LP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm_get_excp_type(path); + info->addr = apm_ll_lp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM + * + * @param path Access path + */ +static inline void apm_ll_lp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(LP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(LP_APM_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable controller clock gating in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } else { + REG_SET_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_LP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable APM reset event bypass + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_enable_reset_event_bypass(bool enable) { if (enable) { REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); @@ -403,26 +653,6 @@ static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) } } -/** - * @brief Fetch the APM Ctrl interrupt source number. - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - */ -static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path) -{ - switch (apm_ctrl) { - case LP_APM0_CTRL : - return (ETS_LP_APM0_INTR_SOURCE); - case HP_APM_CTRL : - return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path); - case LP_APM_CTRL : - return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path); - } - - return -1; -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/ahb_dma_ll.h b/components/hal/esp32c61/include/hal/ahb_dma_ll.h index bda732a8a0..d2f5f95bfb 100644 --- a/components/hal/esp32c61/include/hal/ahb_dma_ll.h +++ b/components/hal/esp32c61/include/hal/ahb_dma_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -212,6 +212,9 @@ static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; + case 64: + burst_mode = 3; // incr16 + break; default: HAL_ASSERT(false); break; @@ -462,6 +465,9 @@ static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t cha case 32: burst_mode = 2; // incr8 break; + case 64: + burst_mode = 3; // incr16 + break; default: HAL_ASSERT(false); break; diff --git a/components/hal/esp32c61/include/hal/apm_ll.h b/components/hal/esp32c61/include/hal/apm_ll.h index 664160ec2e..ff90cce104 100644 --- a/components/hal/esp32c61/include/hal/apm_ll.h +++ b/components/hal/esp32c61/include/hal/apm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,375 +7,644 @@ #include #include -#include "soc/pcr_reg.h" + +#include "soc/apm_defs.h" #include "soc/tee_reg.h" #include "soc/hp_apm_reg.h" +#include "soc/hp_apm_struct.h" #include "soc/lp_apm_reg.h" +#include "soc/lp_apm_struct.h" +#include "soc/cpu_apm_reg.h" +#include "soc/cpu_apm_struct.h" + +#include "soc/pcr_reg.h" #include "soc/interrupts.h" +#include "hal/apm_types.h" #ifdef __cplusplus extern "C" { #endif -#define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_ID_S 18 -#define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U -#define APM_LL_CTRL_EXCEPTION_MODE_S 16 -#define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U -#define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU -#define APM_LL_CTRL_EXCEPTION_REGION_S 0 -#define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU - -#define APM_LL_HP_MAX_REGION_NUM 15 -#define APM_LL_LP_MAX_REGION_NUM 3 -#define APM_LL_MASTER_MAX 32 - -#define HP_APM_MAX_ACCESS_PATH 0x4 -#define LP_APM_MAX_ACCESS_PATH 0x1 - -#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : \ - (HP_APM_REGION_FILTER_EN_REG); \ - }) - -#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) - -#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ATTR_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_ATTR_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0)) -#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) -#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U -#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1))) - -#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) : \ - (HP_APM_INT_EN_REG); \ - }) - -#define APM_CTRL_CLK_EN (BIT(0)) -#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : \ - (HP_APM_CLOCK_GATE_REG); \ - }) - -#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : \ - (HP_APM_FUNC_CTRL_REG); \ - }) +/* Helper macros for getting pms attributes field mask for given security mode */ +#define APM_REGION_PMS_SHIFT(mode) (4U * ((mode) - 1)) +#define APM_REGION_PMS_MASK(mode) (0x07U << APM_REGION_PMS_SHIFT(mode)) +#define APM_REGION_PMS_FIELD(mode, pms) ((pms) << APM_REGION_PMS_SHIFT(mode)) /** - * @brief APM Master ID - */ -typedef enum { - APM_LL_MASTER_HPCORE = 0, - APM_LL_MASTER_LPCORE = 1, - APM_LL_MASTER_REGDMA = 2, - APM_LL_MASTER_SDIOSLV = 3, - APM_LL_MASTER_MODEM = 4, - APM_LL_MASTER_MEM_MONITOR = 5, - APM_LL_MASTER_TRACE = 6, - APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID - APM_LL_MASTER_GDMA_SPI2 = 16, - APM_LL_MASTER_GDMA_UHCI0 = 18, - APM_LL_MASTER_GDMA_I2S0 = 19, - APM_LL_MASTER_GDMA_AES = 22, - APM_LL_MASTER_GDMA_SHA = 23, - APM_LL_MASTER_GDMA_ADC = 24, - APM_LL_MASTER_GDMA_PARLIO = 25, -} apm_ll_master_id_t; - -/** - * @brief APM Controller - */ -typedef enum { - LP_APM_CTRL = 0, - HP_APM_CTRL = 1, -} apm_ll_apm_ctrl_t; - -/** - * @brief APM Secure Mode - */ -typedef enum { - APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ - APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */ - APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */ - APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */ -} apm_ll_secure_mode_t; - -/** - * @brief APM Ctrl access path - */ -typedef enum { - APM_CTRL_ACCESS_PATH_M0 = 0x0, - APM_CTRL_ACCESS_PATH_M1 = 0x1, - APM_CTRL_ACCESS_PATH_M2 = 0x2, - APM_CTRL_ACCESS_PATH_M3 = 0x3, -} apm_ll_ctrl_access_path_t; - -/** - * @brief APM Ctrl path. - */ -typedef struct { - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM/HP APM. */ - apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */ -} apm_ctrl_path_t; - -/** - * @brief APM exception information - */ -typedef struct { - apm_ctrl_path_t apm_path; - uint8_t excp_regn; - uint8_t excp_mode; - uint8_t excp_id; - uint8_t excp_type; - uint32_t excp_addr; -} apm_ctrl_exception_info_t; - -/** - * @brief Set secure mode + * @brief Set security mode for a specific master in HP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param master_id APM master ID - * @param sec_mode Secure mode + * @param id Master ID + * @param mode Security mode to set */ -static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, - apm_ll_secure_mode_t sec_mode) +static inline void apm_ll_hp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) { - if (apm_ctrl == HP_APM_CTRL) { - REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); - } + REG_WRITE(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, mode); } /** - * @brief TEE controller clock auto gating enable + * @brief Lock master security mode for HP-TEE * - * @param enable Flag for HP clock auto gating enable/disable + * @param id Master ID */ -static inline void apm_tee_ll_clk_gating_enable(bool enable) +static inline void apm_ll_hp_tee_lock_master_sec_mode(apm_master_id_t id) +{ + REG_SET_BIT(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, APM_TEE_MODE_LOCK_BIT); +} + +/** + * @brief Enable/disable clock gating for HP-TEE + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); - } else { REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); + } else { + REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); } } /** - * @brief enable/disable APM Ctrl Region access permission filter + * @brief Enable/disable controller filter for specific path in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Memory Region number - * @param enable Flag for Region access filter enable/disable + * @param path Access path + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } else { - REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } } /** - * @brief enable/disable APM Ctrl access path(M[0:n]) + * @brief Enable/disable all controller filters in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access path - * @param enable Flag for APM Ctrl M path filter enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(HP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in HP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_region_filter(uint32_t regn_num, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } } /** - * @brief APM Ctrl Region start address configuration + * @brief Set region start address in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param addr Region start address + * @param regn_num Region number + * @param addr Start address */ -static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) +static inline void apm_ll_hp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) { - REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr); + REG_WRITE(HP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); } /** - * @brief APM Ctrl Region end address configuration + * @brief Set region end address in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param addr Region end address + * @param regn_num Region number + * @param addr End address */ -static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) +static inline void apm_ll_hp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) { - REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr); + REG_WRITE(HP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); } /** - * @brief HP Region pms attributes configuration + * @brief Set security mode region attributes in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param sec_mode Secure mode of the Master - * @param regn_pms XWR permissions for the given secure mode and Region number + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes */ -static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) +static inline void apm_ll_hp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) { - uint32_t val = 0; - val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num)); - val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode); - val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); - REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val); + uint32_t reg = HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); } /** - * @brief Get APM Ctrl access path(M[0:n]) exception status + * @brief Lock security mode region attributes in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access path + * @param regn_num Region number */ -static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) +static inline void apm_ll_hp_apm_lock_sec_mode_region_attr(uint32_t regn_num) { - return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path)); + REG_SET_BIT(HP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); } /** - * @brief Clear APM Ctrl access path(M[0:n]) exception + * @brief Get exception data (regn, master, security mode) from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param amp_m_path APM Ctrl access path + * @param path Access path + * @return Exception data */ -static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) +static inline uint32_t apm_ll_hp_apm_get_excp_data(apm_ctrl_access_path_t path) { - REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path), - APM_CTRL_M_REGION_STATUS_CLR); + return REG_READ(HP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); } /** - * @brief Get APM Ctrl access path(M[0:n]) exception information + * @brief Get exception status from HP-APM * - * @param excp_info Exception related information like addr, - * region, apm_ctrl, apm_m_path, sec_mode and master id + * @param path Access path + * @return Exception type */ -static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info) +static inline uint32_t apm_ll_hp_apm_get_excp_type(apm_ctrl_access_path_t path) { - excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_ID); - excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_MODE); - excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_REGION); - excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path); - excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path)); + return REG_READ(HP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); } /** - * @brief Interrupt enable for APM Ctrl at access path(M[0:n]) + * @brief Get exception address from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - * @param enable Flag for access path interrupt enable/disable + * @param path Access path + * @return Exception address */ -static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline uint32_t apm_ll_hp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from HP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_hp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + hp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_hp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_hp_apm_get_excp_type(path); + info->addr = apm_ll_hp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in HP-APM + * + * @param path Access path + */ +static inline void apm_ll_hp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(HP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in HP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(HP_APM_INT_EN_REG, BIT(path)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(path)); } } /** - * @brief APM Ctrl clock auto gating enable + * @brief Get controller interrupt source number from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param enable Flag for HP clock auto gating enable/disable + * @param path Access path + * @return Interrupt source number */ -static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +static inline int apm_ll_hp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_HP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable controller clock gating in HP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); } } /** - * @brief APM/TEE/HP System Reg reset event bypass enable + * @brief Enable/disable controller filter for specific path in LP-APM * - * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, - * but also some reset events. - * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. - * Some reset events will be bypassed. - * - * @param enable Flag for event bypass enable/disable + * @param path Access path + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) +static inline void apm_ll_lp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + (void)path; + if (enable) { + REG_SET_BIT(LP_APM_FUNC_CTRL_REG, LP_APM_M0_FUNC_EN); + } else { + REG_CLR_BIT(LP_APM_FUNC_CTRL_REG, LP_APM_M0_FUNC_EN); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in LP-APM + * + * @param regn_num Region number + */ +static inline void apm_ll_lp_apm_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(LP_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_EXCEPTION_INFO0_REG); +} + +/** + * @brief Get exception status from LP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_STATUS_REG); +} + +/** + * @brief Get exception address from LP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_EXCEPTION_INFO1_REG); +} + +/** + * @brief Get exception information from LP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm_get_excp_type(path); + info->addr = apm_ll_lp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM + * + * @param path Access path + */ +static inline void apm_ll_lp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + (void)path; + REG_SET_BIT(LP_APM_M0_STATUS_CLR_REG, LP_APM_M0_EXCEPTION_STATUS_CLR); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + (void)path; + if (enable) { + REG_SET_BIT(LP_APM_INT_EN_REG, LP_APM_M0_APM_INT_EN); + } else { + REG_CLR_BIT(LP_APM_INT_EN_REG, LP_APM_M0_APM_INT_EN); + } +} + +/** + * @brief Enable/disable controller clock gating in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } else { + REG_SET_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + (void)path; + return ETS_LP_APM_M0_INTR_SOURCE; +} + +/** + * @brief Enable/disable controller filter for specific path in CPU-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path)); + } else { + REG_CLR_BIT(CPU_APM_FUNC_CTRL_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable all controller filters in CPU-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(CPU_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in CPU-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(CPU_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in CPU-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_cpu_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(CPU_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in CPU-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_cpu_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(CPU_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in CPU-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_cpu_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Lock security mode region attributes in CPU-APM + * + * @param regn_num Region number + */ +static inline void apm_ll_cpu_apm_lock_sec_mode_region_attr(uint32_t regn_num) +{ + REG_SET_BIT(CPU_APM_REGION0_ATTR_REG + APM_REGION_ATTR_OFFSET * regn_num, APM_REGION_LOCK_BIT); +} + +/** + * @brief Get exception data (regn, master, security mode) from CPU-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception status from CPU-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception address from CPU-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_cpu_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + return REG_READ(CPU_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); +} + +/** + * @brief Get exception information from CPU-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_cpu_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + cpu_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_cpu_apm_get_excp_data(path); + info->regn = reg.apm_m0_exception_region; + info->mode = reg.apm_m0_exception_mode; + info->id = reg.apm_m0_exception_id; + + info->type = apm_ll_cpu_apm_get_excp_type(path); + info->addr = apm_ll_cpu_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in CPU-APM + * + * @param path Access path + */ +static inline void apm_ll_cpu_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(CPU_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in CPU-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + if (enable) { + REG_SET_BIT(CPU_APM_INT_EN_REG, BIT(path)); + } else { + REG_CLR_BIT(CPU_APM_INT_EN_REG, BIT(path)); + } +} + +/** + * @brief Enable/disable controller clock gating in CPU-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_cpu_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN); + } else { + REG_SET_BIT(CPU_APM_CLOCK_GATE_REG, CPU_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from CPU-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_cpu_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_CPU_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable APM reset event bypass + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_enable_reset_event_bypass(bool enable) { if (enable) { REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); @@ -384,24 +653,6 @@ static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) } } -/** - * @brief Fetch the APM Ctrl interrupt source number. - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - */ -static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path) -{ - switch (apm_ctrl) { - case HP_APM_CTRL : - return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path); - case LP_APM_CTRL : - return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path); - } - - return -1; -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c61/include/hal/axi_icm_ll.h b/components/hal/esp32c61/include/hal/axi_icm_ll.h new file mode 100644 index 0000000000..1742a9933c --- /dev/null +++ b/components/hal/esp32c61/include/hal/axi_icm_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/hp_system_struct.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set arbitration priority for GDMA master port + * + * @param priority Arbitration priority for GDMA master port + */ +static inline void axi_icm_ll_set_gdma_arbiter_prio(uint8_t priority) +{ + HAL_ASSERT(priority < 2); // Ensure priority is within valid range (0-1) + HP_SYSTEM.system_axi_mst_pri.system_dma_priority = priority; +} + +/** + * @brief Set arbitration priority for Cache master port + * + * @param priority Arbitration priority for Cache master port + */ +static inline void axi_icm_ll_set_cache_arbiter_prio(uint8_t priority) +{ + HAL_ASSERT(priority < 2); // Ensure priority is within valid range (0-1) + HP_SYSTEM.system_axi_mst_pri.system_cache_priority = priority; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b636530415..965c7627f9 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -246,11 +246,11 @@ static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t ma HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_CLR_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } @@ -268,11 +268,11 @@ static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t m HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2 | CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0); uint32_t ibus_mask = 0; - ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_ICACHE_SHUT_IBUS0 : 0); + ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, ibus_mask); uint32_t dbus_mask = 0; - dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS0 : 0); + dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_CACHE_SHUT_BUS1 : 0); REG_SET_BIT(CACHE_L1_CACHE_CTRL_REG, dbus_mask); } diff --git a/components/hal/esp32c61/include/hal/efuse_ll.h b/components/hal/esp32c61/include/hal/efuse_ll.h index f86f8392ba..e1b0a9a641 100644 --- a/components/hal/esp32c61/include/hal/efuse_ll.h +++ b/components/hal/esp32c61/include/hal/efuse_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -57,6 +57,46 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en return EFUSE0.rd_repeat_data1.secure_boot_en; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ocode(void) +{ + return EFUSE0.rd_sys_part1_data4.ocode; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void) +{ + return (EFUSE0.rd_mac_sys3.active_hp_dbias_1 << 3)|EFUSE0.rd_mac_sys2.active_hp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void) +{ + return EFUSE0.rd_mac_sys3.active_lp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_dbg(void) +{ + return EFUSE0.rd_mac_sys3.lslp_hp_dbg; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_lslp_hp_dbias(void) +{ + return EFUSE0.rd_mac_sys3.lslp_hp_dbias; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_dbg(void) +{ + return EFUSE0.rd_mac_sys3.dslp_lp_dbg; +} + +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_dslp_lp_dbias(void) +{ + return EFUSE0.rd_mac_sys3.dslp_lp_dbias; +} + +__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void) +{ + return EFUSE0.rd_mac_sys3.lp_hp_dbias_vol_gap; +} + // use efuse_hal_get_major_chip_version() to get major chip version __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void) { @@ -105,6 +145,11 @@ __attribute__((always_inline)) static inline void efuse_ll_set_ecdsa_key_blk(ecd EFUSE0.conf.cfg_ecdsa_blk = efuse_blk; } +__attribute__((always_inline)) static inline uint32_t efuse_ll_get_recovery_bootloader_sector(void) +{ + return EFUSE0.rd_repeat_data3.recovery_bootloader_flash_sector; +} + /******************* eFuse control functions *************************/ __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void) diff --git a/components/hal/esp32c61/include/hal/gpio_ll.h b/components/hal/esp32c61/include/hal/gpio_ll.h index d8c3603db8..11048e7d56 100644 --- a/components/hal/esp32c61/include/hal/gpio_ll.h +++ b/components/hal/esp32c61/include/hal/gpio_ll.h @@ -38,7 +38,7 @@ extern "C" { #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(0)) #define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(1)) -#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTR_SOURCE +#define GPIO_LL_INTR_SOURCE0 ETS_GPIO_INTERRUPT_PRO_SOURCE /** * @brief Get the configuration for an IO diff --git a/components/hal/esp32c61/include/hal/spi_ll.h b/components/hal/esp32c61/include/hal/spi_ll.h index 1ad870726c..f0d77b567d 100644 --- a/components/hal/esp32c61/include/hal/spi_ll.h +++ b/components/hal/esp32c61/include/hal/spi_ll.h @@ -1,17 +1,15 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /******************************************************************************* * NOTICE - * The hal is not public api, don't use in application code. - * See readme.md in soc/include/hal/readme.md + * The LL layer for ESP32C61 SPI register operations + * It is NOT public api, don't use in application code. ******************************************************************************/ -// The LL layer for SPI register operations - #pragma once #include //for abs() @@ -199,6 +197,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->user.usr_miso_highpart = 0; hw->user.usr_mosi_highpart = 0; + //Disable unused error_end condition + hw->user1.mst_wfull_err_end_en = 0; + hw->user2.mst_rempty_err_end_en = 0; + //Disable unneeded ints hw->slave.val = 0; hw->user.val = 0; @@ -717,7 +719,7 @@ static inline void spi_ll_master_keep_cs(spi_dev_t *hw, int keep_active) */ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_point_t sample_point) { - //This is not supported + hw->clock.clk_edge_sel = (sample_point == SPI_SAMPLING_POINT_PHASE_1); } /** @@ -725,7 +727,7 @@ static inline void spi_ll_master_set_rx_timing_mode(spi_dev_t *hw, spi_sampling_ */ static inline bool spi_ll_master_is_rx_std_sample_supported(void) { - return false; + return true; } /** diff --git a/components/hal/esp32c61/include/hal/spimem_flash_ll.h b/components/hal/esp32c61/include/hal/spimem_flash_ll.h index 3fb325e2d1..2174d97944 100644 --- a/components/hal/esp32c61/include/hal/spimem_flash_ll.h +++ b/components/hal/esp32c61/include/hal/spimem_flash_ll.h @@ -215,7 +215,7 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 } /** - * Configure the delay after Suspend/Resume + * Configure the delay after Suspend * * @param dev Beginning address of the peripheral registers. * @param dly_val delay time @@ -223,10 +223,21 @@ static inline void spimem_flash_ll_set_read_sus_status(spi_mem_dev_t *dev, uint3 static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dly_val) { dev->ctrl1.cs_hold_dly_res = dly_val; - dev->sus_status.flash_per_dly_128 = 1; dev->sus_status.flash_pes_dly_128 = 1; } +/** + * Configure the delay after Resume + * + * @param dev Beginning address of the peripheral registers. + * @param dly_val delay time + */ +static inline void spimem_flash_ll_set_rs_delay(spi_mem_dev_t *dev, uint32_t dly_val) +{ + dev->ctrl1.cs_hold_dly_per = dly_val; + dev->sus_status.flash_per_dly_128 = 1; +} + /** * Configure the cs hold delay time(used to set the minimum CS high time tSHSL) * diff --git a/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h b/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h index ba16f6f8a3..66f01baeb3 100644 --- a/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h +++ b/components/hal/esp32c61/include/hal/usb_serial_jtag_ll.h @@ -116,7 +116,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len) int i; for (i = 0; i < (int)rd_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break; - buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte; + buf[i] = USB_SERIAL_JTAG.ep1.val; } return i; } @@ -135,7 +135,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w int i; for (i = 0; i < (int)wr_len; i++) { if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break; - USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i]; + USB_SERIAL_JTAG.ep1.val = buf[i]; } return i; } diff --git a/components/hal/esp32h2/include/hal/apm_ll.h b/components/hal/esp32h2/include/hal/apm_ll.h index cc0046ce27..3428628ffe 100644 --- a/components/hal/esp32h2/include/hal/apm_ll.h +++ b/components/hal/esp32h2/include/hal/apm_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,377 +7,423 @@ #include #include -#include "esp_err.h" -#include "soc/pcr_reg.h" + +#include "soc/apm_defs.h" #include "soc/tee_reg.h" -#include "soc/lp_apm0_reg.h" #include "soc/hp_apm_reg.h" +#include "soc/hp_apm_struct.h" #include "soc/lp_apm_reg.h" +#include "soc/lp_apm_struct.h" + +#include "soc/pcr_reg.h" #include "soc/interrupts.h" +#include "hal/apm_types.h" #ifdef __cplusplus extern "C" { #endif -#define APM_LL_CTRL_EXCEPTION_ID 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_ID_S 18 -#define APM_LL_CTRL_EXCEPTION_ID_V 0x0000001FU -#define APM_LL_CTRL_EXCEPTION_MODE 0x00000003U -#define APM_LL_CTRL_EXCEPTION_MODE_S 16 -#define APM_LL_CTRL_EXCEPTION_MODE_V 0x00000003U -#define APM_LL_CTRL_EXCEPTION_REGION 0x0000FFFFU -#define APM_LL_CTRL_EXCEPTION_REGION_S 0 -#define APM_LL_CTRL_EXCEPTION_REGION_V 0x0000FFFFU - -#define APM_LL_HP_MAX_REGION_NUM 15 -#define APM_LL_LP_MAX_REGION_NUM 3 -#define APM_LL_MASTER_MAX 32 - -#define HP_APM_MAX_ACCESS_PATH 0x4 -#define LP_APM_MAX_ACCESS_PATH 0x1 - -#define APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION_FILTER_EN_REG) : \ - (HP_APM_REGION_FILTER_EN_REG); \ - }) - -#define TEE_LL_MODE_CTRL_REG(master_id) (TEE_M0_MODE_CTRL_REG + 4 * (master_id)) - -#define APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_ADDR_START_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_ADDR_END_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)) : \ - (HP_APM_REGION0_PMS_ATTR_REG + 0xC * (regn_num)); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_CTRL_M_REGION_STATUS_CLR (BIT(0)) -#define APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_CLR_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_TEE_EXCP_INFO0_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_EXCEPTION_INFO0_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_STATUS_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_TEE_EXCP_INFO1_REG(apm_ctrl, apm_m_path) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)) : \ - (HP_APM_M0_EXCEPTION_INFO1_REG + 0x10 * (apm_m_path)); \ - }) - -#define APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms) ((regn_pms) << (4 * (sec_mode - 1))) -#define APM_LL_SEC_MODE_REGION_ATTR_V 0x00000003U -#define APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode) (APM_LL_SEC_MODE_REGION_ATTR_V << (4 * (sec_mode - 1))) - -#define APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_INT_EN_REG) : \ - (HP_APM_INT_EN_REG); \ - }) - -#define APM_CTRL_CLK_EN (BIT(0)) -#define APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_CLOCK_GATE_REG) : \ - (HP_APM_CLOCK_GATE_REG); \ - }) - -#define APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl) \ - ({\ - (LP_APM_CTRL == apm_ctrl) ? (LP_APM_FUNC_CTRL_REG) : \ - (HP_APM_FUNC_CTRL_REG); \ - }) +/* Helper macros for calculating pms attr field position for given security mode */ +#define APM_REGION_PMS_SHIFT(mode) (4U * ((mode) - 1)) +#define APM_REGION_PMS_MASK(mode) (0x07U << APM_REGION_PMS_SHIFT(mode)) +#define APM_REGION_PMS_FIELD(mode, pms) ((pms) << APM_REGION_PMS_SHIFT(mode)) /** - * @brief APM Master ID - */ -typedef enum { - APM_LL_MASTER_HPCORE = 0, - APM_LL_MASTER_LPCORE = 1, - APM_LL_MASTER_REGDMA = 2, - APM_LL_MASTER_SDIOSLV = 3, - APM_LL_MASTER_MODEM = 4, - APM_LL_MASTER_MEM_MONITOR = 5, - APM_LL_MASTER_TRACE = 6, - APM_LL_MASTER_GDMA = 16, // The beginning of GDMA master ID - APM_LL_MASTER_GDMA_SPI2 = 16, - APM_LL_MASTER_GDMA_UHCI0 = 18, - APM_LL_MASTER_GDMA_I2S0 = 19, - APM_LL_MASTER_GDMA_AES = 22, - APM_LL_MASTER_GDMA_SHA = 23, - APM_LL_MASTER_GDMA_ADC = 24, - APM_LL_MASTER_GDMA_PARLIO = 25, -} apm_ll_master_id_t; - -/** - * @brief APM Controller - */ -typedef enum { - LP_APM_CTRL = 0, - HP_APM_CTRL = 1, -} apm_ll_apm_ctrl_t; - -/** - * @brief APM Secure Mode - */ -typedef enum { - APM_LL_SECURE_MODE_TEE = 0, /* Trusted execution environment mode */ - APM_LL_SECURE_MODE_REE0 = 1, /* Rich execution environment mode0 */ - APM_LL_SECURE_MODE_REE1 = 2, /* Rich execution environment mode1 */ - APM_LL_SECURE_MODE_REE2 = 3, /* Rich execution environment mode2 */ -} apm_ll_secure_mode_t; - -/** - * @brief APM Ctrl access path - */ -typedef enum { - APM_CTRL_ACCESS_PATH_M0 = 0x0, - APM_CTRL_ACCESS_PATH_M1 = 0x1, - APM_CTRL_ACCESS_PATH_M2 = 0x2, - APM_CTRL_ACCESS_PATH_M3 = 0x3, -} apm_ll_ctrl_access_path_t; - -/** - * @brief APM Ctrl path. - */ -typedef struct { - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM/HP APM. */ - apm_ll_ctrl_access_path_t apm_m_path; /* APM Ctrl access path M[0:n]. */ -} apm_ctrl_path_t; - -/** - * @brief APM exception information - */ -typedef struct { - apm_ctrl_path_t apm_path; - uint8_t excp_regn; - uint8_t excp_mode; - uint8_t excp_id; - uint8_t excp_type; - uint32_t excp_addr; -} apm_ctrl_exception_info_t; - -/** - * @brief Set secure mode + * @brief Set security mode for a specific master in HP-TEE * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param master_id APM master ID - * @param sec_mode Secure mode + * @param id Master ID + * @param mode Security mode to set */ -static inline void apm_tee_ll_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, - apm_ll_secure_mode_t sec_mode) +static inline void apm_ll_hp_tee_set_master_sec_mode(apm_master_id_t id, apm_security_mode_t mode) { - if (apm_ctrl == HP_APM_CTRL) { - REG_WRITE(TEE_LL_MODE_CTRL_REG(master_id), sec_mode); - } + REG_WRITE(TEE_M0_MODE_CTRL_REG + APM_TEE_MODE_CTRL_OFFSET * id, mode); } /** - * @brief TEE controller clock auto gating enable + * @brief Enable/disable clock gating for HP-TEE * - * @param enable Flag for HP clock auto gating enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_tee_ll_clk_gating_enable(bool enable) +static inline void apm_ll_hp_tee_enable_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); - } else { REG_CLR_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); + } else { + REG_SET_BIT(TEE_CLOCK_GATE_REG, TEE_CLK_EN); } } /** - * @brief enable/disable APM Ctrl Region access permission filter + * @brief Enable/disable controller filter for specific path in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Memory Region number - * @param enable Flag for Region access filter enable/disable + * @param path Access path + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_SET_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } else { - REG_CLR_BIT(APM_CTRL_REGION_FILTER_EN_REG(apm_ctrl), BIT(regn_num)); + REG_CLR_BIT(HP_APM_FUNC_CTRL_REG, BIT(path)); } } /** - * @brief enable/disable APM Ctrl access path(M[0:n]) + * @brief Enable/disable all controller filters in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access path - * @param enable Flag for APM Ctrl M path filter enable/disable + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_hp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(HP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in HP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_region_filter(uint32_t regn_num, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_FUNC_CTRL_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(HP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); } } /** - * @brief APM Ctrl Region start address configuration + * @brief Set region start address in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param addr Region start address + * @param regn_num Region number + * @param addr Start address */ -static inline void apm_ll_apm_ctrl_set_region_start_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) +static inline void apm_ll_hp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) { - REG_WRITE(APM_LL_REGION_ADDR_START_REG(apm_ctrl, regn_num), addr); + REG_WRITE(HP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); } /** - * @brief APM Ctrl Region end address configuration + * @brief Set region end address in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param addr Region end address + * @param regn_num Region number + * @param addr End address */ -static inline void apm_ll_apm_ctrl_set_region_end_address(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, uint32_t addr) +static inline void apm_ll_hp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) { - REG_WRITE(APM_LL_REGION_ADDR_END_REG(apm_ctrl, regn_num), addr); + REG_WRITE(HP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); } /** - * @brief HP Region pms attributes configuration + * @brief Set security mode region attributes in HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param regn_num Region number to be configured - * @param sec_mode Secure mode of the Master - * @param regn_pms XWR permissions for the given secure mode and Region number + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes */ -static inline void apm_ll_apm_ctrl_sec_mode_region_attr_config(apm_ll_apm_ctrl_t apm_ctrl, - uint32_t regn_num, apm_ll_secure_mode_t sec_mode, uint32_t regn_pms) +static inline void apm_ll_hp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) { - uint32_t val = 0; - val = REG_READ(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num)); - val &= ~APM_LL_SEC_MODE_REGION_ATTR_M(sec_mode); - val |= APM_LL_SEC_MODE_REGION_ATTR(sec_mode, regn_pms); - REG_WRITE(APM_LL_REGION_ADDR_ATTR_REG(apm_ctrl, regn_num), val); + uint32_t reg = HP_APM_REGION0_PMS_ATTR_REG + APM_REGION_PMS_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); } /** - * @brief Get APM Ctrl access path(M[0:n]) exception status + * @brief Get exception data (regn, master, security mode) from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access path + * @param path Access path + * @return Exception data */ -static inline uint8_t apm_ll_apm_ctrl_exception_status(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) +static inline uint32_t apm_ll_hp_apm_get_excp_data(apm_ctrl_access_path_t path) { - return REG_READ(APM_LL_APM_CTRL_EXCP_STATUS_REG(apm_ctrl, apm_m_path)); + return REG_READ(HP_APM_M0_EXCEPTION_INFO0_REG + APM_EXCP_INFO_OFFSET * path); } /** - * @brief Clear APM Ctrl access path(M[0:n]) exception + * @brief Get exception status from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param amp_m_path APM Ctrl access path + * @param path Access path + * @return Exception type */ -static inline void apm_ll_apm_ctrl_exception_clear(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path) +static inline uint32_t apm_ll_hp_apm_get_excp_type(apm_ctrl_access_path_t path) { - REG_SET_BIT(APM_LL_APM_CTRL_EXCP_CLR_REG(apm_ctrl, apm_m_path), - APM_CTRL_M_REGION_STATUS_CLR); + return REG_READ(HP_APM_M0_STATUS_REG + APM_EXCP_INFO_OFFSET * path); } /** - * @brief Get APM Ctrl access path(M[0:n]) exception information + * @brief Get exception address from HP-APM * - * @param excp_info Exception related information like addr, - * region, apm_ctrl, apm_m_path, sec_mode and master id + * @param path Access path + * @return Exception address */ -static inline void apm_ll_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info) +static inline uint32_t apm_ll_hp_apm_get_excp_addr(apm_ctrl_access_path_t path) { - excp_info->excp_id = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_ID); - excp_info->excp_mode = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_MODE); - excp_info->excp_regn = REG_GET_FIELD(APM_LL_TEE_EXCP_INFO0_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path), - APM_LL_CTRL_EXCEPTION_REGION); - excp_info->excp_type = apm_ll_apm_ctrl_exception_status(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path); - excp_info->excp_addr = REG_READ(APM_LL_TEE_EXCP_INFO1_REG(excp_info->apm_path.apm_ctrl, excp_info->apm_path.apm_m_path)); + return REG_READ(HP_APM_M0_EXCEPTION_INFO1_REG + APM_EXCP_INFO_OFFSET * path); } /** - * @brief Interrupt enable for APM Ctrl at access path(M[0:n]) + * @brief Get exception information from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - * @param enable Flag for access path interrupt enable/disable + * @param path Access path + * @param info Pointer to store exception information */ -static inline void apm_ll_apm_ctrl_interrupt_enable(apm_ll_apm_ctrl_t apm_ctrl, - apm_ll_ctrl_access_path_t apm_m_path, bool enable) +static inline void apm_ll_hp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + hp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_hp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_hp_apm_get_excp_type(path); + info->addr = apm_ll_hp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in HP-APM + * + * @param path Access path + */ +static inline void apm_ll_hp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + REG_SET_BIT(HP_APM_M0_STATUS_CLR_REG + APM_EXCP_INFO_OFFSET * path, APM_EXCP_STATUS_CLR_BIT); +} + +/** + * @brief Enable/disable controller interrupt in HP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_SET_BIT(HP_APM_INT_EN_REG, BIT(path)); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_INT_EN_REG(apm_ctrl), BIT(apm_m_path)); + REG_CLR_BIT(HP_APM_INT_EN_REG, BIT(path)); } } /** - * @brief APM Ctrl clock auto gating enable + * @brief Get controller interrupt source number from HP-APM * - * @param apm_ctrl APM Ctrl (LP_APM/HP_APM) - * @param enable Flag for HP clock auto gating enable/disable + * @param path Access path + * @return Interrupt source number */ -static inline void apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable) +static inline int apm_ll_hp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + return ETS_HP_APM_M0_INTR_SOURCE + path; +} + +/** + * @brief Enable/disable controller clock gating in HP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_hp_apm_enable_ctrl_clk_gating(bool enable) { if (enable) { - REG_SET_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_CLR_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); } else { - REG_CLR_BIT(APM_LL_APM_CTRL_CLOCK_GATE_REG(apm_ctrl), APM_CTRL_CLK_EN); + REG_SET_BIT(HP_APM_CLOCK_GATE_REG, HP_APM_CLK_EN); } } /** - * @brief APM/TEE/HP System Reg reset event bypass enable + * @brief Enable/disable controller filter for specific path in LP-APM * - * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, - * but also some reset events. - * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. - * Some reset events will be bypassed. - * - * @param enable Flag for event bypass enable/disable + * @param path Access path + * @param enable True to enable, false to disable */ -static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) +static inline void apm_ll_lp_apm_enable_ctrl_filter(apm_ctrl_access_path_t path, bool enable) +{ + (void)path; + if (enable) { + REG_SET_BIT(LP_APM_FUNC_CTRL_REG, LP_APM_M0_PMS_FUNC_EN); + } else { + REG_CLR_BIT(LP_APM_FUNC_CTRL_REG, LP_APM_M0_PMS_FUNC_EN); + } +} + +/** + * @brief Enable/disable all controller filters in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_filter_all(bool enable) +{ + REG_WRITE(LP_APM_FUNC_CTRL_REG, enable ? UINT32_MAX : 0); +} + +/** + * @brief Enable/disable region filter in LP-APM + * + * @param regn_num Region number + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_region_filter(uint32_t regn_num, bool enable) +{ + if (enable) { + REG_SET_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } else { + REG_CLR_BIT(LP_APM_REGION_FILTER_EN_REG, BIT(regn_num)); + } +} + +/** + * @brief Set region start address in LP-APM + * + * @param regn_num Region number + * @param addr Start address + */ +static inline void apm_ll_lp_apm_set_region_start_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_START_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set region end address in LP-APM + * + * @param regn_num Region number + * @param addr End address + */ +static inline void apm_ll_lp_apm_set_region_end_addr(uint32_t regn_num, uint32_t addr) +{ + REG_WRITE(LP_APM_REGION0_ADDR_END_REG + APM_REGION_ADDR_OFFSET * regn_num, addr); +} + +/** + * @brief Set security mode region attributes in LP-APM + * + * @param regn_num Region number + * @param mode Security mode + * @param regn_pms Region PMS attributes + */ +static inline void apm_ll_lp_apm_set_sec_mode_region_attr(uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms) +{ + uint32_t reg = LP_APM_REGION0_PMS_ATTR_REG + APM_REGION_PMS_ATTR_OFFSET * regn_num; + uint32_t val = REG_READ(reg); + val &= ~APM_REGION_PMS_MASK(mode); + val |= APM_REGION_PMS_FIELD(mode, regn_pms); + REG_WRITE(reg, val); +} + +/** + * @brief Get exception data (regn, master, security mode) from LP-APM + * + * @param path Access path + * @return Exception data + */ +static inline uint32_t apm_ll_lp_apm_get_excp_data(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_EXCEPTION_INFO0_REG); +} + +/** + * @brief Get exception status from LP-APM + * + * @param path Access path + * @return Exception type + */ +static inline uint32_t apm_ll_lp_apm_get_excp_type(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_STATUS_REG); +} + +/** + * @brief Get exception address from LP-APM + * + * @param path Access path + * @return Exception address + */ +static inline uint32_t apm_ll_lp_apm_get_excp_addr(apm_ctrl_access_path_t path) +{ + (void)path; + return REG_READ(LP_APM_M0_EXCEPTION_INFO1_REG); +} + +/** + * @brief Get exception information from LP-APM + * + * @param path Access path + * @param info Pointer to store exception information + */ +static inline void apm_ll_lp_apm_get_excp_info(apm_ctrl_access_path_t path, apm_ctrl_exception_info_t *info) +{ + lp_apm_m0_exception_info0_reg_t reg; + reg.val = apm_ll_lp_apm_get_excp_data(path); + info->regn = reg.m0_exception_region; + info->mode = reg.m0_exception_mode; + info->id = reg.m0_exception_id; + + info->type = apm_ll_lp_apm_get_excp_type(path); + info->addr = apm_ll_lp_apm_get_excp_addr(path); +} + +/** + * @brief Clear controller exception status in LP-APM + * + * @param path Access path + */ +static inline void apm_ll_lp_apm_clear_ctrl_excp_status(apm_ctrl_access_path_t path) +{ + (void)path; + REG_SET_BIT(LP_APM_M0_STATUS_CLR_REG, LP_APM_M0_REGION_STATUS_CLR); +} + +/** + * @brief Enable/disable controller interrupt in LP-APM + * + * @param path Access path + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_intr(apm_ctrl_access_path_t path, bool enable) +{ + (void)path; + if (enable) { + REG_SET_BIT(LP_APM_INT_EN_REG, LP_APM_M0_APM_INT_EN); + } else { + REG_CLR_BIT(LP_APM_INT_EN_REG, LP_APM_M0_APM_INT_EN); + } +} + +/** + * @brief Enable/disable controller clock gating in LP-APM + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_lp_apm_enable_ctrl_clk_gating(bool enable) +{ + if (enable) { + REG_CLR_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } else { + REG_SET_BIT(LP_APM_CLOCK_GATE_REG, LP_APM_CLK_EN); + } +} + +/** + * @brief Get controller interrupt source number from LP-APM + * + * @param path Access path + * @return Interrupt source number + */ +static inline int apm_ll_lp_apm_get_ctrl_intr_src(apm_ctrl_access_path_t path) +{ + (void)path; + return ETS_LP_APM_M0_INTR_SOURCE; +} + +/** + * @brief Enable/disable APM reset event bypass + * + * @param enable True to enable, false to disable + */ +static inline void apm_ll_enable_reset_event_bypass(bool enable) { if (enable) { REG_SET_BIT(PCR_RESET_EVENT_BYPASS_REG, PCR_RESET_EVENT_BYPASS_APM); @@ -386,24 +432,6 @@ static inline void apm_ll_apm_ctrl_reset_event_enable(bool enable) } } -/** - * @brief Fetch the APM Ctrl interrupt source number. - * - * @param apm_ctrl APM Ctrl (LP_APM0/HP_APM/LP_APM) - * @param apm_m_path APM Ctrl access patch(M[0:n]) - */ -static inline int apm_ll_apm_ctrl_get_int_src_num(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_ctrl_access_path_t apm_m_path) -{ - switch (apm_ctrl) { - case HP_APM_CTRL : - return (ETS_HP_APM_M0_INTR_SOURCE + apm_m_path); - case LP_APM_CTRL : - return (ETS_LP_APM_M0_INTR_SOURCE + apm_m_path); - } - - return -1; -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h21/include/hal/spi_ll.h b/components/hal/esp32h21/include/hal/spi_ll.h index dbbaa0d50a..c4e7caba82 100644 --- a/components/hal/esp32h21/include/hal/spi_ll.h +++ b/components/hal/esp32h21/include/hal/spi_ll.h @@ -6,8 +6,8 @@ /******************************************************************************* * NOTICE - * The LL layer for SPI register operations - * Not public api, don't use in application code. + * The LL layer for ESP32H21 SPI register operations + * It is NOT public api, don't use in application code. ******************************************************************************/ #pragma once @@ -162,6 +162,10 @@ static inline void spi_ll_master_init(spi_dev_t *hw) hw->user.usr_miso_highpart = 0; hw->user.usr_mosi_highpart = 0; + //Disable unused error_end condition + hw->user1.mst_wfull_err_end_en = 0; + hw->user2.mst_rempty_err_end_en = 0; + //Disable unneeded ints hw->slave.val = 0; hw->user.val = 0; diff --git a/components/hal/esp32p4/include/hal/key_mgr_ll.h b/components/hal/esp32p4/include/hal/key_mgr_ll.h index 3aa13bc363..d7fb6e8f93 100644 --- a/components/hal/esp32p4/include/hal/key_mgr_ll.h +++ b/components/hal/esp32p4/include/hal/key_mgr_ll.h @@ -19,6 +19,7 @@ #include "hal/key_mgr_types.h" #include "soc/keymng_reg.h" #include "soc/hp_sys_clkrst_struct.h" +#include "esp_private/esp_crypto_lock_internal.h" #ifdef __cplusplus extern "C" { @@ -149,7 +150,8 @@ static inline void key_mgr_ll_use_sw_init_key(void) static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) { REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA); } else { @@ -173,7 +175,8 @@ static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_typ static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type) { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA)); break; @@ -207,20 +210,38 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void) static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type) { switch(key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA); break; case ESP_KEY_MGR_XTS_AES_128_KEY: case ESP_KEY_MGR_XTS_AES_256_KEY: REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_XTS); break; + default: + HAL_ASSERT(false && "Unsupported key type"); + return; } } /* @brief Configure the key purpose to be used by the Key Manager for key generator operation */ static inline void key_mgr_ll_set_key_purpose(const esp_key_mgr_key_purpose_t key_purpose) { - REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, key_purpose); + switch(key_purpose) { + case ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192: + case ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256: + REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_ECDSA); + break; + case ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1: + REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_XTS_AES_256_1); + break; + case ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2: + REG_SET_FIELD(KEYMNG_CONF_REG, KEYMNG_KEY_PURPOSE, KEYMNG_KEY_PURPOSE_XTS_AES_256_2); + break; + default: + HAL_ASSERT(false && "Unsupported mode"); + return; + } } /** @@ -250,7 +271,8 @@ static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type { switch (key_type) { - case ESP_KEY_MGR_ECDSA_KEY: + case ESP_KEY_MGR_ECDSA_192_KEY: + case ESP_KEY_MGR_ECDSA_256_KEY: return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_VLD); break; diff --git a/components/hal/hmac_hal.c b/components/hal/hmac_hal.c index 59dcc1f945..99bb565863 100644 --- a/components/hal/hmac_hal.c +++ b/components/hal/hmac_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,11 @@ #include "stdio.h" #include "hal/hmac_hal.h" #include "hal/hmac_ll.h" +#include "soc/soc_caps.h" + +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY +#include "hal/key_mgr_hal.h" +#endif void hmac_hal_start(void) { @@ -18,6 +23,20 @@ uint32_t hmac_hal_configure(hmac_hal_output_t config, uint32_t key_id) { hmac_ll_wait_idle(); hmac_ll_config_output(config); + +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY + if (key_id == HMAC_KEY_KM) { + if (config == HMAC_OUTPUT_USER) { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_HMAC_KEY, ESP_KEY_MGR_USE_OWN_KEY); + } else { + // No other HMAC output type is allowed when using key manager + return 1; + } + } else { + key_mgr_hal_set_key_usage(ESP_KEY_MGR_HMAC_KEY, ESP_KEY_MGR_USE_EFUSE_KEY); + } +#endif + hmac_ll_config_hw_key_id(key_id); hmac_ll_config_finish(); hmac_ll_wait_idle(); diff --git a/components/hal/huk_hal.c b/components/hal/huk_hal.c index 70aa576459..c9f9e51399 100644 --- a/components/hal/huk_hal.c +++ b/components/hal/huk_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -13,6 +13,7 @@ #include "hal/log.h" #include "rom/km.h" #include "esp_err.h" +#include "soc/soc_caps.h" esp_huk_state_t huk_hal_get_state(void) { @@ -28,11 +29,11 @@ static void inline huk_hal_wait_for_state(esp_huk_state_t state) esp_err_t huk_hal_configure(const esp_huk_mode_t huk_mode, uint8_t *huk_info_buf) { - if (esp_rom_km_huk_conf(huk_mode, huk_info_buf) == ETS_OK) { - return ESP_OK; - } else { + if (esp_rom_km_huk_conf(huk_mode, huk_info_buf) != ETS_OK) { return ESP_FAIL; } + + return ESP_OK; } uint8_t huk_hal_get_risk_level(void) @@ -44,3 +45,10 @@ uint32_t huk_hal_get_date_info(void) { return huk_ll_get_date_info(); } + +#if SOC_HUK_MEM_NEEDS_RECHARGE +void huk_hal_recharge_huk_memory(void) +{ + huk_ll_recharge_huk_memory(); +} +#endif diff --git a/components/hal/include/hal/apm_hal.h b/components/hal/include/hal/apm_hal.h index 6f95b26af4..9e636c8a0c 100644 --- a/components/hal/include/hal/apm_hal.h +++ b/components/hal/include/hal/apm_hal.h @@ -9,10 +9,12 @@ extern "C" { #endif +#include #include "esp_err.h" #include "soc/soc_caps.h" #if SOC_APM_SUPPORTED #include "hal/apm_ll.h" +#include "hal/apm_types.h" #if CONFIG_IDF_TARGET_ESP32P4 @@ -102,158 +104,261 @@ void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data); #else /** - * @brief Region configuration data. + * @brief Helper macro to create a region entry configuration + * + */ +#define APM_HAL_REGION_ENTRY_BASE(PATH,NUM, START, END, PMS) \ + .path_id = (PATH), \ + .regn_num = (NUM), \ + .regn_start_addr = ((START) & ~0x03U), \ + .regn_end_addr = (((END) - 1U) & ~0x03U), \ + .regn_pms = (PMS), \ + .filter_en = true + + +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK +#define APM_HAL_REGION_ENTRY(PATH, NUM, START, END, PMS, LOCK) \ + { APM_HAL_REGION_ENTRY_BASE(PATH, NUM, START, END, PMS), .lock_en = LOCK } +#else +#define APM_HAL_REGION_ENTRY(PATH, NUM, START, END, PMS) \ + { APM_HAL_REGION_ENTRY_BASE(PATH, NUM, START, END, PMS) } +#endif + +/** + * @brief Helper macro to create a security mode configuration + * + */ +#define APM_HAL_SEC_MODE_CFG(CTRL_MOD, MODE, REGNS) \ + { \ + .ctrl_mod = (CTRL_MOD), \ + .mode = (MODE), \ + .regn_count = sizeof(REGNS) / sizeof((REGNS)[0]), \ + .regions = (REGNS), \ + } + +/** + * @brief APM controller info structure */ typedef struct { - uint32_t regn_num; /* Address Region number cover by this configuration data. */ - uint32_t regn_start_addr; /* Address Region start address. */ - uint32_t regn_end_addr; /* Address Region end address. */ - uint32_t regn_pms; /* Access Permission for Master in different secure mode. */ - bool filter_enable; /* Address Region Filter enable/disable. */ - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */ - apm_ll_secure_mode_t sec_mode; /* Master secure mode: TEE/REE[0-2].*/ -} apm_ctrl_region_config_data_t; + apm_ctrl_module_t ctrl_mod; /*!< APM controller module */ + apm_ctrl_access_path_t path; /*!< Access path */ +} apm_hal_ctrl_info_t; /** - * @brief Secure mode(TEE/REE[0:2] configuration data. + * @brief APM region configuration structure */ typedef struct { - apm_ll_apm_ctrl_t apm_ctrl; /* APM Ctrl: LP APM0/HP APM/LP APM. */ - apm_ll_secure_mode_t sec_mode; /* Secure mode to be configured TEE/REE[0:2]. */ - uint8_t apm_m_cnt; /* Access path M count. */ - uint32_t regn_count; /* Access Ctrl region count. */ - uint32_t master_ids; /* Bit mask for masters to be part of this secure mode. */ - apm_ctrl_region_config_data_t *pms_data; /* Region configuration data. */ -} apm_ctrl_secure_mode_config_t; + apm_ctrl_access_path_t path_id; /*!< Path identifier */ + uint32_t regn_num; /*!< Region number */ + uint32_t regn_start_addr; /*!< Region start address */ + uint32_t regn_end_addr; /*!< Region end address */ + uint32_t regn_pms; /*!< Region permissions */ + bool filter_en; /*!< Filter enable flag */ +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK + bool lock_en; /*!< Lock enable flag */ +#endif +} apm_hal_ctrl_region_cfg_t; /** - * @brief Set secure mode - * - * @param apm_ctrl APM Ctrl to be configured - * @param master_id APM master ID - * @param sec_mode Secure mode + * @brief APM security mode configuration structure */ -void apm_tee_hal_set_master_secure_mode(apm_ll_apm_ctrl_t apm_ctrl, apm_ll_master_id_t master_id, - apm_ll_secure_mode_t sec_mode); +typedef struct { + apm_ctrl_module_t ctrl_mod; /*!< APM controller module */ + apm_security_mode_t mode; /*!< Security mode */ + uint32_t regn_count; /*!< Number of regions */ + apm_hal_ctrl_region_cfg_t *regions; /*!< Array of region configurations */ +} apm_hal_ctrl_sec_mode_cfg_t; /** - * @brief Set all masters to a given secure mode + * @brief Set security mode for specified masters * - * @param sec_mode Secure mode + * @param master_mask Mask of masters to configure + * @param mode Security mode to set */ -void apm_tee_hal_set_master_secure_mode_all(apm_ll_secure_mode_t sec_mode); +void apm_hal_set_master_sec_mode(uint32_t master_mask, apm_security_mode_t mode); /** - * @brief TEE controller clock auto gating enable + * @brief Set security mode for all masters * - * @param enable Flag for HP clock auto gating enable/disable + * @param mode Security mode to set */ -void apm_tee_hal_clk_gating_enable(bool enable); +void apm_hal_set_master_sec_mode_all(apm_security_mode_t mode); + +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK +/** + * @brief Lock security mode for specified masters + * + * @param master_mask Mask of masters to configure + */ +void apm_hal_lock_master_sec_mode(uint32_t master_mask); /** - * @brief enable/disable APM Ctrl Region access permission filter + * @brief Lock security mode for all masters * - * @param apm_ctrl APM Ctrl to be configured - * @param regn_num Memory Region number - * @param enable Flag for Region access filter enable/disable */ -void apm_hal_apm_ctrl_region_filter_enable(apm_ll_apm_ctrl_t apm_ctrl, uint32_t regn_num, bool enable); +void apm_hal_lock_master_sec_mode_all(void); +#endif + +#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL +/** + * @brief Set access permissions for the specified peripherals in the given TEE ctrl module + * + * @param ctrl_mod TEE ctrl module + * @param periph_mask Peripheral mask + * @param mode Security mode + * @param pms Access permissions + */ +void apm_hal_tee_set_peri_access(apm_tee_ctrl_module_t ctrl_mod, uint64_t periph_mask, apm_security_mode_t mode, apm_perm_t pms); /** - * @brief enable/disable APM Ctrl access path(M[0:n]) + * @brief Set access permissions for all peripherals in the given TEE ctrl module * - * @param apm_path APM controller and access path to be configured - * @param enable Flag for M path filter enable/disable + * @param ctrl_mod TEE ctrl module + * @param mode Security mode + * @param pms Access permissions */ -void apm_hal_apm_ctrl_filter_enable(apm_ctrl_path_t *apm_path, bool enable); +void apm_hal_tee_set_peri_access_all(apm_tee_ctrl_module_t ctrl_mod, apm_security_mode_t mode, apm_perm_t pms); +#endif /** - * @brief enable/disable all available APM Ctrl access path(M[0:n]) + * @brief Enable/disable TEE clock gating for a APM controller module * - * @param enable Flag for M path filter enable/disable + * @param ctrl_mod TEE controller module + * @param enable True to enable, false to disable */ -void apm_hal_apm_ctrl_filter_enable_all(bool enable); +void apm_hal_tee_enable_clk_gating(apm_tee_ctrl_module_t ctrl_mod, bool enable); /** - * @brief Region configuration + * @brief Enable/disable controller filter for specific path * - * @param pms_data Region configuration data + * @param ctrl_mod APM controller module + * @param path Access path + * @param enable True to enable, false to disable */ -void apm_hal_apm_ctrl_region_config(const apm_ctrl_region_config_data_t *pms_data); +void apm_hal_enable_ctrl_filter(apm_ctrl_module_t ctrl_mod, apm_ctrl_access_path_t path, bool enable); /** - * @brief Get APM Ctrl access path(M[0:n]) exception status + * @brief Enable/disable all controller filters * - * @param apm_path APM controller and access path to be configured + * @param enable True to enable, false to disable */ -uint8_t apm_hal_apm_ctrl_exception_status(apm_ctrl_path_t *apm_path); +void apm_hal_enable_ctrl_filter_all(bool enable); /** - * @brief Clear APM Ctrl access path(M[0:n]) exception + * @brief Enable/disable region filter * - * @param apm_path APM controller and access path to be configured + * @param ctrl_mod APM controller module + * @param regn_num Region number + * @param enable True to enable, false to disable */ -void apm_hal_apm_ctrl_exception_clear(apm_ctrl_path_t *apm_path); +void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable); /** - * @brief Get APM Ctrl access path exception information + * @brief Set the start address for the given region * - * @param excp_info Exception related information like addr, - * region, amp_ctrl, apm_m_path, sec_mode and master id + * @param ctrl_mod APM controller module + * @param regn_num Region number + * @param addr Address */ -void apm_hal_apm_ctrl_get_exception_info(apm_ctrl_exception_info_t *excp_info); +void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr); /** - * @brief APM Ctrl interrupt enable for access path(M[0:n]) + * @brief Set the end address for the given region * - * @param apm_path APM controller and access path to be configured - * @param enable Flag for access path interrupt enable/disable + * @param ctrl_mod APM controller module + * @param regn_num Region number + * @param addr Address */ -void apm_hal_apm_ctrl_interrupt_enable(apm_ctrl_path_t *apm_path, bool enable); +void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr); /** - * @brief APM Ctrl clock auto gating enable + * @brief Set the permissions for the specified security mode for the given region * - * @apm_ctrl APM Ctrl - * @param enable Flag for HP clock auto gating enable/disable + * @param ctrl_mod APM controller module + * @param regn_num Region number + * @param mode Security mode */ -void apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable); +void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms); /** - * @brief TEE/REE execution environment configuration. + * @brief Set region filter configuration * - * This API will be called from TEE mode initialization code which is - * responsible to setup TEE/REE execution environment. - * It includes, allocation of all bus masters, memory ranges and other - * peripherals to the given secure mode. - * All this information should be passed by the TEE mode initialization code. - * - * @sec_mode_data APM Ctl configuration data. + * @param ctrl_mod APM controller module + * @param mode Security mode + * @param regn_cfg Region configuration */ -void apm_hal_apm_ctrl_master_sec_mode_config(apm_ctrl_secure_mode_config_t *sec_mode_data); +void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg); + +#if SOC_APM_SUPPORT_CTRL_CFG_LOCK +/** + * @brief Lock region filter configuration + * + * @param ctrl_mod APM controller module + * @param regn_num Region number + */ +void apm_hal_lock_region_filter_cfg(apm_ctrl_module_t ctrl_mod, uint32_t regn_num); +#endif /** - * @brief APM/TEE/HP System Reg reset event bypass enable + * @brief Set controller security mode configuration * - * Disable: tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, - * but also some reset events. - * Enable: tee_reg/apm_reg/hp_system_reg will only be reset by power-reset. - * Some reset events will be bypassed. - * - * @param enable Flag for event bypass enable/disable + * @param cfg Security mode configuration */ -void apm_hal_apm_ctrl_reset_event_enable(bool enable); +void apm_hal_set_ctrl_sec_mode_cfg(const apm_hal_ctrl_sec_mode_cfg_t *cfg); /** - * @brief Fetch the APM Ctrl access path interrupt source number. + * @brief Get exception type * - * @param apm_path APM controller and access path to be configured - * - * @return - * - valid interrupt source number on success - * - -1: invalid interrupt source + * @param ctrl_info Controller information + * @return Exception type */ -int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); +uint32_t apm_hal_get_exception_type(apm_hal_ctrl_info_t *ctrl_info); + +/** + * @brief Clear exception status + * + * @param ctrl_info Controller information + */ +void apm_hal_clear_exception_status(apm_hal_ctrl_info_t *ctrl_info); + +/** + * @brief Get exception information + * + * @param ctrl_info Controller information + * @param excp_info Exception information structure to fill + */ +void apm_hal_get_exception_info(apm_hal_ctrl_info_t *ctrl_info, apm_ctrl_exception_info_t *excp_info); + +/** + * @brief Enable/disable interrupt + * + * @param ctrl_info Controller information + * @param enable True to enable, false to disable + */ +void apm_hal_enable_intr(apm_hal_ctrl_info_t *ctrl_info, bool enable); + +/** + * @brief Get interrupt source number + * + * @param ctrl_info Controller information + * @return Interrupt source number + */ +int apm_hal_get_intr_src_num(apm_hal_ctrl_info_t *ctrl_info); + +/** + * @brief Enable/disable reset event bypass + * + * @param enable True to enable, false to disable + */ +void apm_hal_enable_reset_event_bypass(bool enable); + +/** + * @brief Enable/disable controller clock gating + * + * @param ctrl_mod APM controller module + * @param enable True to enable, false to disable + */ +void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable); #endif //CONFIG_IDF_TARGET_ESP32P4 @@ -261,14 +366,14 @@ int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path); #if CONFIG_IDF_TARGET_ESP32H4 #include "soc/hp_apm_reg.h" -#define apm_hal_apm_ctrl_filter_enable_all(en) \ +#define apm_hal_enable_ctrl_filter_all(en) \ REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); #else #include "soc/hp_apm_reg.h" #include "soc/lp_apm_reg.h" #include "soc/lp_apm0_reg.h" -#define apm_hal_apm_ctrl_filter_enable_all(en) \ +#define apm_hal_enable_ctrl_filter_all(en) \ REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ REG_WRITE(LP_APM0_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \ REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); diff --git a/components/hal/include/hal/apm_types.h b/components/hal/include/hal/apm_types.h index 26a474faf8..b01633c3f7 100644 --- a/components/hal/include/hal/apm_types.h +++ b/components/hal/include/hal/apm_types.h @@ -1,22 +1,121 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include +#include "soc/soc_caps.h" + #ifdef __cplusplus extern "C" { #endif /** - * @brief APM Region PMS authority + * @brief Master IDs for APM */ typedef enum { - APM_REGION_PMS_X = 0x1, /*!< Region executive authority. */ - APM_REGION_PMS_W = 0x2, /*!< Region write authority. */ - APM_REGION_PMS_R = 0x4, /*!< Region read authority. */ -} apm_region_pms_t; + APM_MASTER_HPCORE = 0, /*!< HP CPU */ +#if SOC_LP_CORE_SUPPORTED + APM_MASTER_LPCORE = 1, /*!< LP CPU */ +#endif /* SOC_LP_CORE_SUPPORTED */ + APM_MASTER_REGDMA = 2, +#if SOC_SDIO_SLAVE_SUPPORTED + APM_MASTER_SDIOSLV = 3, /*!< SDIO slave */ +#endif /* SOC_SDIO_SLAVE_SUPPORTED */ + APM_MASTER_MODEM = 4, /*!< Modem */ + APM_MASTER_MEM_MON = 5, /*!< Memory monitor */ + APM_MASTER_TRACE = 6, /*!< Trace */ +#if SOC_SPIRAM_SUPPORTED + APM_MASTER_PSRAM_MEM_MON = 8, /*!< PSRAM memory monitor */ +#endif /* SOC_SPIRAM_SUPPORTED */ +#if SOC_GPSPI_SUPPORTED && SOC_AHB_GDMA_VERSION == 1 + APM_MASTER_GDMA_GPSPI = 16, /*!< GDMA for GPSPI/SPI2 */ +#elif SOC_GPSPI_SUPPORTED && SOC_AHB_GDMA_VERSION == 2 + APM_MASTER_GDMA_GPSPI = 17, +#endif /* SOC_GPSPI_SUPPORTED */ +#if SOC_UHCI_SUPPORTED + APM_MASTER_GDMA_UHCI = 18, /*!< GDMA for UHCI */ +#endif /* SOC_UHCI_SUPPORTED */ + APM_MASTER_GDMA_I2S = 19, /*!< GDMA for I2S */ +#if SOC_AES_SUPPORTED + APM_MASTER_GDMA_AES = 22, /*!< GDMA for AES */ +#endif /* SOC_AES_SUPPORTED */ + APM_MASTER_GDMA_SHA = 23, /*!< GDMA for SHA */ + APM_MASTER_GDMA_ADC = 24, /*!< GDMA for ADC */ +#if SOC_PARLIO_SUPPORTED + APM_MASTER_GDMA_PARLIO = 25, /*!< GDMA for PARLIO */ +#endif /* SOC_PARLIO_SUPPORTED */ + APM_MASTER_MAX = 32, /*!< Maximum master ID */ +} apm_master_id_t; + +/** + * @brief APM controller modules + */ +typedef enum { + APM_CTRL_HP_APM = 0, /*!< High-performance APM controller */ +#if SOC_APM_LP_APM0_SUPPORTED + APM_CTRL_LP_APM0, /*!< Low-power APM0 controller */ +#endif + APM_CTRL_LP_APM, /*!< Low-power APM controller */ +#if SOC_APM_CPU_APM_SUPPORTED + APM_CTRL_CPU_APM, /*!< CPU APM controller */ +#endif +} apm_ctrl_module_t; + +/** + * @brief TEE controller modules + */ +typedef enum { + APM_TEE_CTRL_HP = 0, /*!< High-performance TEE controller */ +#if SOC_APM_SUPPORT_LP_TEE_CTRL + APM_TEE_CTRL_LP = 1, /*!< Low-power TEE controller */ +#endif +} apm_tee_ctrl_module_t; + +/** + * @brief APM controller access paths + */ +typedef enum { + APM_CTRL_ACCESS_PATH_M0 = 0, /*!< Access path M0 */ + APM_CTRL_ACCESS_PATH_M1 = 1, /*!< Access path M1 */ + APM_CTRL_ACCESS_PATH_M2 = 2, /*!< Access path M2 */ + APM_CTRL_ACCESS_PATH_M3 = 3, /*!< Access path M3 */ + APM_CTRL_ACCESS_PATH_M4 = 4, /*!< Access path M4 */ +} apm_ctrl_access_path_t; + +/** + * @brief Security modes for APM + */ +typedef enum { + APM_SEC_MODE_TEE = 0, /*!< Trusted Execution Environment mode */ + APM_SEC_MODE_REE0 = 1, /*!< Rich Execution Environment mode 0 */ + APM_SEC_MODE_REE1 = 2, /*!< Rich Execution Environment mode 1 */ + APM_SEC_MODE_REE2 = 3, /*!< Rich Execution Environment mode 2 */ +} apm_security_mode_t; + +/** + * @brief Access permission flags + */ +typedef enum { + APM_PERM_NONE = 0, /*!< No permissions */ + APM_PERM_X = 1, /*!< Execute */ + APM_PERM_W = 2, /*!< Write */ + APM_PERM_R = 4, /*!< Read */ + APM_PERM_ALL = 7, /*!< All access */ +} apm_perm_t; + +/** + * @brief APM controller exception info structure + */ +typedef struct { + uint32_t regn; /*!< Region number */ + uint32_t mode; /*!< Security mode */ + uint32_t id; /*!< Master ID */ + uint32_t type; /*!< Exception type */ + uint32_t addr; /*!< Exception address */ +} apm_ctrl_exception_info_t; #ifdef __cplusplus } diff --git a/components/hal/include/hal/ds_hal.h b/components/hal/include/hal/ds_hal.h index bf9a18df5d..766854d8b9 100644 --- a/components/hal/include/hal/ds_hal.h +++ b/components/hal/include/hal/ds_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -15,6 +15,7 @@ #include #include #include +#include "soc/soc_caps.h" #include "hal/ds_types.h" #ifdef __cplusplus @@ -38,6 +39,13 @@ void ds_hal_finish(void); */ void ds_hal_configure_iv(const uint32_t *iv); +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +/** + * @brief Set the DS key source. + */ +void ds_hal_set_key_source(ds_key_source_t key_source); +#endif + /** * @brief Write the message which should be signed. * diff --git a/components/hal/include/hal/ds_types.h b/components/hal/include/hal/ds_types.h index f739a11b66..7734a6fae1 100644 --- a/components/hal/include/hal/ds_types.h +++ b/components/hal/include/hal/ds_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,8 @@ extern "C" { #endif +#include "soc/soc_caps.h" + /** * The result when checking whether the key to decrypt the RSA parameters is ready. */ @@ -25,6 +27,13 @@ typedef enum { DS_SIGNATURE_PADDING_AND_MD_FAIL = 3, /**< Both padding and MD check failed. */ } ds_signature_check_t; +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +typedef enum { + DS_KEY_SOURCE_EFUSE = 0, + DS_KEY_SOURCE_KEY_MGR = 1, +} ds_key_source_t; +#endif + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/hmac_types.h b/components/hal/include/hal/hmac_types.h index af309b3fe5..5be28942d6 100644 --- a/components/hal/include/hal/hmac_types.h +++ b/components/hal/include/hal/hmac_types.h @@ -1,14 +1,31 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once +#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { #endif +/** + * The possible efuse keys for the HMAC peripheral + */ +typedef enum { + HMAC_KEY0 = 0, + HMAC_KEY1, + HMAC_KEY2, + HMAC_KEY3, + HMAC_KEY4, + HMAC_KEY5, +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY + HMAC_KEY_KM = 7, +#endif + HMAC_KEY_MAX = 8, +} hmac_key_id_t; + /** * The HMAC peripheral can be configured to deliver its output to the user directly, or to deliver * the output directly to another peripheral instead, e.g. the Digital Signature peripheral. diff --git a/components/hal/include/hal/huk_hal.h b/components/hal/include/hal/huk_hal.h index e158f1fc66..3bdd04c896 100644 --- a/components/hal/include/hal/huk_hal.h +++ b/components/hal/include/hal/huk_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include "soc/soc_caps.h" -#if SOC_KEY_MANAGER_SUPPORTED +#if SOC_HUK_SUPPORTED #include "hal/huk_types.h" #include #include "esp_err.h" @@ -51,6 +51,13 @@ uint8_t huk_hal_get_risk_level(void); */ uint32_t huk_hal_get_date_info(void); +#if SOC_HUK_MEM_NEEDS_RECHARGE +/** + * @brief Recharge HUK memory + */ +void huk_hal_recharge_huk_memory(void); +#endif + #ifdef __cplusplus } #endif diff --git a/components/hal/include/hal/huk_types.h b/components/hal/include/hal/huk_types.h index 8812fe6f2f..a0f6319313 100644 --- a/components/hal/include/hal/huk_types.h +++ b/components/hal/include/hal/huk_types.h @@ -11,12 +11,12 @@ #include "esp_assert.h" #include "rom/km.h" +#include "rom/key_mgr.h" #ifdef __cplusplus extern "C" { #endif -#define HUK_INFO_SIZE 384 #define HUK_RISK_ALERT_LEVEL 4 /** @@ -35,7 +35,7 @@ ESP_STATIC_ASSERT(sizeof(esp_huk_mode_t) == sizeof(huk_mode_t), "Size of esp_huk */ typedef enum { ESP_HUK_STATE_IDLE = 0, /* Key Manager is idle */ - ESP_HUK_STATE_LOAD, /* Key Manager is read to recieve input */ + ESP_HUK_STATE_LOAD, /* Key Manager is read to receive input */ ESP_HUK_STATE_GAIN, /* Key Manager is ready to provide output */ ESP_HUK_STATE_BUSY /* Key Manager is busy */ } esp_huk_state_t; diff --git a/components/hal/include/hal/key_mgr_hal.h b/components/hal/include/hal/key_mgr_hal.h index 8a3ca092dc..8434601a5d 100644 --- a/components/hal/include/hal/key_mgr_hal.h +++ b/components/hal/include/hal/key_mgr_hal.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -111,11 +111,11 @@ void key_mgr_hal_write_public_info(const uint8_t *public_info_buf, const size_t */ void key_mgr_hal_read_public_info(uint8_t *public_info_buf, const size_t read_len); -/* @brief Set the AES-XTS key length for the Key Manager */ -void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_xts_aes_key_len_t key_len); +/* @brief Set the XTS-AES key length for the Key Manager */ +void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len); -/* @brief Get the AES-XTS key length for the Key Manager */ -esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_aes_xts_key_len(void); +/* @brief Get the XTS-AES key length for the Key Manager */ +esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type); /** * @brief Read state of Key Manager diff --git a/components/hal/include/hal/key_mgr_types.h b/components/hal/include/hal/key_mgr_types.h index 31ea39aeb4..550b333621 100644 --- a/components/hal/include/hal/key_mgr_types.h +++ b/components/hal/include/hal/key_mgr_types.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,17 +30,31 @@ typedef enum { * @brief Length of the XTS AES key */ typedef enum { - ESP_KEY_MGR_XTS_AES_LEN_256 = 0, /* xts-aes key is 256 bit, please note that xts-aes algorithm is XTS_AES_128*/ - ESP_KEY_MGR_XTS_AES_LEN_512, /* xts-aes key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */ + ESP_KEY_MGR_XTS_AES_LEN_256 = 0, /* xts-aes key is 256 bit, please note that xts-aes algorithm is XTS_AES_128 */ + ESP_KEY_MGR_XTS_AES_LEN_512, /* xts-aes key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */ } esp_key_mgr_xts_aes_key_len_t; +/** + * @brief Length of the PSRAM key + */ +typedef enum { + ESP_KEY_MGR_PSRAM_LEN_256 = 0, /* psram key is 256 bit, please note that xts-aes algorithm is XTS_AES_128 */ + ESP_KEY_MGR_PSRAM_LEN_512, /* psram key is 512 bit, please note that xts-aes algorithm is XTS_AES_256 */ +} esp_key_mgr_psram_key_len_t; + /** * @brief Type of the key: ECDSA, XTS */ typedef enum { - ESP_KEY_MGR_ECDSA_KEY = 0, /* ECDSA key */ - ESP_KEY_MGR_XTS_AES_128_KEY, /* XTS-AES 128 key */ - ESP_KEY_MGR_XTS_AES_256_KEY, /* XTS-AES 256 key */ + ESP_KEY_MGR_XTS_AES_128_KEY, /* XTS-AES 128-bit key */ + ESP_KEY_MGR_XTS_AES_256_KEY, /* XTS-AES 256-bit key */ + ESP_KEY_MGR_ECDSA_192_KEY, /* ECDSA 192-bit key */ + ESP_KEY_MGR_ECDSA_256_KEY, /* ECDSA 256-bit key */ + ESP_KEY_MGR_ECDSA_384_KEY, /* ECDSA 384-bit key */ + ESP_KEY_MGR_HMAC_KEY, /* HMAC key */ + ESP_KEY_MGR_DS_KEY, /* Digital signature key */ + ESP_KEY_MGR_PSRAM_128_KEY, /* PSRAM 128-bit key */ + ESP_KEY_MGR_PSRAM_256_KEY, /* PSRAM 256-bit key */ } esp_key_mgr_key_type_t; /* @@ -48,7 +62,7 @@ typedef enum { */ typedef enum { ESP_KEY_MGR_USE_OWN_KEY = 0, /* Use key from the key manager */ - ESP_KEY_MGR_USE_EFUSE_KEY, /* Use key from the eFuse */ + ESP_KEY_MGR_USE_EFUSE_KEY, /* Use key from the eFuse */ ESP_KEY_MGR_USAGE_INVALID, } esp_key_mgr_key_usage_t; @@ -56,10 +70,21 @@ typedef enum { * @brief Key Purpose to be set for a particular key in the Key Manager */ typedef enum { - ESP_KEY_MGR_KEY_PURPOSE_ECDSA = 1, - ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 = 2, /* First half of the XTS AES 256 bit key */ - ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 = 3, /* Second half of the XTS AES 256 bit key */ - ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128 = 4, /* XTS AES 128 bit key */ + ESP_KEY_MGR_KEY_PURPOSE_ECDSA_192 = 1, /* ECDSA 192-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_ECDSA_256 = 2, /* ECDSA 256-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1 = 3, /* First half of flash 256-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_1 = ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_1, + ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2 = 4, /* Second half of flash 256-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_256_2 = ESP_KEY_MGR_KEY_PURPOSE_FLASH_256_2, + ESP_KEY_MGR_KEY_PURPOSE_FLASH_128 = 5, /* Flash 128-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_XTS_AES_128 = ESP_KEY_MGR_KEY_PURPOSE_FLASH_128, + ESP_KEY_MGR_KEY_PURPOSE_HMAC = 6, /* HMAC key */ + ESP_KEY_MGR_KEY_PURPOSE_DS = 7, /* Digital signature key */ + ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_1 = 8, /* First half of PSRAM 256-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_PSRAM_256_2 = 9, /* Second half of PSRAM 256-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_PSRAM_128 = 10, /* PSRAM 128-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_L = 11, /* Lower half of ECDSA 384-bit key */ + ESP_KEY_MGR_KEY_PURPOSE_ECDSA_384_H = 12, /* Higher half of ECDSA 384-bit key */ } esp_key_mgr_key_purpose_t; /** @@ -86,7 +111,7 @@ typedef enum { // store huk info, occupy 96 words typedef struct PACKED_ATTR { -#define HUK_INFO_LEN 384 +#define HUK_INFO_LEN 660 uint8_t info[HUK_INFO_LEN]; uint32_t crc; } esp_key_mgr_huk_info_t; diff --git a/components/hal/include/hal/spi_flash_hal.h b/components/hal/include/hal/spi_flash_hal.h index a0f0ee1746..e21a42fec2 100644 --- a/components/hal/include/hal/spi_flash_hal.h +++ b/components/hal/include/hal/spi_flash_hal.h @@ -57,6 +57,7 @@ typedef struct { #define SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR BIT(0) ///< Slice data according to DTR mode, the address and length must be even (A0=0). int freq_mhz; /// Flash clock frequency. uint8_t tsus_val; ///< Tsus value of suspend (us) + uint8_t trs_val; ///< Trs value of suspend (us) bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay. } spi_flash_hal_context_t; ESP_STATIC_ASSERT(sizeof(spi_flash_hal_context_t) == 48, "size of spi_flash_hal_context_t incorrect. Please check data compatibility with the ROM"); @@ -94,6 +95,7 @@ typedef struct { int freq_mhz; ///< SPI flash clock speed (MHZ). int clock_src_freq; ///< SPI flash clock source (MHZ). uint8_t tsus_val; ///< Tsus value of suspend (us). + uint8_t trs_val; ///< Trs value of suspend (us) bool auto_waiti_pes; ///< True for auto-wait idle after suspend command. False for using time delay. } spi_flash_hal_config_t; diff --git a/components/hal/key_mgr_hal.c b/components/hal/key_mgr_hal.c index 3658371fd5..5dcb67f5b2 100644 --- a/components/hal/key_mgr_hal.c +++ b/components/hal/key_mgr_hal.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -79,14 +79,14 @@ bool key_mgr_hal_is_huk_valid(void) return key_mgr_ll_is_huk_valid(); } -void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_xts_aes_key_len_t key_len) +void key_mgr_hal_set_xts_aes_key_len(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_xts_aes_key_len_t key_len) { - key_mgr_ll_set_xts_aes_key_len(key_len); + key_mgr_ll_set_xts_aes_key_len(key_type, key_len); } -esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_xts_aes_key_len(void) +esp_key_mgr_xts_aes_key_len_t key_mgr_hal_get_xts_aes_key_len(const esp_key_mgr_key_type_t key_type) { - return key_mgr_ll_get_xts_aes_key_len(); + return key_mgr_ll_get_xts_aes_key_len(key_type); } void key_mgr_hal_continue(void) diff --git a/components/hal/mpi_hal.c b/components/hal/mpi_hal.c index 8302ae847a..014ab14655 100644 --- a/components/hal/mpi_hal.c +++ b/components/hal/mpi_hal.c @@ -15,7 +15,6 @@ size_t mpi_hal_calc_hardware_words(size_t words) void mpi_hal_enable_hardware_hw_op(void) { - mpi_ll_power_up(); while (mpi_ll_check_memory_init_complete()) { } // Note: from enabling RSA clock to here takes about 1.3us @@ -27,7 +26,7 @@ void mpi_hal_enable_hardware_hw_op(void) void mpi_hal_disable_hardware_hw_op(void) { - mpi_ll_power_down(); + } void mpi_hal_interrupt_enable(bool enable) diff --git a/components/hal/spi_flash_hal.c b/components/hal/spi_flash_hal.c index 46a63c773f..de457e1d1b 100644 --- a/components/hal/spi_flash_hal.c +++ b/components/hal/spi_flash_hal.c @@ -131,6 +131,7 @@ esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_ data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND; data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME; data_out->tsus_val = cfg->tsus_val; + data_out->trs_val = cfg->trs_val; data_out->auto_waiti_pes = cfg->auto_waiti_pes; } diff --git a/components/hal/spi_flash_hal_iram.c b/components/hal/spi_flash_hal_iram.c index e4f62e956c..611756b72e 100644 --- a/components/hal/spi_flash_hal_iram.c +++ b/components/hal/spi_flash_hal_iram.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -154,6 +154,11 @@ void spi_flash_hal_setup_auto_suspend_mode(spi_flash_host_inst_t *host) // tsus = ceil(ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); uint32_t tsus = (ctx->tsus_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->tsus_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); spimem_flash_ll_set_sus_delay(dev, tsus); +#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + // trs = ceil(ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles); + uint32_t trs = (ctx->trs_val * ctx->freq_mhz / spimem_flash_ll_get_tsus_unit_in_cycles(dev)) + ((ctx->trs_val * ctx->freq_mhz) % spimem_flash_ll_get_tsus_unit_in_cycles(dev) != 0); + spimem_flash_ll_set_rs_delay(dev, trs); +#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR // tshsl2 = ceil(SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() * 0.001); uint32_t tshsl2 = (SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz() / 1000) + ((SPI_FLASH_TSHSL2_SAFE_VAL_NS * spimem_flash_ll_get_source_freq_mhz()) % 1000 != 0); spimem_flash_set_cs_hold_delay(dev, tshsl2); diff --git a/components/hal/test_apps/crypto/main/aes/aes_block.c b/components/hal/test_apps/crypto/main/aes/aes_block.c index d64beb007d..15de815e8c 100644 --- a/components/hal/test_apps/crypto/main/aes/aes_block.c +++ b/components/hal/test_apps/crypto/main/aes/aes_block.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 */ @@ -8,7 +8,7 @@ #include #include -#include "esp_private/esp_crypto_lock_internal.h" +#include "esp_crypto_periph_clk.h" #include "hal/aes_types.h" #include "hal/aes_hal.h" #include "hal/aes_ll.h" @@ -30,10 +30,7 @@ void aes_crypt_cbc_block(int mode, uint32_t *iv_words = (uint32_t *)iv; unsigned char temp[16]; - AES_RCC_ATOMIC() { - aes_ll_enable_bus_clock(true); - aes_ll_reset_register(); - } + esp_crypto_aes_enable_periph_clk(true); /* Sets the key used for AES encryption/decryption */ aes_hal_setkey(key, key_bytes, mode); @@ -71,9 +68,7 @@ void aes_crypt_cbc_block(int mode, } } - AES_RCC_ATOMIC() { - aes_ll_enable_bus_clock(false); - } + esp_crypto_aes_enable_periph_clk(false); } @@ -89,10 +84,7 @@ void aes_crypt_ctr_block(uint8_t key_bytes, int c, i; size_t n = *nc_off; - AES_RCC_ATOMIC() { - aes_ll_enable_bus_clock(true); - aes_ll_reset_register(); - } + esp_crypto_aes_enable_periph_clk(true); /* Sets the key used for AES encryption/decryption */ aes_hal_setkey(key, key_bytes, ESP_AES_ENCRYPT); @@ -113,9 +105,7 @@ void aes_crypt_ctr_block(uint8_t key_bytes, *nc_off = n; - AES_RCC_ATOMIC() { - aes_ll_enable_bus_clock(false); - } + esp_crypto_aes_enable_periph_clk(false); } #endif diff --git a/components/hal/test_apps/crypto/main/ds/ds_types.h b/components/hal/test_apps/crypto/main/ds/ds_types.h new file mode 100644 index 0000000000..6b82bf20fe --- /dev/null +++ b/components/hal/test_apps/crypto/main/ds/ds_types.h @@ -0,0 +1,47 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Unlicense OR CC0-1.0 + */ +#include +#include "soc/soc_caps.h" + +#define ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL (0x1) /*!< HMAC peripheral problem */ +#define ESP_ERR_HW_CRYPTO_DS_INVALID_KEY (0x2) /*!< given HMAC key isn't correct, HMAC peripheral problem */ +#define ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST (0x4) /*!< message digest check failed, result is invalid */ +#define ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING (0x5) /*!< padding check failed, but result is produced anyway and can be read*/ + +#define ESP_DS_IV_BIT_LEN 128 +#define ESP_DS_IV_LEN (ESP_DS_IV_BIT_LEN / 8) +#define ESP_DS_SIGNATURE_MAX_BIT_LEN SOC_RSA_MAX_BIT_LEN +#define ESP_DS_SIGNATURE_MD_BIT_LEN 256 +#define ESP_DS_SIGNATURE_M_PRIME_BIT_LEN 32 +#define ESP_DS_SIGNATURE_L_BIT_LEN 32 +#define ESP_DS_SIGNATURE_PADDING_BIT_LEN 64 + +#define ESP_DS_C_LEN (((ESP_DS_SIGNATURE_MAX_BIT_LEN * 3 \ + + ESP_DS_SIGNATURE_MD_BIT_LEN \ + + ESP_DS_SIGNATURE_M_PRIME_BIT_LEN \ + + ESP_DS_SIGNATURE_L_BIT_LEN \ + + ESP_DS_SIGNATURE_PADDING_BIT_LEN) / 8)) + +typedef enum { + ESP_DS_RSA_1024 = (1024 / 32) - 1, + ESP_DS_RSA_2048 = (2048 / 32) - 1, + ESP_DS_RSA_3072 = (3072 / 32) - 1, + ESP_DS_RSA_4096 = (4096 / 32) - 1 +} esp_digital_signature_length_t; + +typedef struct esp_digital_signature_data { + esp_digital_signature_length_t rsa_length; + uint32_t iv[ESP_DS_IV_BIT_LEN / 32]; + uint8_t c[ESP_DS_C_LEN]; +} esp_ds_data_t; + +typedef struct { + uint32_t Y[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; + uint32_t M[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; + uint32_t Rb[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; + uint32_t M_prime; + uint32_t length; +} esp_ds_p_data_t; diff --git a/components/hal/test_apps/crypto/main/ds/test_ds.c b/components/hal/test_apps/crypto/main/ds/test_ds.c index ab8654623b..e56d2f3c57 100644 --- a/components/hal/test_apps/crypto/main/ds/test_ds.c +++ b/components/hal/test_apps/crypto/main/ds/test_ds.c @@ -13,84 +13,23 @@ #include "soc/soc_caps.h" #include "esp_log.h" +#include "ds_types.h" const static char *TAG = "test_ds"; #include "rom/efuse.h" -#if CONFIG_IDF_TARGET_ESP32S2 -#include "esp32s2/rom/digital_signature.h" -#include "esp32s2/rom/aes.h" -#include "esp32s2/rom/sha.h" -#include "esp32s2/rom/hmac.h" -#include "soc/soc_memory_layout.h" -#elif CONFIG_IDF_TARGET_ESP32C3 -#include "esp32c3/rom/digital_signature.h" -#include "esp32c3/rom/hmac.h" -#elif CONFIG_IDF_TARGET_ESP32S3 -#include "esp32s3/rom/digital_signature.h" -#include "esp32s3/rom/aes.h" -#include "esp32s3/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32C6 -#include "esp32c6/rom/digital_signature.h" -#include "esp32c6/rom/aes.h" -#include "esp32c6/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32H2 -#include "esp32h2/rom/digital_signature.h" -#include "esp32h2/rom/aes.h" -#include "esp32h2/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32P4 -#include "esp32p4/rom/digital_signature.h" -#include "esp32p4/rom/aes.h" -#include "esp32p4/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32C5 -#include "esp32c5/rom/digital_signature.h" -#include "esp32c5/rom/aes.h" -#include "esp32c5/rom/sha.h" -#elif CONFIG_IDF_TARGET_ESP32H21 -#include "esp32h21/rom/digital_signature.h" -#include "esp32h21/rom/aes.h" -#include "esp32h21/rom/sha.h" +#include "rom/sha.h" +#include "rom/digital_signature.h" +#include "rom/aes.h" +#include "rom/hmac.h" + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +#include "hal/key_mgr_ll.h" #endif -#define ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL (0x1) /*!< HMAC peripheral problem */ -#define ESP_ERR_HW_CRYPTO_DS_INVALID_KEY (0x2) /*!< given HMAC key isn't correct, HMAC peripheral problem */ -#define ESP_ERR_HW_CRYPTO_DS_INVALID_DIGEST (0x4) /*!< message digest check failed, result is invalid */ -#define ESP_ERR_HW_CRYPTO_DS_INVALID_PADDING (0x5) /*!< padding check failed, but result is produced anyway and can be read*/ - -#define ESP_DS_IV_BIT_LEN 128 -#define ESP_DS_IV_LEN (ESP_DS_IV_BIT_LEN / 8) -#define ESP_DS_SIGNATURE_MAX_BIT_LEN SOC_RSA_MAX_BIT_LEN -#define ESP_DS_SIGNATURE_MD_BIT_LEN 256 -#define ESP_DS_SIGNATURE_M_PRIME_BIT_LEN 32 -#define ESP_DS_SIGNATURE_L_BIT_LEN 32 -#define ESP_DS_SIGNATURE_PADDING_BIT_LEN 64 - -#define ESP_DS_C_LEN (((ESP_DS_SIGNATURE_MAX_BIT_LEN * 3 \ - + ESP_DS_SIGNATURE_MD_BIT_LEN \ - + ESP_DS_SIGNATURE_M_PRIME_BIT_LEN \ - + ESP_DS_SIGNATURE_L_BIT_LEN \ - + ESP_DS_SIGNATURE_PADDING_BIT_LEN) / 8)) - -typedef enum { - ESP_DS_RSA_1024 = (1024 / 32) - 1, - ESP_DS_RSA_2048 = (2048 / 32) - 1, - ESP_DS_RSA_3072 = (3072 / 32) - 1, - ESP_DS_RSA_4096 = (4096 / 32) - 1 -} esp_digital_signature_length_t; - -typedef struct esp_digital_signature_data { - esp_digital_signature_length_t rsa_length; - uint32_t iv[ESP_DS_IV_BIT_LEN / 32]; - uint8_t c[ESP_DS_C_LEN]; -} esp_ds_data_t; - -typedef struct { - uint32_t Y[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; - uint32_t M[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; - uint32_t Rb[ESP_DS_SIGNATURE_MAX_BIT_LEN / 32]; - uint32_t M_prime; - uint32_t length; -} esp_ds_p_data_t; +#if CONFIG_IDF_TARGET_ESP32S2 +#include "soc/soc_memory_layout.h" +#endif #define NUM_RESULTS 10 @@ -128,43 +67,23 @@ _Static_assert(NUM_RESULTS == NUM_MESSAGES, "expected_results size should be the #include "hal/hmac_hal.h" #include "hal/hmac_ll.h" #include "hal/sha_ll.h" - +#include "esp_crypto_periph_clk.h" static void ds_acquire_enable(void) { - HMAC_RCC_ATOMIC() { - hmac_ll_enable_bus_clock(true); - hmac_ll_reset_register(); - } - - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(true); - sha_ll_reset_register(); - } - - DS_RCC_ATOMIC() { - ds_ll_enable_bus_clock(true); - ds_ll_reset_register(); - } - - hmac_hal_start(); + // We also enable SHA and HMAC here. SHA is used by HMAC, HMAC is used by DS. + esp_crypto_hmac_enable_periph_clk(true); + esp_crypto_sha_enable_periph_clk(true); + esp_crypto_mpi_enable_periph_clk(true); + esp_crypto_ds_enable_periph_clk(true); } static void ds_disable_release(void) { - ds_hal_finish(); - - DS_RCC_ATOMIC() { - ds_ll_enable_bus_clock(false); - } - - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(false); - } - - HMAC_RCC_ATOMIC() { - hmac_ll_enable_bus_clock(false); - } + esp_crypto_mpi_enable_periph_clk(false); + esp_crypto_sha_enable_periph_clk(false); + esp_crypto_hmac_enable_periph_clk(false); + esp_crypto_ds_enable_periph_clk(false); } @@ -172,11 +91,22 @@ static esp_err_t esp_ds_start_sign(const void *message, const esp_ds_data_t *dat { ds_acquire_enable(); - uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); - if (conf_error) { - ds_disable_release(); - return ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL; +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY + if (key_id == HMAC_KEY_KM) { + ds_hal_set_key_source(DS_KEY_SOURCE_KEY_MGR); + } else { + ds_hal_set_key_source(DS_KEY_SOURCE_EFUSE); +#endif + hmac_hal_start(); + uint32_t conf_error = hmac_hal_configure(HMAC_OUTPUT_DS, key_id); + if (conf_error) { + ds_disable_release(); + ESP_LOGE(TAG, "HMAC configure failed"); + return ESP_ERR_HW_CRYPTO_DS_HMAC_FAIL; + } +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY } +#endif ds_hal_start(); @@ -211,13 +141,13 @@ static esp_err_t esp_ds_finish_sign(void *signature, const esp_ds_data_t *data) } hmac_hal_clean(); - + ds_hal_finish(); ds_disable_release(); return return_value; } -static esp_err_t esp_ds_sign(const void *message, +esp_err_t esp_ds_sign(const void *message, const esp_ds_data_t *data, uint32_t key_id, void *signature) @@ -287,8 +217,8 @@ static void ds_disable_release(void) } static esp_err_t esp_ds_start_sign(const void *message, - const esp_ds_data_t *data, - uint32_t key_id) + const esp_ds_data_t *data, + uint32_t key_id) { ds_acquire_enable(); diff --git a/components/hal/test_apps/crypto/main/ecc/test_ecc.c b/components/hal/test_apps/crypto/main/ecc/test_ecc.c index 433915e575..603771d081 100644 --- a/components/hal/test_apps/crypto/main/ecc/test_ecc.c +++ b/components/hal/test_apps/crypto/main/ecc/test_ecc.c @@ -9,7 +9,7 @@ #include #include #include "sdkconfig.h" -#include "esp_private/esp_crypto_lock_internal.h" +#include "esp_crypto_periph_clk.h" #include "esp_log.h" #include "ecc_params.h" #include "soc/soc_caps.h" @@ -43,24 +43,6 @@ static void ecc_be_to_le(const uint8_t* be_point, uint8_t *le_point, uint8_t len } } -static void ecc_enable_and_reset(void) -{ - ECC_RCC_ATOMIC() { - ecc_ll_enable_bus_clock(true); - ecc_ll_power_up(); - ecc_ll_reset_register(); - } -} - -static void ecc_disable(void) -{ - ECC_RCC_ATOMIC() { - ecc_ll_enable_bus_clock(false); - ecc_ll_power_down(); - } -} - - TEST_GROUP(ecc); TEST_SETUP(ecc) @@ -79,7 +61,7 @@ TEST_TEAR_DOWN(ecc) static void ecc_point_mul(const uint8_t *k_le, const uint8_t *x_le, const uint8_t *y_le, uint8_t len, bool verify_first, uint8_t *res_x_le, uint8_t *res_y_le) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_mul_param(k_le, x_le, y_le, len); if (verify_first) { @@ -95,7 +77,7 @@ static void ecc_point_mul(const uint8_t *k_le, const uint8_t *x_le, const uint8_ } ecc_hal_read_mul_result(res_x_le, res_y_le, len); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); } static void test_ecc_point_mul_inner(bool verify_first) @@ -161,7 +143,7 @@ TEST(ecc, ecc_point_multiplication_on_SECP192R1_and_SECP256R1) #if SOC_ECC_CONSTANT_TIME_POINT_MUL -#define CONST_TIME_DEVIATION_PERCENT 0.002 +#define CONST_TIME_DEVIATION_PERCENT 0.0025 static void test_ecc_point_mul_inner_constant_time(void) { @@ -237,7 +219,7 @@ TEST(ecc, ecc_point_multiplication_const_time_check_on_SECP192R1_and_SECP256R1) #if SOC_ECC_SUPPORT_POINT_VERIFY && !defined(SOC_ECC_SUPPORT_POINT_VERIFY_QUIRK) static int ecc_point_verify(const uint8_t *x_le, const uint8_t *y_le, uint8_t len) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_verify_param(x_le, y_le, len); ecc_hal_set_mode(ECC_MODE_VERIFY); @@ -248,7 +230,7 @@ static int ecc_point_verify(const uint8_t *x_le, const uint8_t *y_le, uint8_t le } int ret = ecc_hal_read_verify_result(); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); return ret; } @@ -297,7 +279,7 @@ TEST(ecc, ecc_point_verification_and_multiplication_on_SECP192R1_and_SECP256R1) #if SOC_ECC_SUPPORT_POINT_DIVISION static void ecc_point_inv_mul(const uint8_t *num_le, const uint8_t *deno_le, uint8_t len, uint8_t *res_le) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); uint8_t zero[32] = {0}; ecc_hal_write_mul_param(zero, num_le, deno_le, len); @@ -311,7 +293,7 @@ static void ecc_point_inv_mul(const uint8_t *num_le, const uint8_t *deno_le, uin } ecc_hal_read_mul_result(zero, res_le, len); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); } TEST(ecc, ecc_inverse_multiplication_or_mod_division_using_SECP192R1_and_SECP256R1_order_of_curve) @@ -329,7 +311,7 @@ TEST(ecc, ecc_inverse_multiplication_or_mod_division_using_SECP192R1_and_SECP256 static void ecc_jacob_mul(uint8_t *k_le, uint8_t *x_le, uint8_t *y_le, uint8_t len, bool verify_first, uint8_t *res_x_le, uint8_t *res_y_le, uint8_t *res_z_le) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_mul_param(k_le, x_le, y_le, len); if (verify_first) { @@ -344,7 +326,7 @@ static void ecc_jacob_mul(uint8_t *k_le, uint8_t *x_le, uint8_t *y_le, uint8_t l } ecc_hal_read_jacob_mul_result(res_x_le, res_y_le, res_z_le, len); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); } static void test_ecc_jacob_mul_inner(bool verify_first) @@ -393,7 +375,7 @@ TEST(ecc, ecc_jacobian_point_multiplication_on_SECP192R1_and_SECP256R1) #if SOC_ECC_SUPPORT_JACOB_POINT_VERIFY static int ecc_jacob_verify(const uint8_t *x_le, const uint8_t *y_le, const uint8_t *z_le, uint8_t len) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_jacob_verify_param(x_le, y_le, z_le, len); @@ -406,7 +388,7 @@ static int ecc_jacob_verify(const uint8_t *x_le, const uint8_t *y_le, const uint } int ret = ecc_hal_read_verify_result(); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); return ret; } @@ -436,7 +418,7 @@ static void ecc_point_addition(uint8_t *px_le, uint8_t *py_le, uint8_t *qx_le, u uint8_t len, bool jacob_output, uint8_t *x_res_le, uint8_t *y_res_le, uint8_t *z_res_le) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_point_add_param(px_le, py_le, qx_le, qy_le, qz_le, len); @@ -449,7 +431,7 @@ static void ecc_point_addition(uint8_t *px_le, uint8_t *py_le, uint8_t *qx_le, u } ecc_hal_read_point_add_result(x_res_le, y_res_le, z_res_le, len, jacob_output); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); } TEST(ecc, ecc_point_addition_on_SECP192R1_and_SECP256R1) @@ -508,7 +490,7 @@ TEST(ecc, ecc_point_addition_on_SECP192R1_and_SECP256R1) #if SOC_ECC_SUPPORT_MOD_ADD || SOC_ECC_SUPPORT_MOD_SUB || SOC_ECC_SUPPORT_MOD_MUL static void ecc_mod_op(ecc_mode_t mode, const uint8_t *a, const uint8_t *b, uint8_t len, uint8_t *res_le) { - ecc_enable_and_reset(); + esp_crypto_ecc_enable_periph_clk(true); ecc_hal_write_mod_op_param(a, b, len); @@ -521,7 +503,7 @@ static void ecc_mod_op(ecc_mode_t mode, const uint8_t *a, const uint8_t *b, uint } ecc_hal_read_mod_op_result(res_le, len); - ecc_disable(); + esp_crypto_ecc_enable_periph_clk(false); } #endif diff --git a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c index f8bec33c46..6438ede5a5 100644 --- a/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c +++ b/components/hal/test_apps/crypto/main/ecdsa/test_ecdsa.c @@ -10,7 +10,7 @@ #include "esp_crypto_lock.h" #include "esp_efuse_chip.h" -#include "esp_private/esp_crypto_lock_internal.h" +#include "esp_crypto_periph_clk.h" #include "esp_random.h" #include "esp_err.h" #include "esp_efuse.h" @@ -35,41 +35,20 @@ __attribute__((unused)) static const char * TAG = "crypto_test"; static void ecdsa_enable_and_reset(void) { - ECDSA_RCC_ATOMIC() { - ecdsa_ll_enable_bus_clock(true); - ecdsa_ll_reset_register(); - } - - ECC_RCC_ATOMIC() { - ecc_ll_enable_bus_clock(true); - ecc_ll_power_up(); - ecc_ll_reset_register(); - } - + esp_crypto_ecdsa_enable_periph_clk(true); + esp_crypto_ecc_enable_periph_clk(true); #ifdef SOC_ECDSA_USES_MPI - MPI_RCC_ATOMIC() { - mpi_ll_enable_bus_clock(true); - mpi_ll_reset_register(); - } + esp_crypto_mpi_enable_periph_clk(true); #endif } static void ecdsa_disable(void) { #ifdef SOC_ECDSA_USES_MPI - MPI_RCC_ATOMIC() { - mpi_ll_enable_bus_clock(false); - } + esp_crypto_mpi_enable_periph_clk(false); #endif - - ECC_RCC_ATOMIC() { - ecc_ll_enable_bus_clock(false); - ecc_ll_power_down(); - } - - ECDSA_RCC_ATOMIC() { - ecdsa_ll_enable_bus_clock(false); - } + esp_crypto_ecc_enable_periph_clk(false); + esp_crypto_ecdsa_enable_periph_clk(false); } static void ecc_be_to_le(const uint8_t* be_point, uint8_t *le_point, uint8_t len) diff --git a/components/hal/test_apps/crypto/main/hmac/test_hmac.c b/components/hal/test_apps/crypto/main/hmac/test_hmac.c index 3cffb6b8af..930d2a6566 100644 --- a/components/hal/test_apps/crypto/main/hmac/test_hmac.c +++ b/components/hal/test_apps/crypto/main/hmac/test_hmac.c @@ -1,11 +1,11 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #include -#include "esp_private/esp_crypto_lock_internal.h" +#include "esp_crypto_periph_clk.h" #include "esp_log.h" #include "memory_checks.h" #include "unity_fixture.h" @@ -61,24 +61,13 @@ static void write_and_padd(uint8_t *block, const uint8_t *data, uint16_t data_le bzero(block + data_len + 1, SHA256_BLOCK_SZ - data_len - 1); } -static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t message_len, uint8_t *hmac) +esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t message_len, uint8_t *hmac) { const uint8_t *message_bytes = (const uint8_t *)message; - HMAC_RCC_ATOMIC() { - hmac_ll_enable_bus_clock(true); - hmac_ll_reset_register(); - } - - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(true); - sha_ll_reset_register(); - } - - DS_RCC_ATOMIC() { - ds_ll_enable_bus_clock(true); - ds_ll_reset_register(); - } + esp_crypto_hmac_enable_periph_clk(true); + esp_crypto_sha_enable_periph_clk(true); + esp_crypto_ds_enable_periph_clk(true); hmac_hal_start(); @@ -130,17 +119,9 @@ static esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t mes hmac_hal_read_result_256(hmac); - DS_RCC_ATOMIC() { - ds_ll_enable_bus_clock(false); - } - - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(false); - } - - HMAC_RCC_ATOMIC() { - hmac_ll_enable_bus_clock(false); - } + esp_crypto_hmac_enable_periph_clk(false); + esp_crypto_sha_enable_periph_clk(false); + esp_crypto_ds_enable_periph_clk(false); return ESP_OK; } diff --git a/components/hal/test_apps/crypto/main/key_manager/ecdsa_256_key.pem b/components/hal/test_apps/crypto/main/key_manager/ecdsa_256_key.pem new file mode 100644 index 0000000000..5e4dc4d806 --- /dev/null +++ b/components/hal/test_apps/crypto/main/key_manager/ecdsa_256_key.pem @@ -0,0 +1,5 @@ +-----BEGIN EC PRIVATE KEY----- +MHcCAQEEICySt/VCEPFi962COuQDE+cXD3Bz8XjZy2O5SM1LsHsGoAoGCCqGSM49 +AwEHoUQDQgAEBYu5KXarLURySNNaeZcxtBTxC0vJAM/evz9NC01IjCVQlOLJ4Y6i +3UviK3bgk+3FqpJBM+SQCqeDgd7ktPtr9Q== +-----END EC PRIVATE KEY----- diff --git a/components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py b/components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py index 053c2e41a2..3853455e1e 100644 --- a/components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py +++ b/components/hal/test_apps/crypto/main/key_manager/gen_key_manager_test_cases.py @@ -1,19 +1,29 @@ -# SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD # SPDX-License-Identifier: Unlicense OR CC0-1.0 +import argparse +import hashlib +import hmac import os +import random import struct from typing import Any from cryptography.hazmat.backends import default_backend from cryptography.hazmat.primitives import serialization from cryptography.hazmat.primitives.asymmetric import ec -from cryptography.hazmat.primitives.ciphers import algorithms +from cryptography.hazmat.primitives.asymmetric import rsa from cryptography.hazmat.primitives.ciphers import Cipher +from cryptography.hazmat.primitives.ciphers import algorithms from cryptography.hazmat.primitives.ciphers import modes +from cryptography.utils import int_to_bytes from ecdsa.curves import NIST256p +supported_targets = {'esp32p4', 'esp32c5'} +supported_ds_key_size = {'esp32p4': [4096, 3072, 2048, 1024], 'esp32c5': [3072, 2048, 1024]} + # Constants TEST_COUNT = 5 +STORAGE_PARTITION_OFFSET = 0x160000 # Helper functions @@ -45,7 +55,9 @@ def calculate_aes_cipher(data: bytes, key: bytes) -> Any: return encryptor.update(data) + encryptor.finalize() -def _flash_encryption_operation_aes_xts(input_data: bytes, flash_address: int, key: bytes, do_decrypt: bool = False) -> bytes: +def _flash_encryption_operation_aes_xts( + input_data: bytes, flash_address: int, key: bytes, do_decrypt: bool = False +) -> bytes: backend = default_backend() indata = input_data @@ -54,9 +66,9 @@ def _flash_encryption_operation_aes_xts(input_data: bytes, flash_address: int, k indata = (b'\x00' * pad_left) + indata pad_right = (0x80 - (len(indata) % 0x80)) % 0x80 - indata += (b'\x00' * pad_right) + indata += b'\x00' * pad_right - inblocks = [indata[i:i + 0x80] for i in range(0, len(indata), 0x80)] + inblocks = [indata[i : i + 0x80] for i in range(0, len(indata), 0x80)] output = b'' for inblock in inblocks: @@ -68,17 +80,17 @@ def _flash_encryption_operation_aes_xts(input_data: bytes, flash_address: int, k outblock = encryptor.update(inblock[::-1]) output += outblock[::-1] - return output[pad_left:len(output) - pad_right] + return output[pad_left : len(output) - pad_right] -def generate_xts_test_data(key: bytes, base_flash_address: int = 0x120000) -> list: +def generate_xts_test_data(key: bytes, base_flash_address: int = STORAGE_PARTITION_OFFSET) -> list: xts_test_data = [] plaintext_data = bytes(range(1, 129)) data_size = 16 flash_address = base_flash_address for i in range(TEST_COUNT): data_size = (data_size * 2) % 256 - if (data_size < 16): + if data_size < 16: data_size = 16 input_data = plaintext_data[:data_size] flash_address = base_flash_address + (i * 0x100) @@ -96,7 +108,7 @@ def generate_ecdsa_256_key_and_pub_key(filename: str) -> tuple: pem = private_key.private_bytes( encoding=serialization.Encoding.PEM, format=serialization.PrivateFormat.TraditionalOpenSSL, - encryption_algorithm=serialization.NoEncryption() + encryption_algorithm=serialization.NoEncryption(), ) with open('ecdsa_256_key.pem', 'wb') as pem_file: @@ -134,10 +146,120 @@ def generate_k1_G(key_file_path: str) -> tuple: return k1_G, k1_G -def write_to_c_header(init_key: bytes, k1: bytes, k2_info: bytes, k1_encrypted_32: list, - test_data_xts_aes_128: list, k1_encrypted_64: list, - xts_test_data_xts_aes_256: list, pubx: bytes, - puby: bytes, k1_G_0: bytes, k1_G_1: bytes) -> None: +def generate_hmac_test_data(key: bytes) -> tuple: + hmac_message = ( + 'Deleniti voluptas explicabo et assumenda. Sed et aliquid minus quis. ' + 'Praesentium cupiditate quia nemo est. Laboriosam pariatur ut distinctio tenetur. ' + 'Sunt architecto iure aspernatur soluta ut recusandae. ' + 'Ut quibusdam occaecati ut qui sit dignissimos eaque..' + ).encode('utf-8') + hmac_result = hmac.HMAC(key, hmac_message, hashlib.sha256).digest() + return hmac_message, hmac_result + + +def number_as_bytes(number, pad_bits=0): # type: (int, int) -> bytes + """ + Given a number, format as a little endian array of bytes + """ + result = int_to_bytes(number)[::-1] # type: bytes + while pad_bits != 0 and len(result) < (pad_bits // 8): + result += b'\x00' + return result + + +def number_as_bignum_words(number): # type: (int) -> str + """ + Given a number, format result as a C array of words + (little-endian, same as ESP32 RSA peripheral or mbedTLS) + """ + result = [] + while number != 0: + result.append('0x%08x' % (number & 0xFFFFFFFF)) + number >>= 32 + return '{ ' + ', '.join(result) + ' }' + + +def generate_ds_encrypted_input_params(aes_key: bytes, target: str) -> tuple: + iv = os.urandom(16) + max_key_size = max(supported_ds_key_size[target]) + key_size = max_key_size + private_key = rsa.generate_private_key(public_exponent=65537, key_size=key_size, backend=default_backend()) + + priv_numbers = private_key.private_numbers() + pub_numbers = private_key.public_key().public_numbers() + Y = priv_numbers.d + M = pub_numbers.n + + rr = 1 << (key_size * 2) + rinv = rr % pub_numbers.n + mprime = -rsa._modinv(M, 1 << 32) + mprime &= 0xFFFFFFFF + length = key_size // 32 - 1 + + # calculate MD from preceding values and IV + # Y_max_key_size || M_max_key_size || Rb_max_key_size || M_prime32 || LENGTH32 || IV128 + md_in = ( + number_as_bytes(Y, max_key_size) + + number_as_bytes(M, max_key_size) + + number_as_bytes(rinv, max_key_size) + + struct.pack(' None: with open('key_manager_test_cases.h', 'w', encoding='utf-8') as file: header_content = """#include @@ -154,13 +276,30 @@ typedef struct test_ecdsa_data { uint8_t puby[32]; } test_ecdsa_data_t; +typedef struct test_hmac_data { + uint8_t message[%d]; + uint8_t hmac_result[32]; +} test_hmac_data_t; + +typedef struct test_ds_data { + uint8_t ds_message[%d / 8]; + uint8_t ds_encrypted_input_params[%d]; + uint8_t ds_encrypted_input_params_iv[16]; + size_t ds_key_size; + uint8_t ds_result[%d]; +} test_ds_data_t; + typedef struct test_data { uint8_t init_key[32]; uint8_t k2_info[64]; uint8_t k1_encrypted[2][32]; // For both 256-bit and 512-bit keys uint8_t plaintext_data[128]; - test_xts_data_t xts_test_data[TEST_COUNT]; - test_ecdsa_data_t ecdsa_test_data; + union { + test_xts_data_t xts_test_data[TEST_COUNT]; + test_ecdsa_data_t ecdsa_test_data; + test_hmac_data_t hmac_test_data; + test_ds_data_t ds_test_data; + }; } test_data_aes_mode_t; typedef struct test_data_ecdh0 { @@ -176,10 +315,23 @@ test_data_aes_mode_t test_data_xts_aes_128 = { .k1_encrypted = { { %s }, { } }, .plaintext_data = { %s }, .xts_test_data = { -""" % (key_to_c_format(init_key), key_to_c_format(k2_info), key_to_c_format(k1_encrypted_32[0]), key_to_c_format(bytes(range(1, 129)))) +""" % ( + len(hmac_message), + ds_key_size, + len(ds_encrypted_input_params), + len(ds_result), + key_to_c_format(init_key), + key_to_c_format(k2_info), + key_to_c_format(k1_encrypted_32_reversed[0]), + key_to_c_format(bytes(range(1, 129))), + ) for data_size, flash_address, ciphertext in test_data_xts_aes_128: - header_content += f'\t\t{{.data_size = {data_size}, .data_offset = 0x{flash_address:x}, .ciphertext = {{{key_to_c_format(ciphertext)}}}}},\n' + header_content += ( + f'\t\t{{.data_size = {data_size}, ' + f'.data_offset = 0x{flash_address:x}, ' + f'.ciphertext = {{{key_to_c_format(ciphertext)}}}}},\n' + ) header_content += '\t}\n};\n\n' # For 64-byte k1 key @@ -187,14 +339,22 @@ test_data_aes_mode_t test_data_xts_aes_128 = { header_content += 'test_data_aes_mode_t test_data_xts_aes_256 = {\n' header_content += f'\t.init_key = {{{key_to_c_format(init_key)}}},\n' header_content += f'\t.k2_info = {{{key_to_c_format(k2_info)}}},\n' - header_content += f'\t.k1_encrypted = {{{{{key_to_c_format(k1_encrypted_64[0])}}}, {{{key_to_c_format(k1_encrypted_64[1])}}}}},\n' + header_content += ( + f'\t.k1_encrypted = {{{{{key_to_c_format(k1_encrypted_64_reversed[0])}}}, ' + f'{{{key_to_c_format(k1_encrypted_64_reversed[1])}}}}},\n' + ) header_content += f'\t.plaintext_data = {{{key_to_c_format(bytes(range(1, 129)))}}},\n' header_content += ' .xts_test_data = {\n' for data_size, flash_address, ciphertext in xts_test_data_xts_aes_256: - header_content += f' {{.data_size = {data_size}, .data_offset = 0x{flash_address:x}, .ciphertext = {{{key_to_c_format(ciphertext)}}}}},\n' - header_content += ' }\n};\n' - header_content += ''' + header_content += ( + f'\t\t{{.data_size = {data_size}, ' + f'.data_offset = 0x{flash_address:x}, ' + f'.ciphertext = {{{key_to_c_format(ciphertext)}}}}},\n' + ) + header_content += '\t}\n};\n' + + header_content += """ test_data_aes_mode_t test_data_ecdsa = { .init_key = { %s }, .k2_info = { %s }, @@ -204,8 +364,15 @@ test_data_aes_mode_t test_data_ecdsa = { .puby = { %s } } };\n -''' % (key_to_c_format(init_key), key_to_c_format(k2_info), key_to_c_format(k1_encrypted_32[0]), key_to_c_format(pubx),key_to_c_format(puby)) - header_content += ''' +""" % ( + key_to_c_format(init_key), + key_to_c_format(k2_info), + key_to_c_format(k1_encrypted_32_reversed[0]), + key_to_c_format(pubx), + key_to_c_format(puby), + ) + + header_content += """ test_data_ecdh0_mode_t test_data_ecdh0 = { .plaintext_data = { %s }, .k1 = { @@ -217,41 +384,132 @@ test_data_ecdh0_mode_t test_data_ecdh0 = { { %s }, } };\n +""" % ( + key_to_c_format(bytes(range(1, 129))), + key_to_c_format(k1), + key_to_c_format(k1), + key_to_c_format(k1_G_0), + key_to_c_format(k1_G_1), + ) -''' % (key_to_c_format(bytes(range(1, 129))), key_to_c_format(k1), key_to_c_format(k1), key_to_c_format(k1_G_0), key_to_c_format(k1_G_1)) + header_content += """ +test_data_aes_mode_t test_data_hmac = { + .init_key = { %s }, + .k2_info = { %s }, + .k1_encrypted = { { %s }, { } }, + .hmac_test_data = { + .message = { %s }, + .hmac_result = { %s } + } +};\n +""" % ( + key_to_c_format(init_key), + key_to_c_format(k2_info), + key_to_c_format(k1_encrypted_32[0]), + key_to_c_format(hmac_message), + key_to_c_format(hmac_result), + ) + + header_content += """ +test_data_aes_mode_t test_data_ds = { + .init_key = { %s }, + .k2_info = { %s }, + .k1_encrypted = { { %s }, { } }, + .ds_test_data = { + .ds_message = { %s }, + .ds_encrypted_input_params = { %s }, + .ds_encrypted_input_params_iv = { %s }, + .ds_key_size = %d, + .ds_result = { %s } + } +};\n +""" % ( + key_to_c_format(init_key), + key_to_c_format(k2_info), + key_to_c_format(k1_encrypted_32_reversed[0]), + key_to_c_format(ds_message), + key_to_c_format(ds_encrypted_input_params), + key_to_c_format(ds_encrypted_input_params_iv), + ds_key_size, + key_to_c_format(ds_result), + ) file.write(header_content) -# Main script logic follows as per your provided structure -init_key = key_from_file_or_generate('init_key.bin', 32) -k2 = key_from_file_or_generate('k2.bin', 32) -rand_num = key_from_file_or_generate('rand_num.bin', 32) +def generate_tests_cases(target: str) -> None: + # Main script logic follows as per your provided structure + init_key = key_from_file_or_generate('init_key.bin', 32) + k2 = key_from_file_or_generate('k2.bin', 32) + rand_num = key_from_file_or_generate('rand_num.bin', 32) -temp_result_inner = calculate_aes_cipher(k2, rand_num) -temp_result_outer = calculate_aes_cipher(temp_result_inner + rand_num, init_key) -k2_info = temp_result_outer + temp_result_inner = calculate_aes_cipher(k2, rand_num) + temp_result_outer = calculate_aes_cipher(temp_result_inner + rand_num, init_key) + k2_info = temp_result_outer -k1_32 = key_from_file_or_generate('k1.bin', 32) -k1_64 = key_from_file_or_generate('k1_64.bin', 64) + k1_32 = key_from_file_or_generate('k1.bin', 32) + k1_64 = key_from_file_or_generate('k1_64.bin', 64) -k1_32_reversed = k1_32[::-1] + k1_32_reversed = k1_32[::-1] -k1_64_reversed = k1_64[::-1] + k1_64_1 = k1_64[:32] + k1_64_1_reversed = k1_64_1[::-1] + k1_64_2 = k1_64[32:] + k1_64_2_reversed = k1_64_2[::-1] -k1_64_1 = k1_64[:32] -k1_64_1_reversed = k1_64_1[::-1] -k1_64_2 = k1_64[32:] -k1_64_2_reversed = k1_64_2[::-1] + k1_encrypted_32 = [calculate_aes_cipher(k1_32, k2)] + k1_encrypted_64 = [calculate_aes_cipher(k1_64_1, k2), calculate_aes_cipher(k1_64_2, k2)] -k1_encrypted_32 = [calculate_aes_cipher(k1_32_reversed, k2)] -k1_encrypted_64 = [calculate_aes_cipher(k1_64_1_reversed, k2), calculate_aes_cipher(k1_64_2_reversed, k2)] + k1_encrypted_32_reversed = [calculate_aes_cipher(k1_32_reversed, k2)] + k1_encrypted_64_reversed = [calculate_aes_cipher(k1_64_1_reversed, k2), calculate_aes_cipher(k1_64_2_reversed, k2)] -test_data_xts_aes_128 = generate_xts_test_data(k1_32) -xts_test_data_xts_aes_256 = generate_xts_test_data(k1_64) + test_data_xts_aes_128 = generate_xts_test_data(k1_32) + xts_test_data_xts_aes_256 = generate_xts_test_data(k1_64) -pubx, puby = generate_ecdsa_256_key_and_pub_key('k1.bin') + pubx, puby = generate_ecdsa_256_key_and_pub_key('k1.bin') -k1_G_0, k1_G_1 = generate_k1_G('k1.bin') + k1_G_0, k1_G_1 = generate_k1_G('k1.bin') -write_to_c_header(init_key, k1_32, k2_info, k1_encrypted_32, test_data_xts_aes_128, k1_encrypted_64, xts_test_data_xts_aes_256, pubx, puby, k1_G_0, k1_G_1) + hmac_message, hmac_result = generate_hmac_test_data(k1_32) + + ds_message, ds_encrypted_input_params, ds_encrypted_input_params_iv, ds_key_size, ds_result = ( + generate_ds_encrypted_input_params(k1_32, target) + ) + + write_to_c_header( + init_key, + k1_32, + k2_info, + k1_encrypted_32, + k1_encrypted_32_reversed, + test_data_xts_aes_128, + k1_encrypted_64, + k1_encrypted_64_reversed, + xts_test_data_xts_aes_256, + pubx, + puby, + k1_G_0, + k1_G_1, + hmac_message, + hmac_result, + ds_message, + ds_encrypted_input_params, + ds_encrypted_input_params_iv, + ds_key_size, + ds_result, + ) + + +if __name__ == '__main__': + parser = argparse.ArgumentParser(description="""Generates Digital Signature Test Cases""") + + parser.add_argument( + '--target', + required=True, + choices=supported_targets, + help='Target to generate test cases for, different targets support different max key length', + ) + + args = parser.parse_args() + + generate_tests_cases(args.target) diff --git a/components/hal/test_apps/crypto/main/key_manager/init_key.bin b/components/hal/test_apps/crypto/main/key_manager/init_key.bin new file mode 100644 index 0000000000..726a088171 --- /dev/null +++ b/components/hal/test_apps/crypto/main/key_manager/init_key.bin @@ -0,0 +1 @@ +size)); + uint8_t read_data[128]; for (int i = 0; i < TEST_COUNT; i++) { + memset(read_data, 0, sizeof(read_data)); uint32_t address = test_data->xts_test_data[i].data_offset; uint32_t data_size = test_data->xts_test_data[i].data_size; + ESP_ERROR_CHECK(esp_flash_write_encrypted(NULL, address, test_data->plaintext_data, data_size)); - static uint8_t read_data[128]; ESP_ERROR_CHECK(esp_flash_read(NULL, read_data, address, data_size)); + TEST_ASSERT_EQUAL_HEX8_ARRAY(test_data->xts_test_data[i].ciphertext, read_data, data_size); } } @@ -70,18 +72,20 @@ static void test_xts_aes_key_ecdh0_mode(test_data_ecdh0_mode_t *test_data) const esp_partition_t *partition = get_test_storage_partition(); ESP_ERROR_CHECK(esp_partition_erase_range(partition, 0, partition->size)); + uint8_t read_data[128] = { 0 }; uint32_t address = partition->address; uint32_t data_size = 32; - print_data_in_hex(test_data->plaintext_data, data_size, "Plaintext data"); + ESP_LOG_BUFFER_HEXDUMP("Plaintext data", test_data->plaintext_data, data_size, ESP_LOG_DEBUG); ESP_ERROR_CHECK(esp_flash_write_encrypted(NULL, address, test_data->plaintext_data, data_size)); - static uint8_t read_data[128]; ESP_ERROR_CHECK(esp_flash_read(NULL, read_data, address, data_size)); - print_data_in_hex(read_data, data_size, "Encrypted data"); + + ESP_LOG_BUFFER_HEXDUMP("Encrypted data", read_data, data_size, ESP_LOG_DEBUG); } -static void key_mgr_test_xts_aes_128(void) +#if SOC_FLASH_ENCRYPTION_XTS_AES_128 +static void key_mgr_test_xts_aes_128_aes_mode(void) { static esp_key_mgr_aes_key_config_t key_config; memcpy(key_config.k2_info, (uint8_t*) test_data_xts_aes_128.k2_info, KEY_MGR_K2_INFO_SIZE); @@ -95,9 +99,27 @@ static void key_mgr_test_xts_aes_128(void) TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); test_xts_aes_key_aes_mode(&test_data_xts_aes_128); TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); - } +static void key_mgr_test_xts_aes_128_ecdh0_mode(void) +{ + static esp_key_mgr_ecdh0_key_config_t key_config; + memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); + key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + static esp_key_mgr_ecdh0_info_t ecdh0_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); + + ESP_LOG_BUFFER_HEXDUMP("K2_G", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + test_xts_aes_key_ecdh0_mode(&test_data_ecdh0); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_128 */ + +#if SOC_FLASH_ENCRYPTION_XTS_AES_256 static void key_mgr_test_xts_aes_256_aes_mode(void) { static esp_key_mgr_aes_key_config_t key_config; @@ -115,11 +137,80 @@ static void key_mgr_test_xts_aes_256_aes_mode(void) TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } -#ifdef SOC_ECDSA_SUPPORT_EXPORT_PUBKEY +static void key_mgr_test_xts_aes_256_ecdh0_mode(void) +{ + static esp_key_mgr_ecdh0_key_config_t key_config; + memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); + memcpy(key_config.k1_G[1], (uint8_t*) test_data_ecdh0.k1_G[1], KEY_MGR_ECDH0_INFO_SIZE); + key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + static esp_key_mgr_ecdh0_info_t ecdh0_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); + + ESP_LOG_BUFFER_HEXDUMP("K2_G_0", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("K2_G_1", ecdh0_info.k2_G[1], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + test_xts_aes_key_ecdh0_mode(&test_data_ecdh0); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_256 */ + +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS +static void test_xts_aes_key_random_mode(void) +{ + const esp_partition_t *partition = get_test_storage_partition(); + ESP_ERROR_CHECK(esp_partition_erase_range(partition, 0, partition->size)); + uint8_t plaintext_data[1024] = {[0 ... 1023] = 0xBE}; + const int write_size = 16; + for (int i = 0; i < sizeof(plaintext_data) / write_size; i++) { + ESP_LOGI("", " i = %d", i); + ESP_ERROR_CHECK(esp_flash_write_encrypted(NULL, partition->address + (i * write_size), plaintext_data, write_size)); + static uint8_t read_data[128]; + ESP_ERROR_CHECK(esp_partition_read(partition, write_size * i, read_data, write_size)); + TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext_data + (i * write_size), read_data, write_size); + } +} + +#if SOC_FLASH_ENCRYPTION_XTS_AES_128 +static void key_mgr_test_xts_aes_128_random_mode(void) +{ + static esp_key_mgr_random_key_config_t key_config; + key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + test_xts_aes_key_random_mode(); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_128 */ + +#if SOC_FLASH_ENCRYPTION_XTS_AES_256 +static void key_mgr_test_xts_aes_256_random_mode(void) +{ + static esp_key_mgr_random_key_config_t key_config; + key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + test_xts_aes_key_random_mode(); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_256 */ +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ +#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY +#if SOC_ECDSA_SUPPORT_EXPORT_PUBKEY extern void test_ecdsa_export_pubkey(bool is_p256, uint8_t *ecdsa_pub_x, uint8_t *ecdsa_pub_y, bool use_km_key); extern void test_ecdsa_export_pubkey_inner(bool is_p256, uint8_t *exported_pub_x, uint8_t *exported_pub_y, bool use_km_key, uint16_t *len); #endif +extern void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, bool use_km_key, ecdsa_sign_type_t k_type); +extern int test_ecdsa_verify(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, uint8_t *pub_x, uint8_t *pub_y); extern void test_ecdsa_sign_and_verify(bool is_p256, uint8_t* sha, uint8_t* pub_x, uint8_t* pub_y, bool use_km_key, ecdsa_sign_type_t k_type); /* @@ -137,11 +228,6 @@ void test_ecdsa_key_aes_mode(test_data_aes_mode_t *ecdsa_test_data, ecdsa_sign_t #endif } - -extern void test_ecdsa_sign(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, bool use_km_key, ecdsa_sign_type_t k_type); - -extern int test_ecdsa_verify(bool is_p256, uint8_t* sha, uint8_t* r_le, uint8_t* s_le, uint8_t *pub_x, uint8_t *pub_y); - void key_mgr_test_ecdsa_key(bool is_p256, ecdsa_sign_type_t k_type) { uint8_t pub_x[32] = {}; @@ -151,18 +237,17 @@ void key_mgr_test_ecdsa_key(bool is_p256, ecdsa_sign_type_t k_type) test_ecdsa_sign(is_p256, sha256_digest, r_le, s_le, 1, k_type); - print_data_in_hex(sha256_digest, sizeof(sha256_digest), "ECDSA message sha256 digest"); - print_data_in_hex(r_le, sizeof(r_le), "ECDSA signature r_le"); - print_data_in_hex(s_le, sizeof(s_le), "ECDSA signature s_le"); + ESP_LOG_BUFFER_HEXDUMP("ECDSA message sha256 digest", sha256_digest, sizeof(sha256_digest), ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("ECDSA signature r_le", r_le, sizeof(r_le), ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("ECDSA signature s_le", s_le, sizeof(s_le), ESP_LOG_DEBUG); // Export the pubkey from ECDSA peripheral uint16_t pubkey_len = 0; test_ecdsa_export_pubkey_inner(is_p256, pub_x, pub_y, 1, &pubkey_len); - print_data_in_hex(pub_x, pubkey_len, "ECDSA key pubx"); - print_data_in_hex(pub_y, pubkey_len, "ECDSA key puby"); + ESP_LOG_BUFFER_HEXDUMP("ECDSA key pubx", pub_x, pubkey_len, ESP_LOG_DEBUG); + ESP_LOG_BUFFER_HEXDUMP("ECDSA key puby", pub_y, pubkey_len, ESP_LOG_DEBUG); TEST_ASSERT_EQUAL(0, test_ecdsa_verify(is_p256, sha256_digest, r_le, s_le, pub_x, pub_y)); - } static void key_mgr_test_ecdsa_p256_aes_mode(void) @@ -172,7 +257,7 @@ static void key_mgr_test_ecdsa_p256_aes_mode(void) memcpy(key_config.k1_encrypted, (uint8_t*) test_data_ecdsa.k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); memcpy(key_config.sw_init_key, (uint8_t*) test_data_ecdsa.init_key, KEY_MGR_SW_INIT_KEY_SIZE); key_config.use_pre_generated_sw_init_key = 1; - key_config.key_type = ESP_KEY_MGR_ECDSA_KEY; + key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY; static esp_key_mgr_key_recovery_info_t key_recovery_info; TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info)); @@ -185,56 +270,16 @@ static void key_mgr_test_ecdsa_p256_aes_mode(void) TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } -static void key_mgr_test_xts_aes_128_ecdh0_mode(void) -{ - printf("\nKey Manager ECDH0 deployment: XTS_AES_128 key\n"); - static esp_key_mgr_ecdh0_key_config_t key_config; - memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); - key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; - - static esp_key_mgr_key_recovery_info_t key_recovery_info; - static esp_key_mgr_ecdh0_info_t ecdh0_info; - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); - - print_data_in_hex(ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, "K2_G"); - - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); - test_xts_aes_key_ecdh0_mode(&test_data_ecdh0); - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); -} - -static void key_mgr_test_xts_aes_256_ecdh0_mode(void) -{ - printf("\nKey Manager ECDH0 deployment: XTS_AES_256 key\n"); - static esp_key_mgr_ecdh0_key_config_t key_config; - memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); - memcpy(key_config.k1_G[1], (uint8_t*) test_data_ecdh0.k1_G[1], KEY_MGR_ECDH0_INFO_SIZE); - key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY; - - static esp_key_mgr_key_recovery_info_t key_recovery_info; - static esp_key_mgr_ecdh0_info_t ecdh0_info; - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); - - print_data_in_hex(ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, "K2_G_0"); - print_data_in_hex(ecdh0_info.k2_G[1], KEY_MGR_ECDH0_INFO_SIZE, "K2_G_1"); - - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); - test_xts_aes_key_ecdh0_mode(&test_data_ecdh0); - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); -} - static void key_mgr_test_ecdsa_ecdh0_mode(void) { - printf("\nKey Manager ECDH0 deployment: ECDSA_256 key\n"); static esp_key_mgr_ecdh0_key_config_t key_config; memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); - key_config.key_type = ESP_KEY_MGR_ECDSA_KEY; + key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY; static esp_key_mgr_key_recovery_info_t key_recovery_info; static esp_key_mgr_ecdh0_info_t ecdh0_info; TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); - - print_data_in_hex(ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, "K2_G"); + ESP_LOG_BUFFER_HEXDUMP("K2_G", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG); TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); #ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE @@ -246,72 +291,142 @@ static void key_mgr_test_ecdsa_ecdh0_mode(void) static void key_mgr_test_ecdsa_random_mode(void) { - printf("\nKey Manager Random deployment: ECDSA_256 key\n"); static esp_key_mgr_random_key_config_t key_config; - key_config.key_type = ESP_KEY_MGR_ECDSA_KEY; + key_config.key_type = ESP_KEY_MGR_ECDSA_256_KEY; static esp_key_mgr_key_recovery_info_t key_recovery_info; TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info)); TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); - #ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_DETERMINISITIC); #endif key_mgr_test_ecdsa_key(1, ECDSA_K_TYPE_TRNG); - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } +#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */ -#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY +extern esp_err_t hmac_calculate(uint32_t key_id, const void *message, size_t message_len, uint8_t *hmac); -static void test_xts_aes_key_random_mode(void) +static void key_mgr_test_hmac_key_aes_mode(test_data_aes_mode_t *test_data) { - const esp_partition_t *partition = get_test_storage_partition(); - ESP_ERROR_CHECK(esp_partition_erase_range(partition, 0, partition->size)); - uint8_t plaintext_data[1024] = {[0 ... 1023] = 0xBE}; - const int write_size = 16; - for (int i = 0; i < sizeof(plaintext_data) / write_size; i++) { - printf("\n i = %d\n", i); - ESP_ERROR_CHECK(esp_flash_write_encrypted(NULL, partition->address + (i * write_size), plaintext_data, write_size)); - static uint8_t read_data[128]; - ESP_ERROR_CHECK(esp_partition_read(partition, write_size * i, read_data, write_size)); - TEST_ASSERT_EQUAL_HEX8_ARRAY(plaintext_data + (i * write_size), read_data, write_size); - } + uint8_t hmac[32] = {0}; + TEST_ASSERT_EQUAL(ESP_OK, hmac_calculate(HMAC_KEY_KM, test_data->hmac_test_data.message, sizeof(test_data->hmac_test_data.message), hmac)); + TEST_ASSERT_EQUAL_HEX8_ARRAY(test_data->hmac_test_data.hmac_result, hmac, sizeof(test_data->hmac_test_data.hmac_result)); +} + +static void key_mgr_test_hmac_key_ecdh0_mode(const uint8_t *message, size_t message_len) +{ + uint8_t hmac[32] = {0}; + TEST_ASSERT_EQUAL(ESP_OK, hmac_calculate(HMAC_KEY_KM, message, message_len, hmac)); + // We cannot verify the result here as the HMAC key deployed is unknown. +} + +static void key_mgr_test_hmac_key_aes_random_mode(const uint8_t *message, size_t message_len) +{ + uint8_t hmac[32] = {0}; + TEST_ASSERT_EQUAL(ESP_OK, hmac_calculate(HMAC_KEY_KM, message, message_len, hmac)); + // We cannot verify the result here as the HMAC key deployed is unknown. } -static void key_mgr_test_xts_aes_128_random_mode(void) +static void key_mgr_test_hmac_aes_mode(void) { - static esp_key_mgr_random_key_config_t key_config; - key_config.key_type = ESP_KEY_MGR_XTS_AES_128_KEY; + static esp_key_mgr_aes_key_config_t key_config; + memcpy(key_config.k2_info, (uint8_t*) test_data_hmac.k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config.k1_encrypted, (uint8_t*) test_data_hmac.k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config.sw_init_key, (uint8_t*) test_data_hmac.init_key, KEY_MGR_SW_INIT_KEY_SIZE); + key_config.use_pre_generated_sw_init_key = 1; + key_config.key_type = ESP_KEY_MGR_HMAC_KEY; static esp_key_mgr_key_recovery_info_t key_recovery_info; - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info)); - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); - test_xts_aes_key_random_mode(); - TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info)); + ESP_LOG_BUFFER_HEXDUMP("key_info", key_recovery_info.key_info, sizeof(esp_key_mgr_key_info_t), ESP_LOG_DEBUG); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + key_mgr_test_hmac_key_aes_mode(&test_data_hmac); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } -static void key_mgr_test_xts_aes_256_random_mode(void) +static void key_mgr_test_hmac_ecdh0_mode(void) +{ + static esp_key_mgr_ecdh0_key_config_t key_config; + memcpy(key_config.k1_G[0], (uint8_t*) test_data_ecdh0.k1_G[0], KEY_MGR_ECDH0_INFO_SIZE); + key_config.key_type = ESP_KEY_MGR_HMAC_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + static esp_key_mgr_ecdh0_info_t ecdh0_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_ecdh0_mode(&key_config, &key_recovery_info, &ecdh0_info)); + + ESP_LOG_BUFFER_HEXDUMP("K2_G", ecdh0_info.k2_G[0], KEY_MGR_ECDH0_INFO_SIZE, ESP_LOG_DEBUG); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + key_mgr_test_hmac_key_ecdh0_mode(test_data_hmac.hmac_test_data.message, sizeof(test_data_hmac.hmac_test_data.message)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} + +static void key_mgr_test_hmac_random_mode(void) { static esp_key_mgr_random_key_config_t key_config; - key_config.key_type = ESP_KEY_MGR_XTS_AES_256_KEY; + key_config.key_type = ESP_KEY_MGR_HMAC_KEY; static esp_key_mgr_key_recovery_info_t key_recovery_info; TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_random_mode(&key_config, &key_recovery_info)); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); - test_xts_aes_key_random_mode(); + key_mgr_test_hmac_key_aes_random_mode(test_data_hmac.hmac_test_data.message, sizeof(test_data_hmac.hmac_test_data.message)); TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); } -#endif +#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +extern esp_err_t esp_ds_sign(const void *message, + const esp_ds_data_t *data, + uint32_t key_id, + void *signature); + +static void key_mgr_test_ds_key_aes_mode(test_data_aes_mode_t *test_data) +{ + esp_ds_data_t esp_ds_data = {0}; + esp_ds_data.rsa_length = test_data->ds_test_data.ds_key_size / 32 - 1; + memcpy(esp_ds_data.iv, test_data->ds_test_data.ds_encrypted_input_params_iv, sizeof(esp_ds_data.iv)); + memcpy(esp_ds_data.c, test_data->ds_test_data.ds_encrypted_input_params, sizeof(esp_ds_data.c)); + + uint8_t signature[4096 / 8] = {0}; // Max possible RSA signature size + + esp_err_t ds_r = esp_ds_sign(test_data->ds_test_data.ds_message, + &esp_ds_data, + HMAC_KEY_KM, + signature); + + TEST_ASSERT_EQUAL(ESP_OK, ds_r); + TEST_ASSERT_EQUAL_HEX8_ARRAY(test_data->ds_test_data.ds_result, signature, sizeof(test_data->ds_test_data.ds_result)); +} + +static void key_mgr_test_ds_aes_mode(void) +{ + static esp_key_mgr_aes_key_config_t key_config; + memcpy(key_config.k2_info, (uint8_t*) test_data_ds.k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config.k1_encrypted, (uint8_t*) test_data_ds.k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config.sw_init_key, (uint8_t*) test_data_ds.init_key, KEY_MGR_SW_INIT_KEY_SIZE); + key_config.use_pre_generated_sw_init_key = 1; + key_config.key_type = ESP_KEY_MGR_DS_KEY; + + static esp_key_mgr_key_recovery_info_t key_recovery_info; + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deploy_key_in_aes_mode(&key_config, &key_recovery_info)); + + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_activate_key(&key_recovery_info)); + key_mgr_test_ds_key_aes_mode(&test_data_ds); + TEST_ASSERT_EQUAL(ESP_OK, esp_key_mgr_deactivate_key(key_recovery_info.key_type)); +} +#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */ TEST_GROUP(key_manager); TEST_SETUP(key_manager) { test_utils_record_free_mem(); - TEST_ESP_OK(test_utils_set_leak_level(700, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL)); + TEST_ESP_OK(test_utils_set_leak_level(800, ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_GENERAL)); } TEST_TEAR_DOWN(key_manager) @@ -320,55 +435,124 @@ TEST_TEAR_DOWN(key_manager) test_utils_get_leak_level(ESP_LEAK_TYPE_CRITICAL, ESP_COMP_LEAK_ALL)); } +#if SOC_KEY_MANAGER_FE_KEY_DEPLOY +#if SOC_FLASH_ENCRYPTION_XTS_AES_128 TEST(key_manager, xts_aes_128_key_aes_deployment) { - key_mgr_test_xts_aes_128(); + key_mgr_test_xts_aes_128_aes_mode(); } +TEST(key_manager, xts_key_128_ecdh0_deployment) +{ + key_mgr_test_xts_aes_128_ecdh0_mode(); +} + +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS +TEST(key_manager, xts_key_128_random_deployment) +{ + key_mgr_test_xts_aes_128_random_mode(); +} +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_128 */ + +#if SOC_FLASH_ENCRYPTION_XTS_AES_256 TEST(key_manager, xts_aes_256_key_aes_deployment) { key_mgr_test_xts_aes_256_aes_mode(); } -TEST(key_manager, ecdsa_key_aes_deployment) +TEST(key_manager, xts_key_256_ecdh0_deployment) +{ + key_mgr_test_xts_aes_256_ecdh0_mode(); +} + +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS +TEST(key_manager, xts_key_256_random_deployment) +{ + key_mgr_test_xts_aes_256_random_mode(); +} +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_256 */ +#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY +TEST(key_manager, ecdsa_p256_key_aes_deployment) { key_mgr_test_ecdsa_p256_aes_mode(); } -TEST(key_manager, xts_key_ecdh0_deployment) -{ - key_mgr_test_xts_aes_128_ecdh0_mode(); - key_mgr_test_xts_aes_256_ecdh0_mode(); -} - -TEST(key_manager, ecdsa_key_ecdh0_deployment) +TEST(key_manager, ecdsa_p256_key_ecdh0_deployment) { key_mgr_test_ecdsa_ecdh0_mode(); } -TEST(key_manager, ecdsa_key_random_deployment) +TEST(key_manager, ecdsa_p256_key_random_deployment) { key_mgr_test_ecdsa_random_mode(); } +#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */ -#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS -TEST(key_manager, xts_key_random_deployment) +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY +TEST(key_manager, hmac_key_aes_deployment) { - key_mgr_test_xts_aes_128_random_mode(); - key_mgr_test_xts_aes_256_random_mode(); + key_mgr_test_hmac_aes_mode(); } -#endif + +TEST(key_manager, hmac_key_ecdh0_deployment) +{ + key_mgr_test_hmac_ecdh0_mode(); +} + +TEST(key_manager, hmac_key_random_deployment) +{ + key_mgr_test_hmac_random_mode(); +} +#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY +TEST(key_manager, ds_key_aes_deployment) +{ + key_mgr_test_ds_aes_mode(); +} +#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */ TEST_GROUP_RUNNER(key_manager) { +#if SOC_KEY_MANAGER_FE_KEY_DEPLOY +#if SOC_FLASH_ENCRYPTION_XTS_AES_128 RUN_TEST_CASE(key_manager, xts_aes_128_key_aes_deployment); - RUN_TEST_CASE(key_manager, xts_aes_256_key_aes_deployment); - RUN_TEST_CASE(key_manager, ecdsa_key_aes_deployment); - RUN_TEST_CASE(key_manager, xts_key_ecdh0_deployment); - RUN_TEST_CASE(key_manager, ecdsa_key_ecdh0_deployment); - RUN_TEST_CASE(key_manager, ecdsa_key_random_deployment); + RUN_TEST_CASE(key_manager, xts_key_128_ecdh0_deployment); #if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS - RUN_TEST_CASE(key_manager, xts_key_random_deployment); -#endif + // This tests expects Flash encryption to be enabled as the test compares the decrypted flash data with the plaintext data + RUN_TEST_CASE(key_manager, xts_key_128_random_deployment); +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_128 */ +#if SOC_FLASH_ENCRYPTION_XTS_AES_256 + RUN_TEST_CASE(key_manager, xts_aes_256_key_aes_deployment); + RUN_TEST_CASE(key_manager, xts_key_256_ecdh0_deployment); +#if CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS + RUN_TEST_CASE(key_manager, xts_key_256_random_deployment); +#endif /* CONFIG_CRYPTO_TEST_APP_ENABLE_FPGA_TESTS */ +#endif /* SOC_FLASH_ENCRYPTION_XTS_AES_256 */ +#endif /* SOC_KEY_MANAGER_FE_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY + RUN_TEST_CASE(key_manager, ecdsa_p256_key_aes_deployment); + RUN_TEST_CASE(key_manager, ecdsa_p256_key_ecdh0_deployment); + RUN_TEST_CASE(key_manager, ecdsa_p256_key_random_deployment); +#endif /* SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_HMAC_KEY_DEPLOY + RUN_TEST_CASE(key_manager, hmac_key_aes_deployment); + RUN_TEST_CASE(key_manager, hmac_key_ecdh0_deployment); + RUN_TEST_CASE(key_manager, hmac_key_random_deployment); +#endif /* SOC_KEY_MANAGER_HMAC_KEY_DEPLOY */ + +#if SOC_KEY_MANAGER_DS_KEY_DEPLOY + RUN_TEST_CASE(key_manager, ds_key_aes_deployment); + // Verifying deployment of a DS key using the ECDH0 and Random mode of the Key Manager + // is not possible as the deployed DS key is not known to user in these modes to + // pre-generate the ciphertext input data. +#endif /* SOC_KEY_MANAGER_DS_KEY_DEPLOY */ } diff --git a/components/hal/test_apps/crypto/main/mpi/test_mpi.c b/components/hal/test_apps/crypto/main/mpi/test_mpi.c index 029abe5343..d0c971e9f1 100644 --- a/components/hal/test_apps/crypto/main/mpi/test_mpi.c +++ b/components/hal/test_apps/crypto/main/mpi/test_mpi.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -19,17 +19,13 @@ #include "hal/mpi_hal.h" #include "hal/mpi_ll.h" #include "mpi_params.h" +#include "esp_crypto_periph_clk.h" #define _DEBUG_ 0 static void esp_mpi_enable_hardware_hw_op( void ) { - /* Enable RSA hardware */ - MPI_RCC_ATOMIC() { - mpi_ll_enable_bus_clock(true); - mpi_ll_reset_register(); - } - + esp_crypto_mpi_enable_periph_clk(true); mpi_hal_enable_hardware_hw_op(); } @@ -37,11 +33,7 @@ static void esp_mpi_enable_hardware_hw_op( void ) static void esp_mpi_disable_hardware_hw_op( void ) { mpi_hal_disable_hardware_hw_op(); - - /* Disable RSA hardware */ - MPI_RCC_ATOMIC() { - mpi_ll_enable_bus_clock(false); - } + esp_crypto_mpi_enable_periph_clk(false); } diff --git a/components/hal/test_apps/crypto/main/sha/sha_block.c b/components/hal/test_apps/crypto/main/sha/sha_block.c index 852e0efe33..e18745f25d 100644 --- a/components/hal/test_apps/crypto/main/sha/sha_block.c +++ b/components/hal/test_apps/crypto/main/sha/sha_block.c @@ -12,7 +12,7 @@ #include "soc/periph_defs.h" #include "esp_private/periph_ctrl.h" -#include "esp_private/esp_crypto_lock_internal.h" +#include "esp_crypto_periph_clk.h" #include "hal/sha_hal.h" #include "hal/sha_ll.h" #include "sha_block.h" @@ -68,10 +68,7 @@ static void sha1_update_block(sha1_ctx* ctx, esp_sha_type sha_type, const unsign if ( (ilen >= 64) || local_len) { /* Enable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(true); - sha_ll_reset_register(); - } + esp_crypto_sha_enable_periph_clk(true); sha_hal_wait_idle(); sha_hal_set_mode(sha_type); @@ -103,9 +100,7 @@ static void sha1_update_block(sha1_ctx* ctx, esp_sha_type sha_type, const unsign sha_hal_read_digest(sha_type, ctx->state); /* Disable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(false); - } + esp_crypto_sha_enable_periph_clk(false); } if ( ilen > 0 ) { @@ -172,10 +167,7 @@ static void sha256_update_block(sha256_ctx* ctx, esp_sha_type sha_type, const un if ( (ilen >= 64) || local_len) { /* Enable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(true); - sha_ll_reset_register(); - } + esp_crypto_sha_enable_periph_clk(true); sha_hal_wait_idle(); sha_hal_set_mode(sha_type); @@ -207,9 +199,7 @@ static void sha256_update_block(sha256_ctx* ctx, esp_sha_type sha_type, const un sha_hal_read_digest(sha_type, ctx->state); /* Disable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(false); - } + esp_crypto_sha_enable_periph_clk(false); } if ( ilen > 0 ) { @@ -321,10 +311,7 @@ static void sha512_update_block(sha512_ctx* ctx, esp_sha_type sha_type, const un if ( (ilen >= 128) || local_len) { /* Enable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(true); - sha_ll_reset_register(); - } + esp_crypto_sha_enable_periph_clk(true); sha_hal_wait_idle(); sha_hal_set_mode(sha_type); @@ -360,9 +347,7 @@ static void sha512_update_block(sha512_ctx* ctx, esp_sha_type sha_type, const un sha_hal_read_digest(sha_type, ctx->state); /* Disable peripheral module */ - SHA_RCC_ATOMIC() { - sha_ll_enable_bus_clock(false); - } + esp_crypto_sha_enable_periph_clk(false); } if ( ilen > 0 ) { diff --git a/components/mbedtls/port/bignum/bignum_alt.c b/components/mbedtls/port/bignum/bignum_alt.c index ceb263b8d5..5717faf3b4 100644 --- a/components/mbedtls/port/bignum/bignum_alt.c +++ b/components/mbedtls/port/bignum/bignum_alt.c @@ -24,8 +24,6 @@ void esp_mpi_enable_hardware_hw_op( void ) void esp_mpi_disable_hardware_hw_op( void ) { - mpi_hal_disable_hardware_hw_op(); - /* Disable RSA hardware */ esp_crypto_mpi_enable_periph_clk(false); diff --git a/components/mbedtls/test_apps/main/CMakeLists.txt b/components/mbedtls/test_apps/main/CMakeLists.txt index 7059105e28..a99a7c0520 100644 --- a/components/mbedtls/test_apps/main/CMakeLists.txt +++ b/components/mbedtls/test_apps/main/CMakeLists.txt @@ -7,7 +7,7 @@ set(TEST_CRTS "crts/server_cert_chain.pem" idf_component_register(SRC_DIRS "." PRIV_INCLUDE_DIRS "." - PRIV_REQUIRES efuse cmock test_utils mbedtls esp_timer unity spi_flash esp_psram + PRIV_REQUIRES efuse cmock test_utils mbedtls esp_timer unity spi_flash esp_psram esp_security EMBED_TXTFILES ${TEST_CRTS} WHOLE_ARCHIVE) diff --git a/components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c b/components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c index 1325e419c2..8cdc46fc73 100644 --- a/components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c +++ b/components/mbedtls/test_apps/main/test_mbedtls_ecdsa.c @@ -205,20 +205,20 @@ const uint8_t ecdsa192_sign_pub_y[] = { /* Big endian */ const uint8_t init_key[] = { - 0x4d, 0x21, 0x64, 0x21, 0x8f, 0xa2, 0xe3, 0xa0, 0xab, 0x74, 0xb5, 0xab, 0x17, 0x9a, 0x5d, 0x08, 0x58, 0xf4, 0x22, 0x03, 0xbd, 0x52, 0xe7, 0x88, 0x3c, 0x22, 0x0f, 0x95, 0x89, 0x70, 0xe1, 0x93 + 0xee, 0x89, 0x95, 0xda, 0x3c, 0x8a, 0x43, 0x83, 0xa9, 0x4b, 0x25, 0x5b, 0x04, 0x7e, 0xf1, 0x57, 0xb8, 0xe8, 0x06, 0x45, 0x87, 0x76, 0xee, 0x1b, 0x4e, 0x2e, 0x55, 0xa7, 0x1f, 0x25, 0xe1, 0x94, }; /* Big endian */ const uint8_t k2_info[] = { - 0xd8, 0xcd, 0x04, 0x45, 0xb4, 0x45, 0xc4, 0x15, 0xf6, 0x40, 0x1c, 0x7d, 0x90, 0x1b, 0x99, 0xa4, 0x79, 0x6b, 0xfb, 0x5b, 0x2a, 0x40, 0x60, 0xe1, 0xc1, 0xe1, 0x48, 0xcd, 0x46, 0x6b, 0x9b, 0x48, 0xda, 0x7a, 0x70, 0x0a, 0x78, 0x0b, 0x9d, 0xf9, 0x0e, 0xed, 0x91, 0xfc, 0xa5, 0xc2, 0x96, 0x05, 0x91, 0x76, 0xdb, 0x68, 0x84, 0x5d, 0x5e, 0x5b, 0xa6, 0xe9, 0x6b, 0x3b, 0x12, 0x50, 0x05, 0xc3 + 0x8f, 0x96, 0x33, 0x47, 0xe1, 0xa5, 0x57, 0xe9, 0x2a, 0x51, 0xa9, 0xbe, 0x48, 0x84, 0x25, 0x4e, 0x6f, 0x50, 0x1c, 0x45, 0xdb, 0xb6, 0xfa, 0xeb, 0x35, 0xd2, 0x27, 0x91, 0x3f, 0x67, 0x57, 0xd9, 0xcb, 0x55, 0xe4, 0x2b, 0x18, 0x16, 0xe7, 0xce, 0x6c, 0xf2, 0x58, 0x71, 0x17, 0x76, 0x2a, 0x86, 0x05, 0xe7, 0x37, 0x45, 0x71, 0x34, 0xca, 0xaf, 0x60, 0x07, 0xdf, 0xf4, 0xd2, 0xee, 0x3d, 0x4b, }; -const uint8_t k1_ecdsa256_xts_encrypt[] = { - 0x9f, 0x64, 0x80, 0x16, 0xa3, 0xab, 0x26, 0x64, 0x9b, 0xe6, 0x86, 0xcd, 0xf5, 0x14, 0x11, 0xb9, 0xb0, 0xe9, 0x87, 0xf6, 0xfe, 0x1b, 0x98, 0x0f, 0x9c, 0x3e, 0x21, 0xa7, 0xfa, 0x53, 0x47, 0x60 +const uint8_t k1_ecdsa256_encrypt[] = { + 0xcb, 0x8b, 0x74, 0xfb, 0xdf, 0x8f, 0x52, 0x0a, 0xff, 0x00, 0xf2, 0x83, 0xfa, 0xdb, 0x34, 0x18, 0xbe, 0xae, 0xe2, 0x58, 0x75, 0x94, 0x69, 0x89, 0xdd, 0x72, 0xdb, 0x04, 0x2c, 0xad, 0x4e, 0x3a, }; -const uint8_t k1_ecdsa192_xts_encrypt[] = { - 0x54, 0xf5, 0x97, 0xb8, 0xff, 0x1d, 0x34, 0x85, 0x8d, 0xf1, 0x43, 0xaa, 0xc0, 0x0f, 0xe2, 0x4d, 0x0b, 0xee, 0xdd, 0x89, 0x31, 0x39, 0x1b, 0xbe, 0x9b, 0x55, 0x53, 0xe0, 0xc7, 0xd9, 0x79, 0xaf +const uint8_t k1_ecdsa192_encrypt[] = { + 0xde, 0xe9, 0x9c, 0x89, 0xf2, 0x3b, 0x29, 0xb7, 0x9e, 0x33, 0xec, 0x76, 0x75, 0x2f, 0x3e, 0xab, 0x61, 0x06, 0x4d, 0xea, 0x05, 0x2c, 0xc3, 0x29, 0x1c, 0x7f, 0xb7, 0x3d, 0xb8, 0x1c, 0xb2, 0x17, }; void test_ecdsa_sign(mbedtls_ecp_group_id id, const uint8_t *hash, const uint8_t *pub_x, const uint8_t *pub_y, bool is_deterministic, int efuse_key_block) @@ -273,8 +273,47 @@ TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][efuse_ke test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, false, SECP256R1_EFUSE_BLOCK); } -#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE +#if SOC_KEY_MANAGER_SUPPORTED +static void deploy_key_in_key_manager(const uint8_t *k1_encrypted, esp_key_mgr_key_type_t key_type) { + esp_key_mgr_aes_key_config_t *key_config = NULL; + key_config = heap_caps_calloc(1, sizeof(esp_key_mgr_aes_key_config_t), MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(key_config); + key_config->key_type = key_type; + key_config->use_pre_generated_sw_init_key = 1; + memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); + memcpy(key_config->k1_encrypted[0], (uint8_t*) k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); + memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); + + esp_key_mgr_key_recovery_info_t *key_info = NULL; + key_info = heap_caps_calloc(1, sizeof(esp_key_mgr_key_recovery_info_t), MALLOC_CAP_INTERNAL); + TEST_ASSERT_NOT_NULL(key_info); + + esp_key_mgr_deploy_key_in_aes_mode(key_config, key_info); + + ESP_LOGI(TAG, "Key deployed successfully"); + esp_key_mgr_activate_key(key_info); + + free(key_info); + free(key_config); +} + +TEST_CASE("mbedtls ECDSA signature generation on SECP192R1", "[mbedtls][key_manager_key]") +{ + deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY); + test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY); +} + +TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][key_manager_key]") +{ + deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY); + test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY); +} +#endif /* SOC_KEY_MANAGER_SUPPORTED */ + +#ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP192R1", "[mbedtls][efuse_key]") { if (!ecdsa_ll_is_deterministic_mode_supported()) { @@ -293,48 +332,32 @@ TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP256R1", "[mbe } } +#if SOC_KEY_MANAGER_SUPPORTED +TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP192R1", "[mbedtls][key_manager_key]") +{ + if (!ecdsa_ll_is_deterministic_mode_supported()) { + ESP_LOGI(TAG, "Skipping test because ECDSA deterministic mode is not supported."); + } else { + deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY); + test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, true, USE_ECDSA_KEY_FROM_KEY_MANAGER); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY); + } +} + +TEST_CASE("mbedtls ECDSA deterministic signature generation on SECP256R1", "[mbedtls][key_manager_key]") +{ + if (!ecdsa_ll_is_deterministic_mode_supported()) { + ESP_LOGI(TAG, "Skipping test because ECDSA deterministic mode is not supported."); + } else { + deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY); + test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, true, USE_ECDSA_KEY_FROM_KEY_MANAGER); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY); + } +} +#endif /* SOC_KEY_MANAGER_SUPPORTED */ #endif /* SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE */ -#if SOC_KEY_MANAGER_SUPPORTED -void deploy_key_in_key_manager(const uint8_t *k1_encrypted) { - esp_key_mgr_aes_key_config_t *key_config; - - key_config = heap_caps_calloc(1, sizeof(esp_key_mgr_aes_key_config_t), MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(key_config); - memcpy(key_config->k2_info, (uint8_t*) k2_info, KEY_MGR_K2_INFO_SIZE); - memcpy(key_config->k1_encrypted[0], (uint8_t*) k1_encrypted, KEY_MGR_K1_ENCRYPTED_SIZE); - memcpy(key_config->sw_init_key, (uint8_t*) init_key, KEY_MGR_SW_INIT_KEY_SIZE); - key_config->use_pre_generated_sw_init_key = 1; - key_config->key_type = ESP_KEY_MGR_ECDSA_KEY; - - esp_key_mgr_key_recovery_info_t *key_info; - key_info = heap_caps_calloc(1, sizeof(esp_key_mgr_key_recovery_info_t), MALLOC_CAP_INTERNAL); - TEST_ASSERT_NOT_NULL(key_config); - - esp_key_mgr_deploy_key_in_aes_mode(key_config, key_info); - printf("\nkey deployed successfully\n"); - esp_key_mgr_activate_key(key_info); - free(key_info); - free(key_config); -} - -TEST_CASE("mbedtls ECDSA signature generation on SECP192R1", "[mbedtls][key_manager_key]") -{ - deploy_key_in_key_manager(k1_ecdsa192_xts_encrypt); - test_ecdsa_sign(MBEDTLS_ECP_DP_SECP192R1, sha, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER); - esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY); -} - -TEST_CASE("mbedtls ECDSA signature generation on SECP256R1", "[mbedtls][key_manager_key]") -{ - deploy_key_in_key_manager(k1_ecdsa256_xts_encrypt); - test_ecdsa_sign(MBEDTLS_ECP_DP_SECP256R1, sha, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, false, USE_ECDSA_KEY_FROM_KEY_MANAGER); - esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY); -} -#endif - #ifdef SOC_ECDSA_SUPPORT_EXPORT_PUBKEY - void test_ecdsa_export_pubkey(mbedtls_ecp_group_id id, const uint8_t *pub_x, const uint8_t *pub_y, int efuse_key_block) { uint8_t export_pub_x[32] = {0}; @@ -344,9 +367,14 @@ void test_ecdsa_export_pubkey(mbedtls_ecp_group_id id, const uint8_t *pub_x, con esp_ecdsa_pk_conf_t pk_conf = { .grp_id = id, .load_pubkey = true, - .efuse_block = efuse_key_block, }; + if (efuse_key_block == USE_ECDSA_KEY_FROM_KEY_MANAGER) { + pk_conf.use_km_key = true; + } else { + pk_conf.efuse_block = efuse_key_block; + } + if (id == MBEDTLS_ECP_DP_SECP192R1) { len = 24; } else if (id == MBEDTLS_ECP_DP_SECP256R1) { @@ -382,18 +410,17 @@ TEST_CASE("mbedtls ECDSA export public key on SECP256R1", "[mbedtls][efuse_key]" #if SOC_KEY_MANAGER_SUPPORTED TEST_CASE("mbedtls ECDSA export public key on SECP192R1", "[mbedtls][key_manager_key]") { - deploy_key_in_key_manager(k1_ecdsa192_xts_encrypt); + deploy_key_in_key_manager(k1_ecdsa192_encrypt, ESP_KEY_MGR_ECDSA_192_KEY); test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP192R1, ecdsa192_sign_pub_x, ecdsa192_sign_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER); - esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_192_KEY); } TEST_CASE("mbedtls ECDSA export public key on SECP256R1", "[mbedtls][key_manager_key]") { - deploy_key_in_key_manager(k1_ecdsa256_xts_encrypt); + deploy_key_in_key_manager(k1_ecdsa256_encrypt, ESP_KEY_MGR_ECDSA_256_KEY); test_ecdsa_export_pubkey(MBEDTLS_ECP_DP_SECP256R1, ecdsa256_sign_pub_x, ecdsa256_sign_pub_y, USE_ECDSA_KEY_FROM_KEY_MANAGER); - esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_KEY); + esp_key_mgr_deactivate_key(ESP_KEY_MGR_ECDSA_256_KEY); } #endif #endif /* SOC_ECDSA_SUPPORT_EXPORT_PUBKEY */ - #endif /* CONFIG_MBEDTLS_HARDWARE_ECDSA_SIGN */ diff --git a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in index 03b766da04..d23b2d83e6 100644 --- a/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c5/include/soc/Kconfig.soc_caps.in @@ -239,6 +239,14 @@ config SOC_RNG_SUPPORTED bool default y +config SOC_KEY_MANAGER_SUPPORTED + bool + default y + +config SOC_HUK_SUPPORTED + bool + default y + config SOC_MODEM_CLOCK_SUPPORTED bool default y @@ -255,6 +263,10 @@ config SOC_PM_SUPPORTED bool default y +config SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED + bool + default y + config SOC_SPIRAM_SUPPORTED bool default y @@ -1011,6 +1023,10 @@ config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION bool default y +config SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + bool + default y + config SOC_PARLIO_SUPPORT_SLEEP_RETENTION bool default y @@ -1219,6 +1235,10 @@ config SOC_SPI_MEM_SUPPORT_TIMING_TUNING bool default y +config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + bool + default y + config SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY bool default y @@ -1383,6 +1403,14 @@ config SOC_EFUSE_ECDSA_KEY_P384 bool default y +config SOC_HUK_MEM_NEEDS_RECHARGE + bool + default y + +config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT + bool + default y + config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY bool default y @@ -1391,6 +1419,14 @@ config SOC_KEY_MANAGER_FE_KEY_DEPLOY bool default y +config SOC_KEY_MANAGER_HMAC_KEY_DEPLOY + bool + default y + +config SOC_KEY_MANAGER_DS_KEY_DEPLOY + bool + default y + config SOC_SECURE_BOOT_V2_RSA bool default y @@ -1441,11 +1477,11 @@ config SOC_PSRAM_ENCRYPTION_XTS_AES_256 config SOC_RECOVERY_BOOTLOADER_SUPPORTED bool - default n + default y config SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED bool - default n + default y config SOC_APM_CTRL_FILTER_SUPPORTED bool @@ -1455,6 +1491,18 @@ config SOC_APM_LP_APM0_SUPPORTED bool default y +config SOC_APM_CPU_APM_SUPPORTED + bool + default y + +config SOC_APM_SUPPORT_LP_TEE_CTRL + bool + default y + +config SOC_APM_SUPPORT_CTRL_CFG_LOCK + bool + default y + config SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL bool default y diff --git a/components/soc/esp32c5/include/soc/apm_defs.h b/components/soc/esp32c5/include/soc/apm_defs.h new file mode 100644 index 0000000000..0095add7b4 --- /dev/null +++ b/components/soc/esp32c5/include/soc/apm_defs.h @@ -0,0 +1,127 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of paths for each supported APM controller */ +#define APM_CTRL_HP_APM_PATH_NUM (5) +#define APM_CTRL_LP_APM0_PATH_NUM (1) +#define APM_CTRL_LP_APM_PATH_NUM (2) +#define APM_CTRL_CPU_APM_PATH_NUM (2) +/* Number of regions for each supported APM controller */ +#define APM_CTRL_HP_APM_REGION_NUM (16) +#define APM_CTRL_LP_APM0_REGION_NUM (8) +#define APM_CTRL_LP_APM_REGION_NUM (8) +#define APM_CTRL_CPU_APM_REGION_NUM (8) + +/* Register offset for TEE mode control */ +#define APM_TEE_MODE_CTRL_OFFSET (0x04) +/* Register offset between TEE ctrl periph registers */ +#define APM_TEE_PERI_CTRL_OFFSET (0x04) +/* Register offset between region bound address registers */ +#define APM_REGION_ADDR_OFFSET (0x0C) +/* Register offset between region pms attribute registers */ +#define APM_REGION_ATTR_OFFSET (0x0C) +/* Register offset between exception info registers */ +#define APM_EXCP_INFO_OFFSET (0x10) + +/* Bit to clear exception status */ +#define APM_EXCP_STATUS_CLR_BIT (BIT(0)) +/* Bit to lock TEE mode */ +#define APM_TEE_MODE_LOCK_BIT (BIT(2)) +/* Bit to lock region pms attributes */ +#define APM_REGION_LOCK_BIT (BIT(11)) + +/* APM controller masters mask */ +#define APM_MASTER_MASK_ALL (0x03CE017FU) +/* HP-TEE controller peripherals mask */ +#define APM_TEE_HP_PERIPH_MASK_ALL (0x0017FF7FFC7DFEEFULL) +/* LP-TEE controller peripherals mask */ +#define APM_TEE_LP_PERIPH_MASK_ALL (0x0007B4FFULL) + +/** + * @brief HP-TEE Controller Peripherals + */ +typedef enum { + APM_TEE_HP_PERIPH_UART0 = 0, /*!< UART0 */ + APM_TEE_HP_PERIPH_UART1, /*!< UART1 */ + APM_TEE_HP_PERIPH_UHCI0, /*!< UHCI0 */ + APM_TEE_HP_PERIPH_I2C_EXT0, /*!< I2C0 */ + APM_TEE_HP_PERIPH_I2S = 5, /*!< I2S */ + APM_TEE_HP_PERIPH_PARL_IO, /*!< Parallel IO */ + APM_TEE_HP_PERIPH_PWM, /*!< PWM */ + APM_TEE_HP_PERIPH_LEDC = 9, /*!< LED Control */ + APM_TEE_HP_PERIPH_TWAI0, /*!< TWAI0 */ + APM_TEE_HP_PERIPH_USB_SJ, /*!< USB Serial JTAG */ + APM_TEE_HP_PERIPH_RMT, /*!< RMT */ + APM_TEE_HP_PERIPH_GDMA, /*!< GDMA */ + APM_TEE_HP_PERIPH_REGDMA, /*!< REGDMA */ + APM_TEE_HP_PERIPH_ETM, /*!< Event Task Matrix */ + APM_TEE_HP_PERIPH_INTMTX, /*!< Interrupt Matrix */ + APM_TEE_HP_PERIPH_APB_ADC = 18, /*!< ADC */ + APM_TEE_HP_PERIPH_TG0, /*!< Timer Group 0 */ + APM_TEE_HP_PERIPH_TG1, /*!< Timer Group 1 */ + APM_TEE_HP_PERIPH_SYSTIMER, /*!< Systimer */ + APM_TEE_HP_PERIPH_MISC, /*!< Misc */ + APM_TEE_HP_PERIPH_PVT_MON = 26, /*!< PVT Monitor */ + APM_TEE_HP_PERIPH_PCNT, /*!< Pulse Counter */ + APM_TEE_HP_PERIPH_IOMUX, /*!< IO MUX */ + APM_TEE_HP_PERIPH_PSRAM_MON, /*!< PSRAM Monitor */ + APM_TEE_HP_PERIPH_MEM_MON, /*!< Memory Monitor */ + APM_TEE_HP_PERIPH_SYSTEM_REG, /*!< System registers */ + APM_TEE_HP_PERIPH_PCR_REG, /*!< PCR registers */ + APM_TEE_HP_PERIPH_MSPI, /*!< MSPI */ + APM_TEE_HP_PERIPH_HP_APM, /*!< HP APM */ + APM_TEE_HP_PERIPH_CPU_APM, /*!< CPU APM */ + APM_TEE_HP_PERIPH_TEE, /*!< TEE */ + APM_TEE_HP_PERIPH_CRYPTO, /*!< Crypto */ + APM_TEE_HP_PERIPH_TRACE, /*!< Trace */ + APM_TEE_HP_PERIPH_CPU_BUS_MON = 40, /*!< CPU Bus Monitor */ + APM_TEE_HP_PERIPH_INTPRI_REG, /*!< Interrupt Priority registers */ + APM_TEE_HP_PERIPH_CACHE_CFG, /*!< Cache */ + APM_TEE_HP_PERIPH_MODEM, /*!< Modem */ + APM_TEE_HP_PERIPH_TWAI1, /*!< TWAI1 */ + APM_TEE_HP_PERIPH_SPI2, /*!< SPI2 */ + APM_TEE_HP_PERIPH_BIT_SCRAMBLER, /*!< Bit Scrambler */ + APM_TEE_HP_PERIPH_KEY_MANAGER, /*!< Key Manager */ + APM_TEE_HP_PERIPH_MODEM_PWR, /*!< Modem Power */ + APM_TEE_HP_PERIPH_HINF, /*!< Host Interface */ + APM_TEE_HP_PERIPH_SLC, /*!< SLC */ + APM_TEE_HP_PERIPH_SLC_HOST = 52, /*!< SLC Host */ + APM_TEE_HP_PERIPH_MAX /*!< Maximum ID */ +} apm_tee_hp_periph_t; + +/** + * @brief LP-TEE Controller Peripherals + */ +typedef enum { + APM_TEE_LP_PERIPH_EFUSE = 0, /*!< EFUSE */ + APM_TEE_LP_PERIPH_PMU, /*!< PMU */ + APM_TEE_LP_PERIPH_CLKRST, /*!< CLKRST */ + APM_TEE_LP_PERIPH_LP_AON_CTRL, /*!< LP_AON_CTRL */ + APM_TEE_LP_PERIPH_LP_TIMER, /*!< LP_TIMER */ + APM_TEE_LP_PERIPH_LP_WDT, /*!< LP_WDT */ + APM_TEE_LP_PERIPH_LP_PERI, /*!< LP_PERI */ + APM_TEE_LP_PERIPH_LP_ANA_PERI, /*!< LP_ANA_PERI */ + APM_TEE_LP_PERIPH_LP_IO = 10, /*!< LP_IO */ + APM_TEE_LP_PERIPH_LP_TEE = 12, /*!< LP_TEE */ + APM_TEE_LP_PERIPH_UART, /*!< UART */ + APM_TEE_LP_PERIPH_I2C_EXT = 15, /*!< I2C_EXT */ + APM_TEE_LP_PERIPH_I2C_ANA_MST, /*!< I2C_ANA_MST */ + APM_TEE_LP_PERIPH_HUK, /*!< HUK */ + APM_TEE_LP_PERIPH_LP_APM, /*!< LP_APM */ + APM_TEE_LP_PERIPH_MAX /*!< Max ID */ +} apm_tee_lp_periph_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c5/include/soc/clk_tree_defs.h b/components/soc/esp32c5/include/soc/clk_tree_defs.h index 04341d8d63..3ba1a8ed27 100644 --- a/components/soc/esp32c5/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c5/include/soc/clk_tree_defs.h @@ -62,16 +62,50 @@ typedef enum { SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ } soc_root_clk_t; +// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] +// {[upstream]clock_name}: XTAL, (BB)PLL, etc. +// [attr] - optional: FAST, SLOW, D, F +/** + * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) + * + * @note enum starts from 1, to save 0 for special purpose + */ +typedef enum { + // For CPU domain + SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ + // For RTC domain + SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ + SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ + // For digital domain: peripherals, WIFI, BLE + SOC_MOD_CLK_PLL_F12M, /*!< PLL_F12M_CLK is derived from SPLL (clock gating + fixed divider of 40), it has a fixed frequency of 12MHz */ + SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + fixed divider of 24), it has a fixed frequency of 20MHz */ + SOC_MOD_CLK_PLL_F40M, /*!< PLL_F40M_CLK is derived from SPLL (clock gating + fixed divider of 12), it has a fixed frequency of 40MHz */ + SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from SPLL (clock gating + fixed divider of 10), it has a fixed frequency of 48MHz */ + SOC_MOD_CLK_PLL_F60M, /*!< PLL_F60M_CLK is derived from SPLL (clock gating + fixed divider of 8), it has a fixed frequency of 60MHz */ + SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ + SOC_MOD_CLK_PLL_F120M, /*!< PLL_F120M_CLK is derived from SPLL (clock gating + fixed divider of 4), it has a fixed frequency of 120MHz */ + SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ + SOC_MOD_CLK_MODEM_APB = SOC_MOD_CLK_PLL_F160M, /*!< Modem APB clock comes from the CLK_160M_REF */ + SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ + SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ + SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ + SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 48MHz crystal */ + // For LP peripherals + SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 48MHz crystal, passing a div of 2 to the LP peripherals */ + SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ +} soc_module_clk_t; + /** * @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK * @note Enum values are matched with the register field values on purpose */ typedef enum { - SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL_F160M = 2, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ - SOC_CPU_CLK_SRC_PLL_F240M = 3, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ - SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ + SOC_CPU_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */ + SOC_CPU_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M_CLK as CPU_CLK source (PLL_F160M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ + SOC_CPU_CLK_SRC_PLL_F240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M_CLK as CPU_CLK source (PLL_F240M_CLK is derived from SPLL (480MHz), which is the output of the main crystal oscillator frequency multiplier) */ + SOC_CPU_CLK_SRC_INVALID = SOC_MOD_CLK_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; /** @@ -109,34 +143,6 @@ typedef enum { SOC_XTAL_FREQ_48M = 48, /*!< 48MHz XTAL */ } soc_xtal_freq_t; -// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr] -// {[upstream]clock_name}: XTAL, (BB)PLL, etc. -// [attr] - optional: FAST, SLOW, D, F -/** - * @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.) - * - * @note enum starts from 1, to save 0 for special purpose - */ -typedef enum { - // For CPU domain - SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */ - // For RTC domain - SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */ - SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */ - // For digital domain: peripherals, WIFI, BLE - SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */ - SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */ - SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */ - SOC_MOD_CLK_SPLL, /*!< SPLL is from the main XTAL oscillator frequency multipliers, it has a "fixed" frequency of 480MHz */ - SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */ - SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ - SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 48MHz crystal */ - // For LP peripherals - SOC_MOD_CLK_XTAL_D2, /*!< XTAL_D2_CLK comes from the external 48MHz crystal, passing a div of 2 to the LP peripherals */ - - SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */ -} soc_module_clk_t; - //////////////////////////////////////////////////SYSTIMER////////////////////////////////////////////////////////////// /** diff --git a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h index 5581950d7c..93b0983691 100644 --- a/components/soc/esp32c5/include/soc/pmu_icg_mapping.h +++ b/components/soc/esp32c5/include/soc/pmu_icg_mapping.h @@ -33,6 +33,7 @@ #define PMU_ICG_APB_ENA_MEM_MONITOR 25 #define PMU_ICG_APB_ENA_IOMUX 26 #define PMU_ICG_APB_ENA_PVT_MONITOR 27 +#define PMU_ICG_APB_ENA_BS 28 #define PMU_ICG_FUNC_ENA_GDMA 0 #define PMU_ICG_FUNC_ENA_SPI2 1 #define PMU_ICG_FUNC_ENA_I2S_RX 2 diff --git a/components/soc/esp32c5/include/soc/soc_caps.h b/components/soc/esp32c5/include/soc/soc_caps.h index 4e469989dd..9e9c4ee8d2 100644 --- a/components/soc/esp32c5/include/soc/soc_caps.h +++ b/components/soc/esp32c5/include/soc/soc_caps.h @@ -76,12 +76,13 @@ #define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32C5] IDF-8715 #define SOC_ECDSA_SUPPORTED 1 #define SOC_RNG_SUPPORTED 1 -// #define SOC_KEY_MANAGER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8621 -// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617 +#define SOC_KEY_MANAGER_SUPPORTED 1 +#define SOC_HUK_SUPPORTED 1 #define SOC_MODEM_CLOCK_SUPPORTED 1 #define SOC_LIGHT_SLEEP_SUPPORTED 1 #define SOC_DEEP_SLEEP_SUPPORTED 1 #define SOC_PM_SUPPORTED 1 +#define SOC_CLOCK_TREE_MANAGEMENT_SUPPORTED 1 #define SOC_SPIRAM_SUPPORTED 1 #define SOC_BT_SUPPORTED 1 @@ -390,6 +391,7 @@ #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ #define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */ +#define SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA 1 /*!< Support to treat DMA EOF as TX unit EOF */ #define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */ #define SOC_PARLIO_SUPPORT_SPI_LCD 1 /*!< Support to drive SPI interfaced LCD */ #define SOC_PARLIO_SUPPORT_I80_LCD 1 /*!< Support to drive I80 interfaced LCD */ @@ -478,6 +480,7 @@ #define SOC_SPI_MEM_SUPPORT_WB_MODE_INDEPENDENT_CONTROL (1) #define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1) #define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1) +#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1) #define SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY (1) #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 @@ -536,9 +539,15 @@ #define SOC_EFUSE_ECDSA_KEY_P192 1 #define SOC_EFUSE_ECDSA_KEY_P384 1 +/*-------------------------- HUK CAPS----------------------------*/ +#define SOC_HUK_MEM_NEEDS_RECHARGE 1 + /*-------------------------- Key Manager CAPS----------------------------*/ -#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */ -#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */ +#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */ +#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */ +#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */ +#define SOC_KEY_MANAGER_HMAC_KEY_DEPLOY 1 /*!< Key manager responsible to deploy HMAC key */ +#define SOC_KEY_MANAGER_DS_KEY_DEPLOY 1 /*!< Key manager responsible to deploy DS key */ /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 @@ -560,14 +569,17 @@ /*------------------------Bootloader CAPS---------------------------------*/ /* Support Recovery Bootloader */ -#define SOC_RECOVERY_BOOTLOADER_SUPPORTED (0) +#define SOC_RECOVERY_BOOTLOADER_SUPPORTED (1) /* Support Anti-rollback */ -#define SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED (0) +#define SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED (1) /*-------------------------- APM CAPS-----------------------------------------*/ -#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ -#define SOC_APM_LP_APM0_SUPPORTED 1 /*!< Support for LP APM0 control filter */ -#define SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL 1 /*!< Support for TEE controller per-peripheral access control */ +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ +#define SOC_APM_LP_APM0_SUPPORTED 1 /*!< Support for LP APM0 control filter */ +#define SOC_APM_CPU_APM_SUPPORTED 1 /*!< Support for CPU APM control filter */ +#define SOC_APM_SUPPORT_LP_TEE_CTRL 1 /*!< Support for LP TEE controller */ +#define SOC_APM_SUPPORT_CTRL_CFG_LOCK 1 /*!< Support for APM controller configuration lock */ +#define SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL 1 /*!< Support for TEE controller per-peripheral access control */ /*------------------------ Anti DPA (Security) CAPS --------------------------*/ #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 diff --git a/components/soc/esp32c5/register/soc/cpu_apm_reg.h b/components/soc/esp32c5/register/soc/cpu_apm_reg.h index 9c6a7cbe52..daf755e202 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_reg.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** CPU_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_BASE + 0x0) /** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define CPU_APM_REGION_FILTER_EN 0x000000FFU #define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) @@ -37,7 +37,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_START_L_S 0 /** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define CPU_APM_REGION0_ADDR_START 0x0000007FU #define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) @@ -63,7 +63,7 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION0_ADDR_END_L_S 0 /** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define CPU_APM_REGION0_ADDR_END 0x0000007FU #define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) @@ -78,74 +78,78 @@ extern "C" { #define CPU_APM_REGION0_ADDR_END_H_S 19 /** CPU_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_BASE + 0xc) /** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_X (BIT(0)) #define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) #define CPU_APM_REGION0_R0_X_V 0x00000001U #define CPU_APM_REGION0_R0_X_S 0 /** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_W (BIT(1)) #define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) #define CPU_APM_REGION0_R0_W_V 0x00000001U #define CPU_APM_REGION0_R0_W_S 1 /** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define CPU_APM_REGION0_R0_R (BIT(2)) #define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) #define CPU_APM_REGION0_R0_R_V 0x00000001U #define CPU_APM_REGION0_R0_R_S 2 /** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_X (BIT(4)) #define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) #define CPU_APM_REGION0_R1_X_V 0x00000001U #define CPU_APM_REGION0_R1_X_S 4 /** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_W (BIT(5)) #define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) #define CPU_APM_REGION0_R1_W_V 0x00000001U #define CPU_APM_REGION0_R1_W_S 5 /** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define CPU_APM_REGION0_R1_R (BIT(6)) #define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) #define CPU_APM_REGION0_R1_R_V 0x00000001U #define CPU_APM_REGION0_R1_R_S 6 /** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_X (BIT(8)) #define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) #define CPU_APM_REGION0_R2_X_V 0x00000001U #define CPU_APM_REGION0_R2_X_S 8 /** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_W (BIT(9)) #define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) #define CPU_APM_REGION0_R2_W_V 0x00000001U #define CPU_APM_REGION0_R2_W_S 9 /** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define CPU_APM_REGION0_R2_R (BIT(10)) #define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) #define CPU_APM_REGION0_R2_R_V 0x00000001U #define CPU_APM_REGION0_R2_R_S 10 /** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0's configuration registers + * (CPU_APM_REGION0_ADDR_START_REG, CPU_APM_REGION0_ADDR_END_REG, and + * CPU_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION0_LOCK (BIT(11)) #define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) @@ -164,7 +168,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_START_L_S 0 /** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define CPU_APM_REGION1_ADDR_START 0x0000007FU #define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) @@ -190,7 +194,7 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION1_ADDR_END_L_S 0 /** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define CPU_APM_REGION1_ADDR_END 0x0000007FU #define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) @@ -205,74 +209,78 @@ extern "C" { #define CPU_APM_REGION1_ADDR_END_H_S 19 /** CPU_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_BASE + 0x18) /** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_X (BIT(0)) #define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) #define CPU_APM_REGION1_R0_X_V 0x00000001U #define CPU_APM_REGION1_R0_X_S 0 /** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_W (BIT(1)) #define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) #define CPU_APM_REGION1_R0_W_V 0x00000001U #define CPU_APM_REGION1_R0_W_S 1 /** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define CPU_APM_REGION1_R0_R (BIT(2)) #define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) #define CPU_APM_REGION1_R0_R_V 0x00000001U #define CPU_APM_REGION1_R0_R_S 2 /** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_X (BIT(4)) #define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) #define CPU_APM_REGION1_R1_X_V 0x00000001U #define CPU_APM_REGION1_R1_X_S 4 /** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_W (BIT(5)) #define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) #define CPU_APM_REGION1_R1_W_V 0x00000001U #define CPU_APM_REGION1_R1_W_S 5 /** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define CPU_APM_REGION1_R1_R (BIT(6)) #define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) #define CPU_APM_REGION1_R1_R_V 0x00000001U #define CPU_APM_REGION1_R1_R_S 6 /** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_X (BIT(8)) #define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) #define CPU_APM_REGION1_R2_X_V 0x00000001U #define CPU_APM_REGION1_R2_X_S 8 /** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_W (BIT(9)) #define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) #define CPU_APM_REGION1_R2_W_V 0x00000001U #define CPU_APM_REGION1_R2_W_S 9 /** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define CPU_APM_REGION1_R2_R (BIT(10)) #define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) #define CPU_APM_REGION1_R2_R_V 0x00000001U #define CPU_APM_REGION1_R2_R_S 10 /** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1's configuration registers + * (CPU_APM_REGION1_ADDR_START_REG, CPU_APM_REGION1_ADDR_END_REG, and + * CPU_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION1_LOCK (BIT(11)) #define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) @@ -291,7 +299,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_START_L_S 0 /** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define CPU_APM_REGION2_ADDR_START 0x0000007FU #define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) @@ -317,7 +325,7 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION2_ADDR_END_L_S 0 /** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define CPU_APM_REGION2_ADDR_END 0x0000007FU #define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) @@ -332,74 +340,78 @@ extern "C" { #define CPU_APM_REGION2_ADDR_END_H_S 19 /** CPU_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_BASE + 0x24) /** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_X (BIT(0)) #define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) #define CPU_APM_REGION2_R0_X_V 0x00000001U #define CPU_APM_REGION2_R0_X_S 0 /** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_W (BIT(1)) #define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) #define CPU_APM_REGION2_R0_W_V 0x00000001U #define CPU_APM_REGION2_R0_W_S 1 /** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define CPU_APM_REGION2_R0_R (BIT(2)) #define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) #define CPU_APM_REGION2_R0_R_V 0x00000001U #define CPU_APM_REGION2_R0_R_S 2 /** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_X (BIT(4)) #define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) #define CPU_APM_REGION2_R1_X_V 0x00000001U #define CPU_APM_REGION2_R1_X_S 4 /** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_W (BIT(5)) #define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) #define CPU_APM_REGION2_R1_W_V 0x00000001U #define CPU_APM_REGION2_R1_W_S 5 /** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define CPU_APM_REGION2_R1_R (BIT(6)) #define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) #define CPU_APM_REGION2_R1_R_V 0x00000001U #define CPU_APM_REGION2_R1_R_S 6 /** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_X (BIT(8)) #define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) #define CPU_APM_REGION2_R2_X_V 0x00000001U #define CPU_APM_REGION2_R2_X_S 8 /** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_W (BIT(9)) #define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) #define CPU_APM_REGION2_R2_W_V 0x00000001U #define CPU_APM_REGION2_R2_W_S 9 /** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define CPU_APM_REGION2_R2_R (BIT(10)) #define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) #define CPU_APM_REGION2_R2_R_V 0x00000001U #define CPU_APM_REGION2_R2_R_S 10 /** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2's configuration registers + * (CPU_APM_REGION2_ADDR_START_REG, CPU_APM_REGION2_ADDR_END_REG, and + * CPU_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION2_LOCK (BIT(11)) #define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) @@ -418,7 +430,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_START_L_S 0 /** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define CPU_APM_REGION3_ADDR_START 0x0000007FU #define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) @@ -444,7 +456,7 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION3_ADDR_END_L_S 0 /** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define CPU_APM_REGION3_ADDR_END 0x0000007FU #define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) @@ -459,74 +471,78 @@ extern "C" { #define CPU_APM_REGION3_ADDR_END_H_S 19 /** CPU_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_BASE + 0x30) /** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_X (BIT(0)) #define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) #define CPU_APM_REGION3_R0_X_V 0x00000001U #define CPU_APM_REGION3_R0_X_S 0 /** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_W (BIT(1)) #define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) #define CPU_APM_REGION3_R0_W_V 0x00000001U #define CPU_APM_REGION3_R0_W_S 1 /** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define CPU_APM_REGION3_R0_R (BIT(2)) #define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) #define CPU_APM_REGION3_R0_R_V 0x00000001U #define CPU_APM_REGION3_R0_R_S 2 /** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_X (BIT(4)) #define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) #define CPU_APM_REGION3_R1_X_V 0x00000001U #define CPU_APM_REGION3_R1_X_S 4 /** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_W (BIT(5)) #define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) #define CPU_APM_REGION3_R1_W_V 0x00000001U #define CPU_APM_REGION3_R1_W_S 5 /** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define CPU_APM_REGION3_R1_R (BIT(6)) #define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) #define CPU_APM_REGION3_R1_R_V 0x00000001U #define CPU_APM_REGION3_R1_R_S 6 /** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_X (BIT(8)) #define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) #define CPU_APM_REGION3_R2_X_V 0x00000001U #define CPU_APM_REGION3_R2_X_S 8 /** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_W (BIT(9)) #define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) #define CPU_APM_REGION3_R2_W_V 0x00000001U #define CPU_APM_REGION3_R2_W_S 9 /** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define CPU_APM_REGION3_R2_R (BIT(10)) #define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) #define CPU_APM_REGION3_R2_R_V 0x00000001U #define CPU_APM_REGION3_R2_R_S 10 /** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3's configuration registers + * (CPU_APM_REGION3_ADDR_START_REG, CPU_APM_REGION3_ADDR_END_REG, and + * CPU_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION3_LOCK (BIT(11)) #define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) @@ -545,7 +561,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_START_L_S 0 /** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define CPU_APM_REGION4_ADDR_START 0x0000007FU #define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) @@ -571,7 +587,7 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION4_ADDR_END_L_S 0 /** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define CPU_APM_REGION4_ADDR_END 0x0000007FU #define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) @@ -586,74 +602,78 @@ extern "C" { #define CPU_APM_REGION4_ADDR_END_H_S 19 /** CPU_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_BASE + 0x3c) /** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_X (BIT(0)) #define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) #define CPU_APM_REGION4_R0_X_V 0x00000001U #define CPU_APM_REGION4_R0_X_S 0 /** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_W (BIT(1)) #define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) #define CPU_APM_REGION4_R0_W_V 0x00000001U #define CPU_APM_REGION4_R0_W_S 1 /** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define CPU_APM_REGION4_R0_R (BIT(2)) #define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) #define CPU_APM_REGION4_R0_R_V 0x00000001U #define CPU_APM_REGION4_R0_R_S 2 /** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_X (BIT(4)) #define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) #define CPU_APM_REGION4_R1_X_V 0x00000001U #define CPU_APM_REGION4_R1_X_S 4 /** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_W (BIT(5)) #define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) #define CPU_APM_REGION4_R1_W_V 0x00000001U #define CPU_APM_REGION4_R1_W_S 5 /** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define CPU_APM_REGION4_R1_R (BIT(6)) #define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) #define CPU_APM_REGION4_R1_R_V 0x00000001U #define CPU_APM_REGION4_R1_R_S 6 /** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_X (BIT(8)) #define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) #define CPU_APM_REGION4_R2_X_V 0x00000001U #define CPU_APM_REGION4_R2_X_S 8 /** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_W (BIT(9)) #define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) #define CPU_APM_REGION4_R2_W_V 0x00000001U #define CPU_APM_REGION4_R2_W_S 9 /** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define CPU_APM_REGION4_R2_R (BIT(10)) #define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) #define CPU_APM_REGION4_R2_R_V 0x00000001U #define CPU_APM_REGION4_R2_R_S 10 /** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4's configuration registers + * (CPU_APM_REGION4_ADDR_START_REG, CPU_APM_REGION4_ADDR_END_REG, and + * CPU_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION4_LOCK (BIT(11)) #define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) @@ -672,7 +692,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_START_L_S 0 /** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define CPU_APM_REGION5_ADDR_START 0x0000007FU #define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) @@ -698,7 +718,7 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION5_ADDR_END_L_S 0 /** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define CPU_APM_REGION5_ADDR_END 0x0000007FU #define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) @@ -713,74 +733,78 @@ extern "C" { #define CPU_APM_REGION5_ADDR_END_H_S 19 /** CPU_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_BASE + 0x48) /** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_X (BIT(0)) #define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) #define CPU_APM_REGION5_R0_X_V 0x00000001U #define CPU_APM_REGION5_R0_X_S 0 /** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_W (BIT(1)) #define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) #define CPU_APM_REGION5_R0_W_V 0x00000001U #define CPU_APM_REGION5_R0_W_S 1 /** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define CPU_APM_REGION5_R0_R (BIT(2)) #define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) #define CPU_APM_REGION5_R0_R_V 0x00000001U #define CPU_APM_REGION5_R0_R_S 2 /** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_X (BIT(4)) #define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) #define CPU_APM_REGION5_R1_X_V 0x00000001U #define CPU_APM_REGION5_R1_X_S 4 /** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_W (BIT(5)) #define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) #define CPU_APM_REGION5_R1_W_V 0x00000001U #define CPU_APM_REGION5_R1_W_S 5 /** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define CPU_APM_REGION5_R1_R (BIT(6)) #define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) #define CPU_APM_REGION5_R1_R_V 0x00000001U #define CPU_APM_REGION5_R1_R_S 6 /** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_X (BIT(8)) #define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) #define CPU_APM_REGION5_R2_X_V 0x00000001U #define CPU_APM_REGION5_R2_X_S 8 /** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_W (BIT(9)) #define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) #define CPU_APM_REGION5_R2_W_V 0x00000001U #define CPU_APM_REGION5_R2_W_S 9 /** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define CPU_APM_REGION5_R2_R (BIT(10)) #define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) #define CPU_APM_REGION5_R2_R_V 0x00000001U #define CPU_APM_REGION5_R2_R_S 10 /** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5's configuration registers + * (CPU_APM_REGION5_ADDR_START_REG, CPU_APM_REGION5_ADDR_END_REG, and + * CPU_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION5_LOCK (BIT(11)) #define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) @@ -799,7 +823,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_START_L_S 0 /** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define CPU_APM_REGION6_ADDR_START 0x0000007FU #define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) @@ -825,7 +849,7 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION6_ADDR_END_L_S 0 /** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define CPU_APM_REGION6_ADDR_END 0x0000007FU #define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) @@ -840,74 +864,78 @@ extern "C" { #define CPU_APM_REGION6_ADDR_END_H_S 19 /** CPU_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_BASE + 0x54) /** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_X (BIT(0)) #define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) #define CPU_APM_REGION6_R0_X_V 0x00000001U #define CPU_APM_REGION6_R0_X_S 0 /** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_W (BIT(1)) #define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) #define CPU_APM_REGION6_R0_W_V 0x00000001U #define CPU_APM_REGION6_R0_W_S 1 /** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define CPU_APM_REGION6_R0_R (BIT(2)) #define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) #define CPU_APM_REGION6_R0_R_V 0x00000001U #define CPU_APM_REGION6_R0_R_S 2 /** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_X (BIT(4)) #define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) #define CPU_APM_REGION6_R1_X_V 0x00000001U #define CPU_APM_REGION6_R1_X_S 4 /** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_W (BIT(5)) #define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) #define CPU_APM_REGION6_R1_W_V 0x00000001U #define CPU_APM_REGION6_R1_W_S 5 /** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define CPU_APM_REGION6_R1_R (BIT(6)) #define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) #define CPU_APM_REGION6_R1_R_V 0x00000001U #define CPU_APM_REGION6_R1_R_S 6 /** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_X (BIT(8)) #define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) #define CPU_APM_REGION6_R2_X_V 0x00000001U #define CPU_APM_REGION6_R2_X_S 8 /** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_W (BIT(9)) #define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) #define CPU_APM_REGION6_R2_W_V 0x00000001U #define CPU_APM_REGION6_R2_W_S 9 /** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define CPU_APM_REGION6_R2_R (BIT(10)) #define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) #define CPU_APM_REGION6_R2_R_V 0x00000001U #define CPU_APM_REGION6_R2_R_S 10 /** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6's configuration registers + * (CPU_APM_REGION6_ADDR_START_REG, CPU_APM_REGION6_ADDR_END_REG, and + * CPU_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION6_LOCK (BIT(11)) #define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) @@ -926,7 +954,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_START_L_S 0 /** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define CPU_APM_REGION7_ADDR_START 0x0000007FU #define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) @@ -952,7 +980,7 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU #define CPU_APM_REGION7_ADDR_END_L_S 0 /** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define CPU_APM_REGION7_ADDR_END 0x0000007FU #define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) @@ -967,74 +995,78 @@ extern "C" { #define CPU_APM_REGION7_ADDR_END_H_S 19 /** CPU_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_BASE + 0x60) /** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_X (BIT(0)) #define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) #define CPU_APM_REGION7_R0_X_V 0x00000001U #define CPU_APM_REGION7_R0_X_S 0 /** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_W (BIT(1)) #define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) #define CPU_APM_REGION7_R0_W_V 0x00000001U #define CPU_APM_REGION7_R0_W_S 1 /** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define CPU_APM_REGION7_R0_R (BIT(2)) #define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) #define CPU_APM_REGION7_R0_R_V 0x00000001U #define CPU_APM_REGION7_R0_R_S 2 /** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_X (BIT(4)) #define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) #define CPU_APM_REGION7_R1_X_V 0x00000001U #define CPU_APM_REGION7_R1_X_S 4 /** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_W (BIT(5)) #define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) #define CPU_APM_REGION7_R1_W_V 0x00000001U #define CPU_APM_REGION7_R1_W_S 5 /** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define CPU_APM_REGION7_R1_R (BIT(6)) #define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) #define CPU_APM_REGION7_R1_R_V 0x00000001U #define CPU_APM_REGION7_R1_R_S 6 /** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_X (BIT(8)) #define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) #define CPU_APM_REGION7_R2_X_V 0x00000001U #define CPU_APM_REGION7_R2_X_S 8 /** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_W (BIT(9)) #define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) #define CPU_APM_REGION7_R2_W_V 0x00000001U #define CPU_APM_REGION7_R2_W_S 9 /** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define CPU_APM_REGION7_R2_R (BIT(10)) #define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) #define CPU_APM_REGION7_R2_R_V 0x00000001U #define CPU_APM_REGION7_R2_R_S 10 /** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7's configuration registers + * (CPU_APM_REGION7_ADDR_START_REG, CPU_APM_REGION7_ADDR_END_REG, and + * CPU_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define CPU_APM_REGION7_LOCK (BIT(11)) #define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) @@ -1042,18 +1074,22 @@ extern "C" { #define CPU_APM_REGION7_LOCK_S 11 /** CPU_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_BASE + 0xc4) /** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_FUNC_EN (BIT(0)) #define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) #define CPU_APM_M0_FUNC_EN_V 0x00000001U #define CPU_APM_M0_FUNC_EN_S 0 /** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_FUNC_EN (BIT(1)) #define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) @@ -1061,13 +1097,13 @@ extern "C" { #define CPU_APM_M1_FUNC_EN_S 1 /** CPU_APM_M0_STATUS_REG register - * M0 status register + * CPU_APM_CTRL M0 status register */ #define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_BASE + 0xc8) /** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) @@ -1075,11 +1111,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_S 0 /** CPU_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ #define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xcc) /** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) @@ -1087,25 +1123,25 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xd0) /** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) #define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M0_EXCEPTION_REGION_S 0 /** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_MODE 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) #define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M0_EXCEPTION_MODE_S 16 /** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ID 0x0000001FU #define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) @@ -1113,11 +1149,11 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ID_S 18 /** CPU_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ #define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xd4) /** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) @@ -1125,13 +1161,13 @@ extern "C" { #define CPU_APM_M0_EXCEPTION_ADDR_S 0 /** CPU_APM_M1_STATUS_REG register - * M1 status register + * CPU_APM_CTRL M1 status register */ #define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_BASE + 0xd8) /** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U #define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) @@ -1139,11 +1175,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_S 0 /** CPU_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ #define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_BASE + 0xdc) /** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ #define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) #define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) @@ -1151,25 +1187,25 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** CPU_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_BASE + 0xe0) /** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) #define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define CPU_APM_M1_EXCEPTION_REGION_S 0 /** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_MODE 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) #define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U #define CPU_APM_M1_EXCEPTION_MODE_S 16 /** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ID 0x0000001FU #define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) @@ -1177,11 +1213,11 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ID_S 18 /** CPU_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ #define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_BASE + 0xe4) /** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) @@ -1189,22 +1225,22 @@ extern "C" { #define CPU_APM_M1_EXCEPTION_ADDR_S 0 /** CPU_APM_INT_EN_REG register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ #define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_BASE + 0x118) /** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M0_APM_INT_EN (BIT(0)) #define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) #define CPU_APM_M0_APM_INT_EN_V 0x00000001U #define CPU_APM_M0_APM_INT_EN_S 0 /** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define CPU_APM_M1_APM_INT_EN (BIT(1)) #define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) @@ -1217,8 +1253,8 @@ extern "C" { #define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_BASE + 0x7f8) /** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define CPU_APM_CLK_EN (BIT(0)) #define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/cpu_apm_struct.h b/components/soc/esp32c5/register/soc/cpu_apm_struct.h index c8198eeecb..49d283b39c 100644 --- a/components/soc/esp32c5/register/soc/cpu_apm_struct.h +++ b/components/soc/esp32c5/register/soc/cpu_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configures bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -28,7 +28,7 @@ typedef union { } cpu_apm_region_filter_en_reg_t; -/** Group: Region address register */ +/** Group: Region Address Registers */ /** Type of regionn_addr_start register * Region address register */ @@ -39,7 +39,7 @@ typedef union { */ uint32_t regionn_addr_start_l:12; /** regionn_addr_start : R/W; bitpos: [18:12]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:7; /** regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; @@ -60,7 +60,7 @@ typedef union { */ uint32_t regionn_addr_end_l:12; /** regionn_addr_end : R/W; bitpos: [18:12]; default: 127; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:7; /** regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; @@ -71,53 +71,55 @@ typedef union { uint32_t val; } cpu_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n's configuration registers + * (CPU_APM_REGIONn_ADDR_START_REG, CPU_APM_REGIONn_ADDR_END_REG, and + * CPU_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -125,19 +127,21 @@ typedef union { uint32_t val; } cpu_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M0. + * 0: Disable + * 1: Enable */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures whether to enable permission management for CPU_APM_CTRL M1. + * 0: Disable + * 1: Enable */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -146,16 +150,16 @@ typedef union { } cpu_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * CPU_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -163,15 +167,13 @@ typedef union { uint32_t val; } cpu_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * CPU_APM_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -179,23 +181,21 @@ typedef union { uint32_t val; } cpu_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -203,32 +203,28 @@ typedef union { uint32_t val; } cpu_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * CPU_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } cpu_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * CPU_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -236,15 +232,13 @@ typedef union { uint32_t val; } cpu_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * CPU_APM_CTRL M1 status clear register */ typedef union { struct { /** m1_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status. + * Write 1 to clear exception status. */ uint32_t m1_exception_status_clr:1; uint32_t reserved_1:31; @@ -252,23 +246,21 @@ typedef union { uint32_t val; } cpu_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -276,15 +268,13 @@ typedef union { uint32_t val; } cpu_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * CPU_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -292,22 +282,22 @@ typedef union { } cpu_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * CPU_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures whether to enable CPU_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -316,7 +306,7 @@ typedef union { } cpu_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -324,8 +314,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -334,7 +324,7 @@ typedef union { } cpu_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/hp_apm_reg.h b/components/soc/esp32c5/register/soc/hp_apm_reg.h index ae587c5944..4179bf0815 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/hp_apm_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,13 +12,13 @@ extern "C" { #endif /** HP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define HP_APM_REGION_FILTER_EN_REG (DR_REG_HP_APM_BASE + 0x0) /** HP_APM_REGION_FILTER_EN : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ #define HP_APM_REGION_FILTER_EN 0x0000FFFFU #define HP_APM_REGION_FILTER_EN_M (HP_APM_REGION_FILTER_EN_V << HP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4) /** HP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define HP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_START_M (HP_APM_REGION0_ADDR_START_V << HP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define HP_APM_REGION0_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8) /** HP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define HP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION0_ADDR_END_M (HP_APM_REGION0_ADDR_END_V << HP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define HP_APM_REGION0_ADDR_END_S 0 /** HP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION0_ATTR_REG (DR_REG_HP_APM_BASE + 0xc) /** HP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_X (BIT(0)) #define HP_APM_REGION0_R0_X_M (HP_APM_REGION0_R0_X_V << HP_APM_REGION0_R0_X_S) #define HP_APM_REGION0_R0_X_V 0x00000001U #define HP_APM_REGION0_R0_X_S 0 /** HP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_W (BIT(1)) #define HP_APM_REGION0_R0_W_M (HP_APM_REGION0_R0_W_V << HP_APM_REGION0_R0_W_S) #define HP_APM_REGION0_R0_W_V 0x00000001U #define HP_APM_REGION0_R0_W_S 1 /** HP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define HP_APM_REGION0_R0_R (BIT(2)) #define HP_APM_REGION0_R0_R_M (HP_APM_REGION0_R0_R_V << HP_APM_REGION0_R0_R_S) #define HP_APM_REGION0_R0_R_V 0x00000001U #define HP_APM_REGION0_R0_R_S 2 /** HP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_X (BIT(4)) #define HP_APM_REGION0_R1_X_M (HP_APM_REGION0_R1_X_V << HP_APM_REGION0_R1_X_S) #define HP_APM_REGION0_R1_X_V 0x00000001U #define HP_APM_REGION0_R1_X_S 4 /** HP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_W (BIT(5)) #define HP_APM_REGION0_R1_W_M (HP_APM_REGION0_R1_W_V << HP_APM_REGION0_R1_W_S) #define HP_APM_REGION0_R1_W_V 0x00000001U #define HP_APM_REGION0_R1_W_S 5 /** HP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define HP_APM_REGION0_R1_R (BIT(6)) #define HP_APM_REGION0_R1_R_M (HP_APM_REGION0_R1_R_V << HP_APM_REGION0_R1_R_S) #define HP_APM_REGION0_R1_R_V 0x00000001U #define HP_APM_REGION0_R1_R_S 6 /** HP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_X (BIT(8)) #define HP_APM_REGION0_R2_X_M (HP_APM_REGION0_R2_X_V << HP_APM_REGION0_R2_X_S) #define HP_APM_REGION0_R2_X_V 0x00000001U #define HP_APM_REGION0_R2_X_S 8 /** HP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_W (BIT(9)) #define HP_APM_REGION0_R2_W_M (HP_APM_REGION0_R2_W_V << HP_APM_REGION0_R2_W_S) #define HP_APM_REGION0_R2_W_V 0x00000001U #define HP_APM_REGION0_R2_W_S 9 /** HP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define HP_APM_REGION0_R2_R (BIT(10)) #define HP_APM_REGION0_R2_R_M (HP_APM_REGION0_R2_R_V << HP_APM_REGION0_R2_R_S) #define HP_APM_REGION0_R2_R_V 0x00000001U #define HP_APM_REGION0_R2_R_S 10 /** HP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (HP_APM_REGION0_ADDR_START_REG, HP_APM_REGION0_ADDR_END_REG and + * HP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION0_LOCK (BIT(11)) #define HP_APM_REGION0_LOCK_M (HP_APM_REGION0_LOCK_V << HP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x10) /** HP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define HP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_START_M (HP_APM_REGION1_ADDR_START_V << HP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define HP_APM_REGION1_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x14) /** HP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define HP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION1_ADDR_END_M (HP_APM_REGION1_ADDR_END_V << HP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define HP_APM_REGION1_ADDR_END_S 0 /** HP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION1_ATTR_REG (DR_REG_HP_APM_BASE + 0x18) /** HP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_X (BIT(0)) #define HP_APM_REGION1_R0_X_M (HP_APM_REGION1_R0_X_V << HP_APM_REGION1_R0_X_S) #define HP_APM_REGION1_R0_X_V 0x00000001U #define HP_APM_REGION1_R0_X_S 0 /** HP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_W (BIT(1)) #define HP_APM_REGION1_R0_W_M (HP_APM_REGION1_R0_W_V << HP_APM_REGION1_R0_W_S) #define HP_APM_REGION1_R0_W_V 0x00000001U #define HP_APM_REGION1_R0_W_S 1 /** HP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define HP_APM_REGION1_R0_R (BIT(2)) #define HP_APM_REGION1_R0_R_M (HP_APM_REGION1_R0_R_V << HP_APM_REGION1_R0_R_S) #define HP_APM_REGION1_R0_R_V 0x00000001U #define HP_APM_REGION1_R0_R_S 2 /** HP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_X (BIT(4)) #define HP_APM_REGION1_R1_X_M (HP_APM_REGION1_R1_X_V << HP_APM_REGION1_R1_X_S) #define HP_APM_REGION1_R1_X_V 0x00000001U #define HP_APM_REGION1_R1_X_S 4 /** HP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_W (BIT(5)) #define HP_APM_REGION1_R1_W_M (HP_APM_REGION1_R1_W_V << HP_APM_REGION1_R1_W_S) #define HP_APM_REGION1_R1_W_V 0x00000001U #define HP_APM_REGION1_R1_W_S 5 /** HP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define HP_APM_REGION1_R1_R (BIT(6)) #define HP_APM_REGION1_R1_R_M (HP_APM_REGION1_R1_R_V << HP_APM_REGION1_R1_R_S) #define HP_APM_REGION1_R1_R_V 0x00000001U #define HP_APM_REGION1_R1_R_S 6 /** HP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_X (BIT(8)) #define HP_APM_REGION1_R2_X_M (HP_APM_REGION1_R2_X_V << HP_APM_REGION1_R2_X_S) #define HP_APM_REGION1_R2_X_V 0x00000001U #define HP_APM_REGION1_R2_X_S 8 /** HP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_W (BIT(9)) #define HP_APM_REGION1_R2_W_M (HP_APM_REGION1_R2_W_V << HP_APM_REGION1_R2_W_S) #define HP_APM_REGION1_R2_W_V 0x00000001U #define HP_APM_REGION1_R2_W_S 9 /** HP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define HP_APM_REGION1_R2_R (BIT(10)) #define HP_APM_REGION1_R2_R_M (HP_APM_REGION1_R2_R_V << HP_APM_REGION1_R2_R_S) #define HP_APM_REGION1_R2_R_V 0x00000001U #define HP_APM_REGION1_R2_R_S 10 /** HP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (HP_APM_REGION1_ADDR_START_REG, HP_APM_REGION1_ADDR_END_REG and + * HP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION1_LOCK (BIT(11)) #define HP_APM_REGION1_LOCK_M (HP_APM_REGION1_LOCK_V << HP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x1c) /** HP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define HP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_START_M (HP_APM_REGION2_ADDR_START_V << HP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define HP_APM_REGION2_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x20) /** HP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define HP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION2_ADDR_END_M (HP_APM_REGION2_ADDR_END_V << HP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define HP_APM_REGION2_ADDR_END_S 0 /** HP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION2_ATTR_REG (DR_REG_HP_APM_BASE + 0x24) /** HP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_X (BIT(0)) #define HP_APM_REGION2_R0_X_M (HP_APM_REGION2_R0_X_V << HP_APM_REGION2_R0_X_S) #define HP_APM_REGION2_R0_X_V 0x00000001U #define HP_APM_REGION2_R0_X_S 0 /** HP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_W (BIT(1)) #define HP_APM_REGION2_R0_W_M (HP_APM_REGION2_R0_W_V << HP_APM_REGION2_R0_W_S) #define HP_APM_REGION2_R0_W_V 0x00000001U #define HP_APM_REGION2_R0_W_S 1 /** HP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define HP_APM_REGION2_R0_R (BIT(2)) #define HP_APM_REGION2_R0_R_M (HP_APM_REGION2_R0_R_V << HP_APM_REGION2_R0_R_S) #define HP_APM_REGION2_R0_R_V 0x00000001U #define HP_APM_REGION2_R0_R_S 2 /** HP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_X (BIT(4)) #define HP_APM_REGION2_R1_X_M (HP_APM_REGION2_R1_X_V << HP_APM_REGION2_R1_X_S) #define HP_APM_REGION2_R1_X_V 0x00000001U #define HP_APM_REGION2_R1_X_S 4 /** HP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_W (BIT(5)) #define HP_APM_REGION2_R1_W_M (HP_APM_REGION2_R1_W_V << HP_APM_REGION2_R1_W_S) #define HP_APM_REGION2_R1_W_V 0x00000001U #define HP_APM_REGION2_R1_W_S 5 /** HP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define HP_APM_REGION2_R1_R (BIT(6)) #define HP_APM_REGION2_R1_R_M (HP_APM_REGION2_R1_R_V << HP_APM_REGION2_R1_R_S) #define HP_APM_REGION2_R1_R_V 0x00000001U #define HP_APM_REGION2_R1_R_S 6 /** HP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_X (BIT(8)) #define HP_APM_REGION2_R2_X_M (HP_APM_REGION2_R2_X_V << HP_APM_REGION2_R2_X_S) #define HP_APM_REGION2_R2_X_V 0x00000001U #define HP_APM_REGION2_R2_X_S 8 /** HP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_W (BIT(9)) #define HP_APM_REGION2_R2_W_M (HP_APM_REGION2_R2_W_V << HP_APM_REGION2_R2_W_S) #define HP_APM_REGION2_R2_W_V 0x00000001U #define HP_APM_REGION2_R2_W_S 9 /** HP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define HP_APM_REGION2_R2_R (BIT(10)) #define HP_APM_REGION2_R2_R_M (HP_APM_REGION2_R2_R_V << HP_APM_REGION2_R2_R_S) #define HP_APM_REGION2_R2_R_V 0x00000001U #define HP_APM_REGION2_R2_R_S 10 /** HP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (HP_APM_REGION2_ADDR_START_REG, HP_APM_REGION2_ADDR_END_REG and + * HP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION2_LOCK (BIT(11)) #define HP_APM_REGION2_LOCK_M (HP_APM_REGION2_LOCK_V << HP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x28) /** HP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define HP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_START_M (HP_APM_REGION3_ADDR_START_V << HP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define HP_APM_REGION3_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x2c) /** HP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define HP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION3_ADDR_END_M (HP_APM_REGION3_ADDR_END_V << HP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define HP_APM_REGION3_ADDR_END_S 0 /** HP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION3_ATTR_REG (DR_REG_HP_APM_BASE + 0x30) /** HP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_X (BIT(0)) #define HP_APM_REGION3_R0_X_M (HP_APM_REGION3_R0_X_V << HP_APM_REGION3_R0_X_S) #define HP_APM_REGION3_R0_X_V 0x00000001U #define HP_APM_REGION3_R0_X_S 0 /** HP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_W (BIT(1)) #define HP_APM_REGION3_R0_W_M (HP_APM_REGION3_R0_W_V << HP_APM_REGION3_R0_W_S) #define HP_APM_REGION3_R0_W_V 0x00000001U #define HP_APM_REGION3_R0_W_S 1 /** HP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define HP_APM_REGION3_R0_R (BIT(2)) #define HP_APM_REGION3_R0_R_M (HP_APM_REGION3_R0_R_V << HP_APM_REGION3_R0_R_S) #define HP_APM_REGION3_R0_R_V 0x00000001U #define HP_APM_REGION3_R0_R_S 2 /** HP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_X (BIT(4)) #define HP_APM_REGION3_R1_X_M (HP_APM_REGION3_R1_X_V << HP_APM_REGION3_R1_X_S) #define HP_APM_REGION3_R1_X_V 0x00000001U #define HP_APM_REGION3_R1_X_S 4 /** HP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_W (BIT(5)) #define HP_APM_REGION3_R1_W_M (HP_APM_REGION3_R1_W_V << HP_APM_REGION3_R1_W_S) #define HP_APM_REGION3_R1_W_V 0x00000001U #define HP_APM_REGION3_R1_W_S 5 /** HP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define HP_APM_REGION3_R1_R (BIT(6)) #define HP_APM_REGION3_R1_R_M (HP_APM_REGION3_R1_R_V << HP_APM_REGION3_R1_R_S) #define HP_APM_REGION3_R1_R_V 0x00000001U #define HP_APM_REGION3_R1_R_S 6 /** HP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_X (BIT(8)) #define HP_APM_REGION3_R2_X_M (HP_APM_REGION3_R2_X_V << HP_APM_REGION3_R2_X_S) #define HP_APM_REGION3_R2_X_V 0x00000001U #define HP_APM_REGION3_R2_X_S 8 /** HP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_W (BIT(9)) #define HP_APM_REGION3_R2_W_M (HP_APM_REGION3_R2_W_V << HP_APM_REGION3_R2_W_S) #define HP_APM_REGION3_R2_W_V 0x00000001U #define HP_APM_REGION3_R2_W_S 9 /** HP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define HP_APM_REGION3_R2_R (BIT(10)) #define HP_APM_REGION3_R2_R_M (HP_APM_REGION3_R2_R_V << HP_APM_REGION3_R2_R_S) #define HP_APM_REGION3_R2_R_V 0x00000001U #define HP_APM_REGION3_R2_R_S 10 /** HP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (HP_APM_REGION3_ADDR_START_REG, HP_APM_REGION3_ADDR_END_REG and + * HP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION3_LOCK (BIT(11)) #define HP_APM_REGION3_LOCK_M (HP_APM_REGION3_LOCK_V << HP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x34) /** HP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define HP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_START_M (HP_APM_REGION4_ADDR_START_V << HP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define HP_APM_REGION4_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x38) /** HP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define HP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION4_ADDR_END_M (HP_APM_REGION4_ADDR_END_V << HP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define HP_APM_REGION4_ADDR_END_S 0 /** HP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION4_ATTR_REG (DR_REG_HP_APM_BASE + 0x3c) /** HP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_X (BIT(0)) #define HP_APM_REGION4_R0_X_M (HP_APM_REGION4_R0_X_V << HP_APM_REGION4_R0_X_S) #define HP_APM_REGION4_R0_X_V 0x00000001U #define HP_APM_REGION4_R0_X_S 0 /** HP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_W (BIT(1)) #define HP_APM_REGION4_R0_W_M (HP_APM_REGION4_R0_W_V << HP_APM_REGION4_R0_W_S) #define HP_APM_REGION4_R0_W_V 0x00000001U #define HP_APM_REGION4_R0_W_S 1 /** HP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define HP_APM_REGION4_R0_R (BIT(2)) #define HP_APM_REGION4_R0_R_M (HP_APM_REGION4_R0_R_V << HP_APM_REGION4_R0_R_S) #define HP_APM_REGION4_R0_R_V 0x00000001U #define HP_APM_REGION4_R0_R_S 2 /** HP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_X (BIT(4)) #define HP_APM_REGION4_R1_X_M (HP_APM_REGION4_R1_X_V << HP_APM_REGION4_R1_X_S) #define HP_APM_REGION4_R1_X_V 0x00000001U #define HP_APM_REGION4_R1_X_S 4 /** HP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_W (BIT(5)) #define HP_APM_REGION4_R1_W_M (HP_APM_REGION4_R1_W_V << HP_APM_REGION4_R1_W_S) #define HP_APM_REGION4_R1_W_V 0x00000001U #define HP_APM_REGION4_R1_W_S 5 /** HP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define HP_APM_REGION4_R1_R (BIT(6)) #define HP_APM_REGION4_R1_R_M (HP_APM_REGION4_R1_R_V << HP_APM_REGION4_R1_R_S) #define HP_APM_REGION4_R1_R_V 0x00000001U #define HP_APM_REGION4_R1_R_S 6 /** HP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_X (BIT(8)) #define HP_APM_REGION4_R2_X_M (HP_APM_REGION4_R2_X_V << HP_APM_REGION4_R2_X_S) #define HP_APM_REGION4_R2_X_V 0x00000001U #define HP_APM_REGION4_R2_X_S 8 /** HP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_W (BIT(9)) #define HP_APM_REGION4_R2_W_M (HP_APM_REGION4_R2_W_V << HP_APM_REGION4_R2_W_S) #define HP_APM_REGION4_R2_W_V 0x00000001U #define HP_APM_REGION4_R2_W_S 9 /** HP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define HP_APM_REGION4_R2_R (BIT(10)) #define HP_APM_REGION4_R2_R_M (HP_APM_REGION4_R2_R_V << HP_APM_REGION4_R2_R_S) #define HP_APM_REGION4_R2_R_V 0x00000001U #define HP_APM_REGION4_R2_R_S 10 /** HP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (HP_APM_REGION4_ADDR_START_REG, HP_APM_REGION4_ADDR_END_REG and + * HP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION4_LOCK (BIT(11)) #define HP_APM_REGION4_LOCK_M (HP_APM_REGION4_LOCK_V << HP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x40) /** HP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define HP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_START_M (HP_APM_REGION5_ADDR_START_V << HP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define HP_APM_REGION5_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x44) /** HP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define HP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION5_ADDR_END_M (HP_APM_REGION5_ADDR_END_V << HP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define HP_APM_REGION5_ADDR_END_S 0 /** HP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION5_ATTR_REG (DR_REG_HP_APM_BASE + 0x48) /** HP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_X (BIT(0)) #define HP_APM_REGION5_R0_X_M (HP_APM_REGION5_R0_X_V << HP_APM_REGION5_R0_X_S) #define HP_APM_REGION5_R0_X_V 0x00000001U #define HP_APM_REGION5_R0_X_S 0 /** HP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_W (BIT(1)) #define HP_APM_REGION5_R0_W_M (HP_APM_REGION5_R0_W_V << HP_APM_REGION5_R0_W_S) #define HP_APM_REGION5_R0_W_V 0x00000001U #define HP_APM_REGION5_R0_W_S 1 /** HP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define HP_APM_REGION5_R0_R (BIT(2)) #define HP_APM_REGION5_R0_R_M (HP_APM_REGION5_R0_R_V << HP_APM_REGION5_R0_R_S) #define HP_APM_REGION5_R0_R_V 0x00000001U #define HP_APM_REGION5_R0_R_S 2 /** HP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_X (BIT(4)) #define HP_APM_REGION5_R1_X_M (HP_APM_REGION5_R1_X_V << HP_APM_REGION5_R1_X_S) #define HP_APM_REGION5_R1_X_V 0x00000001U #define HP_APM_REGION5_R1_X_S 4 /** HP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_W (BIT(5)) #define HP_APM_REGION5_R1_W_M (HP_APM_REGION5_R1_W_V << HP_APM_REGION5_R1_W_S) #define HP_APM_REGION5_R1_W_V 0x00000001U #define HP_APM_REGION5_R1_W_S 5 /** HP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define HP_APM_REGION5_R1_R (BIT(6)) #define HP_APM_REGION5_R1_R_M (HP_APM_REGION5_R1_R_V << HP_APM_REGION5_R1_R_S) #define HP_APM_REGION5_R1_R_V 0x00000001U #define HP_APM_REGION5_R1_R_S 6 /** HP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_X (BIT(8)) #define HP_APM_REGION5_R2_X_M (HP_APM_REGION5_R2_X_V << HP_APM_REGION5_R2_X_S) #define HP_APM_REGION5_R2_X_V 0x00000001U #define HP_APM_REGION5_R2_X_S 8 /** HP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_W (BIT(9)) #define HP_APM_REGION5_R2_W_M (HP_APM_REGION5_R2_W_V << HP_APM_REGION5_R2_W_S) #define HP_APM_REGION5_R2_W_V 0x00000001U #define HP_APM_REGION5_R2_W_S 9 /** HP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define HP_APM_REGION5_R2_R (BIT(10)) #define HP_APM_REGION5_R2_R_M (HP_APM_REGION5_R2_R_V << HP_APM_REGION5_R2_R_S) #define HP_APM_REGION5_R2_R_V 0x00000001U #define HP_APM_REGION5_R2_R_S 10 /** HP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (HP_APM_REGION5_ADDR_START_REG, HP_APM_REGION5_ADDR_END_REG and + * HP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION5_LOCK (BIT(11)) #define HP_APM_REGION5_LOCK_M (HP_APM_REGION5_LOCK_V << HP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x4c) /** HP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define HP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_START_M (HP_APM_REGION6_ADDR_START_V << HP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define HP_APM_REGION6_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x50) /** HP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define HP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION6_ADDR_END_M (HP_APM_REGION6_ADDR_END_V << HP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define HP_APM_REGION6_ADDR_END_S 0 /** HP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION6_ATTR_REG (DR_REG_HP_APM_BASE + 0x54) /** HP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_X (BIT(0)) #define HP_APM_REGION6_R0_X_M (HP_APM_REGION6_R0_X_V << HP_APM_REGION6_R0_X_S) #define HP_APM_REGION6_R0_X_V 0x00000001U #define HP_APM_REGION6_R0_X_S 0 /** HP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_W (BIT(1)) #define HP_APM_REGION6_R0_W_M (HP_APM_REGION6_R0_W_V << HP_APM_REGION6_R0_W_S) #define HP_APM_REGION6_R0_W_V 0x00000001U #define HP_APM_REGION6_R0_W_S 1 /** HP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define HP_APM_REGION6_R0_R (BIT(2)) #define HP_APM_REGION6_R0_R_M (HP_APM_REGION6_R0_R_V << HP_APM_REGION6_R0_R_S) #define HP_APM_REGION6_R0_R_V 0x00000001U #define HP_APM_REGION6_R0_R_S 2 /** HP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_X (BIT(4)) #define HP_APM_REGION6_R1_X_M (HP_APM_REGION6_R1_X_V << HP_APM_REGION6_R1_X_S) #define HP_APM_REGION6_R1_X_V 0x00000001U #define HP_APM_REGION6_R1_X_S 4 /** HP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_W (BIT(5)) #define HP_APM_REGION6_R1_W_M (HP_APM_REGION6_R1_W_V << HP_APM_REGION6_R1_W_S) #define HP_APM_REGION6_R1_W_V 0x00000001U #define HP_APM_REGION6_R1_W_S 5 /** HP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define HP_APM_REGION6_R1_R (BIT(6)) #define HP_APM_REGION6_R1_R_M (HP_APM_REGION6_R1_R_V << HP_APM_REGION6_R1_R_S) #define HP_APM_REGION6_R1_R_V 0x00000001U #define HP_APM_REGION6_R1_R_S 6 /** HP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_X (BIT(8)) #define HP_APM_REGION6_R2_X_M (HP_APM_REGION6_R2_X_V << HP_APM_REGION6_R2_X_S) #define HP_APM_REGION6_R2_X_V 0x00000001U #define HP_APM_REGION6_R2_X_S 8 /** HP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_W (BIT(9)) #define HP_APM_REGION6_R2_W_M (HP_APM_REGION6_R2_W_V << HP_APM_REGION6_R2_W_S) #define HP_APM_REGION6_R2_W_V 0x00000001U #define HP_APM_REGION6_R2_W_S 9 /** HP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define HP_APM_REGION6_R2_R (BIT(10)) #define HP_APM_REGION6_R2_R_M (HP_APM_REGION6_R2_R_V << HP_APM_REGION6_R2_R_S) #define HP_APM_REGION6_R2_R_V 0x00000001U #define HP_APM_REGION6_R2_R_S 10 /** HP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (HP_APM_REGION6_ADDR_START_REG, HP_APM_REGION6_ADDR_END_REG and + * HP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION6_LOCK (BIT(11)) #define HP_APM_REGION6_LOCK_M (HP_APM_REGION6_LOCK_V << HP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x58) /** HP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define HP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_START_M (HP_APM_REGION7_ADDR_START_V << HP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define HP_APM_REGION7_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x5c) /** HP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define HP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION7_ADDR_END_M (HP_APM_REGION7_ADDR_END_V << HP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define HP_APM_REGION7_ADDR_END_S 0 /** HP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION7_ATTR_REG (DR_REG_HP_APM_BASE + 0x60) /** HP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_X (BIT(0)) #define HP_APM_REGION7_R0_X_M (HP_APM_REGION7_R0_X_V << HP_APM_REGION7_R0_X_S) #define HP_APM_REGION7_R0_X_V 0x00000001U #define HP_APM_REGION7_R0_X_S 0 /** HP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_W (BIT(1)) #define HP_APM_REGION7_R0_W_M (HP_APM_REGION7_R0_W_V << HP_APM_REGION7_R0_W_S) #define HP_APM_REGION7_R0_W_V 0x00000001U #define HP_APM_REGION7_R0_W_S 1 /** HP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define HP_APM_REGION7_R0_R (BIT(2)) #define HP_APM_REGION7_R0_R_M (HP_APM_REGION7_R0_R_V << HP_APM_REGION7_R0_R_S) #define HP_APM_REGION7_R0_R_V 0x00000001U #define HP_APM_REGION7_R0_R_S 2 /** HP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_X (BIT(4)) #define HP_APM_REGION7_R1_X_M (HP_APM_REGION7_R1_X_V << HP_APM_REGION7_R1_X_S) #define HP_APM_REGION7_R1_X_V 0x00000001U #define HP_APM_REGION7_R1_X_S 4 /** HP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_W (BIT(5)) #define HP_APM_REGION7_R1_W_M (HP_APM_REGION7_R1_W_V << HP_APM_REGION7_R1_W_S) #define HP_APM_REGION7_R1_W_V 0x00000001U #define HP_APM_REGION7_R1_W_S 5 /** HP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define HP_APM_REGION7_R1_R (BIT(6)) #define HP_APM_REGION7_R1_R_M (HP_APM_REGION7_R1_R_V << HP_APM_REGION7_R1_R_S) #define HP_APM_REGION7_R1_R_V 0x00000001U #define HP_APM_REGION7_R1_R_S 6 /** HP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_X (BIT(8)) #define HP_APM_REGION7_R2_X_M (HP_APM_REGION7_R2_X_V << HP_APM_REGION7_R2_X_S) #define HP_APM_REGION7_R2_X_V 0x00000001U #define HP_APM_REGION7_R2_X_S 8 /** HP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_W (BIT(9)) #define HP_APM_REGION7_R2_W_M (HP_APM_REGION7_R2_W_V << HP_APM_REGION7_R2_W_S) #define HP_APM_REGION7_R2_W_V 0x00000001U #define HP_APM_REGION7_R2_W_S 9 /** HP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define HP_APM_REGION7_R2_R (BIT(10)) #define HP_APM_REGION7_R2_R_M (HP_APM_REGION7_R2_R_V << HP_APM_REGION7_R2_R_S) #define HP_APM_REGION7_R2_R_V 0x00000001U #define HP_APM_REGION7_R2_R_S 10 /** HP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (HP_APM_REGION7_ADDR_START_REG, HP_APM_REGION7_ADDR_END_REG and + * HP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION7_LOCK (BIT(11)) #define HP_APM_REGION7_LOCK_M (HP_APM_REGION7_LOCK_V << HP_APM_REGION7_LOCK_S) @@ -822,7 +854,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x64) /** HP_APM_REGION8_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 8. + * Configures the start address of region 8. */ #define HP_APM_REGION8_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_START_M (HP_APM_REGION8_ADDR_START_V << HP_APM_REGION8_ADDR_START_S) @@ -834,7 +866,7 @@ extern "C" { */ #define HP_APM_REGION8_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x68) /** HP_APM_REGION8_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 8. + * Configures the end address of region 8. */ #define HP_APM_REGION8_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION8_ADDR_END_M (HP_APM_REGION8_ADDR_END_V << HP_APM_REGION8_ADDR_END_S) @@ -842,74 +874,78 @@ extern "C" { #define HP_APM_REGION8_ADDR_END_S 0 /** HP_APM_REGION8_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION8_ATTR_REG (DR_REG_HP_APM_BASE + 0x6c) /** HP_APM_REGION8_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 8. + * Configures the execution permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_X (BIT(0)) #define HP_APM_REGION8_R0_X_M (HP_APM_REGION8_R0_X_V << HP_APM_REGION8_R0_X_S) #define HP_APM_REGION8_R0_X_V 0x00000001U #define HP_APM_REGION8_R0_X_S 0 /** HP_APM_REGION8_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 8. + * Configures the write permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_W (BIT(1)) #define HP_APM_REGION8_R0_W_M (HP_APM_REGION8_R0_W_V << HP_APM_REGION8_R0_W_S) #define HP_APM_REGION8_R0_W_V 0x00000001U #define HP_APM_REGION8_R0_W_S 1 /** HP_APM_REGION8_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 8. + * Configures the read permission in region 8 in REE0 mode. */ #define HP_APM_REGION8_R0_R (BIT(2)) #define HP_APM_REGION8_R0_R_M (HP_APM_REGION8_R0_R_V << HP_APM_REGION8_R0_R_S) #define HP_APM_REGION8_R0_R_V 0x00000001U #define HP_APM_REGION8_R0_R_S 2 /** HP_APM_REGION8_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 8. + * Configures the execution permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_X (BIT(4)) #define HP_APM_REGION8_R1_X_M (HP_APM_REGION8_R1_X_V << HP_APM_REGION8_R1_X_S) #define HP_APM_REGION8_R1_X_V 0x00000001U #define HP_APM_REGION8_R1_X_S 4 /** HP_APM_REGION8_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 8. + * Configures the write permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_W (BIT(5)) #define HP_APM_REGION8_R1_W_M (HP_APM_REGION8_R1_W_V << HP_APM_REGION8_R1_W_S) #define HP_APM_REGION8_R1_W_V 0x00000001U #define HP_APM_REGION8_R1_W_S 5 /** HP_APM_REGION8_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 8. + * Configures the read permission in region 8 in REE1 mode. */ #define HP_APM_REGION8_R1_R (BIT(6)) #define HP_APM_REGION8_R1_R_M (HP_APM_REGION8_R1_R_V << HP_APM_REGION8_R1_R_S) #define HP_APM_REGION8_R1_R_V 0x00000001U #define HP_APM_REGION8_R1_R_S 6 /** HP_APM_REGION8_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 8. + * Configures the execution permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_X (BIT(8)) #define HP_APM_REGION8_R2_X_M (HP_APM_REGION8_R2_X_V << HP_APM_REGION8_R2_X_S) #define HP_APM_REGION8_R2_X_V 0x00000001U #define HP_APM_REGION8_R2_X_S 8 /** HP_APM_REGION8_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 8. + * Configures the write permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_W (BIT(9)) #define HP_APM_REGION8_R2_W_M (HP_APM_REGION8_R2_W_V << HP_APM_REGION8_R2_W_S) #define HP_APM_REGION8_R2_W_V 0x00000001U #define HP_APM_REGION8_R2_W_S 9 /** HP_APM_REGION8_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 8. + * Configures the read permission in region 8 in REE2 mode. */ #define HP_APM_REGION8_R2_R (BIT(10)) #define HP_APM_REGION8_R2_R_M (HP_APM_REGION8_R2_R_V << HP_APM_REGION8_R2_R_S) #define HP_APM_REGION8_R2_R_V 0x00000001U #define HP_APM_REGION8_R2_R_S 10 /** HP_APM_REGION8_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 8 configuration registers + * (HP_APM_REGION8_ADDR_START_REG, HP_APM_REGION8_ADDR_END_REG and + * HP_APM_REGION8_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION8_LOCK (BIT(11)) #define HP_APM_REGION8_LOCK_M (HP_APM_REGION8_LOCK_V << HP_APM_REGION8_LOCK_S) @@ -921,7 +957,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x70) /** HP_APM_REGION9_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 9. + * Configures the start address of region 9. */ #define HP_APM_REGION9_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_START_M (HP_APM_REGION9_ADDR_START_V << HP_APM_REGION9_ADDR_START_S) @@ -933,7 +969,7 @@ extern "C" { */ #define HP_APM_REGION9_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x74) /** HP_APM_REGION9_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 9. + * Configures the end address of region 9. */ #define HP_APM_REGION9_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION9_ADDR_END_M (HP_APM_REGION9_ADDR_END_V << HP_APM_REGION9_ADDR_END_S) @@ -941,74 +977,78 @@ extern "C" { #define HP_APM_REGION9_ADDR_END_S 0 /** HP_APM_REGION9_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION9_ATTR_REG (DR_REG_HP_APM_BASE + 0x78) /** HP_APM_REGION9_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 9. + * Configures the execution permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_X (BIT(0)) #define HP_APM_REGION9_R0_X_M (HP_APM_REGION9_R0_X_V << HP_APM_REGION9_R0_X_S) #define HP_APM_REGION9_R0_X_V 0x00000001U #define HP_APM_REGION9_R0_X_S 0 /** HP_APM_REGION9_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 9. + * Configures the write permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_W (BIT(1)) #define HP_APM_REGION9_R0_W_M (HP_APM_REGION9_R0_W_V << HP_APM_REGION9_R0_W_S) #define HP_APM_REGION9_R0_W_V 0x00000001U #define HP_APM_REGION9_R0_W_S 1 /** HP_APM_REGION9_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 9. + * Configures the read permission in region 9 in REE0 mode. */ #define HP_APM_REGION9_R0_R (BIT(2)) #define HP_APM_REGION9_R0_R_M (HP_APM_REGION9_R0_R_V << HP_APM_REGION9_R0_R_S) #define HP_APM_REGION9_R0_R_V 0x00000001U #define HP_APM_REGION9_R0_R_S 2 /** HP_APM_REGION9_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 9. + * Configures the execution permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_X (BIT(4)) #define HP_APM_REGION9_R1_X_M (HP_APM_REGION9_R1_X_V << HP_APM_REGION9_R1_X_S) #define HP_APM_REGION9_R1_X_V 0x00000001U #define HP_APM_REGION9_R1_X_S 4 /** HP_APM_REGION9_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 9. + * Configures the write permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_W (BIT(5)) #define HP_APM_REGION9_R1_W_M (HP_APM_REGION9_R1_W_V << HP_APM_REGION9_R1_W_S) #define HP_APM_REGION9_R1_W_V 0x00000001U #define HP_APM_REGION9_R1_W_S 5 /** HP_APM_REGION9_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 9. + * Configures the read permission in region 9 in REE1 mode. */ #define HP_APM_REGION9_R1_R (BIT(6)) #define HP_APM_REGION9_R1_R_M (HP_APM_REGION9_R1_R_V << HP_APM_REGION9_R1_R_S) #define HP_APM_REGION9_R1_R_V 0x00000001U #define HP_APM_REGION9_R1_R_S 6 /** HP_APM_REGION9_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 9. + * Configures the execution permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_X (BIT(8)) #define HP_APM_REGION9_R2_X_M (HP_APM_REGION9_R2_X_V << HP_APM_REGION9_R2_X_S) #define HP_APM_REGION9_R2_X_V 0x00000001U #define HP_APM_REGION9_R2_X_S 8 /** HP_APM_REGION9_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 9. + * Configures the write permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_W (BIT(9)) #define HP_APM_REGION9_R2_W_M (HP_APM_REGION9_R2_W_V << HP_APM_REGION9_R2_W_S) #define HP_APM_REGION9_R2_W_V 0x00000001U #define HP_APM_REGION9_R2_W_S 9 /** HP_APM_REGION9_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 9. + * Configures the read permission in region 9 in REE2 mode. */ #define HP_APM_REGION9_R2_R (BIT(10)) #define HP_APM_REGION9_R2_R_M (HP_APM_REGION9_R2_R_V << HP_APM_REGION9_R2_R_S) #define HP_APM_REGION9_R2_R_V 0x00000001U #define HP_APM_REGION9_R2_R_S 10 /** HP_APM_REGION9_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 9 configuration registers + * (HP_APM_REGION9_ADDR_START_REG, HP_APM_REGION9_ADDR_END_REG and + * HP_APM_REGION9_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION9_LOCK (BIT(11)) #define HP_APM_REGION9_LOCK_M (HP_APM_REGION9_LOCK_V << HP_APM_REGION9_LOCK_S) @@ -1020,7 +1060,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x7c) /** HP_APM_REGION10_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 10. + * Configures the start address of region 10. */ #define HP_APM_REGION10_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_START_M (HP_APM_REGION10_ADDR_START_V << HP_APM_REGION10_ADDR_START_S) @@ -1032,7 +1072,7 @@ extern "C" { */ #define HP_APM_REGION10_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x80) /** HP_APM_REGION10_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 10. + * Configures the end address of region 10. */ #define HP_APM_REGION10_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION10_ADDR_END_M (HP_APM_REGION10_ADDR_END_V << HP_APM_REGION10_ADDR_END_S) @@ -1040,74 +1080,78 @@ extern "C" { #define HP_APM_REGION10_ADDR_END_S 0 /** HP_APM_REGION10_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION10_ATTR_REG (DR_REG_HP_APM_BASE + 0x84) /** HP_APM_REGION10_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 10. + * Configures the execution permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_X (BIT(0)) #define HP_APM_REGION10_R0_X_M (HP_APM_REGION10_R0_X_V << HP_APM_REGION10_R0_X_S) #define HP_APM_REGION10_R0_X_V 0x00000001U #define HP_APM_REGION10_R0_X_S 0 /** HP_APM_REGION10_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 10. + * Configures the write permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_W (BIT(1)) #define HP_APM_REGION10_R0_W_M (HP_APM_REGION10_R0_W_V << HP_APM_REGION10_R0_W_S) #define HP_APM_REGION10_R0_W_V 0x00000001U #define HP_APM_REGION10_R0_W_S 1 /** HP_APM_REGION10_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 10. + * Configures the read permission in region 10 in REE0 mode. */ #define HP_APM_REGION10_R0_R (BIT(2)) #define HP_APM_REGION10_R0_R_M (HP_APM_REGION10_R0_R_V << HP_APM_REGION10_R0_R_S) #define HP_APM_REGION10_R0_R_V 0x00000001U #define HP_APM_REGION10_R0_R_S 2 /** HP_APM_REGION10_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 10. + * Configures the execution permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_X (BIT(4)) #define HP_APM_REGION10_R1_X_M (HP_APM_REGION10_R1_X_V << HP_APM_REGION10_R1_X_S) #define HP_APM_REGION10_R1_X_V 0x00000001U #define HP_APM_REGION10_R1_X_S 4 /** HP_APM_REGION10_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 10. + * Configures the write permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_W (BIT(5)) #define HP_APM_REGION10_R1_W_M (HP_APM_REGION10_R1_W_V << HP_APM_REGION10_R1_W_S) #define HP_APM_REGION10_R1_W_V 0x00000001U #define HP_APM_REGION10_R1_W_S 5 /** HP_APM_REGION10_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 10. + * Configures the read permission in region 10 in REE1 mode. */ #define HP_APM_REGION10_R1_R (BIT(6)) #define HP_APM_REGION10_R1_R_M (HP_APM_REGION10_R1_R_V << HP_APM_REGION10_R1_R_S) #define HP_APM_REGION10_R1_R_V 0x00000001U #define HP_APM_REGION10_R1_R_S 6 /** HP_APM_REGION10_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 10. + * Configures the execution permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_X (BIT(8)) #define HP_APM_REGION10_R2_X_M (HP_APM_REGION10_R2_X_V << HP_APM_REGION10_R2_X_S) #define HP_APM_REGION10_R2_X_V 0x00000001U #define HP_APM_REGION10_R2_X_S 8 /** HP_APM_REGION10_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 10. + * Configures the write permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_W (BIT(9)) #define HP_APM_REGION10_R2_W_M (HP_APM_REGION10_R2_W_V << HP_APM_REGION10_R2_W_S) #define HP_APM_REGION10_R2_W_V 0x00000001U #define HP_APM_REGION10_R2_W_S 9 /** HP_APM_REGION10_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 10. + * Configures the read permission in region 10 in REE2 mode. */ #define HP_APM_REGION10_R2_R (BIT(10)) #define HP_APM_REGION10_R2_R_M (HP_APM_REGION10_R2_R_V << HP_APM_REGION10_R2_R_S) #define HP_APM_REGION10_R2_R_V 0x00000001U #define HP_APM_REGION10_R2_R_S 10 /** HP_APM_REGION10_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 10 configuration registers + * (HP_APM_REGION10_ADDR_START_REG, HP_APM_REGION10_ADDR_END_REG and + * HP_APM_REGION10_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION10_LOCK (BIT(11)) #define HP_APM_REGION10_LOCK_M (HP_APM_REGION10_LOCK_V << HP_APM_REGION10_LOCK_S) @@ -1119,7 +1163,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x88) /** HP_APM_REGION11_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 11. + * Configures the start address of region 11. */ #define HP_APM_REGION11_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_START_M (HP_APM_REGION11_ADDR_START_V << HP_APM_REGION11_ADDR_START_S) @@ -1131,7 +1175,7 @@ extern "C" { */ #define HP_APM_REGION11_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x8c) /** HP_APM_REGION11_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 11. + * Configures the end address of region 11. */ #define HP_APM_REGION11_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION11_ADDR_END_M (HP_APM_REGION11_ADDR_END_V << HP_APM_REGION11_ADDR_END_S) @@ -1139,74 +1183,78 @@ extern "C" { #define HP_APM_REGION11_ADDR_END_S 0 /** HP_APM_REGION11_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION11_ATTR_REG (DR_REG_HP_APM_BASE + 0x90) /** HP_APM_REGION11_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 11. + * Configures the execution permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_X (BIT(0)) #define HP_APM_REGION11_R0_X_M (HP_APM_REGION11_R0_X_V << HP_APM_REGION11_R0_X_S) #define HP_APM_REGION11_R0_X_V 0x00000001U #define HP_APM_REGION11_R0_X_S 0 /** HP_APM_REGION11_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 11. + * Configures the write permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_W (BIT(1)) #define HP_APM_REGION11_R0_W_M (HP_APM_REGION11_R0_W_V << HP_APM_REGION11_R0_W_S) #define HP_APM_REGION11_R0_W_V 0x00000001U #define HP_APM_REGION11_R0_W_S 1 /** HP_APM_REGION11_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 11. + * Configures the read permission in region 11 in REE0 mode. */ #define HP_APM_REGION11_R0_R (BIT(2)) #define HP_APM_REGION11_R0_R_M (HP_APM_REGION11_R0_R_V << HP_APM_REGION11_R0_R_S) #define HP_APM_REGION11_R0_R_V 0x00000001U #define HP_APM_REGION11_R0_R_S 2 /** HP_APM_REGION11_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 11. + * Configures the execution permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_X (BIT(4)) #define HP_APM_REGION11_R1_X_M (HP_APM_REGION11_R1_X_V << HP_APM_REGION11_R1_X_S) #define HP_APM_REGION11_R1_X_V 0x00000001U #define HP_APM_REGION11_R1_X_S 4 /** HP_APM_REGION11_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 11. + * Configures the write permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_W (BIT(5)) #define HP_APM_REGION11_R1_W_M (HP_APM_REGION11_R1_W_V << HP_APM_REGION11_R1_W_S) #define HP_APM_REGION11_R1_W_V 0x00000001U #define HP_APM_REGION11_R1_W_S 5 /** HP_APM_REGION11_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 11. + * Configures the read permission in region 11 in REE1 mode. */ #define HP_APM_REGION11_R1_R (BIT(6)) #define HP_APM_REGION11_R1_R_M (HP_APM_REGION11_R1_R_V << HP_APM_REGION11_R1_R_S) #define HP_APM_REGION11_R1_R_V 0x00000001U #define HP_APM_REGION11_R1_R_S 6 /** HP_APM_REGION11_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 11. + * Configures the execution permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_X (BIT(8)) #define HP_APM_REGION11_R2_X_M (HP_APM_REGION11_R2_X_V << HP_APM_REGION11_R2_X_S) #define HP_APM_REGION11_R2_X_V 0x00000001U #define HP_APM_REGION11_R2_X_S 8 /** HP_APM_REGION11_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 11. + * Configures the write permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_W (BIT(9)) #define HP_APM_REGION11_R2_W_M (HP_APM_REGION11_R2_W_V << HP_APM_REGION11_R2_W_S) #define HP_APM_REGION11_R2_W_V 0x00000001U #define HP_APM_REGION11_R2_W_S 9 /** HP_APM_REGION11_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 11. + * Configures the read permission in region 11 in REE2 mode. */ #define HP_APM_REGION11_R2_R (BIT(10)) #define HP_APM_REGION11_R2_R_M (HP_APM_REGION11_R2_R_V << HP_APM_REGION11_R2_R_S) #define HP_APM_REGION11_R2_R_V 0x00000001U #define HP_APM_REGION11_R2_R_S 10 /** HP_APM_REGION11_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 11 configuration registers + * (HP_APM_REGION11_ADDR_START_REG, HP_APM_REGION11_ADDR_END_REG and + * HP_APM_REGION11_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION11_LOCK (BIT(11)) #define HP_APM_REGION11_LOCK_M (HP_APM_REGION11_LOCK_V << HP_APM_REGION11_LOCK_S) @@ -1218,7 +1266,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_START_REG (DR_REG_HP_APM_BASE + 0x94) /** HP_APM_REGION12_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 12. + * Configures the start address of region 12. */ #define HP_APM_REGION12_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_START_M (HP_APM_REGION12_ADDR_START_V << HP_APM_REGION12_ADDR_START_S) @@ -1230,7 +1278,7 @@ extern "C" { */ #define HP_APM_REGION12_ADDR_END_REG (DR_REG_HP_APM_BASE + 0x98) /** HP_APM_REGION12_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 12. + * Configures the end address of region 12. */ #define HP_APM_REGION12_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION12_ADDR_END_M (HP_APM_REGION12_ADDR_END_V << HP_APM_REGION12_ADDR_END_S) @@ -1238,74 +1286,78 @@ extern "C" { #define HP_APM_REGION12_ADDR_END_S 0 /** HP_APM_REGION12_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION12_ATTR_REG (DR_REG_HP_APM_BASE + 0x9c) /** HP_APM_REGION12_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 12. + * Configures the execution permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_X (BIT(0)) #define HP_APM_REGION12_R0_X_M (HP_APM_REGION12_R0_X_V << HP_APM_REGION12_R0_X_S) #define HP_APM_REGION12_R0_X_V 0x00000001U #define HP_APM_REGION12_R0_X_S 0 /** HP_APM_REGION12_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 12. + * Configures the write permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_W (BIT(1)) #define HP_APM_REGION12_R0_W_M (HP_APM_REGION12_R0_W_V << HP_APM_REGION12_R0_W_S) #define HP_APM_REGION12_R0_W_V 0x00000001U #define HP_APM_REGION12_R0_W_S 1 /** HP_APM_REGION12_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 12. + * Configures the read permission in region 12 in REE0 mode. */ #define HP_APM_REGION12_R0_R (BIT(2)) #define HP_APM_REGION12_R0_R_M (HP_APM_REGION12_R0_R_V << HP_APM_REGION12_R0_R_S) #define HP_APM_REGION12_R0_R_V 0x00000001U #define HP_APM_REGION12_R0_R_S 2 /** HP_APM_REGION12_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 12. + * Configures the execution permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_X (BIT(4)) #define HP_APM_REGION12_R1_X_M (HP_APM_REGION12_R1_X_V << HP_APM_REGION12_R1_X_S) #define HP_APM_REGION12_R1_X_V 0x00000001U #define HP_APM_REGION12_R1_X_S 4 /** HP_APM_REGION12_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 12. + * Configures the write permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_W (BIT(5)) #define HP_APM_REGION12_R1_W_M (HP_APM_REGION12_R1_W_V << HP_APM_REGION12_R1_W_S) #define HP_APM_REGION12_R1_W_V 0x00000001U #define HP_APM_REGION12_R1_W_S 5 /** HP_APM_REGION12_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 12. + * Configures the read permission in region 12 in REE1 mode. */ #define HP_APM_REGION12_R1_R (BIT(6)) #define HP_APM_REGION12_R1_R_M (HP_APM_REGION12_R1_R_V << HP_APM_REGION12_R1_R_S) #define HP_APM_REGION12_R1_R_V 0x00000001U #define HP_APM_REGION12_R1_R_S 6 /** HP_APM_REGION12_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 12. + * Configures the execution permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_X (BIT(8)) #define HP_APM_REGION12_R2_X_M (HP_APM_REGION12_R2_X_V << HP_APM_REGION12_R2_X_S) #define HP_APM_REGION12_R2_X_V 0x00000001U #define HP_APM_REGION12_R2_X_S 8 /** HP_APM_REGION12_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 12. + * Configures the write permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_W (BIT(9)) #define HP_APM_REGION12_R2_W_M (HP_APM_REGION12_R2_W_V << HP_APM_REGION12_R2_W_S) #define HP_APM_REGION12_R2_W_V 0x00000001U #define HP_APM_REGION12_R2_W_S 9 /** HP_APM_REGION12_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 12. + * Configures the read permission in region 12 in REE2 mode. */ #define HP_APM_REGION12_R2_R (BIT(10)) #define HP_APM_REGION12_R2_R_M (HP_APM_REGION12_R2_R_V << HP_APM_REGION12_R2_R_S) #define HP_APM_REGION12_R2_R_V 0x00000001U #define HP_APM_REGION12_R2_R_S 10 /** HP_APM_REGION12_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 12 configuration registers + * (HP_APM_REGION12_ADDR_START_REG, HP_APM_REGION12_ADDR_END_REG and + * HP_APM_REGION12_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION12_LOCK (BIT(11)) #define HP_APM_REGION12_LOCK_M (HP_APM_REGION12_LOCK_V << HP_APM_REGION12_LOCK_S) @@ -1317,7 +1369,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xa0) /** HP_APM_REGION13_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 13. + * Configures the start address of region 13. */ #define HP_APM_REGION13_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_START_M (HP_APM_REGION13_ADDR_START_V << HP_APM_REGION13_ADDR_START_S) @@ -1329,7 +1381,7 @@ extern "C" { */ #define HP_APM_REGION13_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xa4) /** HP_APM_REGION13_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 13. + * Configures the end address of region 13. */ #define HP_APM_REGION13_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION13_ADDR_END_M (HP_APM_REGION13_ADDR_END_V << HP_APM_REGION13_ADDR_END_S) @@ -1337,74 +1389,78 @@ extern "C" { #define HP_APM_REGION13_ADDR_END_S 0 /** HP_APM_REGION13_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION13_ATTR_REG (DR_REG_HP_APM_BASE + 0xa8) /** HP_APM_REGION13_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 13. + * Configures the execution permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_X (BIT(0)) #define HP_APM_REGION13_R0_X_M (HP_APM_REGION13_R0_X_V << HP_APM_REGION13_R0_X_S) #define HP_APM_REGION13_R0_X_V 0x00000001U #define HP_APM_REGION13_R0_X_S 0 /** HP_APM_REGION13_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 13. + * Configures the write permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_W (BIT(1)) #define HP_APM_REGION13_R0_W_M (HP_APM_REGION13_R0_W_V << HP_APM_REGION13_R0_W_S) #define HP_APM_REGION13_R0_W_V 0x00000001U #define HP_APM_REGION13_R0_W_S 1 /** HP_APM_REGION13_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 13. + * Configures the read permission in region 13 in REE0 mode. */ #define HP_APM_REGION13_R0_R (BIT(2)) #define HP_APM_REGION13_R0_R_M (HP_APM_REGION13_R0_R_V << HP_APM_REGION13_R0_R_S) #define HP_APM_REGION13_R0_R_V 0x00000001U #define HP_APM_REGION13_R0_R_S 2 /** HP_APM_REGION13_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 13. + * Configures the execution permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_X (BIT(4)) #define HP_APM_REGION13_R1_X_M (HP_APM_REGION13_R1_X_V << HP_APM_REGION13_R1_X_S) #define HP_APM_REGION13_R1_X_V 0x00000001U #define HP_APM_REGION13_R1_X_S 4 /** HP_APM_REGION13_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 13. + * Configures the write permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_W (BIT(5)) #define HP_APM_REGION13_R1_W_M (HP_APM_REGION13_R1_W_V << HP_APM_REGION13_R1_W_S) #define HP_APM_REGION13_R1_W_V 0x00000001U #define HP_APM_REGION13_R1_W_S 5 /** HP_APM_REGION13_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 13. + * Configures the read permission in region 13 in REE1 mode. */ #define HP_APM_REGION13_R1_R (BIT(6)) #define HP_APM_REGION13_R1_R_M (HP_APM_REGION13_R1_R_V << HP_APM_REGION13_R1_R_S) #define HP_APM_REGION13_R1_R_V 0x00000001U #define HP_APM_REGION13_R1_R_S 6 /** HP_APM_REGION13_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 13. + * Configures the execution permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_X (BIT(8)) #define HP_APM_REGION13_R2_X_M (HP_APM_REGION13_R2_X_V << HP_APM_REGION13_R2_X_S) #define HP_APM_REGION13_R2_X_V 0x00000001U #define HP_APM_REGION13_R2_X_S 8 /** HP_APM_REGION13_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 13. + * Configures the write permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_W (BIT(9)) #define HP_APM_REGION13_R2_W_M (HP_APM_REGION13_R2_W_V << HP_APM_REGION13_R2_W_S) #define HP_APM_REGION13_R2_W_V 0x00000001U #define HP_APM_REGION13_R2_W_S 9 /** HP_APM_REGION13_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 13. + * Configures the read permission in region 13 in REE2 mode. */ #define HP_APM_REGION13_R2_R (BIT(10)) #define HP_APM_REGION13_R2_R_M (HP_APM_REGION13_R2_R_V << HP_APM_REGION13_R2_R_S) #define HP_APM_REGION13_R2_R_V 0x00000001U #define HP_APM_REGION13_R2_R_S 10 /** HP_APM_REGION13_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 13 configuration registers + * (HP_APM_REGION13_ADDR_START_REG, HP_APM_REGION13_ADDR_END_REG and + * HP_APM_REGION13_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION13_LOCK (BIT(11)) #define HP_APM_REGION13_LOCK_M (HP_APM_REGION13_LOCK_V << HP_APM_REGION13_LOCK_S) @@ -1416,7 +1472,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xac) /** HP_APM_REGION14_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 14. + * Configures the start address of region 14. */ #define HP_APM_REGION14_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_START_M (HP_APM_REGION14_ADDR_START_V << HP_APM_REGION14_ADDR_START_S) @@ -1428,7 +1484,7 @@ extern "C" { */ #define HP_APM_REGION14_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xb0) /** HP_APM_REGION14_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 14. + * Configures the end address of region 14. */ #define HP_APM_REGION14_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION14_ADDR_END_M (HP_APM_REGION14_ADDR_END_V << HP_APM_REGION14_ADDR_END_S) @@ -1436,74 +1492,78 @@ extern "C" { #define HP_APM_REGION14_ADDR_END_S 0 /** HP_APM_REGION14_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION14_ATTR_REG (DR_REG_HP_APM_BASE + 0xb4) /** HP_APM_REGION14_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 14. + * Configures the execution permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_X (BIT(0)) #define HP_APM_REGION14_R0_X_M (HP_APM_REGION14_R0_X_V << HP_APM_REGION14_R0_X_S) #define HP_APM_REGION14_R0_X_V 0x00000001U #define HP_APM_REGION14_R0_X_S 0 /** HP_APM_REGION14_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 14. + * Configures the write permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_W (BIT(1)) #define HP_APM_REGION14_R0_W_M (HP_APM_REGION14_R0_W_V << HP_APM_REGION14_R0_W_S) #define HP_APM_REGION14_R0_W_V 0x00000001U #define HP_APM_REGION14_R0_W_S 1 /** HP_APM_REGION14_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 14. + * Configures the read permission in region 14 in REE0 mode. */ #define HP_APM_REGION14_R0_R (BIT(2)) #define HP_APM_REGION14_R0_R_M (HP_APM_REGION14_R0_R_V << HP_APM_REGION14_R0_R_S) #define HP_APM_REGION14_R0_R_V 0x00000001U #define HP_APM_REGION14_R0_R_S 2 /** HP_APM_REGION14_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 14. + * Configures the execution permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_X (BIT(4)) #define HP_APM_REGION14_R1_X_M (HP_APM_REGION14_R1_X_V << HP_APM_REGION14_R1_X_S) #define HP_APM_REGION14_R1_X_V 0x00000001U #define HP_APM_REGION14_R1_X_S 4 /** HP_APM_REGION14_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 14. + * Configures the write permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_W (BIT(5)) #define HP_APM_REGION14_R1_W_M (HP_APM_REGION14_R1_W_V << HP_APM_REGION14_R1_W_S) #define HP_APM_REGION14_R1_W_V 0x00000001U #define HP_APM_REGION14_R1_W_S 5 /** HP_APM_REGION14_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 14. + * Configures the read permission in region 14 in REE1 mode. */ #define HP_APM_REGION14_R1_R (BIT(6)) #define HP_APM_REGION14_R1_R_M (HP_APM_REGION14_R1_R_V << HP_APM_REGION14_R1_R_S) #define HP_APM_REGION14_R1_R_V 0x00000001U #define HP_APM_REGION14_R1_R_S 6 /** HP_APM_REGION14_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 14. + * Configures the execution permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_X (BIT(8)) #define HP_APM_REGION14_R2_X_M (HP_APM_REGION14_R2_X_V << HP_APM_REGION14_R2_X_S) #define HP_APM_REGION14_R2_X_V 0x00000001U #define HP_APM_REGION14_R2_X_S 8 /** HP_APM_REGION14_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 14. + * Configures the write permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_W (BIT(9)) #define HP_APM_REGION14_R2_W_M (HP_APM_REGION14_R2_W_V << HP_APM_REGION14_R2_W_S) #define HP_APM_REGION14_R2_W_V 0x00000001U #define HP_APM_REGION14_R2_W_S 9 /** HP_APM_REGION14_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 14. + * Configures the read permission in region 14 in REE2 mode. */ #define HP_APM_REGION14_R2_R (BIT(10)) #define HP_APM_REGION14_R2_R_M (HP_APM_REGION14_R2_R_V << HP_APM_REGION14_R2_R_S) #define HP_APM_REGION14_R2_R_V 0x00000001U #define HP_APM_REGION14_R2_R_S 10 /** HP_APM_REGION14_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 14 configuration registers + * (HP_APM_REGION14_ADDR_START_REG, HP_APM_REGION14_ADDR_END_REG and + * HP_APM_REGION14_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION14_LOCK (BIT(11)) #define HP_APM_REGION14_LOCK_M (HP_APM_REGION14_LOCK_V << HP_APM_REGION14_LOCK_S) @@ -1515,7 +1575,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_START_REG (DR_REG_HP_APM_BASE + 0xb8) /** HP_APM_REGION15_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 15. + * Configures the start address of region 15. */ #define HP_APM_REGION15_ADDR_START 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_START_M (HP_APM_REGION15_ADDR_START_V << HP_APM_REGION15_ADDR_START_S) @@ -1527,7 +1587,7 @@ extern "C" { */ #define HP_APM_REGION15_ADDR_END_REG (DR_REG_HP_APM_BASE + 0xbc) /** HP_APM_REGION15_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 15. + * Configures the end address of region 15. */ #define HP_APM_REGION15_ADDR_END 0xFFFFFFFFU #define HP_APM_REGION15_ADDR_END_M (HP_APM_REGION15_ADDR_END_V << HP_APM_REGION15_ADDR_END_S) @@ -1535,74 +1595,78 @@ extern "C" { #define HP_APM_REGION15_ADDR_END_S 0 /** HP_APM_REGION15_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define HP_APM_REGION15_ATTR_REG (DR_REG_HP_APM_BASE + 0xc0) /** HP_APM_REGION15_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 15. + * Configures the execution permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_X (BIT(0)) #define HP_APM_REGION15_R0_X_M (HP_APM_REGION15_R0_X_V << HP_APM_REGION15_R0_X_S) #define HP_APM_REGION15_R0_X_V 0x00000001U #define HP_APM_REGION15_R0_X_S 0 /** HP_APM_REGION15_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 15. + * Configures the write permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_W (BIT(1)) #define HP_APM_REGION15_R0_W_M (HP_APM_REGION15_R0_W_V << HP_APM_REGION15_R0_W_S) #define HP_APM_REGION15_R0_W_V 0x00000001U #define HP_APM_REGION15_R0_W_S 1 /** HP_APM_REGION15_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 15. + * Configures the read permission in region 15 in REE0 mode. */ #define HP_APM_REGION15_R0_R (BIT(2)) #define HP_APM_REGION15_R0_R_M (HP_APM_REGION15_R0_R_V << HP_APM_REGION15_R0_R_S) #define HP_APM_REGION15_R0_R_V 0x00000001U #define HP_APM_REGION15_R0_R_S 2 /** HP_APM_REGION15_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 15. + * Configures the execution permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_X (BIT(4)) #define HP_APM_REGION15_R1_X_M (HP_APM_REGION15_R1_X_V << HP_APM_REGION15_R1_X_S) #define HP_APM_REGION15_R1_X_V 0x00000001U #define HP_APM_REGION15_R1_X_S 4 /** HP_APM_REGION15_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 15. + * Configures the write permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_W (BIT(5)) #define HP_APM_REGION15_R1_W_M (HP_APM_REGION15_R1_W_V << HP_APM_REGION15_R1_W_S) #define HP_APM_REGION15_R1_W_V 0x00000001U #define HP_APM_REGION15_R1_W_S 5 /** HP_APM_REGION15_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 15. + * Configures the read permission in region 15 in REE1 mode. */ #define HP_APM_REGION15_R1_R (BIT(6)) #define HP_APM_REGION15_R1_R_M (HP_APM_REGION15_R1_R_V << HP_APM_REGION15_R1_R_S) #define HP_APM_REGION15_R1_R_V 0x00000001U #define HP_APM_REGION15_R1_R_S 6 /** HP_APM_REGION15_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 15. + * Configures the execution permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_X (BIT(8)) #define HP_APM_REGION15_R2_X_M (HP_APM_REGION15_R2_X_V << HP_APM_REGION15_R2_X_S) #define HP_APM_REGION15_R2_X_V 0x00000001U #define HP_APM_REGION15_R2_X_S 8 /** HP_APM_REGION15_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 15. + * Configures the write permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_W (BIT(9)) #define HP_APM_REGION15_R2_W_M (HP_APM_REGION15_R2_W_V << HP_APM_REGION15_R2_W_S) #define HP_APM_REGION15_R2_W_V 0x00000001U #define HP_APM_REGION15_R2_W_S 9 /** HP_APM_REGION15_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 15. + * Configures the read permission in region 15 in REE2 mode. */ #define HP_APM_REGION15_R2_R (BIT(10)) #define HP_APM_REGION15_R2_R_M (HP_APM_REGION15_R2_R_V << HP_APM_REGION15_R2_R_S) #define HP_APM_REGION15_R2_R_V 0x00000001U #define HP_APM_REGION15_R2_R_S 10 /** HP_APM_REGION15_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 15 configuration registers + * (HP_APM_REGION15_ADDR_START_REG, HP_APM_REGION15_ADDR_END_REG and + * HP_APM_REGION15_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define HP_APM_REGION15_LOCK (BIT(11)) #define HP_APM_REGION15_LOCK_M (HP_APM_REGION15_LOCK_V << HP_APM_REGION15_LOCK_S) @@ -1610,39 +1674,39 @@ extern "C" { #define HP_APM_REGION15_LOCK_S 11 /** HP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define HP_APM_FUNC_CTRL_REG (DR_REG_HP_APM_BASE + 0xc4) /** HP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ #define HP_APM_M0_FUNC_EN (BIT(0)) #define HP_APM_M0_FUNC_EN_M (HP_APM_M0_FUNC_EN_V << HP_APM_M0_FUNC_EN_S) #define HP_APM_M0_FUNC_EN_V 0x00000001U #define HP_APM_M0_FUNC_EN_S 0 /** HP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ #define HP_APM_M1_FUNC_EN (BIT(1)) #define HP_APM_M1_FUNC_EN_M (HP_APM_M1_FUNC_EN_V << HP_APM_M1_FUNC_EN_S) #define HP_APM_M1_FUNC_EN_V 0x00000001U #define HP_APM_M1_FUNC_EN_S 1 /** HP_APM_M2_FUNC_EN : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ #define HP_APM_M2_FUNC_EN (BIT(2)) #define HP_APM_M2_FUNC_EN_M (HP_APM_M2_FUNC_EN_V << HP_APM_M2_FUNC_EN_S) #define HP_APM_M2_FUNC_EN_V 0x00000001U #define HP_APM_M2_FUNC_EN_S 2 /** HP_APM_M3_FUNC_EN : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ #define HP_APM_M3_FUNC_EN (BIT(3)) #define HP_APM_M3_FUNC_EN_M (HP_APM_M3_FUNC_EN_V << HP_APM_M3_FUNC_EN_S) #define HP_APM_M3_FUNC_EN_V 0x00000001U #define HP_APM_M3_FUNC_EN_S 3 /** HP_APM_M4_FUNC_EN : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ #define HP_APM_M4_FUNC_EN (BIT(4)) #define HP_APM_M4_FUNC_EN_M (HP_APM_M4_FUNC_EN_V << HP_APM_M4_FUNC_EN_S) @@ -1650,13 +1714,13 @@ extern "C" { #define HP_APM_M4_FUNC_EN_S 4 /** HP_APM_M0_STATUS_REG register - * M0 status register + * HP_APM_CTRL M0 status register */ #define HP_APM_M0_STATUS_REG (DR_REG_HP_APM_BASE + 0xc8) /** HP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M0_EXCEPTION_STATUS 0x00000003U #define HP_APM_M0_EXCEPTION_STATUS_M (HP_APM_M0_EXCEPTION_STATUS_V << HP_APM_M0_EXCEPTION_STATUS_S) @@ -1664,7 +1728,7 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_S 0 /** HP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ #define HP_APM_M0_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xcc) /** HP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1676,25 +1740,25 @@ extern "C" { #define HP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xd0) /** HP_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M0_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_M (HP_APM_M0_EXCEPTION_REGION_V << HP_APM_M0_EXCEPTION_REGION_S) #define HP_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M0_EXCEPTION_REGION_S 0 /** HP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M0_EXCEPTION_MODE 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_M (HP_APM_M0_EXCEPTION_MODE_V << HP_APM_M0_EXCEPTION_MODE_S) #define HP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M0_EXCEPTION_MODE_S 16 /** HP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ID 0x0000001FU #define HP_APM_M0_EXCEPTION_ID_M (HP_APM_M0_EXCEPTION_ID_V << HP_APM_M0_EXCEPTION_ID_S) @@ -1702,11 +1766,11 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ID_S 18 /** HP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ #define HP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xd4) /** HP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M0_EXCEPTION_ADDR_M (HP_APM_M0_EXCEPTION_ADDR_V << HP_APM_M0_EXCEPTION_ADDR_S) @@ -1714,13 +1778,13 @@ extern "C" { #define HP_APM_M0_EXCEPTION_ADDR_S 0 /** HP_APM_M1_STATUS_REG register - * M1 status register + * HP_APM_CTRL M1 status register */ #define HP_APM_M1_STATUS_REG (DR_REG_HP_APM_BASE + 0xd8) /** HP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M1_EXCEPTION_STATUS 0x00000003U #define HP_APM_M1_EXCEPTION_STATUS_M (HP_APM_M1_EXCEPTION_STATUS_V << HP_APM_M1_EXCEPTION_STATUS_S) @@ -1728,7 +1792,7 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_S 0 /** HP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ #define HP_APM_M1_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xdc) /** HP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1740,25 +1804,25 @@ extern "C" { #define HP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xe0) /** HP_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M1_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_M (HP_APM_M1_EXCEPTION_REGION_V << HP_APM_M1_EXCEPTION_REGION_S) #define HP_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M1_EXCEPTION_REGION_S 0 /** HP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M1_EXCEPTION_MODE 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_M (HP_APM_M1_EXCEPTION_MODE_V << HP_APM_M1_EXCEPTION_MODE_S) #define HP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M1_EXCEPTION_MODE_S 16 /** HP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ID 0x0000001FU #define HP_APM_M1_EXCEPTION_ID_M (HP_APM_M1_EXCEPTION_ID_V << HP_APM_M1_EXCEPTION_ID_S) @@ -1766,11 +1830,11 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ID_S 18 /** HP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ #define HP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xe4) /** HP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M1_EXCEPTION_ADDR_M (HP_APM_M1_EXCEPTION_ADDR_V << HP_APM_M1_EXCEPTION_ADDR_S) @@ -1778,13 +1842,13 @@ extern "C" { #define HP_APM_M1_EXCEPTION_ADDR_S 0 /** HP_APM_M2_STATUS_REG register - * M2 status register + * HP_APM_CTRL M2 status register */ #define HP_APM_M2_STATUS_REG (DR_REG_HP_APM_BASE + 0xe8) /** HP_APM_M2_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M2_EXCEPTION_STATUS 0x00000003U #define HP_APM_M2_EXCEPTION_STATUS_M (HP_APM_M2_EXCEPTION_STATUS_V << HP_APM_M2_EXCEPTION_STATUS_S) @@ -1792,7 +1856,7 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_S 0 /** HP_APM_M2_STATUS_CLR_REG register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ #define HP_APM_M2_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xec) /** HP_APM_M2_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1804,25 +1868,25 @@ extern "C" { #define HP_APM_M2_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M2_EXCEPTION_INFO0_REG register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0xf0) /** HP_APM_M2_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M2_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_M (HP_APM_M2_EXCEPTION_REGION_V << HP_APM_M2_EXCEPTION_REGION_S) #define HP_APM_M2_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M2_EXCEPTION_REGION_S 0 /** HP_APM_M2_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M2_EXCEPTION_MODE 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_M (HP_APM_M2_EXCEPTION_MODE_V << HP_APM_M2_EXCEPTION_MODE_S) #define HP_APM_M2_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M2_EXCEPTION_MODE_S 16 /** HP_APM_M2_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ID 0x0000001FU #define HP_APM_M2_EXCEPTION_ID_M (HP_APM_M2_EXCEPTION_ID_V << HP_APM_M2_EXCEPTION_ID_S) @@ -1830,11 +1894,11 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ID_S 18 /** HP_APM_M2_EXCEPTION_INFO1_REG register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ #define HP_APM_M2_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0xf4) /** HP_APM_M2_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M2_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M2_EXCEPTION_ADDR_M (HP_APM_M2_EXCEPTION_ADDR_V << HP_APM_M2_EXCEPTION_ADDR_S) @@ -1842,13 +1906,13 @@ extern "C" { #define HP_APM_M2_EXCEPTION_ADDR_S 0 /** HP_APM_M3_STATUS_REG register - * M3 status register + * HP_APM_CTRL M3 status register */ #define HP_APM_M3_STATUS_REG (DR_REG_HP_APM_BASE + 0xf8) /** HP_APM_M3_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M3_EXCEPTION_STATUS 0x00000003U #define HP_APM_M3_EXCEPTION_STATUS_M (HP_APM_M3_EXCEPTION_STATUS_V << HP_APM_M3_EXCEPTION_STATUS_S) @@ -1856,7 +1920,7 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_S 0 /** HP_APM_M3_STATUS_CLR_REG register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ #define HP_APM_M3_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0xfc) /** HP_APM_M3_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1868,25 +1932,25 @@ extern "C" { #define HP_APM_M3_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M3_EXCEPTION_INFO0_REG register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x100) /** HP_APM_M3_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M3_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_M (HP_APM_M3_EXCEPTION_REGION_V << HP_APM_M3_EXCEPTION_REGION_S) #define HP_APM_M3_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M3_EXCEPTION_REGION_S 0 /** HP_APM_M3_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M3_EXCEPTION_MODE 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_M (HP_APM_M3_EXCEPTION_MODE_V << HP_APM_M3_EXCEPTION_MODE_S) #define HP_APM_M3_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M3_EXCEPTION_MODE_S 16 /** HP_APM_M3_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ID 0x0000001FU #define HP_APM_M3_EXCEPTION_ID_M (HP_APM_M3_EXCEPTION_ID_V << HP_APM_M3_EXCEPTION_ID_S) @@ -1894,11 +1958,11 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ID_S 18 /** HP_APM_M3_EXCEPTION_INFO1_REG register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ #define HP_APM_M3_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x104) /** HP_APM_M3_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M3_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M3_EXCEPTION_ADDR_M (HP_APM_M3_EXCEPTION_ADDR_V << HP_APM_M3_EXCEPTION_ADDR_S) @@ -1906,13 +1970,13 @@ extern "C" { #define HP_APM_M3_EXCEPTION_ADDR_S 0 /** HP_APM_M4_STATUS_REG register - * M4 status register + * HP_APM_CTRL M4 status register */ #define HP_APM_M4_STATUS_REG (DR_REG_HP_APM_BASE + 0x108) /** HP_APM_M4_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define HP_APM_M4_EXCEPTION_STATUS 0x00000003U #define HP_APM_M4_EXCEPTION_STATUS_M (HP_APM_M4_EXCEPTION_STATUS_V << HP_APM_M4_EXCEPTION_STATUS_S) @@ -1920,7 +1984,7 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_S 0 /** HP_APM_M4_STATUS_CLR_REG register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ #define HP_APM_M4_STATUS_CLR_REG (DR_REG_HP_APM_BASE + 0x10c) /** HP_APM_M4_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -1932,25 +1996,25 @@ extern "C" { #define HP_APM_M4_EXCEPTION_STATUS_CLR_S 0 /** HP_APM_M4_EXCEPTION_INFO0_REG register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO0_REG (DR_REG_HP_APM_BASE + 0x110) /** HP_APM_M4_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define HP_APM_M4_EXCEPTION_REGION 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_M (HP_APM_M4_EXCEPTION_REGION_V << HP_APM_M4_EXCEPTION_REGION_S) #define HP_APM_M4_EXCEPTION_REGION_V 0x0000FFFFU #define HP_APM_M4_EXCEPTION_REGION_S 0 /** HP_APM_M4_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define HP_APM_M4_EXCEPTION_MODE 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_M (HP_APM_M4_EXCEPTION_MODE_V << HP_APM_M4_EXCEPTION_MODE_S) #define HP_APM_M4_EXCEPTION_MODE_V 0x00000003U #define HP_APM_M4_EXCEPTION_MODE_S 16 /** HP_APM_M4_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ID 0x0000001FU #define HP_APM_M4_EXCEPTION_ID_M (HP_APM_M4_EXCEPTION_ID_V << HP_APM_M4_EXCEPTION_ID_S) @@ -1958,11 +2022,11 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ID_S 18 /** HP_APM_M4_EXCEPTION_INFO1_REG register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ #define HP_APM_M4_EXCEPTION_INFO1_REG (DR_REG_HP_APM_BASE + 0x114) /** HP_APM_M4_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define HP_APM_M4_EXCEPTION_ADDR 0xFFFFFFFFU #define HP_APM_M4_EXCEPTION_ADDR_M (HP_APM_M4_EXCEPTION_ADDR_V << HP_APM_M4_EXCEPTION_ADDR_S) @@ -1970,49 +2034,49 @@ extern "C" { #define HP_APM_M4_EXCEPTION_ADDR_S 0 /** HP_APM_INT_EN_REG register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ #define HP_APM_INT_EN_REG (DR_REG_HP_APM_BASE + 0x118) /** HP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M0_APM_INT_EN (BIT(0)) #define HP_APM_M0_APM_INT_EN_M (HP_APM_M0_APM_INT_EN_V << HP_APM_M0_APM_INT_EN_S) #define HP_APM_M0_APM_INT_EN_V 0x00000001U #define HP_APM_M0_APM_INT_EN_S 0 /** HP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M1_APM_INT_EN (BIT(1)) #define HP_APM_M1_APM_INT_EN_M (HP_APM_M1_APM_INT_EN_V << HP_APM_M1_APM_INT_EN_S) #define HP_APM_M1_APM_INT_EN_V 0x00000001U #define HP_APM_M1_APM_INT_EN_S 1 /** HP_APM_M2_APM_INT_EN : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M2_APM_INT_EN (BIT(2)) #define HP_APM_M2_APM_INT_EN_M (HP_APM_M2_APM_INT_EN_V << HP_APM_M2_APM_INT_EN_S) #define HP_APM_M2_APM_INT_EN_V 0x00000001U #define HP_APM_M2_APM_INT_EN_S 2 /** HP_APM_M3_APM_INT_EN : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M3_APM_INT_EN (BIT(3)) #define HP_APM_M3_APM_INT_EN_M (HP_APM_M3_APM_INT_EN_V << HP_APM_M3_APM_INT_EN_S) #define HP_APM_M3_APM_INT_EN_V 0x00000001U #define HP_APM_M3_APM_INT_EN_S 3 /** HP_APM_M4_APM_INT_EN : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ #define HP_APM_M4_APM_INT_EN (BIT(4)) #define HP_APM_M4_APM_INT_EN_M (HP_APM_M4_APM_INT_EN_V << HP_APM_M4_APM_INT_EN_S) @@ -2024,9 +2088,9 @@ extern "C" { */ #define HP_APM_CLOCK_GATE_REG (DR_REG_HP_APM_BASE + 0x7f8) /** HP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define HP_APM_CLK_EN (BIT(0)) #define HP_APM_CLK_EN_M (HP_APM_CLK_EN_V << HP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/hp_apm_struct.h b/components/soc/esp32c5/register/soc/hp_apm_struct.h index 87648ad8c3..0f3335eb0c 100644 --- a/components/soc/esp32c5/register/soc/hp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/hp_apm_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [15:0]; default: 1; - * Configure bit $n (0-15) to enable region $n.\\ - * 0: disable \\ - * 1: enable \\ + * Configure bit $n (0-15) to enable region $n (0-15). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:16; uint32_t reserved_16:16; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } hp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } hp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (HP_APM_REGIONn_ADDR_START_REG, HP_APM_REGIONn_ADDR_END_REG and + * HP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,31 +109,29 @@ typedef union { uint32_t val; } hp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for HP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for HP_APM_CTRL M1. */ uint32_t m1_func_en:1; /** m2_func_en : R/W; bitpos: [2]; default: 1; - * PMS M2 function enable + * Configures to enable permission management for HP_APM_CTRL M2. */ uint32_t m2_func_en:1; /** m3_func_en : R/W; bitpos: [3]; default: 1; - * PMS M3 function enable + * Configures to enable permission management for HP_APM_CTRL M3. */ uint32_t m3_func_en:1; /** m4_func_en : R/W; bitpos: [4]; default: 1; - * PMS M4 function enable + * Configures to enable permission management for HP_APM_CTRL M4. */ uint32_t m4_func_en:1; uint32_t reserved_5:27; @@ -142,16 +140,16 @@ typedef union { } hp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * HP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -159,10 +157,8 @@ typedef union { uint32_t val; } hp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * HP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -175,23 +171,21 @@ typedef union { uint32_t val; } hp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:16; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -199,32 +193,28 @@ typedef union { uint32_t val; } hp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * HP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } hp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * HP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -232,10 +222,8 @@ typedef union { uint32_t val; } hp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * HP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -248,23 +236,21 @@ typedef union { uint32_t val; } hp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:16; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -272,32 +258,28 @@ typedef union { uint32_t val; } hp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * HP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; uint32_t val; } hp_apm_m1_exception_info1_reg_t; - -/** Group: M2 status register */ /** Type of m2_status register - * M2 status register + * HP_APM_CTRL M2 status register */ typedef union { struct { /** m2_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m2_exception_status:2; uint32_t reserved_2:30; @@ -305,10 +287,8 @@ typedef union { uint32_t val; } hp_apm_m2_status_reg_t; - -/** Group: M2 status clear register */ /** Type of m2_status_clr register - * M2 status clear register + * HP_APM_CTRL M2 status clear register */ typedef union { struct { @@ -321,23 +301,21 @@ typedef union { uint32_t val; } hp_apm_m2_status_clr_reg_t; - -/** Group: M2 exception_info0 register */ /** Type of m2_exception_info0 register - * M2 exception_info0 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m2_exception_region:16; /** m2_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m2_exception_mode:2; /** m2_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m2_exception_id:5; uint32_t reserved_23:9; @@ -345,32 +323,28 @@ typedef union { uint32_t val; } hp_apm_m2_exception_info0_reg_t; - -/** Group: M2 exception_info1 register */ /** Type of m2_exception_info1 register - * M2 exception_info1 register + * HP_APM_CTRL M2 exception information register */ typedef union { struct { /** m2_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m2_exception_addr:32; }; uint32_t val; } hp_apm_m2_exception_info1_reg_t; - -/** Group: M3 status register */ /** Type of m3_status register - * M3 status register + * HP_APM_CTRL M3 status register */ typedef union { struct { /** m3_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m3_exception_status:2; uint32_t reserved_2:30; @@ -378,10 +352,8 @@ typedef union { uint32_t val; } hp_apm_m3_status_reg_t; - -/** Group: M3 status clear register */ /** Type of m3_status_clr register - * M3 status clear register + * HP_APM_CTRL M3 status clear register */ typedef union { struct { @@ -394,23 +366,21 @@ typedef union { uint32_t val; } hp_apm_m3_status_clr_reg_t; - -/** Group: M3 exception_info0 register */ /** Type of m3_exception_info0 register - * M3 exception_info0 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m3_exception_region:16; /** m3_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m3_exception_mode:2; /** m3_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m3_exception_id:5; uint32_t reserved_23:9; @@ -418,32 +388,28 @@ typedef union { uint32_t val; } hp_apm_m3_exception_info0_reg_t; - -/** Group: M3 exception_info1 register */ /** Type of m3_exception_info1 register - * M3 exception_info1 register + * HP_APM_CTRL M3 exception information register */ typedef union { struct { /** m3_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m3_exception_addr:32; }; uint32_t val; } hp_apm_m3_exception_info1_reg_t; - -/** Group: M4 status register */ /** Type of m4_status register - * M4 status register + * HP_APM_CTRL M4 status register */ typedef union { struct { /** m4_exception_status : RO; bitpos: [1:0]; default: 0; - * Represents exception status.\\ - * bit0: 1 represents authority_exception \\ - * bit1: 1 represents space_exception \\ + * Represents exception status. + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m4_exception_status:2; uint32_t reserved_2:30; @@ -451,10 +417,8 @@ typedef union { uint32_t val; } hp_apm_m4_status_reg_t; - -/** Group: M4 status clear register */ /** Type of m4_status_clr register - * M4 status clear register + * HP_APM_CTRL M4 status clear register */ typedef union { struct { @@ -467,23 +431,21 @@ typedef union { uint32_t val; } hp_apm_m4_status_clr_reg_t; - -/** Group: M4 exception_info0 register */ /** Type of m4_exception_info0 register - * M4 exception_info0 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_region : RO; bitpos: [15:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m4_exception_region:16; /** m4_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m4_exception_mode:2; /** m4_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m4_exception_id:5; uint32_t reserved_23:9; @@ -491,15 +453,13 @@ typedef union { uint32_t val; } hp_apm_m4_exception_info0_reg_t; - -/** Group: M4 exception_info1 register */ /** Type of m4_exception_info1 register - * M4 exception_info1 register + * HP_APM_CTRL M4 exception information register */ typedef union { struct { /** m4_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m4_exception_addr:32; }; @@ -507,40 +467,40 @@ typedef union { } hp_apm_m4_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * HP_APM_CTRL M0/1/2/3/4 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; /** m2_apm_int_en : R/W; bitpos: [2]; default: 0; - * Configures to enable APM M2 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M2 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m2_apm_int_en:1; /** m3_apm_int_en : R/W; bitpos: [3]; default: 0; - * Configures to enable APM M3 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M3 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m3_apm_int_en:1; /** m4_apm_int_en : R/W; bitpos: [4]; default: 0; - * Configures to enable APM M4 interrupt.\\ - * 0: disable \\ - * 1: enable \\ + * Configures to enable HP_APM_CTRL M4 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m4_apm_int_en:1; uint32_t reserved_5:27; @@ -549,16 +509,16 @@ typedef union { } hp_apm_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether to keep the clock always on.\\ - * 0: enable automatic clock gating \\ - * 1: keep the clock always on \\ + * Configures whether to keep the clock always on. + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -567,7 +527,7 @@ typedef union { } hp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/keymng_reg.h b/components/soc/esp32c5/register/soc/keymng_reg.h index 66ab390373..e11f28548f 100644 --- a/components/soc/esp32c5/register/soc/keymng_reg.h +++ b/components/soc/esp32c5/register/soc/keymng_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -148,20 +148,45 @@ extern "C" { #define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU #define KEYMNG_USE_EFUSE_KEY_S 0 -/* KEYMNG_USE_EFUSE_KEY_ECDSA : R/W ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Set this bit to choose efuse key instead of key manager deployed key for ecdsa.*/ +/** KEYMNG_USE_EFUSE_KEY_ECDSA : R/W; bitpos:[0]; default: 0; + * Set this bit to choose efuse key instead of key manager deployed key for ecdsa. + */ #define KEYMNG_USE_EFUSE_KEY_ECDSA (BIT(0)) -#define KEYMNG_USE_EFUSE_KEY_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_ECDSA_S)) -#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_ECDSA_M (KEYMNG_USE_EFUSE_KEY_ECDSA_V << KEYMNG_USE_EFUSE_KEY_ECDSA_S) +#define KEYMNG_USE_EFUSE_KEY_ECDSA_V 0x00000001U #define KEYMNG_USE_EFUSE_KEY_ECDSA_S 0 -/* KEYMNG_USE_EFUSE_KEY_FLASH : R/W ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Set this bit to choose efuse key instead of key manager deployed key for flash.*/ +/** KEYMNG_USE_EFUSE_KEY_FLASH : R/W; bitpos:[1]; default: 0; + * Set this bit to choose efuse key instead of key manager deployed key for flash. + */ #define KEYMNG_USE_EFUSE_KEY_FLASH (BIT(1)) -#define KEYMNG_USE_EFUSE_KEY_FLASH_M ((KEYMNG_USE_EFUSE_KEY_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_FLASH_S)) -#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_FLASH_M (KEYMNG_USE_EFUSE_KEY_FLASH_V << KEYMNG_USE_EFUSE_KEY_FLASH_S) +#define KEYMNG_USE_EFUSE_KEY_FLASH_V 0x00000001U #define KEYMNG_USE_EFUSE_KEY_FLASH_S 1 +/** KEYMNG_USE_EFUSE_KEY_HMAC : R/W; bitpos:[0]; default: 0; + * Set this bit to choose efuse key instead of key manager deployed key for hmac. + */ +#define KEYMNG_USE_EFUSE_KEY_HMAC (BIT(2)) +#define KEYMNG_USE_EFUSE_KEY_HMAC_M (KEYMNG_USE_EFUSE_KEY_HMAC_V << KEYMNG_USE_EFUSE_KEY_HMAC_S) +#define KEYMNG_USE_EFUSE_KEY_HMAC_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_HMAC_S 2 + +/** KEYMNG_USE_EFUSE_KEY_DS : R/W; bitpos:[1]; default: 0; + * Set this bit to choose efuse key instead of key manager deployed key for ds. + */ +#define KEYMNG_USE_EFUSE_KEY_DS (BIT(3)) +#define KEYMNG_USE_EFUSE_KEY_DS_M (KEYMNG_USE_EFUSE_KEY_DS_V << KEYMNG_USE_EFUSE_KEY_DS_S) +#define KEYMNG_USE_EFUSE_KEY_DS_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_DS_S 3 + +/** KEYMNG_USE_EFUSE_KEY_PSRAM : R/W; bitpos:[1]; default: 0; + * Set this bit to choose efuse key instead of key manager deployed key for psram. + */ +#define KEYMNG_USE_EFUSE_KEY_PSRAM (BIT(4)) +#define KEYMNG_USE_EFUSE_KEY_PSRAM_M (KEYMNG_USE_EFUSE_KEY_PSRAM_V << KEYMNG_USE_EFUSE_KEY_PSRAM_S) +#define KEYMNG_USE_EFUSE_KEY_PSRAM_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_PSRAM_S 4 /** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15; * The core clock cycle number to sample one rng input data. Please set it bigger than @@ -208,21 +233,41 @@ extern "C" { #define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU #define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 -/* KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0] ;default: 1'd0 ; */ -/*description: Write 1 to lock reg_use_efuse_key for esdsa*/ - +/** KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA : R/W1 ;bitpos:[0]; default: 0; + * Write 1 to lock reg_use_efuse_key for esdsa + */ #define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA (BIT(0)) -#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M ((KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S)) -#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_M (KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V << KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_V 0x00000001U #define KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA_S 0 - -/* KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1] ;default: 1'd0 ; */ -/*description: Write 1 to lock reg_use_efuse_key for FLASH*/ - +/** KEYMNG_USE_EFUSE_KEY_LOCK_FLASH : R/W1 ;bitpos:[1]; default: 0; + * Write 1 to lock reg_use_efuse_key for FLASH + */ #define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH (BIT(1)) -#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M ((KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V)<<(KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S)) -#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x1 +#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_M (KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V << KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_V 0x00000001U #define KEYMNG_USE_EFUSE_KEY_LOCK_FLASH_S 1 +/** KEYMNG_USE_EFUSE_KEY_LOCK_HMAC : R/W1 ;bitpos:[0]; default: 0; + * Write 1 to lock reg_use_efuse_key for hmac + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC (BIT(2)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_M (KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V << KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_LOCK_HMAC_S 2 +/** KEYMNG_USE_EFUSE_KEY_LOCK_DS : R/W1 ;bitpos:[1]; default: 0; + * Write 1 to lock reg_use_efuse_key for ds + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK_DS (BIT(3)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_M (KEYMNG_USE_EFUSE_KEY_LOCK_DS_V << KEYMNG_USE_EFUSE_KEY_LOCK_DS_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_LOCK_DS_S 3 +/** KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM : R/W1 ;bitpos:[1]; default: 0; + * Write 1 to lock reg_use_efuse_key for PSRAM + */ +#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM (BIT(4)) +#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_M (KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V << KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S) +#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_V 0x00000001U +#define KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM_S 4 /** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0; * Write 1 to lock reg_rnd_switch_cycle. @@ -266,9 +311,10 @@ extern "C" { #define KEYMNG_KGEN_MODE_V 0x00000007U #define KEYMNG_KGEN_MODE_S 0 /** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; - * Set this field to choose the key purpose. 1: ecdsa_key 2: flash_256_1_key. 3: - * flash_256_2_key. 4: flash_128_key. 6: hmac_key. 7: ds_key. 8: psram_256_1_key. 9: - * psram_256_2_key. 10: psram_128_key. Others: reserved. + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. */ #define KEYMNG_KEY_PURPOSE 0x0000000FU #define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) @@ -323,46 +369,62 @@ extern "C" { * Key Manager key status register */ #define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) -/** KEYMNG_KEY_ECDSA_VLD : RO; bitpos: [0]; default: 0; - * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. +/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. */ -#define KEYMNG_KEY_ECDSA_VLD (BIT(0)) -#define KEYMNG_KEY_ECDSA_VLD_M (KEYMNG_KEY_ECDSA_VLD_V << KEYMNG_KEY_ECDSA_VLD_S) -#define KEYMNG_KEY_ECDSA_VLD_V 0x00000001U -#define KEYMNG_KEY_ECDSA_VLD_S 0 -/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [1]; default: 0; +#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0)) +#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S) +#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_192_VLD_S 0 +/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1)) +#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S) +#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_256_VLD_S 1 +/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0; * The status bit for key_flash. 1: The key has been deployed correctly. 0: The * key has not been deployed yet. */ -#define KEYMNG_KEY_FLASH_VLD (BIT(1)) +#define KEYMNG_KEY_FLASH_VLD (BIT(2)) #define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S) #define KEYMNG_KEY_FLASH_VLD_V 0x00000001U -#define KEYMNG_KEY_FLASH_VLD_S 1 -/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [2]; default: 0; +#define KEYMNG_KEY_FLASH_VLD_S 2 +/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0; * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key * has not been deployed yet. */ -#define KEYMNG_KEY_HMAC_VLD (BIT(2)) +#define KEYMNG_KEY_HMAC_VLD (BIT(3)) #define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S) #define KEYMNG_KEY_HMAC_VLD_V 0x00000001U -#define KEYMNG_KEY_HMAC_VLD_S 2 -/** KEYMNG_KEY_DS_VLD : RO; bitpos: [3]; default: 0; +#define KEYMNG_KEY_HMAC_VLD_S 3 +/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0; * The status bit for key_ds. 1: The key has been deployed correctly. 0: The * key has not been deployed yet. */ -#define KEYMNG_KEY_DS_VLD (BIT(3)) +#define KEYMNG_KEY_DS_VLD (BIT(4)) #define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S) #define KEYMNG_KEY_DS_VLD_V 0x00000001U -#define KEYMNG_KEY_DS_VLD_S 3 -/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [4]; default: 0; +#define KEYMNG_KEY_DS_VLD_S 4 +/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0; * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key * has not been deployed yet. */ -#define KEYMNG_KEY_PSRAM_VLD (BIT(4)) +#define KEYMNG_KEY_PSRAM_VLD (BIT(5)) #define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S) #define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U -#define KEYMNG_KEY_PSRAM_VLD_S 4 +#define KEYMNG_KEY_PSRAM_VLD_S 5 +/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ +#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6)) +#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S) +#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U +#define KEYMNG_KEY_ECDSA_384_VLD_S 6 /** KEYMNG_HUK_VLD_REG register * Key Manager HUK status register @@ -380,7 +442,7 @@ extern "C" { * Version control register */ #define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) -/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 36774224; +/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824; * Key Manager version control register. */ #define KEYMNG_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/keymng_reg_eco2.h b/components/soc/esp32c5/register/soc/keymng_reg_eco2.h deleted file mode 100644 index a385df2586..0000000000 --- a/components/soc/esp32c5/register/soc/keymng_reg_eco2.h +++ /dev/null @@ -1,395 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** KEYMNG_CLK_REG register - * Key Manager clock gate control register - */ -#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4) -/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1; - * Write 1 to force on register clock gate. - */ -#define KEYMNG_REG_CG_FORCE_ON (BIT(0)) -#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S) -#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U -#define KEYMNG_REG_CG_FORCE_ON_S 0 -/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0; - * Write 1 to force on memory clock gate. - */ -#define KEYMNG_MEM_CG_FORCE_ON (BIT(1)) -#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S) -#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U -#define KEYMNG_MEM_CG_FORCE_ON_S 1 - -/** KEYMNG_INT_RAW_REG register - * Key Manager interrupt raw register, valid in level. - */ -#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8) -/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the km_prep_done_int interrupt - */ -#define KEYMNG_PREP_DONE_INT_RAW (BIT(0)) -#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S) -#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U -#define KEYMNG_PREP_DONE_INT_RAW_S 0 -/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the km_proc_done_int interrupt - */ -#define KEYMNG_PROC_DONE_INT_RAW (BIT(1)) -#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S) -#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U -#define KEYMNG_PROC_DONE_INT_RAW_S 1 -/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the km_post_done_int interrupt - */ -#define KEYMNG_POST_DONE_INT_RAW (BIT(2)) -#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S) -#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U -#define KEYMNG_POST_DONE_INT_RAW_S 2 - -/** KEYMNG_INT_ST_REG register - * Key Manager interrupt status register. - */ -#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc) -/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the km_prep_done_int interrupt - */ -#define KEYMNG_PREP_DONE_INT_ST (BIT(0)) -#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S) -#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U -#define KEYMNG_PREP_DONE_INT_ST_S 0 -/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the km_proc_done_int interrupt - */ -#define KEYMNG_PROC_DONE_INT_ST (BIT(1)) -#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S) -#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U -#define KEYMNG_PROC_DONE_INT_ST_S 1 -/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the km_post_done_int interrupt - */ -#define KEYMNG_POST_DONE_INT_ST (BIT(2)) -#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S) -#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U -#define KEYMNG_POST_DONE_INT_ST_S 2 - -/** KEYMNG_INT_ENA_REG register - * Key Manager interrupt enable register. - */ -#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10) -/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the km_prep_done_int interrupt - */ -#define KEYMNG_PREP_DONE_INT_ENA (BIT(0)) -#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S) -#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U -#define KEYMNG_PREP_DONE_INT_ENA_S 0 -/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the km_proc_done_int interrupt - */ -#define KEYMNG_PROC_DONE_INT_ENA (BIT(1)) -#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S) -#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U -#define KEYMNG_PROC_DONE_INT_ENA_S 1 -/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the km_post_done_int interrupt - */ -#define KEYMNG_POST_DONE_INT_ENA (BIT(2)) -#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S) -#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U -#define KEYMNG_POST_DONE_INT_ENA_S 2 - -/** KEYMNG_INT_CLR_REG register - * Key Manager interrupt clear register. - */ -#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14) -/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the km_prep_done_int interrupt - */ -#define KEYMNG_PREP_DONE_INT_CLR (BIT(0)) -#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S) -#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U -#define KEYMNG_PREP_DONE_INT_CLR_S 0 -/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the km_proc_done_int interrupt - */ -#define KEYMNG_PROC_DONE_INT_CLR (BIT(1)) -#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S) -#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U -#define KEYMNG_PROC_DONE_INT_CLR_S 1 -/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the km_post_done_int interrupt - */ -#define KEYMNG_POST_DONE_INT_CLR (BIT(2)) -#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S) -#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U -#define KEYMNG_POST_DONE_INT_CLR_S 2 - -/** KEYMNG_STATIC_REG register - * Key Manager static configuration register - */ -#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18) -/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0; - * Set each bit to choose efuse key instead of key manager deployed key. Each bit - * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; - * bit 1 for flash_key; bit 0 for ecdsa_key - */ -#define KEYMNG_USE_EFUSE_KEY 0x0000001FU -#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S) -#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU -#define KEYMNG_USE_EFUSE_KEY_S 0 -/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15; - * The core clock cycle number to sample one rng input data. Please set it bigger than - * the clock cycle ratio: T_rng/T_km - */ -#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU -#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S) -#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU -#define KEYMNG_RND_SWITCH_CYCLE_S 5 -/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0; - * Set this bit to use software written init key instead of efuse_init_key. - */ -#define KEYMNG_USE_SW_INIT_KEY (BIT(10)) -#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S) -#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U -#define KEYMNG_USE_SW_INIT_KEY_S 10 -/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0; - * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use - * xts-aes-256. 0: use xts-aes-128. - */ -#define KEYMNG_FLASH_KEY_LEN (BIT(11)) -#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S) -#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U -#define KEYMNG_FLASH_KEY_LEN_S 11 -/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0; - * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use - * xts-aes-256. 0: use xts-aes-128. - */ -#define KEYMNG_PSRAM_KEY_LEN (BIT(12)) -#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S) -#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U -#define KEYMNG_PSRAM_KEY_LEN_S 12 - -/** KEYMNG_LOCK_REG register - * Key Manager static configuration locker register - */ -#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c) -/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0; - * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of - * reg_use_efuse_key. - */ -#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU -#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S) -#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU -#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0 -/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0; - * Write 1 to lock reg_rnd_switch_cycle. - */ -#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5)) -#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S) -#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U -#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5 -/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0; - * Write 1 to lock reg_use_sw_init_key. - */ -#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6)) -#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S) -#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U -#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6 -/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0; - * Write 1 to lock reg_flash_key_len. - */ -#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7)) -#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S) -#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U -#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7 -/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0; - * Write 1 to lock reg_psram_key_len. - */ -#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8)) -#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S) -#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U -#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8 - -/** KEYMNG_CONF_REG register - * Key Manager configuration register - */ -#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20) -/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0; - * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES - * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. - */ -#define KEYMNG_KGEN_MODE 0x00000007U -#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S) -#define KEYMNG_KGEN_MODE_V 0x00000007U -#define KEYMNG_KGEN_MODE_S 0 -/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0; - * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: - * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: - * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: - * ecdsa_key_384_h. Others: reserved. - */ -#define KEYMNG_KEY_PURPOSE 0x0000000FU -#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S) -#define KEYMNG_KEY_PURPOSE_V 0x0000000FU -#define KEYMNG_KEY_PURPOSE_S 3 - -/** KEYMNG_START_REG register - * Key Manager control register - */ -#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24) -/** KEYMNG_START : WT; bitpos: [0]; default: 0; - * Write 1 to continue Key Manager operation at LOAD/GAIN state. - */ -#define KEYMNG_START (BIT(0)) -#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S) -#define KEYMNG_START_V 0x00000001U -#define KEYMNG_START_S 0 -/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0; - * Write 1 to start Key Manager at IDLE state. - */ -#define KEYMNG_CONTINUE (BIT(1)) -#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S) -#define KEYMNG_CONTINUE_V 0x00000001U -#define KEYMNG_CONTINUE_S 1 - -/** KEYMNG_STATE_REG register - * Key Manager state register - */ -#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28) -/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0; - * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. - */ -#define KEYMNG_STATE 0x00000003U -#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S) -#define KEYMNG_STATE_V 0x00000003U -#define KEYMNG_STATE_S 0 - -/** KEYMNG_RESULT_REG register - * Key Manager operation result register - */ -#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c) -/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0; - * The procedure result bit of Key Manager, only valid when Key Manager procedure is - * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. - */ -#define KEYMNG_PROC_RESULT (BIT(0)) -#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S) -#define KEYMNG_PROC_RESULT_V 0x00000001U -#define KEYMNG_PROC_RESULT_S 0 - -/** KEYMNG_KEY_VLD_REG register - * Key Manager key status register - */ -#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30) -/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0; - * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ -#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0)) -#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S) -#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U -#define KEYMNG_KEY_ECDSA_192_VLD_S 0 -/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0; - * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ -#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1)) -#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S) -#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U -#define KEYMNG_KEY_ECDSA_256_VLD_S 1 -/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0; - * The status bit for key_flash. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ -#define KEYMNG_KEY_FLASH_VLD (BIT(2)) -#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S) -#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U -#define KEYMNG_KEY_FLASH_VLD_S 2 -/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0; - * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. - */ -#define KEYMNG_KEY_HMAC_VLD (BIT(3)) -#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S) -#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U -#define KEYMNG_KEY_HMAC_VLD_S 3 -/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0; - * The status bit for key_ds. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ -#define KEYMNG_KEY_DS_VLD (BIT(4)) -#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S) -#define KEYMNG_KEY_DS_VLD_V 0x00000001U -#define KEYMNG_KEY_DS_VLD_S 4 -/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0; - * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. - */ -#define KEYMNG_KEY_PSRAM_VLD (BIT(5)) -#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S) -#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U -#define KEYMNG_KEY_PSRAM_VLD_S 5 -/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0; - * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ -#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6)) -#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S) -#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U -#define KEYMNG_KEY_ECDSA_384_VLD_S 6 - -/** KEYMNG_HUK_VLD_REG register - * Key Manager HUK status register - */ -#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34) -/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0; - * The HUK status. 0: HUK is not valid. 1: HUK is valid. - */ -#define KEYMNG_HUK_VALID (BIT(0)) -#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S) -#define KEYMNG_HUK_VALID_V 0x00000001U -#define KEYMNG_HUK_VALID_S 0 - -/** KEYMNG_DATE_REG register - * Version control register - */ -#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc) -/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824; - * Key Manager version control register. - */ -#define KEYMNG_DATE 0x0FFFFFFFU -#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S) -#define KEYMNG_DATE_V 0x0FFFFFFFU -#define KEYMNG_DATE_S 0 - -/** KEYMNG_ASSIST_INFO_MEM register - * The memory that stores assist key info. - */ -#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100) -#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64 - -/** KEYMNG_PUBLIC_INFO_MEM register - * The memory that stores public key info. - */ -#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140) -#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64 - -/** KEYMNG_SW_INIT_KEY_MEM register - * The memory that stores software written init key. - */ -#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180) -#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/keymng_struct.h b/components/soc/esp32c5/register/soc/keymng_struct.h index 2512497013..f32ab803a6 100644 --- a/components/soc/esp32c5/register/soc/keymng_struct.h +++ b/components/soc/esp32c5/register/soc/keymng_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -202,9 +202,10 @@ typedef union { */ uint32_t kgen_mode:3; /** key_purpose : R/W; bitpos: [6:3]; default: 0; - * Set this field to choose the key purpose. 1: ecdsa_key 2: flash_256_1_key. 3: - * flash_256_2_key. 4: flash_128_key. 6: hmac_key. 7: ds_key. 8: psram_256_1_key. 9: - * psram_256_2_key. 10: psram_128_key. Others: reserved. + * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: + * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: + * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: + * ecdsa_key_384_h. Others: reserved. */ uint32_t key_purpose:4; uint32_t reserved_7:25; @@ -270,32 +271,42 @@ typedef union { */ typedef union { struct { - /** key_ecdsa_vld : RO; bitpos: [0]; default: 0; - * The status bit for key_ecdsa. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. + /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0; + * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. */ - uint32_t key_ecdsa_vld:1; - /** key_flash_vld : RO; bitpos: [1]; default: 0; + uint32_t key_ecdsa_192_vld:1; + /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0; + * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_256_vld:1; + /** key_flash_vld : RO; bitpos: [2]; default: 0; * The status bit for key_flash. 1: The key has been deployed correctly. 0: The * key has not been deployed yet. */ uint32_t key_flash_vld:1; - /** key_hmac_vld : RO; bitpos: [2]; default: 0; + /** key_hmac_vld : RO; bitpos: [3]; default: 0; * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key * has not been deployed yet. */ uint32_t key_hmac_vld:1; - /** key_ds_vld : RO; bitpos: [3]; default: 0; + /** key_ds_vld : RO; bitpos: [4]; default: 0; * The status bit for key_ds. 1: The key has been deployed correctly. 0: The * key has not been deployed yet. */ uint32_t key_ds_vld:1; - /** key_psram_vld : RO; bitpos: [4]; default: 0; + /** key_psram_vld : RO; bitpos: [5]; default: 0; * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key * has not been deployed yet. */ uint32_t key_psram_vld:1; - uint32_t reserved_5:27; + /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0; + * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The + * key has not been deployed yet. + */ + uint32_t key_ecdsa_384_vld:1; + uint32_t reserved_7:25; }; uint32_t val; } keymng_key_vld_reg_t; @@ -321,7 +332,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774224; + /** date : R/W; bitpos: [27:0]; default: 37781824; * Key Manager version control register. */ uint32_t date:28; @@ -338,7 +349,7 @@ typedef struct { volatile keymng_int_st_reg_t int_st; volatile keymng_int_ena_reg_t int_ena; volatile keymng_int_clr_reg_t int_clr; - volatile keymng_static_reg_t static_cfg; + volatile keymng_static_reg_t static_conf; volatile keymng_lock_reg_t lock; volatile keymng_conf_reg_t conf; volatile keymng_start_reg_t start; diff --git a/components/soc/esp32c5/register/soc/keymng_struct_eco2.h b/components/soc/esp32c5/register/soc/keymng_struct_eco2.h deleted file mode 100644 index faacfdf486..0000000000 --- a/components/soc/esp32c5/register/soc/keymng_struct_eco2.h +++ /dev/null @@ -1,375 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Memory data */ - -/** Group: Clock gate register */ -/** Type of clk register - * Key Manager clock gate control register - */ -typedef union { - struct { - /** reg_cg_force_on : R/W; bitpos: [0]; default: 1; - * Write 1 to force on register clock gate. - */ - uint32_t reg_cg_force_on:1; - /** mem_cg_force_on : R/W; bitpos: [1]; default: 0; - * Write 1 to force on memory clock gate. - */ - uint32_t mem_cg_force_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} keymng_clk_reg_t; - - -/** Group: Interrupt registers */ -/** Type of int_raw register - * Key Manager interrupt raw register, valid in level. - */ -typedef union { - struct { - /** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt status bit for the km_prep_done_int interrupt - */ - uint32_t prep_done_int_raw:1; - /** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt status bit for the km_proc_done_int interrupt - */ - uint32_t proc_done_int_raw:1; - /** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt status bit for the km_post_done_int interrupt - */ - uint32_t post_done_int_raw:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} keymng_int_raw_reg_t; - -/** Type of int_st register - * Key Manager interrupt status register. - */ -typedef union { - struct { - /** prep_done_int_st : RO; bitpos: [0]; default: 0; - * The masked interrupt status bit for the km_prep_done_int interrupt - */ - uint32_t prep_done_int_st:1; - /** proc_done_int_st : RO; bitpos: [1]; default: 0; - * The masked interrupt status bit for the km_proc_done_int interrupt - */ - uint32_t proc_done_int_st:1; - /** post_done_int_st : RO; bitpos: [2]; default: 0; - * The masked interrupt status bit for the km_post_done_int interrupt - */ - uint32_t post_done_int_st:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} keymng_int_st_reg_t; - -/** Type of int_ena register - * Key Manager interrupt enable register. - */ -typedef union { - struct { - /** prep_done_int_ena : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the km_prep_done_int interrupt - */ - uint32_t prep_done_int_ena:1; - /** proc_done_int_ena : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the km_proc_done_int interrupt - */ - uint32_t proc_done_int_ena:1; - /** post_done_int_ena : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the km_post_done_int interrupt - */ - uint32_t post_done_int_ena:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} keymng_int_ena_reg_t; - -/** Type of int_clr register - * Key Manager interrupt clear register. - */ -typedef union { - struct { - /** prep_done_int_clr : WT; bitpos: [0]; default: 0; - * Set this bit to clear the km_prep_done_int interrupt - */ - uint32_t prep_done_int_clr:1; - /** proc_done_int_clr : WT; bitpos: [1]; default: 0; - * Set this bit to clear the km_proc_done_int interrupt - */ - uint32_t proc_done_int_clr:1; - /** post_done_int_clr : WT; bitpos: [2]; default: 0; - * Set this bit to clear the km_post_done_int interrupt - */ - uint32_t post_done_int_clr:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} keymng_int_clr_reg_t; - - -/** Group: Static configuration registers */ -/** Type of static register - * Key Manager static configuration register - */ -typedef union { - struct { - /** use_efuse_key : R/W; bitpos: [4:0]; default: 0; - * Set each bit to choose efuse key instead of key manager deployed key. Each bit - * stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key; - * bit 1 for flash_key; bit 0 for ecdsa_key - */ - uint32_t use_efuse_key:5; - /** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15; - * The core clock cycle number to sample one rng input data. Please set it bigger than - * the clock cycle ratio: T_rng/T_km - */ - uint32_t rnd_switch_cycle:5; - /** use_sw_init_key : R/W; bitpos: [10]; default: 0; - * Set this bit to use software written init key instead of efuse_init_key. - */ - uint32_t use_sw_init_key:1; - /** flash_key_len : R/W; bitpos: [11]; default: 0; - * Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use - * xts-aes-256. 0: use xts-aes-128. - */ - uint32_t flash_key_len:1; - /** psram_key_len : R/W; bitpos: [12]; default: 0; - * Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use - * xts-aes-256. 0: use xts-aes-128. - */ - uint32_t psram_key_len:1; - uint32_t reserved_13:19; - }; - uint32_t val; -} keymng_static_reg_t; - -/** Type of lock register - * Key Manager static configuration locker register - */ -typedef union { - struct { - /** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0; - * Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of - * reg_use_efuse_key. - */ - uint32_t use_efuse_key_lock:5; - /** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0; - * Write 1 to lock reg_rnd_switch_cycle. - */ - uint32_t rnd_switch_cycle_lock:1; - /** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0; - * Write 1 to lock reg_use_sw_init_key. - */ - uint32_t use_sw_init_key_lock:1; - /** flash_key_len_lock : R/W1; bitpos: [7]; default: 0; - * Write 1 to lock reg_flash_key_len. - */ - uint32_t flash_key_len_lock:1; - /** psram_key_len_lock : R/W1; bitpos: [8]; default: 0; - * Write 1 to lock reg_psram_key_len. - */ - uint32_t psram_key_len_lock:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} keymng_lock_reg_t; - - -/** Group: Configuration registers */ -/** Type of conf register - * Key Manager configuration register - */ -typedef union { - struct { - /** kgen_mode : R/W; bitpos: [2:0]; default: 0; - * Set this field to choose the key generator deployment mode. 0: random mode. 1: AES - * mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved. - */ - uint32_t kgen_mode:3; - /** key_purpose : R/W; bitpos: [6:3]; default: 0; - * Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3: - * flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8: - * psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12: - * ecdsa_key_384_h. Others: reserved. - */ - uint32_t key_purpose:4; - uint32_t reserved_7:25; - }; - uint32_t val; -} keymng_conf_reg_t; - - -/** Group: Control registers */ -/** Type of start register - * Key Manager control register - */ -typedef union { - struct { - /** start : WT; bitpos: [0]; default: 0; - * Write 1 to conti Key Manager operation at LOAD/GAIN state. - */ - uint32_t start:1; - /** conti : WT; bitpos: [1]; default: 0; - * Write 1 to start Key Manager at IDLE state. - */ - uint32_t conti:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} keymng_start_reg_t; - - -/** Group: State registers */ -/** Type of state register - * Key Manager state register - */ -typedef union { - struct { - /** state : RO; bitpos: [1:0]; default: 0; - * The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY. - */ - uint32_t state:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} keymng_state_reg_t; - - -/** Group: Result registers */ -/** Type of result register - * Key Manager operation result register - */ -typedef union { - struct { - /** proc_result : RO/SS; bitpos: [0]; default: 0; - * The procedure result bit of Key Manager, only valid when Key Manager procedure is - * done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed. - */ - uint32_t proc_result:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} keymng_result_reg_t; - -/** Type of key_vld register - * Key Manager key status register - */ -typedef union { - struct { - /** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0; - * The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ - uint32_t key_ecdsa_192_vld:1; - /** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0; - * The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ - uint32_t key_ecdsa_256_vld:1; - /** key_flash_vld : RO; bitpos: [2]; default: 0; - * The status bit for key_flash. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ - uint32_t key_flash_vld:1; - /** key_hmac_vld : RO; bitpos: [3]; default: 0; - * The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. - */ - uint32_t key_hmac_vld:1; - /** key_ds_vld : RO; bitpos: [4]; default: 0; - * The status bit for key_ds. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ - uint32_t key_ds_vld:1; - /** key_psram_vld : RO; bitpos: [5]; default: 0; - * The status bit for key_psram. 1: The key has been deployed correctly. 0: The key - * has not been deployed yet. - */ - uint32_t key_psram_vld:1; - /** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0; - * The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The - * key has not been deployed yet. - */ - uint32_t key_ecdsa_384_vld:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} keymng_key_vld_reg_t; - -/** Type of huk_vld register - * Key Manager HUK status register - */ -typedef union { - struct { - /** huk_valid : RO; bitpos: [0]; default: 0; - * The HUK status. 0: HUK is not valid. 1: HUK is valid. - */ - uint32_t huk_valid:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} keymng_huk_vld_reg_t; - - -/** Group: Version register */ -/** Type of date register - * Version control register - */ -typedef union { - struct { - /** date : R/W; bitpos: [27:0]; default: 37781824; - * Key Manager version control register. - */ - uint32_t date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} keymng_date_reg_t; - - -typedef struct { - uint32_t reserved_000; - volatile keymng_clk_reg_t clk; - volatile keymng_int_raw_reg_t int_raw; - volatile keymng_int_st_reg_t int_st; - volatile keymng_int_ena_reg_t int_ena; - volatile keymng_int_clr_reg_t int_clr; - volatile keymng_static_reg_t static_conf; - volatile keymng_lock_reg_t lock; - volatile keymng_conf_reg_t conf; - volatile keymng_start_reg_t start; - volatile keymng_state_reg_t state; - volatile keymng_result_reg_t result; - volatile keymng_key_vld_reg_t key_vld; - volatile keymng_huk_vld_reg_t huk_vld; - uint32_t reserved_038[49]; - volatile keymng_date_reg_t date; - volatile uint32_t assist_info[16]; - volatile uint32_t public_info[16]; - volatile uint32_t sw_init_key[8]; -} keymng_dev_t; - -extern keymng_dev_t KEYMNG; - -#ifndef __cplusplus -_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/lp_apm0_reg.h b/components/soc/esp32c5/register/soc/lp_apm0_reg.h index 789db5cd27..c9850a0f10 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM0_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM0_REGION_FILTER_EN_REG (DR_REG_LP_APM0_BASE + 0x0) /** LP_APM0_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM0_REGION_FILTER_EN 0x000000FFU #define LP_APM0_REGION_FILTER_EN_M (LP_APM0_REGION_FILTER_EN_V << LP_APM0_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4) /** LP_APM0_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0 + * Configures the start address of region 0. */ #define LP_APM0_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_START_M (LP_APM0_REGION0_ADDR_START_V << LP_APM0_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM0_REGION0_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x8) /** LP_APM0_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0 + * Configures the end address of region 0. */ #define LP_APM0_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION0_ADDR_END_M (LP_APM0_REGION0_ADDR_END_V << LP_APM0_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM0_REGION0_ADDR_END_S 0 /** LP_APM0_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION0_ATTR_REG (DR_REG_LP_APM0_BASE + 0xc) /** LP_APM0_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_X (BIT(0)) #define LP_APM0_REGION0_R0_X_M (LP_APM0_REGION0_R0_X_V << LP_APM0_REGION0_R0_X_S) #define LP_APM0_REGION0_R0_X_V 0x00000001U #define LP_APM0_REGION0_R0_X_S 0 /** LP_APM0_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_W (BIT(1)) #define LP_APM0_REGION0_R0_W_M (LP_APM0_REGION0_R0_W_V << LP_APM0_REGION0_R0_W_S) #define LP_APM0_REGION0_R0_W_V 0x00000001U #define LP_APM0_REGION0_R0_W_S 1 /** LP_APM0_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM0_REGION0_R0_R (BIT(2)) #define LP_APM0_REGION0_R0_R_M (LP_APM0_REGION0_R0_R_V << LP_APM0_REGION0_R0_R_S) #define LP_APM0_REGION0_R0_R_V 0x00000001U #define LP_APM0_REGION0_R0_R_S 2 /** LP_APM0_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_X (BIT(4)) #define LP_APM0_REGION0_R1_X_M (LP_APM0_REGION0_R1_X_V << LP_APM0_REGION0_R1_X_S) #define LP_APM0_REGION0_R1_X_V 0x00000001U #define LP_APM0_REGION0_R1_X_S 4 /** LP_APM0_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_W (BIT(5)) #define LP_APM0_REGION0_R1_W_M (LP_APM0_REGION0_R1_W_V << LP_APM0_REGION0_R1_W_S) #define LP_APM0_REGION0_R1_W_V 0x00000001U #define LP_APM0_REGION0_R1_W_S 5 /** LP_APM0_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM0_REGION0_R1_R (BIT(6)) #define LP_APM0_REGION0_R1_R_M (LP_APM0_REGION0_R1_R_V << LP_APM0_REGION0_R1_R_S) #define LP_APM0_REGION0_R1_R_V 0x00000001U #define LP_APM0_REGION0_R1_R_S 6 /** LP_APM0_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_X (BIT(8)) #define LP_APM0_REGION0_R2_X_M (LP_APM0_REGION0_R2_X_V << LP_APM0_REGION0_R2_X_S) #define LP_APM0_REGION0_R2_X_V 0x00000001U #define LP_APM0_REGION0_R2_X_S 8 /** LP_APM0_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_W (BIT(9)) #define LP_APM0_REGION0_R2_W_M (LP_APM0_REGION0_R2_W_V << LP_APM0_REGION0_R2_W_S) #define LP_APM0_REGION0_R2_W_V 0x00000001U #define LP_APM0_REGION0_R2_W_S 9 /** LP_APM0_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM0_REGION0_R2_R (BIT(10)) #define LP_APM0_REGION0_R2_R_M (LP_APM0_REGION0_R2_R_V << LP_APM0_REGION0_R2_R_S) #define LP_APM0_REGION0_R2_R_V 0x00000001U #define LP_APM0_REGION0_R2_R_S 10 /** LP_APM0_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM0_REGION0_ADDR_START_REG, LP_APM0_REGION0_ADDR_END_REG and + * LP_APM0_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION0_LOCK (BIT(11)) #define LP_APM0_REGION0_LOCK_M (LP_APM0_REGION0_LOCK_V << LP_APM0_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x10) /** LP_APM0_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1 + * Configures the start address of region 1. */ #define LP_APM0_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_START_M (LP_APM0_REGION1_ADDR_START_V << LP_APM0_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM0_REGION1_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x14) /** LP_APM0_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1 + * Configures the end address of region 1. */ #define LP_APM0_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION1_ADDR_END_M (LP_APM0_REGION1_ADDR_END_V << LP_APM0_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM0_REGION1_ADDR_END_S 0 /** LP_APM0_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION1_ATTR_REG (DR_REG_LP_APM0_BASE + 0x18) /** LP_APM0_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_X (BIT(0)) #define LP_APM0_REGION1_R0_X_M (LP_APM0_REGION1_R0_X_V << LP_APM0_REGION1_R0_X_S) #define LP_APM0_REGION1_R0_X_V 0x00000001U #define LP_APM0_REGION1_R0_X_S 0 /** LP_APM0_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_W (BIT(1)) #define LP_APM0_REGION1_R0_W_M (LP_APM0_REGION1_R0_W_V << LP_APM0_REGION1_R0_W_S) #define LP_APM0_REGION1_R0_W_V 0x00000001U #define LP_APM0_REGION1_R0_W_S 1 /** LP_APM0_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM0_REGION1_R0_R (BIT(2)) #define LP_APM0_REGION1_R0_R_M (LP_APM0_REGION1_R0_R_V << LP_APM0_REGION1_R0_R_S) #define LP_APM0_REGION1_R0_R_V 0x00000001U #define LP_APM0_REGION1_R0_R_S 2 /** LP_APM0_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_X (BIT(4)) #define LP_APM0_REGION1_R1_X_M (LP_APM0_REGION1_R1_X_V << LP_APM0_REGION1_R1_X_S) #define LP_APM0_REGION1_R1_X_V 0x00000001U #define LP_APM0_REGION1_R1_X_S 4 /** LP_APM0_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_W (BIT(5)) #define LP_APM0_REGION1_R1_W_M (LP_APM0_REGION1_R1_W_V << LP_APM0_REGION1_R1_W_S) #define LP_APM0_REGION1_R1_W_V 0x00000001U #define LP_APM0_REGION1_R1_W_S 5 /** LP_APM0_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM0_REGION1_R1_R (BIT(6)) #define LP_APM0_REGION1_R1_R_M (LP_APM0_REGION1_R1_R_V << LP_APM0_REGION1_R1_R_S) #define LP_APM0_REGION1_R1_R_V 0x00000001U #define LP_APM0_REGION1_R1_R_S 6 /** LP_APM0_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_X (BIT(8)) #define LP_APM0_REGION1_R2_X_M (LP_APM0_REGION1_R2_X_V << LP_APM0_REGION1_R2_X_S) #define LP_APM0_REGION1_R2_X_V 0x00000001U #define LP_APM0_REGION1_R2_X_S 8 /** LP_APM0_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_W (BIT(9)) #define LP_APM0_REGION1_R2_W_M (LP_APM0_REGION1_R2_W_V << LP_APM0_REGION1_R2_W_S) #define LP_APM0_REGION1_R2_W_V 0x00000001U #define LP_APM0_REGION1_R2_W_S 9 /** LP_APM0_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM0_REGION1_R2_R (BIT(10)) #define LP_APM0_REGION1_R2_R_M (LP_APM0_REGION1_R2_R_V << LP_APM0_REGION1_R2_R_S) #define LP_APM0_REGION1_R2_R_V 0x00000001U #define LP_APM0_REGION1_R2_R_S 10 /** LP_APM0_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM0_REGION1_ADDR_START_REG, LP_APM0_REGION1_ADDR_END_REG and + * LP_APM0_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION1_LOCK (BIT(11)) #define LP_APM0_REGION1_LOCK_M (LP_APM0_REGION1_LOCK_V << LP_APM0_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x1c) /** LP_APM0_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2 + * Configures the start address of region 2. */ #define LP_APM0_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_START_M (LP_APM0_REGION2_ADDR_START_V << LP_APM0_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM0_REGION2_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x20) /** LP_APM0_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2 + * Configures the end address of region 2. */ #define LP_APM0_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION2_ADDR_END_M (LP_APM0_REGION2_ADDR_END_V << LP_APM0_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM0_REGION2_ADDR_END_S 0 /** LP_APM0_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION2_ATTR_REG (DR_REG_LP_APM0_BASE + 0x24) /** LP_APM0_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_X (BIT(0)) #define LP_APM0_REGION2_R0_X_M (LP_APM0_REGION2_R0_X_V << LP_APM0_REGION2_R0_X_S) #define LP_APM0_REGION2_R0_X_V 0x00000001U #define LP_APM0_REGION2_R0_X_S 0 /** LP_APM0_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_W (BIT(1)) #define LP_APM0_REGION2_R0_W_M (LP_APM0_REGION2_R0_W_V << LP_APM0_REGION2_R0_W_S) #define LP_APM0_REGION2_R0_W_V 0x00000001U #define LP_APM0_REGION2_R0_W_S 1 /** LP_APM0_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM0_REGION2_R0_R (BIT(2)) #define LP_APM0_REGION2_R0_R_M (LP_APM0_REGION2_R0_R_V << LP_APM0_REGION2_R0_R_S) #define LP_APM0_REGION2_R0_R_V 0x00000001U #define LP_APM0_REGION2_R0_R_S 2 /** LP_APM0_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_X (BIT(4)) #define LP_APM0_REGION2_R1_X_M (LP_APM0_REGION2_R1_X_V << LP_APM0_REGION2_R1_X_S) #define LP_APM0_REGION2_R1_X_V 0x00000001U #define LP_APM0_REGION2_R1_X_S 4 /** LP_APM0_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_W (BIT(5)) #define LP_APM0_REGION2_R1_W_M (LP_APM0_REGION2_R1_W_V << LP_APM0_REGION2_R1_W_S) #define LP_APM0_REGION2_R1_W_V 0x00000001U #define LP_APM0_REGION2_R1_W_S 5 /** LP_APM0_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM0_REGION2_R1_R (BIT(6)) #define LP_APM0_REGION2_R1_R_M (LP_APM0_REGION2_R1_R_V << LP_APM0_REGION2_R1_R_S) #define LP_APM0_REGION2_R1_R_V 0x00000001U #define LP_APM0_REGION2_R1_R_S 6 /** LP_APM0_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_X (BIT(8)) #define LP_APM0_REGION2_R2_X_M (LP_APM0_REGION2_R2_X_V << LP_APM0_REGION2_R2_X_S) #define LP_APM0_REGION2_R2_X_V 0x00000001U #define LP_APM0_REGION2_R2_X_S 8 /** LP_APM0_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_W (BIT(9)) #define LP_APM0_REGION2_R2_W_M (LP_APM0_REGION2_R2_W_V << LP_APM0_REGION2_R2_W_S) #define LP_APM0_REGION2_R2_W_V 0x00000001U #define LP_APM0_REGION2_R2_W_S 9 /** LP_APM0_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM0_REGION2_R2_R (BIT(10)) #define LP_APM0_REGION2_R2_R_M (LP_APM0_REGION2_R2_R_V << LP_APM0_REGION2_R2_R_S) #define LP_APM0_REGION2_R2_R_V 0x00000001U #define LP_APM0_REGION2_R2_R_S 10 /** LP_APM0_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM0_REGION2_ADDR_START_REG, LP_APM0_REGION2_ADDR_END_REG and + * LP_APM0_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION2_LOCK (BIT(11)) #define LP_APM0_REGION2_LOCK_M (LP_APM0_REGION2_LOCK_V << LP_APM0_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x28) /** LP_APM0_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3 + * Configures the start address of region 3. */ #define LP_APM0_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_START_M (LP_APM0_REGION3_ADDR_START_V << LP_APM0_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM0_REGION3_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x2c) /** LP_APM0_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3 + * Configures the end address of region 3. */ #define LP_APM0_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION3_ADDR_END_M (LP_APM0_REGION3_ADDR_END_V << LP_APM0_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM0_REGION3_ADDR_END_S 0 /** LP_APM0_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION3_ATTR_REG (DR_REG_LP_APM0_BASE + 0x30) /** LP_APM0_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_X (BIT(0)) #define LP_APM0_REGION3_R0_X_M (LP_APM0_REGION3_R0_X_V << LP_APM0_REGION3_R0_X_S) #define LP_APM0_REGION3_R0_X_V 0x00000001U #define LP_APM0_REGION3_R0_X_S 0 /** LP_APM0_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_W (BIT(1)) #define LP_APM0_REGION3_R0_W_M (LP_APM0_REGION3_R0_W_V << LP_APM0_REGION3_R0_W_S) #define LP_APM0_REGION3_R0_W_V 0x00000001U #define LP_APM0_REGION3_R0_W_S 1 /** LP_APM0_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM0_REGION3_R0_R (BIT(2)) #define LP_APM0_REGION3_R0_R_M (LP_APM0_REGION3_R0_R_V << LP_APM0_REGION3_R0_R_S) #define LP_APM0_REGION3_R0_R_V 0x00000001U #define LP_APM0_REGION3_R0_R_S 2 /** LP_APM0_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_X (BIT(4)) #define LP_APM0_REGION3_R1_X_M (LP_APM0_REGION3_R1_X_V << LP_APM0_REGION3_R1_X_S) #define LP_APM0_REGION3_R1_X_V 0x00000001U #define LP_APM0_REGION3_R1_X_S 4 /** LP_APM0_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_W (BIT(5)) #define LP_APM0_REGION3_R1_W_M (LP_APM0_REGION3_R1_W_V << LP_APM0_REGION3_R1_W_S) #define LP_APM0_REGION3_R1_W_V 0x00000001U #define LP_APM0_REGION3_R1_W_S 5 /** LP_APM0_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM0_REGION3_R1_R (BIT(6)) #define LP_APM0_REGION3_R1_R_M (LP_APM0_REGION3_R1_R_V << LP_APM0_REGION3_R1_R_S) #define LP_APM0_REGION3_R1_R_V 0x00000001U #define LP_APM0_REGION3_R1_R_S 6 /** LP_APM0_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_X (BIT(8)) #define LP_APM0_REGION3_R2_X_M (LP_APM0_REGION3_R2_X_V << LP_APM0_REGION3_R2_X_S) #define LP_APM0_REGION3_R2_X_V 0x00000001U #define LP_APM0_REGION3_R2_X_S 8 /** LP_APM0_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_W (BIT(9)) #define LP_APM0_REGION3_R2_W_M (LP_APM0_REGION3_R2_W_V << LP_APM0_REGION3_R2_W_S) #define LP_APM0_REGION3_R2_W_V 0x00000001U #define LP_APM0_REGION3_R2_W_S 9 /** LP_APM0_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM0_REGION3_R2_R (BIT(10)) #define LP_APM0_REGION3_R2_R_M (LP_APM0_REGION3_R2_R_V << LP_APM0_REGION3_R2_R_S) #define LP_APM0_REGION3_R2_R_V 0x00000001U #define LP_APM0_REGION3_R2_R_S 10 /** LP_APM0_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM0_REGION3_ADDR_START_REG, LP_APM0_REGION3_ADDR_END_REG and + * LP_APM0_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION3_LOCK (BIT(11)) #define LP_APM0_REGION3_LOCK_M (LP_APM0_REGION3_LOCK_V << LP_APM0_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x34) /** LP_APM0_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4 + * Configures the start address of region 4. */ #define LP_APM0_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_START_M (LP_APM0_REGION4_ADDR_START_V << LP_APM0_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM0_REGION4_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x38) /** LP_APM0_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4 + * Configures the end address of region 4. */ #define LP_APM0_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION4_ADDR_END_M (LP_APM0_REGION4_ADDR_END_V << LP_APM0_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM0_REGION4_ADDR_END_S 0 /** LP_APM0_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION4_ATTR_REG (DR_REG_LP_APM0_BASE + 0x3c) /** LP_APM0_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_X (BIT(0)) #define LP_APM0_REGION4_R0_X_M (LP_APM0_REGION4_R0_X_V << LP_APM0_REGION4_R0_X_S) #define LP_APM0_REGION4_R0_X_V 0x00000001U #define LP_APM0_REGION4_R0_X_S 0 /** LP_APM0_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_W (BIT(1)) #define LP_APM0_REGION4_R0_W_M (LP_APM0_REGION4_R0_W_V << LP_APM0_REGION4_R0_W_S) #define LP_APM0_REGION4_R0_W_V 0x00000001U #define LP_APM0_REGION4_R0_W_S 1 /** LP_APM0_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM0_REGION4_R0_R (BIT(2)) #define LP_APM0_REGION4_R0_R_M (LP_APM0_REGION4_R0_R_V << LP_APM0_REGION4_R0_R_S) #define LP_APM0_REGION4_R0_R_V 0x00000001U #define LP_APM0_REGION4_R0_R_S 2 /** LP_APM0_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_X (BIT(4)) #define LP_APM0_REGION4_R1_X_M (LP_APM0_REGION4_R1_X_V << LP_APM0_REGION4_R1_X_S) #define LP_APM0_REGION4_R1_X_V 0x00000001U #define LP_APM0_REGION4_R1_X_S 4 /** LP_APM0_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_W (BIT(5)) #define LP_APM0_REGION4_R1_W_M (LP_APM0_REGION4_R1_W_V << LP_APM0_REGION4_R1_W_S) #define LP_APM0_REGION4_R1_W_V 0x00000001U #define LP_APM0_REGION4_R1_W_S 5 /** LP_APM0_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM0_REGION4_R1_R (BIT(6)) #define LP_APM0_REGION4_R1_R_M (LP_APM0_REGION4_R1_R_V << LP_APM0_REGION4_R1_R_S) #define LP_APM0_REGION4_R1_R_V 0x00000001U #define LP_APM0_REGION4_R1_R_S 6 /** LP_APM0_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_X (BIT(8)) #define LP_APM0_REGION4_R2_X_M (LP_APM0_REGION4_R2_X_V << LP_APM0_REGION4_R2_X_S) #define LP_APM0_REGION4_R2_X_V 0x00000001U #define LP_APM0_REGION4_R2_X_S 8 /** LP_APM0_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_W (BIT(9)) #define LP_APM0_REGION4_R2_W_M (LP_APM0_REGION4_R2_W_V << LP_APM0_REGION4_R2_W_S) #define LP_APM0_REGION4_R2_W_V 0x00000001U #define LP_APM0_REGION4_R2_W_S 9 /** LP_APM0_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM0_REGION4_R2_R (BIT(10)) #define LP_APM0_REGION4_R2_R_M (LP_APM0_REGION4_R2_R_V << LP_APM0_REGION4_R2_R_S) #define LP_APM0_REGION4_R2_R_V 0x00000001U #define LP_APM0_REGION4_R2_R_S 10 /** LP_APM0_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM0_REGION4_ADDR_START_REG, LP_APM0_REGION4_ADDR_END_REG and + * LP_APM0_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION4_LOCK (BIT(11)) #define LP_APM0_REGION4_LOCK_M (LP_APM0_REGION4_LOCK_V << LP_APM0_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x40) /** LP_APM0_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5 + * Configures the start address of region 5. */ #define LP_APM0_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_START_M (LP_APM0_REGION5_ADDR_START_V << LP_APM0_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM0_REGION5_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x44) /** LP_APM0_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5 + * Configures the end address of region 5. */ #define LP_APM0_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION5_ADDR_END_M (LP_APM0_REGION5_ADDR_END_V << LP_APM0_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM0_REGION5_ADDR_END_S 0 /** LP_APM0_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION5_ATTR_REG (DR_REG_LP_APM0_BASE + 0x48) /** LP_APM0_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_X (BIT(0)) #define LP_APM0_REGION5_R0_X_M (LP_APM0_REGION5_R0_X_V << LP_APM0_REGION5_R0_X_S) #define LP_APM0_REGION5_R0_X_V 0x00000001U #define LP_APM0_REGION5_R0_X_S 0 /** LP_APM0_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_W (BIT(1)) #define LP_APM0_REGION5_R0_W_M (LP_APM0_REGION5_R0_W_V << LP_APM0_REGION5_R0_W_S) #define LP_APM0_REGION5_R0_W_V 0x00000001U #define LP_APM0_REGION5_R0_W_S 1 /** LP_APM0_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM0_REGION5_R0_R (BIT(2)) #define LP_APM0_REGION5_R0_R_M (LP_APM0_REGION5_R0_R_V << LP_APM0_REGION5_R0_R_S) #define LP_APM0_REGION5_R0_R_V 0x00000001U #define LP_APM0_REGION5_R0_R_S 2 /** LP_APM0_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_X (BIT(4)) #define LP_APM0_REGION5_R1_X_M (LP_APM0_REGION5_R1_X_V << LP_APM0_REGION5_R1_X_S) #define LP_APM0_REGION5_R1_X_V 0x00000001U #define LP_APM0_REGION5_R1_X_S 4 /** LP_APM0_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_W (BIT(5)) #define LP_APM0_REGION5_R1_W_M (LP_APM0_REGION5_R1_W_V << LP_APM0_REGION5_R1_W_S) #define LP_APM0_REGION5_R1_W_V 0x00000001U #define LP_APM0_REGION5_R1_W_S 5 /** LP_APM0_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM0_REGION5_R1_R (BIT(6)) #define LP_APM0_REGION5_R1_R_M (LP_APM0_REGION5_R1_R_V << LP_APM0_REGION5_R1_R_S) #define LP_APM0_REGION5_R1_R_V 0x00000001U #define LP_APM0_REGION5_R1_R_S 6 /** LP_APM0_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_X (BIT(8)) #define LP_APM0_REGION5_R2_X_M (LP_APM0_REGION5_R2_X_V << LP_APM0_REGION5_R2_X_S) #define LP_APM0_REGION5_R2_X_V 0x00000001U #define LP_APM0_REGION5_R2_X_S 8 /** LP_APM0_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_W (BIT(9)) #define LP_APM0_REGION5_R2_W_M (LP_APM0_REGION5_R2_W_V << LP_APM0_REGION5_R2_W_S) #define LP_APM0_REGION5_R2_W_V 0x00000001U #define LP_APM0_REGION5_R2_W_S 9 /** LP_APM0_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM0_REGION5_R2_R (BIT(10)) #define LP_APM0_REGION5_R2_R_M (LP_APM0_REGION5_R2_R_V << LP_APM0_REGION5_R2_R_S) #define LP_APM0_REGION5_R2_R_V 0x00000001U #define LP_APM0_REGION5_R2_R_S 10 /** LP_APM0_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM0_REGION5_ADDR_START_REG, LP_APM0_REGION5_ADDR_END_REG and + * LP_APM0_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION5_LOCK (BIT(11)) #define LP_APM0_REGION5_LOCK_M (LP_APM0_REGION5_LOCK_V << LP_APM0_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x4c) /** LP_APM0_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6 + * Configures the start address of region 6. */ #define LP_APM0_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_START_M (LP_APM0_REGION6_ADDR_START_V << LP_APM0_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM0_REGION6_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x50) /** LP_APM0_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6 + * Configures the end address of region 6. */ #define LP_APM0_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION6_ADDR_END_M (LP_APM0_REGION6_ADDR_END_V << LP_APM0_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM0_REGION6_ADDR_END_S 0 /** LP_APM0_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION6_ATTR_REG (DR_REG_LP_APM0_BASE + 0x54) /** LP_APM0_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_X (BIT(0)) #define LP_APM0_REGION6_R0_X_M (LP_APM0_REGION6_R0_X_V << LP_APM0_REGION6_R0_X_S) #define LP_APM0_REGION6_R0_X_V 0x00000001U #define LP_APM0_REGION6_R0_X_S 0 /** LP_APM0_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_W (BIT(1)) #define LP_APM0_REGION6_R0_W_M (LP_APM0_REGION6_R0_W_V << LP_APM0_REGION6_R0_W_S) #define LP_APM0_REGION6_R0_W_V 0x00000001U #define LP_APM0_REGION6_R0_W_S 1 /** LP_APM0_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM0_REGION6_R0_R (BIT(2)) #define LP_APM0_REGION6_R0_R_M (LP_APM0_REGION6_R0_R_V << LP_APM0_REGION6_R0_R_S) #define LP_APM0_REGION6_R0_R_V 0x00000001U #define LP_APM0_REGION6_R0_R_S 2 /** LP_APM0_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_X (BIT(4)) #define LP_APM0_REGION6_R1_X_M (LP_APM0_REGION6_R1_X_V << LP_APM0_REGION6_R1_X_S) #define LP_APM0_REGION6_R1_X_V 0x00000001U #define LP_APM0_REGION6_R1_X_S 4 /** LP_APM0_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_W (BIT(5)) #define LP_APM0_REGION6_R1_W_M (LP_APM0_REGION6_R1_W_V << LP_APM0_REGION6_R1_W_S) #define LP_APM0_REGION6_R1_W_V 0x00000001U #define LP_APM0_REGION6_R1_W_S 5 /** LP_APM0_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM0_REGION6_R1_R (BIT(6)) #define LP_APM0_REGION6_R1_R_M (LP_APM0_REGION6_R1_R_V << LP_APM0_REGION6_R1_R_S) #define LP_APM0_REGION6_R1_R_V 0x00000001U #define LP_APM0_REGION6_R1_R_S 6 /** LP_APM0_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_X (BIT(8)) #define LP_APM0_REGION6_R2_X_M (LP_APM0_REGION6_R2_X_V << LP_APM0_REGION6_R2_X_S) #define LP_APM0_REGION6_R2_X_V 0x00000001U #define LP_APM0_REGION6_R2_X_S 8 /** LP_APM0_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_W (BIT(9)) #define LP_APM0_REGION6_R2_W_M (LP_APM0_REGION6_R2_W_V << LP_APM0_REGION6_R2_W_S) #define LP_APM0_REGION6_R2_W_V 0x00000001U #define LP_APM0_REGION6_R2_W_S 9 /** LP_APM0_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM0_REGION6_R2_R (BIT(10)) #define LP_APM0_REGION6_R2_R_M (LP_APM0_REGION6_R2_R_V << LP_APM0_REGION6_R2_R_S) #define LP_APM0_REGION6_R2_R_V 0x00000001U #define LP_APM0_REGION6_R2_R_S 10 /** LP_APM0_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM0_REGION6_ADDR_START_REG, LP_APM0_REGION6_ADDR_END_REG and + * LP_APM0_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION6_LOCK (BIT(11)) #define LP_APM0_REGION6_LOCK_M (LP_APM0_REGION6_LOCK_V << LP_APM0_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_START_REG (DR_REG_LP_APM0_BASE + 0x58) /** LP_APM0_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7 + * Configures the start address of region 7. */ #define LP_APM0_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_START_M (LP_APM0_REGION7_ADDR_START_V << LP_APM0_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM0_REGION7_ADDR_END_REG (DR_REG_LP_APM0_BASE + 0x5c) /** LP_APM0_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7 + * Configures the end address of region 7. */ #define LP_APM0_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM0_REGION7_ADDR_END_M (LP_APM0_REGION7_ADDR_END_V << LP_APM0_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM0_REGION7_ADDR_END_S 0 /** LP_APM0_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM0_REGION7_ATTR_REG (DR_REG_LP_APM0_BASE + 0x60) /** LP_APM0_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_X (BIT(0)) #define LP_APM0_REGION7_R0_X_M (LP_APM0_REGION7_R0_X_V << LP_APM0_REGION7_R0_X_S) #define LP_APM0_REGION7_R0_X_V 0x00000001U #define LP_APM0_REGION7_R0_X_S 0 /** LP_APM0_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_W (BIT(1)) #define LP_APM0_REGION7_R0_W_M (LP_APM0_REGION7_R0_W_V << LP_APM0_REGION7_R0_W_S) #define LP_APM0_REGION7_R0_W_V 0x00000001U #define LP_APM0_REGION7_R0_W_S 1 /** LP_APM0_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM0_REGION7_R0_R (BIT(2)) #define LP_APM0_REGION7_R0_R_M (LP_APM0_REGION7_R0_R_V << LP_APM0_REGION7_R0_R_S) #define LP_APM0_REGION7_R0_R_V 0x00000001U #define LP_APM0_REGION7_R0_R_S 2 /** LP_APM0_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_X (BIT(4)) #define LP_APM0_REGION7_R1_X_M (LP_APM0_REGION7_R1_X_V << LP_APM0_REGION7_R1_X_S) #define LP_APM0_REGION7_R1_X_V 0x00000001U #define LP_APM0_REGION7_R1_X_S 4 /** LP_APM0_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_W (BIT(5)) #define LP_APM0_REGION7_R1_W_M (LP_APM0_REGION7_R1_W_V << LP_APM0_REGION7_R1_W_S) #define LP_APM0_REGION7_R1_W_V 0x00000001U #define LP_APM0_REGION7_R1_W_S 5 /** LP_APM0_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM0_REGION7_R1_R (BIT(6)) #define LP_APM0_REGION7_R1_R_M (LP_APM0_REGION7_R1_R_V << LP_APM0_REGION7_R1_R_S) #define LP_APM0_REGION7_R1_R_V 0x00000001U #define LP_APM0_REGION7_R1_R_S 6 /** LP_APM0_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_X (BIT(8)) #define LP_APM0_REGION7_R2_X_M (LP_APM0_REGION7_R2_X_V << LP_APM0_REGION7_R2_X_S) #define LP_APM0_REGION7_R2_X_V 0x00000001U #define LP_APM0_REGION7_R2_X_S 8 /** LP_APM0_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_W (BIT(9)) #define LP_APM0_REGION7_R2_W_M (LP_APM0_REGION7_R2_W_V << LP_APM0_REGION7_R2_W_S) #define LP_APM0_REGION7_R2_W_V 0x00000001U #define LP_APM0_REGION7_R2_W_S 9 /** LP_APM0_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM0_REGION7_R2_R (BIT(10)) #define LP_APM0_REGION7_R2_R_M (LP_APM0_REGION7_R2_R_V << LP_APM0_REGION7_R2_R_S) #define LP_APM0_REGION7_R2_R_V 0x00000001U #define LP_APM0_REGION7_R2_R_S 10 /** LP_APM0_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM0_REGION7_ADDR_START_REG, LP_APM0_REGION7_ADDR_END_REG and + * LP_APM0_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM0_REGION7_LOCK (BIT(11)) #define LP_APM0_REGION7_LOCK_M (LP_APM0_REGION7_LOCK_V << LP_APM0_REGION7_LOCK_S) @@ -818,11 +850,11 @@ extern "C" { #define LP_APM0_REGION7_LOCK_S 11 /** LP_APM0_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM0_FUNC_CTRL_REG (DR_REG_LP_APM0_BASE + 0xc4) /** LP_APM0_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ #define LP_APM0_M0_FUNC_EN (BIT(0)) #define LP_APM0_M0_FUNC_EN_M (LP_APM0_M0_FUNC_EN_V << LP_APM0_M0_FUNC_EN_S) @@ -830,13 +862,13 @@ extern "C" { #define LP_APM0_M0_FUNC_EN_S 0 /** LP_APM0_M0_STATUS_REG register - * M0 status register + * LP_APM0_CTRL M0 status register */ #define LP_APM0_M0_STATUS_REG (DR_REG_LP_APM0_BASE + 0xc8) /** LP_APM0_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM0_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM0_M0_EXCEPTION_STATUS_M (LP_APM0_M0_EXCEPTION_STATUS_V << LP_APM0_M0_EXCEPTION_STATUS_S) @@ -844,11 +876,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_S 0 /** LP_APM0_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ #define LP_APM0_M0_STATUS_CLR_REG (DR_REG_LP_APM0_BASE + 0xcc) /** LP_APM0_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ #define LP_APM0_M0_EXCEPTION_STATUS_CLR (BIT(0)) #define LP_APM0_M0_EXCEPTION_STATUS_CLR_M (LP_APM0_M0_EXCEPTION_STATUS_CLR_V << LP_APM0_M0_EXCEPTION_STATUS_CLR_S) @@ -856,25 +888,25 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM0_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM0_BASE + 0xd0) /** LP_APM0_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ #define LP_APM0_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_M (LP_APM0_M0_EXCEPTION_REGION_V << LP_APM0_M0_EXCEPTION_REGION_S) #define LP_APM0_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM0_M0_EXCEPTION_REGION_S 0 /** LP_APM0_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_MODE 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_M (LP_APM0_M0_EXCEPTION_MODE_V << LP_APM0_M0_EXCEPTION_MODE_S) #define LP_APM0_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM0_M0_EXCEPTION_MODE_S 16 /** LP_APM0_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ID 0x0000001FU #define LP_APM0_M0_EXCEPTION_ID_M (LP_APM0_M0_EXCEPTION_ID_V << LP_APM0_M0_EXCEPTION_ID_S) @@ -882,11 +914,11 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ID_S 18 /** LP_APM0_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ #define LP_APM0_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM0_BASE + 0xd4) /** LP_APM0_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ #define LP_APM0_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM0_M0_EXCEPTION_ADDR_M (LP_APM0_M0_EXCEPTION_ADDR_V << LP_APM0_M0_EXCEPTION_ADDR_S) @@ -894,13 +926,13 @@ extern "C" { #define LP_APM0_M0_EXCEPTION_ADDR_S 0 /** LP_APM0_INT_EN_REG register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ #define LP_APM0_INT_EN_REG (DR_REG_LP_APM0_BASE + 0xd8) /** LP_APM0_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM0_M0_APM_INT_EN (BIT(0)) #define LP_APM0_M0_APM_INT_EN_M (LP_APM0_M0_APM_INT_EN_V << LP_APM0_M0_APM_INT_EN_S) @@ -913,8 +945,8 @@ extern "C" { #define LP_APM0_CLOCK_GATE_REG (DR_REG_LP_APM0_BASE + 0xdc) /** LP_APM0_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM0_CLK_EN (BIT(0)) #define LP_APM0_CLK_EN_M (LP_APM0_CLK_EN_V << LP_APM0_CLK_EN_S) @@ -926,7 +958,7 @@ extern "C" { */ #define LP_APM0_DATE_REG (DR_REG_LP_APM0_BASE + 0x7fc) /** LP_APM0_DATE : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ #define LP_APM0_DATE 0x0FFFFFFFU #define LP_APM0_DATE_M (LP_APM0_DATE_V << LP_APM0_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm0_struct.h b/components/soc/esp32c5/register/soc/lp_apm0_struct.h index 542cbede30..bc09871187 100644 --- a/components/soc/esp32c5/register/soc/lp_apm0_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm0_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n(0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm0_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm0_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE2 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM0_REGIONn_ADDR_START_REG, LP_APM0_REGIONn_ADDR_END_REG and + * LP_APM0_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,15 +109,13 @@ typedef union { uint32_t val; } lp_apm0_regionn_attr_reg_t; - -/** Group: APM function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM0_CTRL M0. */ uint32_t m0_func_en:1; uint32_t reserved_1:31; @@ -126,16 +124,16 @@ typedef union { } lp_apm0_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM0_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -143,15 +141,13 @@ typedef union { uint32_t val; } lp_apm0_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM0_CTRL M0 status clear register */ typedef union { struct { /** m0_exception_status_clr : WT; bitpos: [0]; default: 0; - * Configures to clear exception status + * Configures to clear exception status. */ uint32_t m0_exception_status_clr:1; uint32_t reserved_1:31; @@ -159,24 +155,22 @@ typedef union { uint32_t val; } lp_apm0_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -184,15 +178,13 @@ typedef union { uint32_t val; } lp_apm0_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM0_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; @@ -200,16 +192,16 @@ typedef union { } lp_apm0_m0_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM0_CTRL interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures APM M0 interrupt enable. - * 0: disable - * 1: enable + * Configures to enable LP_APM0_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; uint32_t reserved_1:31; @@ -218,7 +210,7 @@ typedef union { } lp_apm0_int_en_reg_t; -/** Group: Clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -226,8 +218,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -236,14 +228,14 @@ typedef union { } lp_apm0_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 35725664; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c5/register/soc/lp_apm_reg.h b/components/soc/esp32c5/register/soc/lp_apm_reg.h index 9e4e42c55e..2a91284eca 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_reg.h +++ b/components/soc/esp32c5/register/soc/lp_apm_reg.h @@ -12,13 +12,13 @@ extern "C" { #endif /** LP_APM_REGION_FILTER_EN_REG register - * Region filter enable register + * Region enable register */ #define LP_APM_REGION_FILTER_EN_REG (DR_REG_LP_APM_BASE + 0x0) /** LP_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ #define LP_APM_REGION_FILTER_EN 0x000000FFU #define LP_APM_REGION_FILTER_EN_M (LP_APM_REGION_FILTER_EN_V << LP_APM_REGION_FILTER_EN_S) @@ -30,7 +30,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4) /** LP_APM_REGION0_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 0. + * Configures the start address of region 0. */ #define LP_APM_REGION0_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_START_M (LP_APM_REGION0_ADDR_START_V << LP_APM_REGION0_ADDR_START_S) @@ -42,7 +42,7 @@ extern "C" { */ #define LP_APM_REGION0_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x8) /** LP_APM_REGION0_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 0. + * Configures the end address of region 0. */ #define LP_APM_REGION0_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION0_ADDR_END_M (LP_APM_REGION0_ADDR_END_V << LP_APM_REGION0_ADDR_END_S) @@ -50,74 +50,78 @@ extern "C" { #define LP_APM_REGION0_ADDR_END_S 0 /** LP_APM_REGION0_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION0_ATTR_REG (DR_REG_LP_APM_BASE + 0xc) /** LP_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 0. + * Configures the execution permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_X (BIT(0)) #define LP_APM_REGION0_R0_X_M (LP_APM_REGION0_R0_X_V << LP_APM_REGION0_R0_X_S) #define LP_APM_REGION0_R0_X_V 0x00000001U #define LP_APM_REGION0_R0_X_S 0 /** LP_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 0. + * Configures the write permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_W (BIT(1)) #define LP_APM_REGION0_R0_W_M (LP_APM_REGION0_R0_W_V << LP_APM_REGION0_R0_W_S) #define LP_APM_REGION0_R0_W_V 0x00000001U #define LP_APM_REGION0_R0_W_S 1 /** LP_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 0. + * Configures the read permission in region 0 in REE0 mode. */ #define LP_APM_REGION0_R0_R (BIT(2)) #define LP_APM_REGION0_R0_R_M (LP_APM_REGION0_R0_R_V << LP_APM_REGION0_R0_R_S) #define LP_APM_REGION0_R0_R_V 0x00000001U #define LP_APM_REGION0_R0_R_S 2 /** LP_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_X (BIT(4)) #define LP_APM_REGION0_R1_X_M (LP_APM_REGION0_R1_X_V << LP_APM_REGION0_R1_X_S) #define LP_APM_REGION0_R1_X_V 0x00000001U #define LP_APM_REGION0_R1_X_S 4 /** LP_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 0. + * Configures the write permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_W (BIT(5)) #define LP_APM_REGION0_R1_W_M (LP_APM_REGION0_R1_W_V << LP_APM_REGION0_R1_W_S) #define LP_APM_REGION0_R1_W_V 0x00000001U #define LP_APM_REGION0_R1_W_S 5 /** LP_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 0. + * Configures the read permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R1_R (BIT(6)) #define LP_APM_REGION0_R1_R_M (LP_APM_REGION0_R1_R_V << LP_APM_REGION0_R1_R_S) #define LP_APM_REGION0_R1_R_V 0x00000001U #define LP_APM_REGION0_R1_R_S 6 /** LP_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 0. + * Configures the execution permission in region 0 in REE1 mode. */ #define LP_APM_REGION0_R2_X (BIT(8)) #define LP_APM_REGION0_R2_X_M (LP_APM_REGION0_R2_X_V << LP_APM_REGION0_R2_X_S) #define LP_APM_REGION0_R2_X_V 0x00000001U #define LP_APM_REGION0_R2_X_S 8 /** LP_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 0. + * Configures the write permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_W (BIT(9)) #define LP_APM_REGION0_R2_W_M (LP_APM_REGION0_R2_W_V << LP_APM_REGION0_R2_W_S) #define LP_APM_REGION0_R2_W_V 0x00000001U #define LP_APM_REGION0_R2_W_S 9 /** LP_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 0. + * Configures the read permission in region 0 in REE2 mode. */ #define LP_APM_REGION0_R2_R (BIT(10)) #define LP_APM_REGION0_R2_R_M (LP_APM_REGION0_R2_R_V << LP_APM_REGION0_R2_R_S) #define LP_APM_REGION0_R2_R_V 0x00000001U #define LP_APM_REGION0_R2_R_S 10 /** LP_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 0 configuration registers + * (LP_APM_REGION0_ADDR_START_REG, LP_APM_REGION0_ADDR_END_REG and + * LP_APM_REGION0_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION0_LOCK (BIT(11)) #define LP_APM_REGION0_LOCK_M (LP_APM_REGION0_LOCK_V << LP_APM_REGION0_LOCK_S) @@ -129,7 +133,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x10) /** LP_APM_REGION1_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 1. + * Configures the start address of region 1. */ #define LP_APM_REGION1_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_START_M (LP_APM_REGION1_ADDR_START_V << LP_APM_REGION1_ADDR_START_S) @@ -141,7 +145,7 @@ extern "C" { */ #define LP_APM_REGION1_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x14) /** LP_APM_REGION1_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 1. + * Configures the end address of region 1. */ #define LP_APM_REGION1_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION1_ADDR_END_M (LP_APM_REGION1_ADDR_END_V << LP_APM_REGION1_ADDR_END_S) @@ -149,74 +153,78 @@ extern "C" { #define LP_APM_REGION1_ADDR_END_S 0 /** LP_APM_REGION1_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION1_ATTR_REG (DR_REG_LP_APM_BASE + 0x18) /** LP_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 1. + * Configures the execution permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_X (BIT(0)) #define LP_APM_REGION1_R0_X_M (LP_APM_REGION1_R0_X_V << LP_APM_REGION1_R0_X_S) #define LP_APM_REGION1_R0_X_V 0x00000001U #define LP_APM_REGION1_R0_X_S 0 /** LP_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 1. + * Configures the write permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_W (BIT(1)) #define LP_APM_REGION1_R0_W_M (LP_APM_REGION1_R0_W_V << LP_APM_REGION1_R0_W_S) #define LP_APM_REGION1_R0_W_V 0x00000001U #define LP_APM_REGION1_R0_W_S 1 /** LP_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 1. + * Configures the read permission in region 1 in REE0 mode. */ #define LP_APM_REGION1_R0_R (BIT(2)) #define LP_APM_REGION1_R0_R_M (LP_APM_REGION1_R0_R_V << LP_APM_REGION1_R0_R_S) #define LP_APM_REGION1_R0_R_V 0x00000001U #define LP_APM_REGION1_R0_R_S 2 /** LP_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_X (BIT(4)) #define LP_APM_REGION1_R1_X_M (LP_APM_REGION1_R1_X_V << LP_APM_REGION1_R1_X_S) #define LP_APM_REGION1_R1_X_V 0x00000001U #define LP_APM_REGION1_R1_X_S 4 /** LP_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 1. + * Configures the write permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_W (BIT(5)) #define LP_APM_REGION1_R1_W_M (LP_APM_REGION1_R1_W_V << LP_APM_REGION1_R1_W_S) #define LP_APM_REGION1_R1_W_V 0x00000001U #define LP_APM_REGION1_R1_W_S 5 /** LP_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 1. + * Configures the read permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R1_R (BIT(6)) #define LP_APM_REGION1_R1_R_M (LP_APM_REGION1_R1_R_V << LP_APM_REGION1_R1_R_S) #define LP_APM_REGION1_R1_R_V 0x00000001U #define LP_APM_REGION1_R1_R_S 6 /** LP_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 1. + * Configures the execution permission in region 1 in REE1 mode. */ #define LP_APM_REGION1_R2_X (BIT(8)) #define LP_APM_REGION1_R2_X_M (LP_APM_REGION1_R2_X_V << LP_APM_REGION1_R2_X_S) #define LP_APM_REGION1_R2_X_V 0x00000001U #define LP_APM_REGION1_R2_X_S 8 /** LP_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 1. + * Configures the write permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_W (BIT(9)) #define LP_APM_REGION1_R2_W_M (LP_APM_REGION1_R2_W_V << LP_APM_REGION1_R2_W_S) #define LP_APM_REGION1_R2_W_V 0x00000001U #define LP_APM_REGION1_R2_W_S 9 /** LP_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 1. + * Configures the read permission in region 1 in REE2 mode. */ #define LP_APM_REGION1_R2_R (BIT(10)) #define LP_APM_REGION1_R2_R_M (LP_APM_REGION1_R2_R_V << LP_APM_REGION1_R2_R_S) #define LP_APM_REGION1_R2_R_V 0x00000001U #define LP_APM_REGION1_R2_R_S 10 /** LP_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 1 configuration registers + * (LP_APM_REGION1_ADDR_START_REG, LP_APM_REGION1_ADDR_END_REG and + * LP_APM_REGION1_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION1_LOCK (BIT(11)) #define LP_APM_REGION1_LOCK_M (LP_APM_REGION1_LOCK_V << LP_APM_REGION1_LOCK_S) @@ -228,7 +236,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x1c) /** LP_APM_REGION2_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 2. + * Configures the start address of region 2. */ #define LP_APM_REGION2_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_START_M (LP_APM_REGION2_ADDR_START_V << LP_APM_REGION2_ADDR_START_S) @@ -240,7 +248,7 @@ extern "C" { */ #define LP_APM_REGION2_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x20) /** LP_APM_REGION2_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 2. + * Configures the end address of region 2. */ #define LP_APM_REGION2_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION2_ADDR_END_M (LP_APM_REGION2_ADDR_END_V << LP_APM_REGION2_ADDR_END_S) @@ -248,74 +256,78 @@ extern "C" { #define LP_APM_REGION2_ADDR_END_S 0 /** LP_APM_REGION2_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION2_ATTR_REG (DR_REG_LP_APM_BASE + 0x24) /** LP_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 2. + * Configures the execution permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_X (BIT(0)) #define LP_APM_REGION2_R0_X_M (LP_APM_REGION2_R0_X_V << LP_APM_REGION2_R0_X_S) #define LP_APM_REGION2_R0_X_V 0x00000001U #define LP_APM_REGION2_R0_X_S 0 /** LP_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 2. + * Configures the write permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_W (BIT(1)) #define LP_APM_REGION2_R0_W_M (LP_APM_REGION2_R0_W_V << LP_APM_REGION2_R0_W_S) #define LP_APM_REGION2_R0_W_V 0x00000001U #define LP_APM_REGION2_R0_W_S 1 /** LP_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 2. + * Configures the read permission in region 2 in REE0 mode. */ #define LP_APM_REGION2_R0_R (BIT(2)) #define LP_APM_REGION2_R0_R_M (LP_APM_REGION2_R0_R_V << LP_APM_REGION2_R0_R_S) #define LP_APM_REGION2_R0_R_V 0x00000001U #define LP_APM_REGION2_R0_R_S 2 /** LP_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_X (BIT(4)) #define LP_APM_REGION2_R1_X_M (LP_APM_REGION2_R1_X_V << LP_APM_REGION2_R1_X_S) #define LP_APM_REGION2_R1_X_V 0x00000001U #define LP_APM_REGION2_R1_X_S 4 /** LP_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 2. + * Configures the write permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_W (BIT(5)) #define LP_APM_REGION2_R1_W_M (LP_APM_REGION2_R1_W_V << LP_APM_REGION2_R1_W_S) #define LP_APM_REGION2_R1_W_V 0x00000001U #define LP_APM_REGION2_R1_W_S 5 /** LP_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 2. + * Configures the read permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R1_R (BIT(6)) #define LP_APM_REGION2_R1_R_M (LP_APM_REGION2_R1_R_V << LP_APM_REGION2_R1_R_S) #define LP_APM_REGION2_R1_R_V 0x00000001U #define LP_APM_REGION2_R1_R_S 6 /** LP_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 2. + * Configures the execution permission in region 2 in REE1 mode. */ #define LP_APM_REGION2_R2_X (BIT(8)) #define LP_APM_REGION2_R2_X_M (LP_APM_REGION2_R2_X_V << LP_APM_REGION2_R2_X_S) #define LP_APM_REGION2_R2_X_V 0x00000001U #define LP_APM_REGION2_R2_X_S 8 /** LP_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 2. + * Configures the write permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_W (BIT(9)) #define LP_APM_REGION2_R2_W_M (LP_APM_REGION2_R2_W_V << LP_APM_REGION2_R2_W_S) #define LP_APM_REGION2_R2_W_V 0x00000001U #define LP_APM_REGION2_R2_W_S 9 /** LP_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 2. + * Configures the read permission in region 2 in REE2 mode. */ #define LP_APM_REGION2_R2_R (BIT(10)) #define LP_APM_REGION2_R2_R_M (LP_APM_REGION2_R2_R_V << LP_APM_REGION2_R2_R_S) #define LP_APM_REGION2_R2_R_V 0x00000001U #define LP_APM_REGION2_R2_R_S 10 /** LP_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 2 configuration registers + * (LP_APM_REGION2_ADDR_START_REG, LP_APM_REGION2_ADDR_END_REG and + * LP_APM_REGION2_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION2_LOCK (BIT(11)) #define LP_APM_REGION2_LOCK_M (LP_APM_REGION2_LOCK_V << LP_APM_REGION2_LOCK_S) @@ -327,7 +339,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x28) /** LP_APM_REGION3_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 3. + * Configures the start address of region 3. */ #define LP_APM_REGION3_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_START_M (LP_APM_REGION3_ADDR_START_V << LP_APM_REGION3_ADDR_START_S) @@ -339,7 +351,7 @@ extern "C" { */ #define LP_APM_REGION3_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x2c) /** LP_APM_REGION3_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 3. + * Configures the end address of region 3. */ #define LP_APM_REGION3_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION3_ADDR_END_M (LP_APM_REGION3_ADDR_END_V << LP_APM_REGION3_ADDR_END_S) @@ -347,74 +359,78 @@ extern "C" { #define LP_APM_REGION3_ADDR_END_S 0 /** LP_APM_REGION3_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION3_ATTR_REG (DR_REG_LP_APM_BASE + 0x30) /** LP_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 3. + * Configures the execution permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_X (BIT(0)) #define LP_APM_REGION3_R0_X_M (LP_APM_REGION3_R0_X_V << LP_APM_REGION3_R0_X_S) #define LP_APM_REGION3_R0_X_V 0x00000001U #define LP_APM_REGION3_R0_X_S 0 /** LP_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 3. + * Configures the write permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_W (BIT(1)) #define LP_APM_REGION3_R0_W_M (LP_APM_REGION3_R0_W_V << LP_APM_REGION3_R0_W_S) #define LP_APM_REGION3_R0_W_V 0x00000001U #define LP_APM_REGION3_R0_W_S 1 /** LP_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 3. + * Configures the read permission in region 3 in REE0 mode. */ #define LP_APM_REGION3_R0_R (BIT(2)) #define LP_APM_REGION3_R0_R_M (LP_APM_REGION3_R0_R_V << LP_APM_REGION3_R0_R_S) #define LP_APM_REGION3_R0_R_V 0x00000001U #define LP_APM_REGION3_R0_R_S 2 /** LP_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_X (BIT(4)) #define LP_APM_REGION3_R1_X_M (LP_APM_REGION3_R1_X_V << LP_APM_REGION3_R1_X_S) #define LP_APM_REGION3_R1_X_V 0x00000001U #define LP_APM_REGION3_R1_X_S 4 /** LP_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 3. + * Configures the write permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_W (BIT(5)) #define LP_APM_REGION3_R1_W_M (LP_APM_REGION3_R1_W_V << LP_APM_REGION3_R1_W_S) #define LP_APM_REGION3_R1_W_V 0x00000001U #define LP_APM_REGION3_R1_W_S 5 /** LP_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 3. + * Configures the read permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R1_R (BIT(6)) #define LP_APM_REGION3_R1_R_M (LP_APM_REGION3_R1_R_V << LP_APM_REGION3_R1_R_S) #define LP_APM_REGION3_R1_R_V 0x00000001U #define LP_APM_REGION3_R1_R_S 6 /** LP_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 3. + * Configures the execution permission in region 3 in REE1 mode. */ #define LP_APM_REGION3_R2_X (BIT(8)) #define LP_APM_REGION3_R2_X_M (LP_APM_REGION3_R2_X_V << LP_APM_REGION3_R2_X_S) #define LP_APM_REGION3_R2_X_V 0x00000001U #define LP_APM_REGION3_R2_X_S 8 /** LP_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 3. + * Configures the write permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_W (BIT(9)) #define LP_APM_REGION3_R2_W_M (LP_APM_REGION3_R2_W_V << LP_APM_REGION3_R2_W_S) #define LP_APM_REGION3_R2_W_V 0x00000001U #define LP_APM_REGION3_R2_W_S 9 /** LP_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 3. + * Configures the read permission in region 3 in REE2 mode. */ #define LP_APM_REGION3_R2_R (BIT(10)) #define LP_APM_REGION3_R2_R_M (LP_APM_REGION3_R2_R_V << LP_APM_REGION3_R2_R_S) #define LP_APM_REGION3_R2_R_V 0x00000001U #define LP_APM_REGION3_R2_R_S 10 /** LP_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 3 configuration registers + * (LP_APM_REGION3_ADDR_START_REG, LP_APM_REGION3_ADDR_END_REG and + * LP_APM_REGION3_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION3_LOCK (BIT(11)) #define LP_APM_REGION3_LOCK_M (LP_APM_REGION3_LOCK_V << LP_APM_REGION3_LOCK_S) @@ -426,7 +442,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x34) /** LP_APM_REGION4_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 4. + * Configures the start address of region 4. */ #define LP_APM_REGION4_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_START_M (LP_APM_REGION4_ADDR_START_V << LP_APM_REGION4_ADDR_START_S) @@ -438,7 +454,7 @@ extern "C" { */ #define LP_APM_REGION4_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x38) /** LP_APM_REGION4_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 4. + * Configures the end address of region 4. */ #define LP_APM_REGION4_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION4_ADDR_END_M (LP_APM_REGION4_ADDR_END_V << LP_APM_REGION4_ADDR_END_S) @@ -446,74 +462,78 @@ extern "C" { #define LP_APM_REGION4_ADDR_END_S 0 /** LP_APM_REGION4_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION4_ATTR_REG (DR_REG_LP_APM_BASE + 0x3c) /** LP_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 4. + * Configures the execution permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_X (BIT(0)) #define LP_APM_REGION4_R0_X_M (LP_APM_REGION4_R0_X_V << LP_APM_REGION4_R0_X_S) #define LP_APM_REGION4_R0_X_V 0x00000001U #define LP_APM_REGION4_R0_X_S 0 /** LP_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 4. + * Configures the write permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_W (BIT(1)) #define LP_APM_REGION4_R0_W_M (LP_APM_REGION4_R0_W_V << LP_APM_REGION4_R0_W_S) #define LP_APM_REGION4_R0_W_V 0x00000001U #define LP_APM_REGION4_R0_W_S 1 /** LP_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 4. + * Configures the read permission in region 4 in REE0 mode. */ #define LP_APM_REGION4_R0_R (BIT(2)) #define LP_APM_REGION4_R0_R_M (LP_APM_REGION4_R0_R_V << LP_APM_REGION4_R0_R_S) #define LP_APM_REGION4_R0_R_V 0x00000001U #define LP_APM_REGION4_R0_R_S 2 /** LP_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_X (BIT(4)) #define LP_APM_REGION4_R1_X_M (LP_APM_REGION4_R1_X_V << LP_APM_REGION4_R1_X_S) #define LP_APM_REGION4_R1_X_V 0x00000001U #define LP_APM_REGION4_R1_X_S 4 /** LP_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 4. + * Configures the write permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_W (BIT(5)) #define LP_APM_REGION4_R1_W_M (LP_APM_REGION4_R1_W_V << LP_APM_REGION4_R1_W_S) #define LP_APM_REGION4_R1_W_V 0x00000001U #define LP_APM_REGION4_R1_W_S 5 /** LP_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 4. + * Configures the read permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R1_R (BIT(6)) #define LP_APM_REGION4_R1_R_M (LP_APM_REGION4_R1_R_V << LP_APM_REGION4_R1_R_S) #define LP_APM_REGION4_R1_R_V 0x00000001U #define LP_APM_REGION4_R1_R_S 6 /** LP_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 4. + * Configures the execution permission in region 4 in REE1 mode. */ #define LP_APM_REGION4_R2_X (BIT(8)) #define LP_APM_REGION4_R2_X_M (LP_APM_REGION4_R2_X_V << LP_APM_REGION4_R2_X_S) #define LP_APM_REGION4_R2_X_V 0x00000001U #define LP_APM_REGION4_R2_X_S 8 /** LP_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 4. + * Configures the write permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_W (BIT(9)) #define LP_APM_REGION4_R2_W_M (LP_APM_REGION4_R2_W_V << LP_APM_REGION4_R2_W_S) #define LP_APM_REGION4_R2_W_V 0x00000001U #define LP_APM_REGION4_R2_W_S 9 /** LP_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 4. + * Configures the read permission in region 4 in REE2 mode. */ #define LP_APM_REGION4_R2_R (BIT(10)) #define LP_APM_REGION4_R2_R_M (LP_APM_REGION4_R2_R_V << LP_APM_REGION4_R2_R_S) #define LP_APM_REGION4_R2_R_V 0x00000001U #define LP_APM_REGION4_R2_R_S 10 /** LP_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 4 configuration registers + * (LP_APM_REGION4_ADDR_START_REG, LP_APM_REGION4_ADDR_END_REG and + * LP_APM_REGION4_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION4_LOCK (BIT(11)) #define LP_APM_REGION4_LOCK_M (LP_APM_REGION4_LOCK_V << LP_APM_REGION4_LOCK_S) @@ -525,7 +545,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x40) /** LP_APM_REGION5_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 5. + * Configures the start address of region 5. */ #define LP_APM_REGION5_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_START_M (LP_APM_REGION5_ADDR_START_V << LP_APM_REGION5_ADDR_START_S) @@ -537,7 +557,7 @@ extern "C" { */ #define LP_APM_REGION5_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x44) /** LP_APM_REGION5_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 5. + * Configures the end address of region 5. */ #define LP_APM_REGION5_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION5_ADDR_END_M (LP_APM_REGION5_ADDR_END_V << LP_APM_REGION5_ADDR_END_S) @@ -545,74 +565,78 @@ extern "C" { #define LP_APM_REGION5_ADDR_END_S 0 /** LP_APM_REGION5_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION5_ATTR_REG (DR_REG_LP_APM_BASE + 0x48) /** LP_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 5. + * Configures the execution permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_X (BIT(0)) #define LP_APM_REGION5_R0_X_M (LP_APM_REGION5_R0_X_V << LP_APM_REGION5_R0_X_S) #define LP_APM_REGION5_R0_X_V 0x00000001U #define LP_APM_REGION5_R0_X_S 0 /** LP_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 5. + * Configures the write permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_W (BIT(1)) #define LP_APM_REGION5_R0_W_M (LP_APM_REGION5_R0_W_V << LP_APM_REGION5_R0_W_S) #define LP_APM_REGION5_R0_W_V 0x00000001U #define LP_APM_REGION5_R0_W_S 1 /** LP_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 5. + * Configures the read permission in region 5 in REE0 mode. */ #define LP_APM_REGION5_R0_R (BIT(2)) #define LP_APM_REGION5_R0_R_M (LP_APM_REGION5_R0_R_V << LP_APM_REGION5_R0_R_S) #define LP_APM_REGION5_R0_R_V 0x00000001U #define LP_APM_REGION5_R0_R_S 2 /** LP_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_X (BIT(4)) #define LP_APM_REGION5_R1_X_M (LP_APM_REGION5_R1_X_V << LP_APM_REGION5_R1_X_S) #define LP_APM_REGION5_R1_X_V 0x00000001U #define LP_APM_REGION5_R1_X_S 4 /** LP_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 5. + * Configures the write permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_W (BIT(5)) #define LP_APM_REGION5_R1_W_M (LP_APM_REGION5_R1_W_V << LP_APM_REGION5_R1_W_S) #define LP_APM_REGION5_R1_W_V 0x00000001U #define LP_APM_REGION5_R1_W_S 5 /** LP_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 5. + * Configures the read permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R1_R (BIT(6)) #define LP_APM_REGION5_R1_R_M (LP_APM_REGION5_R1_R_V << LP_APM_REGION5_R1_R_S) #define LP_APM_REGION5_R1_R_V 0x00000001U #define LP_APM_REGION5_R1_R_S 6 /** LP_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 5. + * Configures the execution permission in region 5 in REE1 mode. */ #define LP_APM_REGION5_R2_X (BIT(8)) #define LP_APM_REGION5_R2_X_M (LP_APM_REGION5_R2_X_V << LP_APM_REGION5_R2_X_S) #define LP_APM_REGION5_R2_X_V 0x00000001U #define LP_APM_REGION5_R2_X_S 8 /** LP_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 5. + * Configures the write permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_W (BIT(9)) #define LP_APM_REGION5_R2_W_M (LP_APM_REGION5_R2_W_V << LP_APM_REGION5_R2_W_S) #define LP_APM_REGION5_R2_W_V 0x00000001U #define LP_APM_REGION5_R2_W_S 9 /** LP_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 5. + * Configures the read permission in region 5 in REE2 mode. */ #define LP_APM_REGION5_R2_R (BIT(10)) #define LP_APM_REGION5_R2_R_M (LP_APM_REGION5_R2_R_V << LP_APM_REGION5_R2_R_S) #define LP_APM_REGION5_R2_R_V 0x00000001U #define LP_APM_REGION5_R2_R_S 10 /** LP_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 5 configuration registers + * (LP_APM_REGION5_ADDR_START_REG, LP_APM_REGION5_ADDR_END_REG and + * LP_APM_REGION5_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION5_LOCK (BIT(11)) #define LP_APM_REGION5_LOCK_M (LP_APM_REGION5_LOCK_V << LP_APM_REGION5_LOCK_S) @@ -624,7 +648,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x4c) /** LP_APM_REGION6_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 6. + * Configures the start address of region 6. */ #define LP_APM_REGION6_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_START_M (LP_APM_REGION6_ADDR_START_V << LP_APM_REGION6_ADDR_START_S) @@ -636,7 +660,7 @@ extern "C" { */ #define LP_APM_REGION6_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x50) /** LP_APM_REGION6_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 6. + * Configures the end address of region 6. */ #define LP_APM_REGION6_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION6_ADDR_END_M (LP_APM_REGION6_ADDR_END_V << LP_APM_REGION6_ADDR_END_S) @@ -644,74 +668,78 @@ extern "C" { #define LP_APM_REGION6_ADDR_END_S 0 /** LP_APM_REGION6_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION6_ATTR_REG (DR_REG_LP_APM_BASE + 0x54) /** LP_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 6. + * Configures the execution permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_X (BIT(0)) #define LP_APM_REGION6_R0_X_M (LP_APM_REGION6_R0_X_V << LP_APM_REGION6_R0_X_S) #define LP_APM_REGION6_R0_X_V 0x00000001U #define LP_APM_REGION6_R0_X_S 0 /** LP_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 6. + * Configures the write permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_W (BIT(1)) #define LP_APM_REGION6_R0_W_M (LP_APM_REGION6_R0_W_V << LP_APM_REGION6_R0_W_S) #define LP_APM_REGION6_R0_W_V 0x00000001U #define LP_APM_REGION6_R0_W_S 1 /** LP_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 6. + * Configures the read permission in region 6 in REE0 mode. */ #define LP_APM_REGION6_R0_R (BIT(2)) #define LP_APM_REGION6_R0_R_M (LP_APM_REGION6_R0_R_V << LP_APM_REGION6_R0_R_S) #define LP_APM_REGION6_R0_R_V 0x00000001U #define LP_APM_REGION6_R0_R_S 2 /** LP_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_X (BIT(4)) #define LP_APM_REGION6_R1_X_M (LP_APM_REGION6_R1_X_V << LP_APM_REGION6_R1_X_S) #define LP_APM_REGION6_R1_X_V 0x00000001U #define LP_APM_REGION6_R1_X_S 4 /** LP_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 6. + * Configures the write permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_W (BIT(5)) #define LP_APM_REGION6_R1_W_M (LP_APM_REGION6_R1_W_V << LP_APM_REGION6_R1_W_S) #define LP_APM_REGION6_R1_W_V 0x00000001U #define LP_APM_REGION6_R1_W_S 5 /** LP_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 6. + * Configures the read permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R1_R (BIT(6)) #define LP_APM_REGION6_R1_R_M (LP_APM_REGION6_R1_R_V << LP_APM_REGION6_R1_R_S) #define LP_APM_REGION6_R1_R_V 0x00000001U #define LP_APM_REGION6_R1_R_S 6 /** LP_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 6. + * Configures the execution permission in region 6 in REE1 mode. */ #define LP_APM_REGION6_R2_X (BIT(8)) #define LP_APM_REGION6_R2_X_M (LP_APM_REGION6_R2_X_V << LP_APM_REGION6_R2_X_S) #define LP_APM_REGION6_R2_X_V 0x00000001U #define LP_APM_REGION6_R2_X_S 8 /** LP_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 6. + * Configures the write permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_W (BIT(9)) #define LP_APM_REGION6_R2_W_M (LP_APM_REGION6_R2_W_V << LP_APM_REGION6_R2_W_S) #define LP_APM_REGION6_R2_W_V 0x00000001U #define LP_APM_REGION6_R2_W_S 9 /** LP_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 6. + * Configures the read permission in region 6 in REE2 mode. */ #define LP_APM_REGION6_R2_R (BIT(10)) #define LP_APM_REGION6_R2_R_M (LP_APM_REGION6_R2_R_V << LP_APM_REGION6_R2_R_S) #define LP_APM_REGION6_R2_R_V 0x00000001U #define LP_APM_REGION6_R2_R_S 10 /** LP_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 6 configuration registers + * (LP_APM_REGION6_ADDR_START_REG, LP_APM_REGION6_ADDR_END_REG and + * LP_APM_REGION6_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION6_LOCK (BIT(11)) #define LP_APM_REGION6_LOCK_M (LP_APM_REGION6_LOCK_V << LP_APM_REGION6_LOCK_S) @@ -723,7 +751,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_START_REG (DR_REG_LP_APM_BASE + 0x58) /** LP_APM_REGION7_ADDR_START : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region 7. + * Configures the start address of region 7. */ #define LP_APM_REGION7_ADDR_START 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_START_M (LP_APM_REGION7_ADDR_START_V << LP_APM_REGION7_ADDR_START_S) @@ -735,7 +763,7 @@ extern "C" { */ #define LP_APM_REGION7_ADDR_END_REG (DR_REG_LP_APM_BASE + 0x5c) /** LP_APM_REGION7_ADDR_END : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region 7. + * Configures the end address of region 7. */ #define LP_APM_REGION7_ADDR_END 0xFFFFFFFFU #define LP_APM_REGION7_ADDR_END_M (LP_APM_REGION7_ADDR_END_V << LP_APM_REGION7_ADDR_END_S) @@ -743,74 +771,78 @@ extern "C" { #define LP_APM_REGION7_ADDR_END_S 0 /** LP_APM_REGION7_ATTR_REG register - * Region access authority attribute register + * Region access permissions configuration register */ #define LP_APM_REGION7_ATTR_REG (DR_REG_LP_APM_BASE + 0x60) /** LP_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region 7. + * Configures the execution permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_X (BIT(0)) #define LP_APM_REGION7_R0_X_M (LP_APM_REGION7_R0_X_V << LP_APM_REGION7_R0_X_S) #define LP_APM_REGION7_R0_X_V 0x00000001U #define LP_APM_REGION7_R0_X_S 0 /** LP_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region 7. + * Configures the write permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_W (BIT(1)) #define LP_APM_REGION7_R0_W_M (LP_APM_REGION7_R0_W_V << LP_APM_REGION7_R0_W_S) #define LP_APM_REGION7_R0_W_V 0x00000001U #define LP_APM_REGION7_R0_W_S 1 /** LP_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region 7. + * Configures the read permission in region 7 in REE0 mode. */ #define LP_APM_REGION7_R0_R (BIT(2)) #define LP_APM_REGION7_R0_R_M (LP_APM_REGION7_R0_R_V << LP_APM_REGION7_R0_R_S) #define LP_APM_REGION7_R0_R_V 0x00000001U #define LP_APM_REGION7_R0_R_S 2 /** LP_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_X (BIT(4)) #define LP_APM_REGION7_R1_X_M (LP_APM_REGION7_R1_X_V << LP_APM_REGION7_R1_X_S) #define LP_APM_REGION7_R1_X_V 0x00000001U #define LP_APM_REGION7_R1_X_S 4 /** LP_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region 7. + * Configures the write permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_W (BIT(5)) #define LP_APM_REGION7_R1_W_M (LP_APM_REGION7_R1_W_V << LP_APM_REGION7_R1_W_S) #define LP_APM_REGION7_R1_W_V 0x00000001U #define LP_APM_REGION7_R1_W_S 5 /** LP_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region 7. + * Configures the read permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R1_R (BIT(6)) #define LP_APM_REGION7_R1_R_M (LP_APM_REGION7_R1_R_V << LP_APM_REGION7_R1_R_S) #define LP_APM_REGION7_R1_R_V 0x00000001U #define LP_APM_REGION7_R1_R_S 6 /** LP_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region 7. + * Configures the execution permission in region 7 in REE1 mode. */ #define LP_APM_REGION7_R2_X (BIT(8)) #define LP_APM_REGION7_R2_X_M (LP_APM_REGION7_R2_X_V << LP_APM_REGION7_R2_X_S) #define LP_APM_REGION7_R2_X_V 0x00000001U #define LP_APM_REGION7_R2_X_S 8 /** LP_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region 7. + * Configures the write permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_W (BIT(9)) #define LP_APM_REGION7_R2_W_M (LP_APM_REGION7_R2_W_V << LP_APM_REGION7_R2_W_S) #define LP_APM_REGION7_R2_W_V 0x00000001U #define LP_APM_REGION7_R2_W_S 9 /** LP_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region 7. + * Configures the read permission in region 7 in REE2 mode. */ #define LP_APM_REGION7_R2_R (BIT(10)) #define LP_APM_REGION7_R2_R_M (LP_APM_REGION7_R2_R_V << LP_APM_REGION7_R2_R_S) #define LP_APM_REGION7_R2_R_V 0x00000001U #define LP_APM_REGION7_R2_R_S 10 /** LP_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region 7 configuration registers + * (LP_APM_REGION7_ADDR_START_REG, LP_APM_REGION7_ADDR_END_REG and + * LP_APM_REGION7_ATTR_REG). + * 0: Do not lock + * 1: Lock */ #define LP_APM_REGION7_LOCK (BIT(11)) #define LP_APM_REGION7_LOCK_M (LP_APM_REGION7_LOCK_V << LP_APM_REGION7_LOCK_S) @@ -818,18 +850,18 @@ extern "C" { #define LP_APM_REGION7_LOCK_S 11 /** LP_APM_FUNC_CTRL_REG register - * APM function control register + * APM access path permission management register */ #define LP_APM_FUNC_CTRL_REG (DR_REG_LP_APM_BASE + 0xc4) /** LP_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ #define LP_APM_M0_FUNC_EN (BIT(0)) #define LP_APM_M0_FUNC_EN_M (LP_APM_M0_FUNC_EN_V << LP_APM_M0_FUNC_EN_S) #define LP_APM_M0_FUNC_EN_V 0x00000001U #define LP_APM_M0_FUNC_EN_S 0 /** LP_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ #define LP_APM_M1_FUNC_EN (BIT(1)) #define LP_APM_M1_FUNC_EN_M (LP_APM_M1_FUNC_EN_V << LP_APM_M1_FUNC_EN_S) @@ -837,13 +869,13 @@ extern "C" { #define LP_APM_M1_FUNC_EN_S 1 /** LP_APM_M0_STATUS_REG register - * M0 status register + * LP_APM_CTRL M0 status register */ #define LP_APM_M0_STATUS_REG (DR_REG_LP_APM_BASE + 0xc8) /** LP_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M0_EXCEPTION_STATUS 0x00000003U #define LP_APM_M0_EXCEPTION_STATUS_M (LP_APM_M0_EXCEPTION_STATUS_V << LP_APM_M0_EXCEPTION_STATUS_S) @@ -851,7 +883,7 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_S 0 /** LP_APM_M0_STATUS_CLR_REG register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ #define LP_APM_M0_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xcc) /** LP_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -863,25 +895,25 @@ extern "C" { #define LP_APM_M0_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M0_EXCEPTION_INFO0_REG register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xd0) /** LP_APM_M0_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M0_EXCEPTION_REGION 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_M (LP_APM_M0_EXCEPTION_REGION_V << LP_APM_M0_EXCEPTION_REGION_S) #define LP_APM_M0_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M0_EXCEPTION_REGION_S 0 /** LP_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M0_EXCEPTION_MODE 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_M (LP_APM_M0_EXCEPTION_MODE_V << LP_APM_M0_EXCEPTION_MODE_S) #define LP_APM_M0_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M0_EXCEPTION_MODE_S 16 /** LP_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ID 0x0000001FU #define LP_APM_M0_EXCEPTION_ID_M (LP_APM_M0_EXCEPTION_ID_V << LP_APM_M0_EXCEPTION_ID_S) @@ -889,11 +921,11 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ID_S 18 /** LP_APM_M0_EXCEPTION_INFO1_REG register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ #define LP_APM_M0_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xd4) /** LP_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M0_EXCEPTION_ADDR_M (LP_APM_M0_EXCEPTION_ADDR_V << LP_APM_M0_EXCEPTION_ADDR_S) @@ -901,13 +933,13 @@ extern "C" { #define LP_APM_M0_EXCEPTION_ADDR_S 0 /** LP_APM_M1_STATUS_REG register - * M1 status register + * LP_APM_CTRL M1 status register */ #define LP_APM_M1_STATUS_REG (DR_REG_LP_APM_BASE + 0xd8) /** LP_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ #define LP_APM_M1_EXCEPTION_STATUS 0x00000003U #define LP_APM_M1_EXCEPTION_STATUS_M (LP_APM_M1_EXCEPTION_STATUS_V << LP_APM_M1_EXCEPTION_STATUS_S) @@ -915,7 +947,7 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_S 0 /** LP_APM_M1_STATUS_CLR_REG register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ #define LP_APM_M1_STATUS_CLR_REG (DR_REG_LP_APM_BASE + 0xdc) /** LP_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; @@ -927,25 +959,25 @@ extern "C" { #define LP_APM_M1_EXCEPTION_STATUS_CLR_S 0 /** LP_APM_M1_EXCEPTION_INFO0_REG register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO0_REG (DR_REG_LP_APM_BASE + 0xe0) /** LP_APM_M1_EXCEPTION_REGION : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ #define LP_APM_M1_EXCEPTION_REGION 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_M (LP_APM_M1_EXCEPTION_REGION_V << LP_APM_M1_EXCEPTION_REGION_S) #define LP_APM_M1_EXCEPTION_REGION_V 0x000000FFU #define LP_APM_M1_EXCEPTION_REGION_S 0 /** LP_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ #define LP_APM_M1_EXCEPTION_MODE 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_M (LP_APM_M1_EXCEPTION_MODE_V << LP_APM_M1_EXCEPTION_MODE_S) #define LP_APM_M1_EXCEPTION_MODE_V 0x00000003U #define LP_APM_M1_EXCEPTION_MODE_S 16 /** LP_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ID 0x0000001FU #define LP_APM_M1_EXCEPTION_ID_M (LP_APM_M1_EXCEPTION_ID_V << LP_APM_M1_EXCEPTION_ID_S) @@ -953,11 +985,11 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ID_S 18 /** LP_APM_M1_EXCEPTION_INFO1_REG register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ #define LP_APM_M1_EXCEPTION_INFO1_REG (DR_REG_LP_APM_BASE + 0xe4) /** LP_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ #define LP_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU #define LP_APM_M1_EXCEPTION_ADDR_M (LP_APM_M1_EXCEPTION_ADDR_V << LP_APM_M1_EXCEPTION_ADDR_S) @@ -965,22 +997,22 @@ extern "C" { #define LP_APM_M1_EXCEPTION_ADDR_S 0 /** LP_APM_INT_EN_REG register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ #define LP_APM_INT_EN_REG (DR_REG_LP_APM_BASE + 0xe8) /** LP_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M0_APM_INT_EN (BIT(0)) #define LP_APM_M0_APM_INT_EN_M (LP_APM_M0_APM_INT_EN_V << LP_APM_M0_APM_INT_EN_S) #define LP_APM_M0_APM_INT_EN_V 0x00000001U #define LP_APM_M0_APM_INT_EN_S 0 /** LP_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ #define LP_APM_M1_APM_INT_EN (BIT(1)) #define LP_APM_M1_APM_INT_EN_M (LP_APM_M1_APM_INT_EN_V << LP_APM_M1_APM_INT_EN_S) @@ -988,13 +1020,13 @@ extern "C" { #define LP_APM_M1_APM_INT_EN_S 1 /** LP_APM_CLOCK_GATE_REG register - * clock gating register + * Clock gating register */ #define LP_APM_CLOCK_GATE_REG (DR_REG_LP_APM_BASE + 0xec) /** LP_APM_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_APM_CLK_EN (BIT(0)) #define LP_APM_CLK_EN_M (LP_APM_CLK_EN_V << LP_APM_CLK_EN_S) diff --git a/components/soc/esp32c5/register/soc/lp_apm_struct.h b/components/soc/esp32c5/register/soc/lp_apm_struct.h index 3c7bc3fcc2..fe0bddb019 100644 --- a/components/soc/esp32c5/register/soc/lp_apm_struct.h +++ b/components/soc/esp32c5/register/soc/lp_apm_struct.h @@ -10,16 +10,16 @@ extern "C" { #endif -/** Group: Region filter enable register */ +/** Group: Configuration Registers */ /** Type of region_filter_en register - * Region filter enable register + * Region enable register */ typedef union { struct { /** region_filter_en : R/W; bitpos: [7:0]; default: 1; - * Configure bit $n (0-7) to enable region $n. - * 0: disable - * 1: enable + * Configure bit $n (0-7) to enable region $n (0-7). + * 0: Disable + * 1: Enable */ uint32_t region_filter_en:8; uint32_t reserved_8:24; @@ -27,15 +27,13 @@ typedef union { uint32_t val; } lp_apm_region_filter_en_reg_t; - -/** Group: Region address register */ /** Type of regionn_addr_start register * Region address register */ typedef union { struct { /** regionn_addr_start : R/W; bitpos: [31:0]; default: 0; - * Configures start address of region n. + * Configures the start address of region n. */ uint32_t regionn_addr_start:32; }; @@ -48,60 +46,62 @@ typedef union { typedef union { struct { /** regionn_addr_end : R/W; bitpos: [31:0]; default: 4294967295; - * Configures end address of region n. + * Configures the end address of region n. */ uint32_t regionn_addr_end:32; }; uint32_t val; } lp_apm_regionn_addr_end_reg_t; - -/** Group: Region access authority attribute register */ /** Type of regionn_attr register - * Region access authority attribute register + * Region access permissions configuration register */ typedef union { struct { /** regionn_r0_x : R/W; bitpos: [0]; default: 0; - * Configures the execution authority of REE_MODE 0 in region n. + * Configures the execution permission in region n in REE0 mode. */ uint32_t regionn_r0_x:1; /** regionn_r0_w : R/W; bitpos: [1]; default: 0; - * Configures the write authority of REE_MODE 0 in region n. + * Configures the write permission in region n in REE0 mode. */ uint32_t regionn_r0_w:1; /** regionn_r0_r : R/W; bitpos: [2]; default: 0; - * Configures the read authority of REE_MODE 0 in region n. + * Configures the read permission in region n in REE0 mode. */ uint32_t regionn_r0_r:1; uint32_t reserved_3:1; /** regionn_r1_x : R/W; bitpos: [4]; default: 0; - * Configures the execution authority of REE_MODE 1 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r1_x:1; /** regionn_r1_w : R/W; bitpos: [5]; default: 0; - * Configures the write authority of REE_MODE 1 in region n. + * Configures the write permission in region n in REE1 mode. */ uint32_t regionn_r1_w:1; /** regionn_r1_r : R/W; bitpos: [6]; default: 0; - * Configures the read authority of REE_MODE 1 in region n. + * Configures the read permission in region n in REE1 mode. */ uint32_t regionn_r1_r:1; uint32_t reserved_7:1; /** regionn_r2_x : R/W; bitpos: [8]; default: 0; - * Configures the execution authority of REE_MODE 2 in region n. + * Configures the execution permission in region n in REE1 mode. */ uint32_t regionn_r2_x:1; /** regionn_r2_w : R/W; bitpos: [9]; default: 0; - * Configures the write authority of REE_MODE 2 in region n. + * Configures the write permission in region n in REE2 mode. */ uint32_t regionn_r2_w:1; /** regionn_r2_r : R/W; bitpos: [10]; default: 0; - * Configures the read authority of REE_MODE 2 in region n. + * Configures the read permission in region n in REE2 mode. */ uint32_t regionn_r2_r:1; /** regionn_lock : R/W; bitpos: [11]; default: 0; - * Set 1 to lock region0 configuration + * Configures to lock the value of region n configuration registers + * (LP_APM_REGIONn_ADDR_START_REG, LP_APM_REGIONn_ADDR_END_REG and + * LP_APM_REGIONn_ATTR_REG). + * 0: Do not lock + * 1: Lock */ uint32_t regionn_lock:1; uint32_t reserved_12:20; @@ -109,19 +109,17 @@ typedef union { uint32_t val; } lp_apm_regionn_attr_reg_t; - -/** Group: function control register */ /** Type of func_ctrl register - * APM function control register + * APM access path permission management register */ typedef union { struct { /** m0_func_en : R/W; bitpos: [0]; default: 1; - * PMS M0 function enable + * Configures to enable permission management for LP_APM_CTRL M0. */ uint32_t m0_func_en:1; /** m1_func_en : R/W; bitpos: [1]; default: 1; - * PMS M1 function enable + * Configures to enable permission management for LP_APM_CTRL M1. */ uint32_t m1_func_en:1; uint32_t reserved_2:30; @@ -130,16 +128,16 @@ typedef union { } lp_apm_func_ctrl_reg_t; -/** Group: M0 status register */ +/** Group: Status Registers */ /** Type of m0_status register - * M0 status register + * LP_APM_CTRL M0 status register */ typedef union { struct { /** m0_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m0_exception_status:2; uint32_t reserved_2:30; @@ -147,10 +145,8 @@ typedef union { uint32_t val; } lp_apm_m0_status_reg_t; - -/** Group: M0 status clear register */ /** Type of m0_status_clr register - * M0 status clear register + * LP_APM_CTRL M0 status clear register */ typedef union { struct { @@ -163,24 +159,22 @@ typedef union { uint32_t val; } lp_apm_m0_status_clr_reg_t; - -/** Group: M0 exception_info0 register */ /** Type of m0_exception_info0 register - * M0 exception_info0 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m0_exception_region:8; uint32_t reserved_8:8; /** m0_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m0_exception_mode:2; /** m0_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m0_exception_id:5; uint32_t reserved_23:9; @@ -188,32 +182,28 @@ typedef union { uint32_t val; } lp_apm_m0_exception_info0_reg_t; - -/** Group: M0 exception_info1 register */ /** Type of m0_exception_info1 register - * M0 exception_info1 register + * LP_APM_CTRL M0 exception information register */ typedef union { struct { /** m0_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m0_exception_addr:32; }; uint32_t val; } lp_apm_m0_exception_info1_reg_t; - -/** Group: M1 status register */ /** Type of m1_status register - * M1 status register + * LP_APM_CTRL M1 status register */ typedef union { struct { /** m1_exception_status : RO; bitpos: [1:0]; default: 0; * Represents exception status. - * bit0: 1 represents authority_exception - * bit1: 1 represents space_exception + * bit0: 1 represents permission restrictions + * bit1: 1 represents address out of bounds */ uint32_t m1_exception_status:2; uint32_t reserved_2:30; @@ -221,10 +211,8 @@ typedef union { uint32_t val; } lp_apm_m1_status_reg_t; - -/** Group: M1 status clear register */ /** Type of m1_status_clr register - * M1 status clear register + * LP_APM_CTRL M1 status clear register */ typedef union { struct { @@ -237,24 +225,22 @@ typedef union { uint32_t val; } lp_apm_m1_status_clr_reg_t; - -/** Group: M1 exception_info0 register */ /** Type of m1_exception_info0 register - * M1 exception_info0 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_region : RO; bitpos: [7:0]; default: 0; - * Represents exception region. + * Represents the region where an exception occurs. */ uint32_t m1_exception_region:8; uint32_t reserved_8:8; /** m1_exception_mode : RO; bitpos: [17:16]; default: 0; - * Represents exception mode. + * Represents the master's security mode when an exception occurs. */ uint32_t m1_exception_mode:2; /** m1_exception_id : RO; bitpos: [22:18]; default: 0; - * Represents exception id information. + * Represents master ID when an exception occurs. */ uint32_t m1_exception_id:5; uint32_t reserved_23:9; @@ -262,15 +248,13 @@ typedef union { uint32_t val; } lp_apm_m1_exception_info0_reg_t; - -/** Group: M1 exception_info1 register */ /** Type of m1_exception_info1 register - * M1 exception_info1 register + * LP_APM_CTRL M1 exception information register */ typedef union { struct { /** m1_exception_addr : RO; bitpos: [31:0]; default: 0; - * Represents exception addr. + * Represents the access address when an exception occurs. */ uint32_t m1_exception_addr:32; }; @@ -278,22 +262,22 @@ typedef union { } lp_apm_m1_exception_info1_reg_t; -/** Group: APM interrupt enable register */ +/** Group: Interrupt Registers */ /** Type of int_en register - * APM interrupt enable register + * LP_APM_CTRL M0/1 interrupt enable register */ typedef union { struct { /** m0_apm_int_en : R/W; bitpos: [0]; default: 0; - * Configures to enable APM M0 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M0 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m0_apm_int_en:1; /** m1_apm_int_en : R/W; bitpos: [1]; default: 0; - * Configures to enable APM M1 interrupt. - * 0: disable - * 1: enable + * Configures to enable LP_APM_CTRL M1 interrupt. + * 0: Disable + * 1: Enable */ uint32_t m1_apm_int_en:1; uint32_t reserved_2:30; @@ -302,16 +286,16 @@ typedef union { } lp_apm_int_en_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register - * clock gating register + * Clock gating register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -320,7 +304,7 @@ typedef union { } lp_apm_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ diff --git a/components/soc/esp32c5/register/soc/lp_tee_reg.h b/components/soc/esp32c5/register/soc/lp_tee_reg.h index e9eb72abe8..77abd8f4a9 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_reg.h +++ b/components/soc/esp32c5/register/soc/lp_tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** LP_TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define LP_TEE_M0_MODE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x0) /** LP_TEE_M0_MODE : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define LP_TEE_M0_MODE 0x00000003U #define LP_TEE_M0_MODE_M (LP_TEE_M0_MODE_V << LP_TEE_M0_MODE_S) #define LP_TEE_M0_MODE_V 0x00000003U #define LP_TEE_M0_MODE_S 0 /** LP_TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define LP_TEE_M0_LOCK (BIT(2)) #define LP_TEE_M0_LOCK_M (LP_TEE_M0_LOCK_V << LP_TEE_M0_LOCK_S) @@ -35,7 +37,7 @@ extern "C" { #define LP_TEE_M0_LOCK_S 2 /** LP_TEE_EFUSE_CTRL_REG register - * efuse read/write control register + * eFuse read/write control register */ #define LP_TEE_EFUSE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4) /** LP_TEE_READ_TEE_EFUSE : R/W; bitpos: [0]; default: 1; @@ -112,7 +114,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_EFUSE_S 7 /** LP_TEE_PMU_CTRL_REG register - * pmu read/write control register + * PMU read/write control register */ #define LP_TEE_PMU_CTRL_REG (DR_REG_LP_TEE_BASE + 0x8) /** LP_TEE_READ_TEE_PMU : R/W; bitpos: [0]; default: 1; @@ -189,7 +191,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_PMU_S 7 /** LP_TEE_CLKRST_CTRL_REG register - * clkrst read/write control register + * LP_CLKRST read/write control register */ #define LP_TEE_CLKRST_CTRL_REG (DR_REG_LP_TEE_BASE + 0xc) /** LP_TEE_READ_TEE_CLKRST : R/W; bitpos: [0]; default: 1; @@ -266,7 +268,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_CLKRST_S 7 /** LP_TEE_LP_AON_CTRL_CTRL_REG register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ #define LP_TEE_LP_AON_CTRL_CTRL_REG (DR_REG_LP_TEE_BASE + 0x10) /** LP_TEE_READ_TEE_LP_AON_CTRL : R/W; bitpos: [0]; default: 1; @@ -343,7 +345,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_AON_CTRL_S 7 /** LP_TEE_LP_TIMER_CTRL_REG register - * lp_timer read/write control register + * LP_TIMER read/write control register */ #define LP_TEE_LP_TIMER_CTRL_REG (DR_REG_LP_TEE_BASE + 0x14) /** LP_TEE_READ_TEE_LP_TIMER : R/W; bitpos: [0]; default: 1; @@ -420,7 +422,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TIMER_S 7 /** LP_TEE_LP_WDT_CTRL_REG register - * lp_wdt read/write control register + * LP_WDT read/write control register */ #define LP_TEE_LP_WDT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x18) /** LP_TEE_READ_TEE_LP_WDT : R/W; bitpos: [0]; default: 1; @@ -497,7 +499,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_WDT_S 7 /** LP_TEE_LP_PERI_CTRL_REG register - * lp_peri read/write control register + * LPPERI read/write control register */ #define LP_TEE_LP_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x1c) /** LP_TEE_READ_TEE_LP_PERI : R/W; bitpos: [0]; default: 1; @@ -574,7 +576,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_PERI_S 7 /** LP_TEE_LP_ANA_PERI_CTRL_REG register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ #define LP_TEE_LP_ANA_PERI_CTRL_REG (DR_REG_LP_TEE_BASE + 0x20) /** LP_TEE_READ_TEE_LP_ANA_PERI : R/W; bitpos: [0]; default: 1; @@ -651,7 +653,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_ANA_PERI_S 7 /** LP_TEE_LP_IO_CTRL_REG register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ #define LP_TEE_LP_IO_CTRL_REG (DR_REG_LP_TEE_BASE + 0x2c) /** LP_TEE_READ_TEE_LP_IO : R/W; bitpos: [0]; default: 1; @@ -728,7 +730,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_IO_S 7 /** LP_TEE_LP_TEE_CTRL_REG register - * lp_tee read/write control register + * LP_TEE read/write control register */ #define LP_TEE_LP_TEE_CTRL_REG (DR_REG_LP_TEE_BASE + 0x34) /** LP_TEE_READ_TEE_LP_TEE : R/W; bitpos: [0]; default: 1; @@ -805,7 +807,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_TEE_S 7 /** LP_TEE_UART_CTRL_REG register - * uart read/write control register + * LP_UART read/write control register */ #define LP_TEE_UART_CTRL_REG (DR_REG_LP_TEE_BASE + 0x38) /** LP_TEE_READ_TEE_UART : R/W; bitpos: [0]; default: 1; @@ -882,7 +884,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_UART_S 7 /** LP_TEE_I2C_EXT_CTRL_REG register - * i2c_ext read/write control register + * LP_I2C read/write control register */ #define LP_TEE_I2C_EXT_CTRL_REG (DR_REG_LP_TEE_BASE + 0x40) /** LP_TEE_READ_TEE_I2C_EXT : R/W; bitpos: [0]; default: 1; @@ -959,7 +961,7 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_EXT_S 7 /** LP_TEE_I2C_ANA_MST_CTRL_REG register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ #define LP_TEE_I2C_ANA_MST_CTRL_REG (DR_REG_LP_TEE_BASE + 0x44) /** LP_TEE_READ_TEE_I2C_ANA_MST : R/W; bitpos: [0]; default: 1; @@ -1035,85 +1037,8 @@ extern "C" { #define LP_TEE_WRITE_REE2_I2C_ANA_MST_V 0x00000001U #define LP_TEE_WRITE_REE2_I2C_ANA_MST_S 7 -/** LP_TEE_HUK_CTRL_REG register - * huk read/write control register - */ -#define LP_TEE_HUK_CTRL_REG (DR_REG_LP_TEE_BASE + 0x48) -/** LP_TEE_READ_TEE_HUK : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_TEE_HUK (BIT(0)) -#define LP_TEE_READ_TEE_HUK_M (LP_TEE_READ_TEE_HUK_V << LP_TEE_READ_TEE_HUK_S) -#define LP_TEE_READ_TEE_HUK_V 0x00000001U -#define LP_TEE_READ_TEE_HUK_S 0 -/** LP_TEE_READ_REE0_HUK : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE0_HUK (BIT(1)) -#define LP_TEE_READ_REE0_HUK_M (LP_TEE_READ_REE0_HUK_V << LP_TEE_READ_REE0_HUK_S) -#define LP_TEE_READ_REE0_HUK_V 0x00000001U -#define LP_TEE_READ_REE0_HUK_S 1 -/** LP_TEE_READ_REE1_HUK : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE1_HUK (BIT(2)) -#define LP_TEE_READ_REE1_HUK_M (LP_TEE_READ_REE1_HUK_V << LP_TEE_READ_REE1_HUK_S) -#define LP_TEE_READ_REE1_HUK_V 0x00000001U -#define LP_TEE_READ_REE1_HUK_S 2 -/** LP_TEE_READ_REE2_HUK : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define LP_TEE_READ_REE2_HUK (BIT(3)) -#define LP_TEE_READ_REE2_HUK_M (LP_TEE_READ_REE2_HUK_V << LP_TEE_READ_REE2_HUK_S) -#define LP_TEE_READ_REE2_HUK_V 0x00000001U -#define LP_TEE_READ_REE2_HUK_S 3 -/** LP_TEE_WRITE_TEE_HUK : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_TEE_HUK (BIT(4)) -#define LP_TEE_WRITE_TEE_HUK_M (LP_TEE_WRITE_TEE_HUK_V << LP_TEE_WRITE_TEE_HUK_S) -#define LP_TEE_WRITE_TEE_HUK_V 0x00000001U -#define LP_TEE_WRITE_TEE_HUK_S 4 -/** LP_TEE_WRITE_REE0_HUK : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE0_HUK (BIT(5)) -#define LP_TEE_WRITE_REE0_HUK_M (LP_TEE_WRITE_REE0_HUK_V << LP_TEE_WRITE_REE0_HUK_S) -#define LP_TEE_WRITE_REE0_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE0_HUK_S 5 -/** LP_TEE_WRITE_REE1_HUK : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE1_HUK (BIT(6)) -#define LP_TEE_WRITE_REE1_HUK_M (LP_TEE_WRITE_REE1_HUK_V << LP_TEE_WRITE_REE1_HUK_S) -#define LP_TEE_WRITE_REE1_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE1_HUK_S 6 -/** LP_TEE_WRITE_REE2_HUK : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define LP_TEE_WRITE_REE2_HUK (BIT(7)) -#define LP_TEE_WRITE_REE2_HUK_M (LP_TEE_WRITE_REE2_HUK_V << LP_TEE_WRITE_REE2_HUK_S) -#define LP_TEE_WRITE_REE2_HUK_V 0x00000001U -#define LP_TEE_WRITE_REE2_HUK_S 7 - /** LP_TEE_LP_APM_CTRL_REG register - * lp_apm read/write control register + * LP_APM read/write control register */ #define LP_TEE_LP_APM_CTRL_REG (DR_REG_LP_TEE_BASE + 0x4c) /** LP_TEE_READ_TEE_LP_APM : R/W; bitpos: [0]; default: 1; @@ -1190,14 +1115,14 @@ extern "C" { #define LP_TEE_WRITE_REE2_LP_APM_S 7 /** LP_TEE_FORCE_ACC_HP_REG register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ #define LP_TEE_FORCE_ACC_HP_REG (DR_REG_LP_TEE_BASE + 0x90) /** LP_TEE_FORCE_ACC_HPMEM_EN : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ #define LP_TEE_FORCE_ACC_HPMEM_EN (BIT(0)) #define LP_TEE_FORCE_ACC_HPMEM_EN_M (LP_TEE_FORCE_ACC_HPMEM_EN_V << LP_TEE_FORCE_ACC_HPMEM_EN_S) @@ -1205,13 +1130,13 @@ extern "C" { #define LP_TEE_FORCE_ACC_HPMEM_EN_S 0 /** LP_TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define LP_TEE_BUS_ERR_CONF_REG (DR_REG_LP_TEE_BASE + 0xf0) /** LP_TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define LP_TEE_BUS_ERR_RESP_EN (BIT(0)) #define LP_TEE_BUS_ERR_RESP_EN_M (LP_TEE_BUS_ERR_RESP_EN_V << LP_TEE_BUS_ERR_RESP_EN_S) @@ -1224,8 +1149,8 @@ extern "C" { #define LP_TEE_CLOCK_GATE_REG (DR_REG_LP_TEE_BASE + 0xf8) /** LP_TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define LP_TEE_CLK_EN (BIT(0)) #define LP_TEE_CLK_EN_M (LP_TEE_CLK_EN_V << LP_TEE_CLK_EN_S) @@ -1237,7 +1162,7 @@ extern "C" { */ #define LP_TEE_DATE_REG (DR_REG_LP_TEE_BASE + 0xfc) /** LP_TEE_DATE : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ #define LP_TEE_DATE 0x0FFFFFFFU #define LP_TEE_DATE_M (LP_TEE_DATE_V << LP_TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/lp_tee_struct.h b/components/soc/esp32c5/register/soc/lp_tee_struct.h index 8158b54d22..e344cec804 100644 --- a/components/soc/esp32c5/register/soc/lp_tee_struct.h +++ b/components/soc/esp32c5/register/soc/lp_tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of m0_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** m0_mode : R/W; bitpos: [1:0]; default: 3; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for LP CPU. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t m0_mode:2; /** m0_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures to lock the value of LP_TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t m0_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } lp_tee_m0_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Register */ /** Type of efuse_ctrl register - * efuse read/write control register + * eFuse read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } lp_tee_efuse_ctrl_reg_t; /** Type of pmu_ctrl register - * pmu read/write control register + * PMU read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } lp_tee_pmu_ctrl_reg_t; /** Type of clkrst_ctrl register - * clkrst read/write control register + * LP_CLKRST read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } lp_tee_clkrst_ctrl_reg_t; /** Type of lp_aon_ctrl_ctrl register - * lp_aon_ctrl read/write control register + * LP_AON read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } lp_tee_lp_aon_ctrl_ctrl_reg_t; /** Type of lp_timer_ctrl register - * lp_timer read/write control register + * LP_TIMER read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } lp_tee_lp_timer_ctrl_reg_t; /** Type of lp_wdt_ctrl register - * lp_wdt read/write control register + * LP_WDT read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } lp_tee_lp_wdt_ctrl_reg_t; /** Type of lp_peri_ctrl register - * lp_peri read/write control register + * LPPERI read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } lp_tee_lp_peri_ctrl_reg_t; /** Type of lp_ana_peri_ctrl register - * lp_ana_peri read/write control register + * LP_ANA_PERI read/write control register */ typedef union { struct { @@ -500,7 +502,7 @@ typedef union { } lp_tee_lp_ana_peri_ctrl_reg_t; /** Type of lp_io_ctrl register - * lp_io read/write control register + * LP_GPIO and LP_IO_MUX read/write control register */ typedef union { struct { @@ -558,7 +560,7 @@ typedef union { } lp_tee_lp_io_ctrl_reg_t; /** Type of lp_tee_ctrl register - * lp_tee read/write control register + * LP_TEE read/write control register */ typedef union { struct { @@ -616,7 +618,7 @@ typedef union { } lp_tee_lp_tee_ctrl_reg_t; /** Type of uart_ctrl register - * uart read/write control register + * LP_UART read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } lp_tee_uart_ctrl_reg_t; /** Type of i2c_ext_ctrl register - * i2c_ext read/write control register + * LP_I2C read/write control register */ typedef union { struct { @@ -732,7 +734,7 @@ typedef union { } lp_tee_i2c_ext_ctrl_reg_t; /** Type of i2c_ana_mst_ctrl register - * i2c_ana_mst read/write control register + * I2C_ANA_MST read/write control register */ typedef union { struct { @@ -789,66 +791,8 @@ typedef union { uint32_t val; } lp_tee_i2c_ana_mst_ctrl_reg_t; -/** Type of huk_ctrl register - * huk read/write control register - */ -typedef union { - struct { - /** read_tee_huk : R/W; bitpos: [0]; default: 1; - * Configures huk registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_huk:1; - /** read_ree0_huk : R/W; bitpos: [1]; default: 0; - * Configures huk registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_huk:1; - /** read_ree1_huk : R/W; bitpos: [2]; default: 0; - * Configures huk registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_huk:1; - /** read_ree2_huk : R/W; bitpos: [3]; default: 0; - * Configures huk registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_huk:1; - /** write_tee_huk : R/W; bitpos: [4]; default: 1; - * Configures huk registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_huk:1; - /** write_ree0_huk : R/W; bitpos: [5]; default: 0; - * Configures huk registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_huk:1; - /** write_ree1_huk : R/W; bitpos: [6]; default: 0; - * Configures huk registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_huk:1; - /** write_ree2_huk : R/W; bitpos: [7]; default: 0; - * Configures huk registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_huk:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} lp_tee_huk_ctrl_reg_t; - /** Type of lp_apm_ctrl register - * lp_apm read/write control register + * LP_APM read/write control register */ typedef union { struct { @@ -905,18 +849,16 @@ typedef union { uint32_t val; } lp_tee_lp_apm_ctrl_reg_t; - -/** Group: Force access to hpmem configuration register */ /** Type of force_acc_hp register - * Force access to hpmem configuration register + * Force access to HP SRAM configuration register */ typedef union { struct { /** force_acc_hpmem_en : R/W; bitpos: [0]; default: 0; - * Configures whether to allow LP CPU to force access to HP_MEM regardless of + * Configures whether to allow LP CPU to forcibly access HP SRAM regardless of * permission management. - * 0: disable force access HP_MEM - * 1: enable force access HP_MEM + * 0: Disable force access to HP SRAM + * 1: Enable force access to HP SRAM */ uint32_t force_acc_hpmem_en:1; uint32_t reserved_1:31; @@ -924,17 +866,15 @@ typedef union { uint32_t val; } lp_tee_force_acc_hp_reg_t; - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -943,7 +883,7 @@ typedef union { } lp_tee_bus_err_conf_reg_t; -/** Group: clock gating register */ +/** Group: Clock Gating Registers */ /** Type of clock_gate register * Clock gating register */ @@ -951,8 +891,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -961,14 +901,14 @@ typedef union { } lp_tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 2363416; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -995,7 +935,7 @@ typedef struct { uint32_t reserved_03c; volatile lp_tee_i2c_ext_ctrl_reg_t i2c_ext_ctrl; volatile lp_tee_i2c_ana_mst_ctrl_reg_t i2c_ana_mst_ctrl; - volatile lp_tee_huk_ctrl_reg_t huk_ctrl; + uint32_t reserved_048; volatile lp_tee_lp_apm_ctrl_reg_t lp_apm_ctrl; uint32_t reserved_050[16]; volatile lp_tee_force_acc_hp_reg_t force_acc_hp; diff --git a/components/soc/esp32c5/register/soc/spi1_mem_reg.h b/components/soc/esp32c5/register/soc/spi1_mem_reg.h index d5116a49c6..d153011d6d 100644 --- a/components/soc/esp32c5/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32c5/register/soc/spi1_mem_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -328,13 +328,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 /** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ #define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S) #define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ +#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S) +#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_S 12 /** SPI_MEM_CTRL2_REG(i) register * SPI1 control2 register. diff --git a/components/soc/esp32c5/register/soc/spi1_mem_struct.h b/components/soc/esp32c5/register/soc/spi1_mem_struct.h index d1b4d26a97..67702ddf29 100644 --- a/components/soc/esp32c5/register/soc/spi1_mem_struct.h +++ b/components/soc/esp32c5/register/soc/spi1_mem_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -338,11 +338,16 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ + uint32_t cs_hold_dly_per:10; + uint32_t reserved_22:10; }; uint32_t val; } spi_mem_ctrl1_reg_t; @@ -367,16 +372,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -1222,7 +1227,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774400; + /** date : R/W; bitpos: [27:0]; default: 37786176; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_reg.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h index 40b9b2fef8..857e106ccf 100644 --- a/components/soc/esp32c5/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32c5/register/soc/spi_mem_c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -205,29 +205,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) #define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) #define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) #define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 /** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -488,10 +480,13 @@ extern "C" { /** SPI_MEM_RD_STATUS_REG register * SPI0 read control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2c) /** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE 0x000000FFU #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) @@ -499,6 +494,7 @@ extern "C" { #define SPI_MEM_WB_MODE_S 16 /** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_BITLEN 0x00000007U #define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) @@ -506,6 +502,7 @@ extern "C" { #define SPI_MEM_WB_MODE_BITLEN_S 24 /** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_EN (BIT(27)) #define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) @@ -937,14 +934,16 @@ extern "C" { */ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) /** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_L 0x000000FFU #define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) #define SPI_MEM_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_SCLKCNT_L_S 0 /** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_H 0x000000FFU #define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) @@ -952,7 +951,8 @@ extern "C" { #define SPI_MEM_SCLKCNT_H_S 8 /** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_N 0x000000FFU #define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) @@ -961,6 +961,7 @@ extern "C" { /** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) #define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) @@ -971,27 +972,27 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [12]; default: 0; +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. */ -#define SPI_MEM_FLASH_LOCK_EN (BIT(12)) +#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) #define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) #define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U -#define SPI_MEM_FLASH_LOCK_EN_S 12 -/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [13]; default: 0; +#define SPI_MEM_FLASH_LOCK_EN_S 19 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. */ -#define SPI_MEM_SRAM_LOCK_EN (BIT(13)) +#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) #define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) #define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U -#define SPI_MEM_SRAM_LOCK_EN_S 13 +#define SPI_MEM_SRAM_LOCK_EN_S 20 /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register @@ -1593,7 +1594,7 @@ extern "C" { #define SPI_SMEM_HYPERBUS_CA_S 30 /** SPI_FMEM_PMS0_ATTR_REG register - * MSPI flash PMS section 0 attribute register + * SPI1 flash PMS section 0 attribute register */ #define SPI_FMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x100) /** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1621,7 +1622,7 @@ extern "C" { #define SPI_FMEM_PMS0_ECC_S 2 /** SPI_FMEM_PMS1_ATTR_REG register - * MSPI flash PMS section 1 attribute register + * SPI1 flash PMS section 1 attribute register */ #define SPI_FMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x104) /** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1649,7 +1650,7 @@ extern "C" { #define SPI_FMEM_PMS1_ECC_S 2 /** SPI_FMEM_PMS2_ATTR_REG register - * MSPI flash PMS section 2 attribute register + * SPI1 flash PMS section 2 attribute register */ #define SPI_FMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x108) /** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1677,7 +1678,7 @@ extern "C" { #define SPI_FMEM_PMS2_ECC_S 2 /** SPI_FMEM_PMS3_ATTR_REG register - * MSPI flash PMS section 3 attribute register + * SPI1 flash PMS section 3 attribute register */ #define SPI_FMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x10c) /** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1805,7 +1806,7 @@ extern "C" { #define SPI_FMEM_PMS3_SIZE_S 0 /** SPI_SMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 start address register + * SPI1 external RAM PMS section 0 attribute register */ #define SPI_SMEM_PMS0_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x130) /** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1833,7 +1834,7 @@ extern "C" { #define SPI_SMEM_PMS0_ECC_S 2 /** SPI_SMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 start address register + * SPI1 external RAM PMS section 1 attribute register */ #define SPI_SMEM_PMS1_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x134) /** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1861,7 +1862,7 @@ extern "C" { #define SPI_SMEM_PMS1_ECC_S 2 /** SPI_SMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 start address register + * SPI1 external RAM PMS section 2 attribute register */ #define SPI_SMEM_PMS2_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x138) /** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -1889,7 +1890,7 @@ extern "C" { #define SPI_SMEM_PMS2_ECC_S 2 /** SPI_SMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 start address register + * SPI1 external RAM PMS section 3 attribute register */ #define SPI_SMEM_PMS3_ATTR_REG(i) (REG_SPI_MEM_BASE(i) + 0x13c) /** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; @@ -2669,7 +2670,7 @@ extern "C" { #define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) #define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U #define SPI_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; +/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1; * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. */ @@ -2677,7 +2678,7 @@ extern "C" { #define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) #define SPI_SMEM_DQS0_270_SEL_V 0x00000003U #define SPI_SMEM_DQS0_270_SEL_S 7 -/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; +/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1; * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, * 2'd2: 1.5ns 2'd3: 2.0ns. */ @@ -2685,6 +2686,22 @@ extern "C" { #define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) #define SPI_SMEM_DQS0_90_SEL_V 0x00000003U #define SPI_SMEM_DQS0_90_SEL_S 9 +/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_270_SEL 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S) +#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_270_SEL_S 11 +/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS1_90_SEL 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S) +#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS1_90_SEL_S 13 /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register @@ -3309,6 +3326,13 @@ extern "C" { #define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) #define SPI_CLK_EN_V 0x00000001U #define SPI_CLK_EN_S 0 +/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ +#define SPI_MSPI_CLK_FORCE_ON (BIT(1)) +#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S) +#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U +#define SPI_MSPI_CLK_FORCE_ON_S 1 /** SPI_MEM_NAND_FLASH_EN_REG register * NAND FLASH control register @@ -3755,14 +3779,14 @@ extern "C" { #define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) #define SPI_MMU_MEM_FORCE_ON_V 0x00000001U #define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 1; +/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ #define SPI_MMU_MEM_FORCE_PD (BIT(1)) #define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) #define SPI_MMU_MEM_FORCE_PD_V 0x00000001U #define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; +/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; * Set this bit to force mmu-memory powerup, in this case, the power should also be * controlled by rtc. */ @@ -3770,7 +3794,7 @@ extern "C" { #define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) #define SPI_MMU_MEM_FORCE_PU_V 0x00000001U #define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MMU_PAGE_SIZE : HRO; bitpos: [4:3]; default: 0; +/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ #define SPI_MMU_PAGE_SIZE 0x00000003U @@ -3786,6 +3810,7 @@ extern "C" { #define SPI_MEM_AUX_CTRL_S 16 /** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RDN_ENA (BIT(30)) #define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) @@ -3793,6 +3818,7 @@ extern "C" { #define SPI_MEM_RDN_ENA_S 30 /** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; * MSPI module clock domain and AXI clock domain ECO register result register + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RDN_RESULT (BIT(31)) #define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) @@ -3894,7 +3920,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; * SPI0 register version. */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h deleted file mode 100644 index e247e8d6ef..0000000000 --- a/components/soc/esp32c5/register/soc/spi_mem_c_reg_eco2.h +++ /dev/null @@ -1,3988 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include "soc/soc.h" -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI_MEM_CMD_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_CMD_REG (DR_REG_SPI_BASE + 0x0) -/** SPI_MEM_MST_ST : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ -#define SPI_MEM_MST_ST 0x0000000FU -#define SPI_MEM_MST_ST_M (SPI_MEM_MST_ST_V << SPI_MEM_MST_ST_S) -#define SPI_MEM_MST_ST_V 0x0000000FU -#define SPI_MEM_MST_ST_S 0 -/** SPI_MEM_SLV_ST : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ -#define SPI_MEM_SLV_ST 0x0000000FU -#define SPI_MEM_SLV_ST_M (SPI_MEM_SLV_ST_V << SPI_MEM_SLV_ST_S) -#define SPI_MEM_SLV_ST_V 0x0000000FU -#define SPI_MEM_SLV_ST_S 4 -/** SPI_MEM_USR : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (SPI_MEM_USR_V << SPI_MEM_USR_S) -#define SPI_MEM_USR_V 0x00000001U -#define SPI_MEM_USR_S 18 - -/** SPI_MEM_CTRL_REG register - * SPI0 control register. - */ -#define SPI_MEM_CTRL_REG (DR_REG_SPI_BASE + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT (BIT(0)) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_DQS_ALWAYS_OUT_S 0 -/** SPI_MEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_MEM_WDUMMY_ALWAYS_OUT (BIT(1)) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_M (SPI_MEM_WDUMMY_ALWAYS_OUT_V << SPI_MEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_MEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_MEM_WDUMMY_ALWAYS_OUT_S 1 -/** SPI_MEM_FDUMMY_RIN : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ -#define SPI_MEM_FDUMMY_RIN (BIT(2)) -#define SPI_MEM_FDUMMY_RIN_M (SPI_MEM_FDUMMY_RIN_V << SPI_MEM_FDUMMY_RIN_S) -#define SPI_MEM_FDUMMY_RIN_V 0x00000001U -#define SPI_MEM_FDUMMY_RIN_S 2 -/** SPI_MEM_FDUMMY_WOUT : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ -#define SPI_MEM_FDUMMY_WOUT (BIT(3)) -#define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) -#define SPI_MEM_FDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) -#define SPI_MEM_FDOUT_OCT_V 0x00000001U -#define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) -#define SPI_MEM_FDIN_OCT_V 0x00000001U -#define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (SPI_MEM_FADDR_OCT_V << SPI_MEM_FADDR_OCT_S) -#define SPI_MEM_FADDR_OCT_V 0x00000001U -#define SPI_MEM_FADDR_OCT_S 6 -/** SPI_MEM_FCMD_QUAD : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) -#define SPI_MEM_FCMD_QUAD_V 0x00000001U -#define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (SPI_MEM_FCMD_OCT_V << SPI_MEM_FCMD_OCT_S) -#define SPI_MEM_FCMD_OCT_V 0x00000001U -#define SPI_MEM_FCMD_OCT_S 9 -/** SPI_MEM_FASTRD_MODE : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (SPI_MEM_FASTRD_MODE_V << SPI_MEM_FASTRD_MODE_S) -#define SPI_MEM_FASTRD_MODE_V 0x00000001U -#define SPI_MEM_FASTRD_MODE_S 13 -/** SPI_MEM_FREAD_DUAL : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (SPI_MEM_FREAD_DUAL_V << SPI_MEM_FREAD_DUAL_S) -#define SPI_MEM_FREAD_DUAL_V 0x00000001U -#define SPI_MEM_FREAD_DUAL_S 14 -/** SPI_MEM_Q_POL : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (SPI_MEM_Q_POL_V << SPI_MEM_Q_POL_S) -#define SPI_MEM_Q_POL_V 0x00000001U -#define SPI_MEM_Q_POL_S 18 -/** SPI_MEM_D_POL : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (SPI_MEM_D_POL_V << SPI_MEM_D_POL_S) -#define SPI_MEM_D_POL_V 0x00000001U -#define SPI_MEM_D_POL_S 19 -/** SPI_MEM_FREAD_QUAD : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (SPI_MEM_FREAD_QUAD_V << SPI_MEM_FREAD_QUAD_S) -#define SPI_MEM_FREAD_QUAD_V 0x00000001U -#define SPI_MEM_FREAD_QUAD_S 20 -/** SPI_MEM_WP_REG : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (SPI_MEM_WP_REG_V << SPI_MEM_WP_REG_S) -#define SPI_MEM_WP_REG_V 0x00000001U -#define SPI_MEM_WP_REG_S 21 -/** SPI_MEM_FREAD_DIO : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (SPI_MEM_FREAD_DIO_V << SPI_MEM_FREAD_DIO_S) -#define SPI_MEM_FREAD_DIO_V 0x00000001U -#define SPI_MEM_FREAD_DIO_S 23 -/** SPI_MEM_FREAD_QIO : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) -#define SPI_MEM_FREAD_QIO_V 0x00000001U -#define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ -#define SPI_MEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_MEM_DQS_IE_ALWAYS_ON_M (SPI_MEM_DQS_IE_ALWAYS_ON_V << SPI_MEM_DQS_IE_ALWAYS_ON_S) -#define SPI_MEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_MEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ -#define SPI_MEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_MEM_DATA_IE_ALWAYS_ON_M (SPI_MEM_DATA_IE_ALWAYS_ON_V << SPI_MEM_DATA_IE_ALWAYS_ON_S) -#define SPI_MEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_MEM_DATA_IE_ALWAYS_ON_S 31 - -/** SPI_MEM_CTRL1_REG register - * SPI0 control1 register. - */ -#define SPI_MEM_CTRL1_REG (DR_REG_SPI_BASE + 0xc) -/** SPI_MEM_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ -#define SPI_MEM_CLK_MODE 0x00000003U -#define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) -#define SPI_MEM_CLK_MODE_V 0x00000003U -#define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) -#define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) -#define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) -#define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) -#define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 -/** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ -#define SPI_MEM_RRESP_ECC_ERR_EN (BIT(24)) -#define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) -#define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U -#define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ -#define SPI_MEM_AR_SPLICE_EN (BIT(25)) -#define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) -#define SPI_MEM_AR_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ -#define SPI_MEM_AW_SPLICE_EN (BIT(26)) -#define SPI_MEM_AW_SPLICE_EN_M (SPI_MEM_AW_SPLICE_EN_V << SPI_MEM_AW_SPLICE_EN_S) -#define SPI_MEM_AW_SPLICE_EN_V 0x00000001U -#define SPI_MEM_AW_SPLICE_EN_S 26 -/** SPI_MEM_RAM0_EN : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ -#define SPI_MEM_RAM0_EN (BIT(27)) -#define SPI_MEM_RAM0_EN_M (SPI_MEM_RAM0_EN_V << SPI_MEM_RAM0_EN_S) -#define SPI_MEM_RAM0_EN_V 0x00000001U -#define SPI_MEM_RAM0_EN_S 27 -/** SPI_MEM_DUAL_RAM_EN : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ -#define SPI_MEM_DUAL_RAM_EN (BIT(28)) -#define SPI_MEM_DUAL_RAM_EN_M (SPI_MEM_DUAL_RAM_EN_V << SPI_MEM_DUAL_RAM_EN_S) -#define SPI_MEM_DUAL_RAM_EN_V 0x00000001U -#define SPI_MEM_DUAL_RAM_EN_S 28 -/** SPI_MEM_FAST_WRITE_EN : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ -#define SPI_MEM_FAST_WRITE_EN (BIT(29)) -#define SPI_MEM_FAST_WRITE_EN_M (SPI_MEM_FAST_WRITE_EN_V << SPI_MEM_FAST_WRITE_EN_S) -#define SPI_MEM_FAST_WRITE_EN_V 0x00000001U -#define SPI_MEM_FAST_WRITE_EN_S 29 -/** SPI_MEM_RXFIFO_RST : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (SPI_MEM_RXFIFO_RST_V << SPI_MEM_RXFIFO_RST_S) -#define SPI_MEM_RXFIFO_RST_V 0x00000001U -#define SPI_MEM_RXFIFO_RST_S 30 -/** SPI_MEM_TXFIFO_RST : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ -#define SPI_MEM_TXFIFO_RST (BIT(31)) -#define SPI_MEM_TXFIFO_RST_M (SPI_MEM_TXFIFO_RST_V << SPI_MEM_TXFIFO_RST_S) -#define SPI_MEM_TXFIFO_RST_V 0x00000001U -#define SPI_MEM_TXFIFO_RST_S 31 - -/** SPI_MEM_CTRL2_REG register - * SPI0 control2 register. - */ -#define SPI_MEM_CTRL2_REG (DR_REG_SPI_BASE + 0x10) -/** SPI_MEM_CS_SETUP_TIME : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ -#define SPI_MEM_CS_SETUP_TIME 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_M (SPI_MEM_CS_SETUP_TIME_V << SPI_MEM_CS_SETUP_TIME_S) -#define SPI_MEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_MEM_CS_SETUP_TIME_S 0 -/** SPI_MEM_CS_HOLD_TIME : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ -#define SPI_MEM_CS_HOLD_TIME 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) -#define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (SPI_MEM_ECC_16TO18_BYTE_EN_V << SPI_MEM_ECC_16TO18_BYTE_EN_S) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 -/** SPI_MEM_SPLIT_TRANS_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ -#define SPI_MEM_SPLIT_TRANS_EN (BIT(24)) -#define SPI_MEM_SPLIT_TRANS_EN_M (SPI_MEM_SPLIT_TRANS_EN_V << SPI_MEM_SPLIT_TRANS_EN_S) -#define SPI_MEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_MEM_SPLIT_TRANS_EN_S 24 -/** SPI_MEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ -#define SPI_MEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_M (SPI_MEM_CS_HOLD_DELAY_V << SPI_MEM_CS_HOLD_DELAY_S) -#define SPI_MEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_MEM_CS_HOLD_DELAY_S 25 -/** SPI_MEM_SYNC_RESET : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (SPI_MEM_SYNC_RESET_V << SPI_MEM_SYNC_RESET_S) -#define SPI_MEM_SYNC_RESET_V 0x00000001U -#define SPI_MEM_SYNC_RESET_S 31 - -/** SPI_MEM_CLOCK_REG register - * SPI clock division control register. - */ -#define SPI_MEM_CLOCK_REG (DR_REG_SPI_BASE + 0x14) -/** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to SPI_MEM_CLKCNT_N. - */ -#define SPI_MEM_CLKCNT_L 0x000000FFU -#define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) -#define SPI_MEM_CLKCNT_L_V 0x000000FFU -#define SPI_MEM_CLKCNT_L_S 0 -/** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). - */ -#define SPI_MEM_CLKCNT_H 0x000000FFU -#define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) -#define SPI_MEM_CLKCNT_H_V 0x000000FFU -#define SPI_MEM_CLKCNT_H_S 8 -/** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(SPI_MEM_CLKCNT_N+1) - */ -#define SPI_MEM_CLKCNT_N 0x000000FFU -#define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) -#define SPI_MEM_CLKCNT_N_V 0x000000FFU -#define SPI_MEM_CLKCNT_N_S 16 -/** SPI_MEM_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (SPI_MEM_CLK_EQU_SYSCLK_V << SPI_MEM_CLK_EQU_SYSCLK_S) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x00000001U -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 - -/** SPI_MEM_USER_REG register - * SPI0 user register. - */ -#define SPI_MEM_USER_REG (DR_REG_SPI_BASE + 0x18) -/** SPI_MEM_CS_HOLD : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (SPI_MEM_CS_HOLD_V << SPI_MEM_CS_HOLD_S) -#define SPI_MEM_CS_HOLD_V 0x00000001U -#define SPI_MEM_CS_HOLD_S 6 -/** SPI_MEM_CS_SETUP : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (SPI_MEM_CS_SETUP_V << SPI_MEM_CS_SETUP_S) -#define SPI_MEM_CS_SETUP_V 0x00000001U -#define SPI_MEM_CS_SETUP_S 7 -/** SPI_MEM_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (SPI_MEM_CK_OUT_EDGE_V << SPI_MEM_CK_OUT_EDGE_S) -#define SPI_MEM_CK_OUT_EDGE_V 0x00000001U -#define SPI_MEM_CK_OUT_EDGE_S 9 -/** SPI_MEM_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (SPI_MEM_USR_DUMMY_IDLE_V << SPI_MEM_USR_DUMMY_IDLE_S) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x00000001U -#define SPI_MEM_USR_DUMMY_IDLE_S 26 -/** SPI_MEM_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (SPI_MEM_USR_DUMMY_V << SPI_MEM_USR_DUMMY_S) -#define SPI_MEM_USR_DUMMY_V 0x00000001U -#define SPI_MEM_USR_DUMMY_S 29 - -/** SPI_MEM_USER1_REG register - * SPI0 user1 register. - */ -#define SPI_MEM_USER1_REG (DR_REG_SPI_BASE + 0x1c) -/** SPI_MEM_USR_DUMMY_CYCLELEN : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ -#define SPI_MEM_USR_DBYTELEN 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU -#define SPI_MEM_USR_DBYTELEN_S 6 -/** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_M (SPI_MEM_USR_ADDR_BITLEN_V << SPI_MEM_USR_ADDR_BITLEN_S) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_USR_ADDR_BITLEN_S 26 - -/** SPI_MEM_USER2_REG register - * SPI0 user2 register. - */ -#define SPI_MEM_USER2_REG (DR_REG_SPI_BASE + 0x20) -/** SPI_MEM_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_M (SPI_MEM_USR_COMMAND_VALUE_V << SPI_MEM_USR_COMMAND_VALUE_S) -#define SPI_MEM_USR_COMMAND_VALUE_V 0x0000FFFFU -#define SPI_MEM_USR_COMMAND_VALUE_S 0 -/** SPI_MEM_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_M (SPI_MEM_USR_COMMAND_BITLEN_V << SPI_MEM_USR_COMMAND_BITLEN_S) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0x0000000FU -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 - -/** SPI_MEM_RD_STATUS_REG register - * SPI0 read control register. - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_RD_STATUS_REG (DR_REG_SPI_BASE + 0x2c) -/** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE 0x000000FFU -#define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) -#define SPI_MEM_WB_MODE_V 0x000000FFU -#define SPI_MEM_WB_MODE_S 16 -/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE_BITLEN 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) -#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U -#define SPI_MEM_WB_MODE_BITLEN_S 24 -/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_WB_MODE_EN (BIT(27)) -#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) -#define SPI_MEM_WB_MODE_EN_V 0x00000001U -#define SPI_MEM_WB_MODE_EN_S 27 - -/** SPI_MEM_MISC_REG register - * SPI0 misc register - */ -#define SPI_MEM_MISC_REG (DR_REG_SPI_BASE + 0x34) -/** SPI_MEM_FSUB_PIN : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (SPI_MEM_FSUB_PIN_V << SPI_MEM_FSUB_PIN_S) -#define SPI_MEM_FSUB_PIN_V 0x00000001U -#define SPI_MEM_FSUB_PIN_S 7 -/** SPI_MEM_SSUB_PIN : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (SPI_MEM_SSUB_PIN_V << SPI_MEM_SSUB_PIN_S) -#define SPI_MEM_SSUB_PIN_V 0x00000001U -#define SPI_MEM_SSUB_PIN_S 8 -/** SPI_MEM_CK_IDLE_EDGE : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (SPI_MEM_CK_IDLE_EDGE_V << SPI_MEM_CK_IDLE_EDGE_S) -#define SPI_MEM_CK_IDLE_EDGE_V 0x00000001U -#define SPI_MEM_CK_IDLE_EDGE_S 9 -/** SPI_MEM_CS_KEEP_ACTIVE : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (SPI_MEM_CS_KEEP_ACTIVE_V << SPI_MEM_CS_KEEP_ACTIVE_S) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x00000001U -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 - -/** SPI_MEM_CACHE_FCTRL_REG register - * SPI0 bit mode control register. - */ -#define SPI_MEM_CACHE_FCTRL_REG (DR_REG_SPI_BASE + 0x3c) -/** SPI_MEM_AXI_REQ_EN : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_AXI_REQ_EN (BIT(0)) -#define SPI_MEM_AXI_REQ_EN_M (SPI_MEM_AXI_REQ_EN_V << SPI_MEM_AXI_REQ_EN_S) -#define SPI_MEM_AXI_REQ_EN_V 0x00000001U -#define SPI_MEM_AXI_REQ_EN_S 0 -/** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_ADDR_4BYTE_S 1 -/** SPI_MEM_CACHE_FLASH_USR_CMD : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (SPI_MEM_CACHE_FLASH_USR_CMD_V << SPI_MEM_CACHE_FLASH_USR_CMD_S) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x00000001U -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 -/** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) -#define SPI_MEM_FDIN_DUAL_V 0x00000001U -#define SPI_MEM_FDIN_DUAL_S 3 -/** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) -#define SPI_MEM_FDOUT_DUAL_V 0x00000001U -#define SPI_MEM_FDOUT_DUAL_S 4 -/** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) -#define SPI_MEM_FADDR_DUAL_V 0x00000001U -#define SPI_MEM_FADDR_DUAL_S 5 -/** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) -#define SPI_MEM_FDIN_QUAD_V 0x00000001U -#define SPI_MEM_FDIN_QUAD_S 6 -/** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) -#define SPI_MEM_FDOUT_QUAD_V 0x00000001U -#define SPI_MEM_FDOUT_QUAD_S 7 -/** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) -#define SPI_MEM_FADDR_QUAD_V 0x00000001U -#define SPI_MEM_FADDR_QUAD_S 8 -/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ -#define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_M (SPI_SAME_AW_AR_ADDR_CHK_EN_V << SPI_SAME_AW_AR_ADDR_CHK_EN_S) -#define SPI_SAME_AW_AR_ADDR_CHK_EN_V 0x00000001U -#define SPI_SAME_AW_AR_ADDR_CHK_EN_S 30 -/** SPI_CLOSE_AXI_INF_EN : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ -#define SPI_CLOSE_AXI_INF_EN (BIT(31)) -#define SPI_CLOSE_AXI_INF_EN_M (SPI_CLOSE_AXI_INF_EN_V << SPI_CLOSE_AXI_INF_EN_S) -#define SPI_CLOSE_AXI_INF_EN_V 0x00000001U -#define SPI_CLOSE_AXI_INF_EN_S 31 - -/** SPI_MEM_CACHE_SCTRL_REG register - * SPI0 external RAM control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_CACHE_SCTRL_REG (DR_REG_SPI_BASE + 0x40) -/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_USR_SADDR_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U -#define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) -#define SPI_MEM_USR_SRAM_DIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_DIO_S 1 -/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) -#define SPI_MEM_USR_SRAM_QIO_V 0x00000001U -#define SPI_MEM_USR_SRAM_QIO_S 2 -/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; - * reserved - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) -#define SPI_MEM_SRAM_OCT_V 0x00000001U -#define SPI_MEM_SRAM_OCT_S 21 -/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003FU -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M (SPI_MEM_SRAM_WDUMMY_CYCLELEN_V << SPI_MEM_SRAM_WDUMMY_CYCLELEN_S) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x0000003FU -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 - -/** SPI_MEM_SRAM_CMD_REG register - * SPI0 external RAM mode control register - */ -#define SPI_MEM_SRAM_CMD_REG (DR_REG_SPI_BASE + 0x44) -/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLK_MODE 0x00000003U -#define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) -#define SPI_MEM_SCLK_MODE_V 0x00000003U -#define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SWB_MODE 0x000000FFU -#define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) -#define SPI_MEM_SWB_MODE_V 0x000000FFU -#define SPI_MEM_SWB_MODE_S 2 -/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) -#define SPI_MEM_SDIN_DUAL_V 0x00000001U -#define SPI_MEM_SDIN_DUAL_S 10 -/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) -#define SPI_MEM_SDOUT_DUAL_V 0x00000001U -#define SPI_MEM_SDOUT_DUAL_S 11 -/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) -#define SPI_MEM_SADDR_DUAL_V 0x00000001U -#define SPI_MEM_SADDR_DUAL_S 12 -/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) -#define SPI_MEM_SDIN_QUAD_V 0x00000001U -#define SPI_MEM_SDIN_QUAD_S 14 -/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) -#define SPI_MEM_SDOUT_QUAD_V 0x00000001U -#define SPI_MEM_SDOUT_QUAD_S 15 -/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) -#define SPI_MEM_SADDR_QUAD_V 0x00000001U -#define SPI_MEM_SADDR_QUAD_S 16 -/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) -#define SPI_MEM_SCMD_QUAD_V 0x00000001U -#define SPI_MEM_SCMD_QUAD_S 17 -/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) -#define SPI_MEM_SDIN_OCT_V 0x00000001U -#define SPI_MEM_SDIN_OCT_S 18 -/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) -#define SPI_MEM_SDOUT_OCT_V 0x00000001U -#define SPI_MEM_SDOUT_OCT_S 19 -/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) -#define SPI_MEM_SADDR_OCT_V 0x00000001U -#define SPI_MEM_SADDR_OCT_S 20 -/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (SPI_MEM_SCMD_OCT_V << SPI_MEM_SCMD_OCT_S) -#define SPI_MEM_SCMD_OCT_V 0x00000001U -#define SPI_MEM_SCMD_OCT_S 21 -/** SPI_MEM_SDUMMY_RIN : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDUMMY_RIN (BIT(22)) -#define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) -#define SPI_MEM_SDUMMY_RIN_V 0x00000001U -#define SPI_MEM_SDUMMY_RIN_S 22 -/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDUMMY_WOUT (BIT(23)) -#define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) -#define SPI_MEM_SDUMMY_WOUT_V 0x00000001U -#define SPI_MEM_SDUMMY_WOUT_S 23 -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT (BIT(24)) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ -#define SPI_SMEM_WDUMMY_ALWAYS_OUT (BIT(25)) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U -#define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_MEM_SDIN_HEX : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDIN_HEX (BIT(26)) -#define SPI_MEM_SDIN_HEX_M (SPI_MEM_SDIN_HEX_V << SPI_MEM_SDIN_HEX_S) -#define SPI_MEM_SDIN_HEX_V 0x00000001U -#define SPI_MEM_SDIN_HEX_S 26 -/** SPI_MEM_SDOUT_HEX : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SDOUT_HEX (BIT(27)) -#define SPI_MEM_SDOUT_HEX_M (SPI_MEM_SDOUT_HEX_V << SPI_MEM_SDOUT_HEX_S) -#define SPI_MEM_SDOUT_HEX_V 0x00000001U -#define SPI_MEM_SDOUT_HEX_S 27 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ -#define SPI_SMEM_DQS_IE_ALWAYS_ON (BIT(30)) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) -#define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ -#define SPI_SMEM_DATA_IE_ALWAYS_ON (BIT(31)) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_M (SPI_SMEM_DATA_IE_ALWAYS_ON_V << SPI_SMEM_DATA_IE_ALWAYS_ON_S) -#define SPI_SMEM_DATA_IE_ALWAYS_ON_V 0x00000001U -#define SPI_SMEM_DATA_IE_ALWAYS_ON_S 31 - -/** SPI_MEM_SRAM_DRD_CMD_REG register - * SPI0 external RAM DDR read command control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_DRD_CMD_REG (DR_REG_SPI_BASE + 0x48) -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 - -/** SPI_MEM_SRAM_DWR_CMD_REG register - * SPI0 external RAM DDR write command control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_DWR_CMD_REG (DR_REG_SPI_BASE + 0x4c) -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0x0000000FU -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 - -/** SPI_MEM_SRAM_CLK_REG register - * SPI0 external RAM clock control register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_SRAM_CLK_REG (DR_REG_SPI_BASE + 0x50) -/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_L 0x000000FFU -#define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) -#define SPI_MEM_SCLKCNT_L_V 0x000000FFU -#define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_H 0x000000FFU -#define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) -#define SPI_MEM_SCLKCNT_H_V 0x000000FFU -#define SPI_MEM_SCLKCNT_H_S 8 -/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(SPI_MEM_SCLKCNT_N+1) - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLKCNT_N 0x000000FFU -#define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) -#define SPI_MEM_SCLKCNT_N_V 0x000000FFU -#define SPI_MEM_SCLKCNT_N_S 16 -/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk - * is divided from system clock. - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (SPI_MEM_SCLK_EQU_SYSCLK_V << SPI_MEM_SCLK_EQU_SYSCLK_S) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x00000001U -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 - -/** SPI_MEM_FSM_REG register - * SPI0 FSM status register - */ -#define SPI_MEM_FSM_REG (DR_REG_SPI_BASE + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ -#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU -#define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU -#define SPI_MEM_LOCK_DELAY_TIME_S 7 -/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ -#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) -#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) -#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U -#define SPI_MEM_FLASH_LOCK_EN_S 19 -/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ -#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) -#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) -#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U -#define SPI_MEM_SRAM_LOCK_EN_S 20 - -/** SPI_MEM_INT_ENA_REG register - * SPI0 interrupt enable register - */ -#define SPI_MEM_INT_ENA_REG (DR_REG_SPI_BASE + 0xc0) -/** SPI_MEM_SLV_ST_END_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ENA (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ENA_M (SPI_MEM_SLV_ST_END_INT_ENA_V << SPI_MEM_SLV_ST_END_INT_ENA_S) -#define SPI_MEM_SLV_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ENA_S 3 -/** SPI_MEM_MST_ST_END_INT_ENA : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ENA (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) -#define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (SPI_MEM_ECC_ERR_INT_ENA_V << SPI_MEM_ECC_ERR_INT_ENA_S) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ENA_S 5 -/** SPI_MEM_PMS_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ENA (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ENA_M (SPI_MEM_PMS_REJECT_INT_ENA_V << SPI_MEM_PMS_REJECT_INT_ENA_S) -#define SPI_MEM_PMS_REJECT_INT_ENA_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ENA_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 - -/** SPI_MEM_INT_CLR_REG register - * SPI0 interrupt clear register - */ -#define SPI_MEM_INT_CLR_REG (DR_REG_SPI_BASE + 0xc4) -/** SPI_MEM_SLV_ST_END_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_CLR (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_CLR_M (SPI_MEM_SLV_ST_END_INT_CLR_V << SPI_MEM_SLV_ST_END_INT_CLR_S) -#define SPI_MEM_SLV_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_CLR_S 3 -/** SPI_MEM_MST_ST_END_INT_CLR : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_CLR (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) -#define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (SPI_MEM_ECC_ERR_INT_CLR_V << SPI_MEM_ECC_ERR_INT_CLR_S) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_CLR_S 5 -/** SPI_MEM_PMS_REJECT_INT_CLR : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_CLR (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_CLR_M (SPI_MEM_PMS_REJECT_INT_CLR_V << SPI_MEM_PMS_REJECT_INT_CLR_S) -#define SPI_MEM_PMS_REJECT_INT_CLR_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_CLR_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_CLR : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 - -/** SPI_MEM_INT_RAW_REG register - * SPI0 interrupt raw register - */ -#define SPI_MEM_INT_RAW_REG (DR_REG_SPI_BASE + 0xc8) -/** SPI_MEM_SLV_ST_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ -#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_RAW_M (SPI_MEM_SLV_ST_END_INT_RAW_V << SPI_MEM_SLV_ST_END_INT_RAW_S) -#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_RAW_S 3 -/** SPI_MEM_MST_ST_END_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ -#define SPI_MEM_MST_ST_END_INT_RAW (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) -#define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (SPI_MEM_ECC_ERR_INT_RAW_V << SPI_MEM_ECC_ERR_INT_RAW_S) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_RAW_S 5 -/** SPI_MEM_PMS_REJECT_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ -#define SPI_MEM_PMS_REJECT_INT_RAW (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_RAW_M (SPI_MEM_PMS_REJECT_INT_RAW_V << SPI_MEM_PMS_REJECT_INT_RAW_S) -#define SPI_MEM_PMS_REJECT_INT_RAW_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_RAW_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 - -/** SPI_MEM_INT_ST_REG register - * SPI0 interrupt status register - */ -#define SPI_MEM_INT_ST_REG (DR_REG_SPI_BASE + 0xcc) -/** SPI_MEM_SLV_ST_END_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ -#define SPI_MEM_SLV_ST_END_INT_ST (BIT(3)) -#define SPI_MEM_SLV_ST_END_INT_ST_M (SPI_MEM_SLV_ST_END_INT_ST_V << SPI_MEM_SLV_ST_END_INT_ST_S) -#define SPI_MEM_SLV_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_SLV_ST_END_INT_ST_S 3 -/** SPI_MEM_MST_ST_END_INT_ST : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ -#define SPI_MEM_MST_ST_END_INT_ST (BIT(4)) -#define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) -#define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U -#define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) -#define SPI_MEM_ECC_ERR_INT_ST_M (SPI_MEM_ECC_ERR_INT_ST_V << SPI_MEM_ECC_ERR_INT_ST_S) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_ECC_ERR_INT_ST_S 5 -/** SPI_MEM_PMS_REJECT_INT_ST : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ -#define SPI_MEM_PMS_REJECT_INT_ST (BIT(6)) -#define SPI_MEM_PMS_REJECT_INT_ST_M (SPI_MEM_PMS_REJECT_INT_ST_V << SPI_MEM_PMS_REJECT_INT_ST_S) -#define SPI_MEM_PMS_REJECT_INT_ST_V 0x00000001U -#define SPI_MEM_PMS_REJECT_INT_ST_S 6 -/** SPI_MEM_AXI_RADDR_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_RADDR_ERR_INT_ST (BIT(7)) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ -#define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U -#define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 -/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 -/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U -#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 -/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 -/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U -#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 - -/** SPI_MEM_DDR_REG register - * SPI0 flash DDR mode control register - */ -#define SPI_MEM_DDR_REG (DR_REG_SPI_BASE + 0xd4) -/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) -#define SPI_FMEM_DDR_EN_V 0x00000001U -#define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) -#define SPI_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) -#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) -#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) -#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ -#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) -#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ -#define SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) -#define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ -#define SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) -#define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) -#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) -#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) -#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) -#define SPI_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ -#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) -#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ -#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) -#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) -#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_FMEM_HYPERBUS_CA_S 30 - -/** SPI_SMEM_DDR_REG register - * SPI0 external RAM DDR mode control register - */ -#define SPI_SMEM_DDR_REG (DR_REG_SPI_BASE + 0xd8) -/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ -#define SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) -#define SPI_SMEM_DDR_EN_V 0x00000001U -#define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ -#define SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) -#define SPI_SMEM_VAR_DUMMY_V 0x00000001U -#define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) -#define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ -#define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) -#define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ -#define SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) -#define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ -#define SPI_SMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) -#define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) -#define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ -#define SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) -#define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U -#define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ -#define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) -#define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ -#define SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) -#define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ -#define SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) -#define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ -#define SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) -#define SPI_SMEM_DQS_CA_IN_V 0x00000001U -#define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ -#define SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ -#define SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) -#define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ -#define SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) -#define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ -#define SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_SMEM_HYPERBUS_CA_M (SPI_SMEM_HYPERBUS_CA_V << SPI_SMEM_HYPERBUS_CA_S) -#define SPI_SMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_SMEM_HYPERBUS_CA_S 30 - -/** SPI_FMEM_PMS0_ATTR_REG register - * SPI1 flash PMS section 0 attribute register - */ -#define SPI_FMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x100) -/** SPI_FMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS0_RD_ATTR_M (SPI_FMEM_PMS0_RD_ATTR_V << SPI_FMEM_PMS0_RD_ATTR_S) -#define SPI_FMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_RD_ATTR_S 0 -/** SPI_FMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS0_WR_ATTR_M (SPI_FMEM_PMS0_WR_ATTR_V << SPI_FMEM_PMS0_WR_ATTR_S) -#define SPI_FMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS0_WR_ATTR_S 1 -/** SPI_FMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 0 is configured by registers SPI_FMEM_PMS0_ADDR_REG and - * SPI_FMEM_PMS0_SIZE_REG. - */ -#define SPI_FMEM_PMS0_ECC (BIT(2)) -#define SPI_FMEM_PMS0_ECC_M (SPI_FMEM_PMS0_ECC_V << SPI_FMEM_PMS0_ECC_S) -#define SPI_FMEM_PMS0_ECC_V 0x00000001U -#define SPI_FMEM_PMS0_ECC_S 2 - -/** SPI_FMEM_PMS1_ATTR_REG register - * SPI1 flash PMS section 1 attribute register - */ -#define SPI_FMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x104) -/** SPI_FMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS1_RD_ATTR_M (SPI_FMEM_PMS1_RD_ATTR_V << SPI_FMEM_PMS1_RD_ATTR_S) -#define SPI_FMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_RD_ATTR_S 0 -/** SPI_FMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS1_WR_ATTR_M (SPI_FMEM_PMS1_WR_ATTR_V << SPI_FMEM_PMS1_WR_ATTR_S) -#define SPI_FMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS1_WR_ATTR_S 1 -/** SPI_FMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 1 is configured by registers SPI_FMEM_PMS1_ADDR_REG and - * SPI_FMEM_PMS1_SIZE_REG. - */ -#define SPI_FMEM_PMS1_ECC (BIT(2)) -#define SPI_FMEM_PMS1_ECC_M (SPI_FMEM_PMS1_ECC_V << SPI_FMEM_PMS1_ECC_S) -#define SPI_FMEM_PMS1_ECC_V 0x00000001U -#define SPI_FMEM_PMS1_ECC_S 2 - -/** SPI_FMEM_PMS2_ATTR_REG register - * SPI1 flash PMS section 2 attribute register - */ -#define SPI_FMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x108) -/** SPI_FMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS2_RD_ATTR_M (SPI_FMEM_PMS2_RD_ATTR_V << SPI_FMEM_PMS2_RD_ATTR_S) -#define SPI_FMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_RD_ATTR_S 0 -/** SPI_FMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS2_WR_ATTR_M (SPI_FMEM_PMS2_WR_ATTR_V << SPI_FMEM_PMS2_WR_ATTR_S) -#define SPI_FMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS2_WR_ATTR_S 1 -/** SPI_FMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 2 is configured by registers SPI_FMEM_PMS2_ADDR_REG and - * SPI_FMEM_PMS2_SIZE_REG. - */ -#define SPI_FMEM_PMS2_ECC (BIT(2)) -#define SPI_FMEM_PMS2_ECC_M (SPI_FMEM_PMS2_ECC_V << SPI_FMEM_PMS2_ECC_S) -#define SPI_FMEM_PMS2_ECC_V 0x00000001U -#define SPI_FMEM_PMS2_ECC_S 2 - -/** SPI_FMEM_PMS3_ATTR_REG register - * SPI1 flash PMS section 3 attribute register - */ -#define SPI_FMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x10c) -/** SPI_FMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_FMEM_PMS3_RD_ATTR_M (SPI_FMEM_PMS3_RD_ATTR_V << SPI_FMEM_PMS3_RD_ATTR_S) -#define SPI_FMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_RD_ATTR_S 0 -/** SPI_FMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_FMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_FMEM_PMS3_WR_ATTR_M (SPI_FMEM_PMS3_WR_ATTR_V << SPI_FMEM_PMS3_WR_ATTR_S) -#define SPI_FMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_FMEM_PMS3_WR_ATTR_S 1 -/** SPI_FMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section 3 is configured by registers SPI_FMEM_PMS3_ADDR_REG and - * SPI_FMEM_PMS3_SIZE_REG. - */ -#define SPI_FMEM_PMS3_ECC (BIT(2)) -#define SPI_FMEM_PMS3_ECC_M (SPI_FMEM_PMS3_ECC_V << SPI_FMEM_PMS3_ECC_S) -#define SPI_FMEM_PMS3_ECC_V 0x00000001U -#define SPI_FMEM_PMS3_ECC_S 2 - -/** SPI_FMEM_PMS0_ADDR_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 0 start address value - */ -#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS0_ADDR_S_S 0 - -/** SPI_FMEM_PMS1_ADDR_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 1 start address value - */ -#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS1_ADDR_S_S 0 - -/** SPI_FMEM_PMS2_ADDR_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 2 start address value - */ -#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS2_ADDR_S_S 0 - -/** SPI_FMEM_PMS3_ADDR_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section 3 start address value - */ -#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_FMEM_PMS3_ADDR_S_S 0 - -/** SPI_FMEM_PMS0_SIZE_REG register - * SPI1 flash PMS section 0 start address register - */ -#define SPI_FMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, - * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) - */ -#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS0_SIZE_S 0 - -/** SPI_FMEM_PMS1_SIZE_REG register - * SPI1 flash PMS section 1 start address register - */ -#define SPI_FMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, - * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) - */ -#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS1_SIZE_S 0 - -/** SPI_FMEM_PMS2_SIZE_REG register - * SPI1 flash PMS section 2 start address register - */ -#define SPI_FMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, - * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) - */ -#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS2_SIZE_S 0 - -/** SPI_FMEM_PMS3_SIZE_REG register - * SPI1 flash PMS section 3 start address register - */ -#define SPI_FMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, - * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) - */ -#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_FMEM_PMS3_SIZE_S 0 - -/** SPI_SMEM_PMS0_ATTR_REG register - * SPI1 external RAM PMS section 0 attribute register - */ -#define SPI_SMEM_PMS0_ATTR_REG (DR_REG_SPI_BASE + 0x130) -/** SPI_SMEM_PMS0_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 0 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS0_RD_ATTR_M (SPI_SMEM_PMS0_RD_ATTR_V << SPI_SMEM_PMS0_RD_ATTR_S) -#define SPI_SMEM_PMS0_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_RD_ATTR_S 0 -/** SPI_SMEM_PMS0_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 0 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS0_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS0_WR_ATTR_M (SPI_SMEM_PMS0_WR_ATTR_V << SPI_SMEM_PMS0_WR_ATTR_S) -#define SPI_SMEM_PMS0_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS0_WR_ATTR_S 1 -/** SPI_SMEM_PMS0_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 0 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 0 is configured by registers SPI_SMEM_PMS0_ADDR_REG and - * SPI_SMEM_PMS0_SIZE_REG. - */ -#define SPI_SMEM_PMS0_ECC (BIT(2)) -#define SPI_SMEM_PMS0_ECC_M (SPI_SMEM_PMS0_ECC_V << SPI_SMEM_PMS0_ECC_S) -#define SPI_SMEM_PMS0_ECC_V 0x00000001U -#define SPI_SMEM_PMS0_ECC_S 2 - -/** SPI_SMEM_PMS1_ATTR_REG register - * SPI1 external RAM PMS section 1 attribute register - */ -#define SPI_SMEM_PMS1_ATTR_REG (DR_REG_SPI_BASE + 0x134) -/** SPI_SMEM_PMS1_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 1 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS1_RD_ATTR_M (SPI_SMEM_PMS1_RD_ATTR_V << SPI_SMEM_PMS1_RD_ATTR_S) -#define SPI_SMEM_PMS1_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_RD_ATTR_S 0 -/** SPI_SMEM_PMS1_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 1 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS1_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS1_WR_ATTR_M (SPI_SMEM_PMS1_WR_ATTR_V << SPI_SMEM_PMS1_WR_ATTR_S) -#define SPI_SMEM_PMS1_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS1_WR_ATTR_S 1 -/** SPI_SMEM_PMS1_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 1 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 1 is configured by registers SPI_SMEM_PMS1_ADDR_REG and - * SPI_SMEM_PMS1_SIZE_REG. - */ -#define SPI_SMEM_PMS1_ECC (BIT(2)) -#define SPI_SMEM_PMS1_ECC_M (SPI_SMEM_PMS1_ECC_V << SPI_SMEM_PMS1_ECC_S) -#define SPI_SMEM_PMS1_ECC_V 0x00000001U -#define SPI_SMEM_PMS1_ECC_S 2 - -/** SPI_SMEM_PMS2_ATTR_REG register - * SPI1 external RAM PMS section 2 attribute register - */ -#define SPI_SMEM_PMS2_ATTR_REG (DR_REG_SPI_BASE + 0x138) -/** SPI_SMEM_PMS2_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 2 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS2_RD_ATTR_M (SPI_SMEM_PMS2_RD_ATTR_V << SPI_SMEM_PMS2_RD_ATTR_S) -#define SPI_SMEM_PMS2_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_RD_ATTR_S 0 -/** SPI_SMEM_PMS2_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 2 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS2_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS2_WR_ATTR_M (SPI_SMEM_PMS2_WR_ATTR_V << SPI_SMEM_PMS2_WR_ATTR_S) -#define SPI_SMEM_PMS2_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS2_WR_ATTR_S 1 -/** SPI_SMEM_PMS2_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 2 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 2 is configured by registers SPI_SMEM_PMS2_ADDR_REG and - * SPI_SMEM_PMS2_SIZE_REG. - */ -#define SPI_SMEM_PMS2_ECC (BIT(2)) -#define SPI_SMEM_PMS2_ECC_M (SPI_SMEM_PMS2_ECC_V << SPI_SMEM_PMS2_ECC_S) -#define SPI_SMEM_PMS2_ECC_V 0x00000001U -#define SPI_SMEM_PMS2_ECC_S 2 - -/** SPI_SMEM_PMS3_ATTR_REG register - * SPI1 external RAM PMS section 3 attribute register - */ -#define SPI_SMEM_PMS3_ATTR_REG (DR_REG_SPI_BASE + 0x13c) -/** SPI_SMEM_PMS3_RD_ATTR : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section 3 read accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_RD_ATTR (BIT(0)) -#define SPI_SMEM_PMS3_RD_ATTR_M (SPI_SMEM_PMS3_RD_ATTR_V << SPI_SMEM_PMS3_RD_ATTR_S) -#define SPI_SMEM_PMS3_RD_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_RD_ATTR_S 0 -/** SPI_SMEM_PMS3_WR_ATTR : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section 3 write accessible. 0: Not allowed. - */ -#define SPI_SMEM_PMS3_WR_ATTR (BIT(1)) -#define SPI_SMEM_PMS3_WR_ATTR_M (SPI_SMEM_PMS3_WR_ATTR_V << SPI_SMEM_PMS3_WR_ATTR_S) -#define SPI_SMEM_PMS3_WR_ATTR_V 0x00000001U -#define SPI_SMEM_PMS3_WR_ATTR_S 1 -/** SPI_SMEM_PMS3_ECC : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section 3 ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section 3 is configured by registers SPI_SMEM_PMS3_ADDR_REG and - * SPI_SMEM_PMS3_SIZE_REG. - */ -#define SPI_SMEM_PMS3_ECC (BIT(2)) -#define SPI_SMEM_PMS3_ECC_M (SPI_SMEM_PMS3_ECC_V << SPI_SMEM_PMS3_ECC_S) -#define SPI_SMEM_PMS3_ECC_V 0x00000001U -#define SPI_SMEM_PMS3_ECC_S 2 - -/** SPI_SMEM_PMS0_ADDR_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_ADDR_REG (DR_REG_SPI_BASE + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 0 start address value - */ -#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS0_ADDR_S_S 0 - -/** SPI_SMEM_PMS1_ADDR_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_ADDR_REG (DR_REG_SPI_BASE + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 1 start address value - */ -#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS1_ADDR_S_S 0 - -/** SPI_SMEM_PMS2_ADDR_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_ADDR_REG (DR_REG_SPI_BASE + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 2 start address value - */ -#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS2_ADDR_S_S 0 - -/** SPI_SMEM_PMS3_ADDR_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_ADDR_REG (DR_REG_SPI_BASE + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section 3 start address value - */ -#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU -#define SPI_SMEM_PMS3_ADDR_S_S 0 - -/** SPI_SMEM_PMS0_SIZE_REG register - * SPI1 external RAM PMS section 0 start address register - */ -#define SPI_SMEM_PMS0_SIZE_REG (DR_REG_SPI_BASE + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, - * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) - */ -#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS0_SIZE_S 0 - -/** SPI_SMEM_PMS1_SIZE_REG register - * SPI1 external RAM PMS section 1 start address register - */ -#define SPI_SMEM_PMS1_SIZE_REG (DR_REG_SPI_BASE + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, - * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) - */ -#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS1_SIZE_S 0 - -/** SPI_SMEM_PMS2_SIZE_REG register - * SPI1 external RAM PMS section 2 start address register - */ -#define SPI_SMEM_PMS2_SIZE_REG (DR_REG_SPI_BASE + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, - * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) - */ -#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS2_SIZE_S 0 - -/** SPI_SMEM_PMS3_SIZE_REG register - * SPI1 external RAM PMS section 3 start address register - */ -#define SPI_SMEM_PMS3_SIZE_REG (DR_REG_SPI_BASE + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, - * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) - */ -#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU -#define SPI_SMEM_PMS3_SIZE_S 0 - -/** SPI_MEM_PMS_REJECT_REG register - * SPI1 access reject register - */ -#define SPI_MEM_PMS_REJECT_REG (DR_REG_SPI_BASE + 0x160) -/** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ -#define SPI_MEM_PM_EN (BIT(27)) -#define SPI_MEM_PM_EN_M (SPI_MEM_PM_EN_V << SPI_MEM_PM_EN_S) -#define SPI_MEM_PM_EN_V 0x00000001U -#define SPI_MEM_PM_EN_S 27 -/** SPI_MEM_PMS_LD : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_LD (BIT(28)) -#define SPI_MEM_PMS_LD_M (SPI_MEM_PMS_LD_V << SPI_MEM_PMS_LD_S) -#define SPI_MEM_PMS_LD_V 0x00000001U -#define SPI_MEM_PMS_LD_S 28 -/** SPI_MEM_PMS_ST : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_ST (BIT(29)) -#define SPI_MEM_PMS_ST_M (SPI_MEM_PMS_ST_V << SPI_MEM_PMS_ST_S) -#define SPI_MEM_PMS_ST_V 0x00000001U -#define SPI_MEM_PMS_ST_S 29 -/** SPI_MEM_PMS_MULTI_HIT : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_MULTI_HIT (BIT(30)) -#define SPI_MEM_PMS_MULTI_HIT_M (SPI_MEM_PMS_MULTI_HIT_V << SPI_MEM_PMS_MULTI_HIT_S) -#define SPI_MEM_PMS_MULTI_HIT_V 0x00000001U -#define SPI_MEM_PMS_MULTI_HIT_S 30 -/** SPI_MEM_PMS_IVD : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_PMS_IVD (BIT(31)) -#define SPI_MEM_PMS_IVD_M (SPI_MEM_PMS_IVD_V << SPI_MEM_PMS_IVD_S) -#define SPI_MEM_PMS_IVD_V 0x00000001U -#define SPI_MEM_PMS_IVD_S 31 - -/** SPI_MEM_PMS_REJECT_ADDR_REG register - * SPI1 access reject addr register - */ -#define SPI_MEM_PMS_REJECT_ADDR_REG (DR_REG_SPI_BASE + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_REJECT_ADDR_S 0 - -/** SPI_MEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_MEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x168) -/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_CNT 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) -#define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU -#define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ -#define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) -#define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU -#define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ -#define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_FMEM_ECC_ERR_INT_EN_M (SPI_FMEM_ECC_ERR_INT_EN_V << SPI_FMEM_ECC_ERR_INT_EN_S) -#define SPI_FMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_FMEM_ECC_ERR_INT_EN_S 17 -/** SPI_FMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ -#define SPI_FMEM_PAGE_SIZE 0x00000003U -#define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) -#define SPI_FMEM_PAGE_SIZE_V 0x00000003U -#define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) -#define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) -#define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 21 -/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) -#define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) -#define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 22 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN (BIT(24)) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U -#define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ -#define SPI_MEM_ECC_ERR_BITS 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_M (SPI_MEM_ECC_ERR_BITS_V << SPI_MEM_ECC_ERR_BITS_S) -#define SPI_MEM_ECC_ERR_BITS_V 0x0000007FU -#define SPI_MEM_ECC_ERR_BITS_S 25 - -/** SPI_MEM_ECC_ERR_ADDR_REG register - * MSPI ECC error address register - */ -#define SPI_MEM_ECC_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ -#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_ECC_ERR_ADDR_S 0 - -/** SPI_MEM_AXI_ERR_ADDR_REG register - * SPI0 AXI request error address. - */ -#define SPI_MEM_AXI_ERR_ADDR_REG (DR_REG_SPI_BASE + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ -#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU -#define SPI_MEM_AXI_ERR_ADDR_S 0 - -/** SPI_SMEM_ECC_CTRL_REG register - * MSPI ECC control register - */ -#define SPI_SMEM_ECC_CTRL_REG (DR_REG_SPI_BASE + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ -#define SPI_SMEM_ECC_ERR_INT_EN (BIT(17)) -#define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) -#define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U -#define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ -#define SPI_SMEM_PAGE_SIZE 0x00000003U -#define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) -#define SPI_SMEM_PAGE_SIZE_V 0x00000003U -#define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ -#define SPI_SMEM_ECC_ADDR_EN (BIT(20)) -#define SPI_SMEM_ECC_ADDR_EN_M (SPI_SMEM_ECC_ADDR_EN_V << SPI_SMEM_ECC_ADDR_EN_S) -#define SPI_SMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_SMEM_ECC_ADDR_EN_S 20 - -/** SPI_SMEM_AXI_ADDR_CTRL_REG register - * SPI0 AXI address control register - */ -#define SPI_SMEM_AXI_ADDR_CTRL_REG (DR_REG_SPI_BASE + 0x178) -/** SPI_MEM_ALL_FIFO_EMPTY : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ -#define SPI_MEM_ALL_FIFO_EMPTY (BIT(26)) -#define SPI_MEM_ALL_FIFO_EMPTY_M (SPI_MEM_ALL_FIFO_EMPTY_V << SPI_MEM_ALL_FIFO_EMPTY_S) -#define SPI_MEM_ALL_FIFO_EMPTY_V 0x00000001U -#define SPI_MEM_ALL_FIFO_EMPTY_S 26 -/** SPI_RDATA_AFIFO_REMPTY : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RDATA_AFIFO_REMPTY (BIT(27)) -#define SPI_RDATA_AFIFO_REMPTY_M (SPI_RDATA_AFIFO_REMPTY_V << SPI_RDATA_AFIFO_REMPTY_S) -#define SPI_RDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_RDATA_AFIFO_REMPTY_S 27 -/** SPI_RADDR_AFIFO_REMPTY : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ -#define SPI_RADDR_AFIFO_REMPTY (BIT(28)) -#define SPI_RADDR_AFIFO_REMPTY_M (SPI_RADDR_AFIFO_REMPTY_V << SPI_RADDR_AFIFO_REMPTY_S) -#define SPI_RADDR_AFIFO_REMPTY_V 0x00000001U -#define SPI_RADDR_AFIFO_REMPTY_S 28 -/** SPI_WDATA_AFIFO_REMPTY : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WDATA_AFIFO_REMPTY (BIT(29)) -#define SPI_WDATA_AFIFO_REMPTY_M (SPI_WDATA_AFIFO_REMPTY_V << SPI_WDATA_AFIFO_REMPTY_S) -#define SPI_WDATA_AFIFO_REMPTY_V 0x00000001U -#define SPI_WDATA_AFIFO_REMPTY_S 29 -/** SPI_WBLEN_AFIFO_REMPTY : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ -#define SPI_WBLEN_AFIFO_REMPTY (BIT(30)) -#define SPI_WBLEN_AFIFO_REMPTY_M (SPI_WBLEN_AFIFO_REMPTY_V << SPI_WBLEN_AFIFO_REMPTY_S) -#define SPI_WBLEN_AFIFO_REMPTY_V 0x00000001U -#define SPI_WBLEN_AFIFO_REMPTY_S 30 -/** SPI_ALL_AXI_TRANS_AFIFO_EMPTY : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY (BIT(31)) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_M (SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V << SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S) -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_V 0x00000001U -#define SPI_ALL_AXI_TRANS_AFIFO_EMPTY_S 31 - -/** SPI_MEM_AXI_ERR_RESP_EN_REG register - * SPI0 AXI error response enable register - */ -#define SPI_MEM_AXI_ERR_RESP_EN_REG (DR_REG_SPI_BASE + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) -#define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) -#define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_M (SPI_MEM_AW_RESP_EN_AXI_WSTRB_V << SPI_MEM_AW_RESP_EN_AXI_WSTRB_S) -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_V 0x00000001U -#define SPI_MEM_AW_RESP_EN_AXI_WSTRB_S 6 -/** SPI_MEM_AR_RESP_EN_MMU_VLD : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_VLD (BIT(7)) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_M (SPI_MEM_AR_RESP_EN_MMU_VLD_V << SPI_MEM_AR_RESP_EN_MMU_VLD_S) -#define SPI_MEM_AR_RESP_EN_MMU_VLD_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_VLD_S 7 -/** SPI_MEM_AR_RESP_EN_MMU_GID : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_GID (BIT(8)) -#define SPI_MEM_AR_RESP_EN_MMU_GID_M (SPI_MEM_AR_RESP_EN_MMU_GID_V << SPI_MEM_AR_RESP_EN_MMU_GID_S) -#define SPI_MEM_AR_RESP_EN_MMU_GID_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_GID_S 8 -/** SPI_MEM_AR_RESP_EN_MMU_ECC : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_ECC (BIT(9)) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_M (SPI_MEM_AR_RESP_EN_MMU_ECC_V << SPI_MEM_AR_RESP_EN_MMU_ECC_S) -#define SPI_MEM_AR_RESP_EN_MMU_ECC_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_ECC_S 9 -/** SPI_MEM_AR_RESP_EN_MMU_SENS : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ -#define SPI_MEM_AR_RESP_EN_MMU_SENS (BIT(10)) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_M (SPI_MEM_AR_RESP_EN_MMU_SENS_V << SPI_MEM_AR_RESP_EN_MMU_SENS_S) -#define SPI_MEM_AR_RESP_EN_MMU_SENS_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_MMU_SENS_S 10 -/** SPI_MEM_AR_RESP_EN_AXI_SIZE : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ -#define SPI_MEM_AR_RESP_EN_AXI_SIZE (BIT(11)) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_M (SPI_MEM_AR_RESP_EN_AXI_SIZE_V << SPI_MEM_AR_RESP_EN_AXI_SIZE_S) -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_V 0x00000001U -#define SPI_MEM_AR_RESP_EN_AXI_SIZE_S 11 - -/** SPI_MEM_TIMING_CALI_REG register - * SPI0 flash timing calibration register - */ -#define SPI_MEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x180) -/** SPI_MEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (SPI_MEM_TIMING_CLK_ENA_V << SPI_MEM_TIMING_CLK_ENA_S) -#define SPI_MEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_MEM_TIMING_CLK_ENA_S 0 -/** SPI_MEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (SPI_MEM_TIMING_CALI_V << SPI_MEM_TIMING_CALI_S) -#define SPI_MEM_TIMING_CALI_V 0x00000001U -#define SPI_MEM_TIMING_CALI_S 1 -/** SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ -#define SPI_MEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_MEM_DLL_TIMING_CALI_M (SPI_MEM_DLL_TIMING_CALI_V << SPI_MEM_DLL_TIMING_CALI_S) -#define SPI_MEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_MEM_DLL_TIMING_CALI_S 5 -/** SPI_MEM_TIMING_CALI_UPDATE : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ -#define SPI_MEM_TIMING_CALI_UPDATE (BIT(6)) -#define SPI_MEM_TIMING_CALI_UPDATE_M (SPI_MEM_TIMING_CALI_UPDATE_V << SPI_MEM_TIMING_CALI_UPDATE_S) -#define SPI_MEM_TIMING_CALI_UPDATE_V 0x00000001U -#define SPI_MEM_TIMING_CALI_UPDATE_S 6 - -/** SPI_MEM_DIN_MODE_REG register - * MSPI flash input timing delay mode control register - */ -#define SPI_MEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x184) -/** SPI_MEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN0_MODE 0x00000007U -#define SPI_MEM_DIN0_MODE_M (SPI_MEM_DIN0_MODE_V << SPI_MEM_DIN0_MODE_S) -#define SPI_MEM_DIN0_MODE_V 0x00000007U -#define SPI_MEM_DIN0_MODE_S 0 -/** SPI_MEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN1_MODE 0x00000007U -#define SPI_MEM_DIN1_MODE_M (SPI_MEM_DIN1_MODE_V << SPI_MEM_DIN1_MODE_S) -#define SPI_MEM_DIN1_MODE_V 0x00000007U -#define SPI_MEM_DIN1_MODE_S 3 -/** SPI_MEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN2_MODE 0x00000007U -#define SPI_MEM_DIN2_MODE_M (SPI_MEM_DIN2_MODE_V << SPI_MEM_DIN2_MODE_S) -#define SPI_MEM_DIN2_MODE_V 0x00000007U -#define SPI_MEM_DIN2_MODE_S 6 -/** SPI_MEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_MEM_DIN3_MODE 0x00000007U -#define SPI_MEM_DIN3_MODE_M (SPI_MEM_DIN3_MODE_V << SPI_MEM_DIN3_MODE_S) -#define SPI_MEM_DIN3_MODE_V 0x00000007U -#define SPI_MEM_DIN3_MODE_S 9 -/** SPI_MEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN4_MODE 0x00000007U -#define SPI_MEM_DIN4_MODE_M (SPI_MEM_DIN4_MODE_V << SPI_MEM_DIN4_MODE_S) -#define SPI_MEM_DIN4_MODE_V 0x00000007U -#define SPI_MEM_DIN4_MODE_S 12 -/** SPI_MEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN5_MODE 0x00000007U -#define SPI_MEM_DIN5_MODE_M (SPI_MEM_DIN5_MODE_V << SPI_MEM_DIN5_MODE_S) -#define SPI_MEM_DIN5_MODE_V 0x00000007U -#define SPI_MEM_DIN5_MODE_S 15 -/** SPI_MEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN6_MODE 0x00000007U -#define SPI_MEM_DIN6_MODE_M (SPI_MEM_DIN6_MODE_V << SPI_MEM_DIN6_MODE_S) -#define SPI_MEM_DIN6_MODE_V 0x00000007U -#define SPI_MEM_DIN6_MODE_S 18 -/** SPI_MEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DIN7_MODE 0x00000007U -#define SPI_MEM_DIN7_MODE_M (SPI_MEM_DIN7_MODE_V << SPI_MEM_DIN7_MODE_S) -#define SPI_MEM_DIN7_MODE_V 0x00000007U -#define SPI_MEM_DIN7_MODE_S 21 -/** SPI_MEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ -#define SPI_MEM_DINS_MODE 0x00000007U -#define SPI_MEM_DINS_MODE_M (SPI_MEM_DINS_MODE_V << SPI_MEM_DINS_MODE_S) -#define SPI_MEM_DINS_MODE_V 0x00000007U -#define SPI_MEM_DINS_MODE_S 24 - -/** SPI_MEM_DIN_NUM_REG register - * MSPI flash input timing delay number control register - */ -#define SPI_MEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x188) -/** SPI_MEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN0_NUM 0x00000003U -#define SPI_MEM_DIN0_NUM_M (SPI_MEM_DIN0_NUM_V << SPI_MEM_DIN0_NUM_S) -#define SPI_MEM_DIN0_NUM_V 0x00000003U -#define SPI_MEM_DIN0_NUM_S 0 -/** SPI_MEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN1_NUM 0x00000003U -#define SPI_MEM_DIN1_NUM_M (SPI_MEM_DIN1_NUM_V << SPI_MEM_DIN1_NUM_S) -#define SPI_MEM_DIN1_NUM_V 0x00000003U -#define SPI_MEM_DIN1_NUM_S 2 -/** SPI_MEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN2_NUM 0x00000003U -#define SPI_MEM_DIN2_NUM_M (SPI_MEM_DIN2_NUM_V << SPI_MEM_DIN2_NUM_S) -#define SPI_MEM_DIN2_NUM_V 0x00000003U -#define SPI_MEM_DIN2_NUM_S 4 -/** SPI_MEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN3_NUM 0x00000003U -#define SPI_MEM_DIN3_NUM_M (SPI_MEM_DIN3_NUM_V << SPI_MEM_DIN3_NUM_S) -#define SPI_MEM_DIN3_NUM_V 0x00000003U -#define SPI_MEM_DIN3_NUM_S 6 -/** SPI_MEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN4_NUM 0x00000003U -#define SPI_MEM_DIN4_NUM_M (SPI_MEM_DIN4_NUM_V << SPI_MEM_DIN4_NUM_S) -#define SPI_MEM_DIN4_NUM_V 0x00000003U -#define SPI_MEM_DIN4_NUM_S 8 -/** SPI_MEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN5_NUM 0x00000003U -#define SPI_MEM_DIN5_NUM_M (SPI_MEM_DIN5_NUM_V << SPI_MEM_DIN5_NUM_S) -#define SPI_MEM_DIN5_NUM_V 0x00000003U -#define SPI_MEM_DIN5_NUM_S 10 -/** SPI_MEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN6_NUM 0x00000003U -#define SPI_MEM_DIN6_NUM_M (SPI_MEM_DIN6_NUM_V << SPI_MEM_DIN6_NUM_S) -#define SPI_MEM_DIN6_NUM_V 0x00000003U -#define SPI_MEM_DIN6_NUM_S 12 -/** SPI_MEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DIN7_NUM 0x00000003U -#define SPI_MEM_DIN7_NUM_M (SPI_MEM_DIN7_NUM_V << SPI_MEM_DIN7_NUM_S) -#define SPI_MEM_DIN7_NUM_V 0x00000003U -#define SPI_MEM_DIN7_NUM_S 14 -/** SPI_MEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_MEM_DINS_NUM 0x00000003U -#define SPI_MEM_DINS_NUM_M (SPI_MEM_DINS_NUM_V << SPI_MEM_DINS_NUM_S) -#define SPI_MEM_DINS_NUM_V 0x00000003U -#define SPI_MEM_DINS_NUM_S 16 - -/** SPI_MEM_DOUT_MODE_REG register - * MSPI flash output timing adjustment control register - */ -#define SPI_MEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x18c) -/** SPI_MEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (SPI_MEM_DOUT0_MODE_V << SPI_MEM_DOUT0_MODE_S) -#define SPI_MEM_DOUT0_MODE_V 0x00000001U -#define SPI_MEM_DOUT0_MODE_S 0 -/** SPI_MEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (SPI_MEM_DOUT1_MODE_V << SPI_MEM_DOUT1_MODE_S) -#define SPI_MEM_DOUT1_MODE_V 0x00000001U -#define SPI_MEM_DOUT1_MODE_S 1 -/** SPI_MEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (SPI_MEM_DOUT2_MODE_V << SPI_MEM_DOUT2_MODE_S) -#define SPI_MEM_DOUT2_MODE_V 0x00000001U -#define SPI_MEM_DOUT2_MODE_S 2 -/** SPI_MEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (SPI_MEM_DOUT3_MODE_V << SPI_MEM_DOUT3_MODE_S) -#define SPI_MEM_DOUT3_MODE_V 0x00000001U -#define SPI_MEM_DOUT3_MODE_S 3 -/** SPI_MEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (SPI_MEM_DOUT4_MODE_V << SPI_MEM_DOUT4_MODE_S) -#define SPI_MEM_DOUT4_MODE_V 0x00000001U -#define SPI_MEM_DOUT4_MODE_S 4 -/** SPI_MEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (SPI_MEM_DOUT5_MODE_V << SPI_MEM_DOUT5_MODE_S) -#define SPI_MEM_DOUT5_MODE_V 0x00000001U -#define SPI_MEM_DOUT5_MODE_S 5 -/** SPI_MEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (SPI_MEM_DOUT6_MODE_V << SPI_MEM_DOUT6_MODE_S) -#define SPI_MEM_DOUT6_MODE_V 0x00000001U -#define SPI_MEM_DOUT6_MODE_S 6 -/** SPI_MEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (SPI_MEM_DOUT7_MODE_V << SPI_MEM_DOUT7_MODE_S) -#define SPI_MEM_DOUT7_MODE_V 0x00000001U -#define SPI_MEM_DOUT7_MODE_S 7 -/** SPI_MEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (SPI_MEM_DOUTS_MODE_V << SPI_MEM_DOUTS_MODE_S) -#define SPI_MEM_DOUTS_MODE_V 0x00000001U -#define SPI_MEM_DOUTS_MODE_S 8 - -/** SPI_SMEM_TIMING_CALI_REG register - * MSPI external RAM timing calibration register - */ -#define SPI_SMEM_TIMING_CALI_REG (DR_REG_SPI_BASE + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ -#define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) -#define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U -#define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ -#define SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) -#define SPI_SMEM_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U -#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ -#define SPI_SMEM_DLL_TIMING_CALI (BIT(5)) -#define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) -#define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U -#define SPI_SMEM_DLL_TIMING_CALI_S 5 -/** SPI_SMEM_DQS0_270_SEL : HRO; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_270_SEL 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) -#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_270_SEL_S 7 -/** SPI_SMEM_DQS0_90_SEL : HRO; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS0_90_SEL 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) -#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U -#define SPI_SMEM_DQS0_90_SEL_S 9 -/** SPI_SMEM_DQS1_270_SEL : HRO; bitpos: [12:11]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS1_270_SEL 0x00000003U -#define SPI_SMEM_DQS1_270_SEL_M (SPI_SMEM_DQS1_270_SEL_V << SPI_SMEM_DQS1_270_SEL_S) -#define SPI_SMEM_DQS1_270_SEL_V 0x00000003U -#define SPI_SMEM_DQS1_270_SEL_S 11 -/** SPI_SMEM_DQS1_90_SEL : HRO; bitpos: [14:13]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ -#define SPI_SMEM_DQS1_90_SEL 0x00000003U -#define SPI_SMEM_DQS1_90_SEL_M (SPI_SMEM_DQS1_90_SEL_V << SPI_SMEM_DQS1_90_SEL_S) -#define SPI_SMEM_DQS1_90_SEL_V 0x00000003U -#define SPI_SMEM_DQS1_90_SEL_S 13 - -/** SPI_SMEM_DIN_MODE_REG register - * MSPI external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_MODE_REG (DR_REG_SPI_BASE + 0x194) -/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN0_MODE 0x00000007U -#define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) -#define SPI_SMEM_DIN0_MODE_V 0x00000007U -#define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN1_MODE 0x00000007U -#define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) -#define SPI_SMEM_DIN1_MODE_V 0x00000007U -#define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN2_MODE 0x00000007U -#define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) -#define SPI_SMEM_DIN2_MODE_V 0x00000007U -#define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN3_MODE 0x00000007U -#define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) -#define SPI_SMEM_DIN3_MODE_V 0x00000007U -#define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN4_MODE 0x00000007U -#define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) -#define SPI_SMEM_DIN4_MODE_V 0x00000007U -#define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN5_MODE 0x00000007U -#define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) -#define SPI_SMEM_DIN5_MODE_V 0x00000007U -#define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN6_MODE 0x00000007U -#define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) -#define SPI_SMEM_DIN6_MODE_V 0x00000007U -#define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN7_MODE 0x00000007U -#define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) -#define SPI_SMEM_DIN7_MODE_V 0x00000007U -#define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_MODE 0x00000007U -#define SPI_SMEM_DINS_MODE_M (SPI_SMEM_DINS_MODE_V << SPI_SMEM_DINS_MODE_S) -#define SPI_SMEM_DINS_MODE_V 0x00000007U -#define SPI_SMEM_DINS_MODE_S 24 - -/** SPI_SMEM_DIN_NUM_REG register - * MSPI external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_NUM_REG (DR_REG_SPI_BASE + 0x198) -/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN0_NUM 0x00000003U -#define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) -#define SPI_SMEM_DIN0_NUM_V 0x00000003U -#define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN1_NUM 0x00000003U -#define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) -#define SPI_SMEM_DIN1_NUM_V 0x00000003U -#define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN2_NUM 0x00000003U -#define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) -#define SPI_SMEM_DIN2_NUM_V 0x00000003U -#define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN3_NUM 0x00000003U -#define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) -#define SPI_SMEM_DIN3_NUM_V 0x00000003U -#define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN4_NUM 0x00000003U -#define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) -#define SPI_SMEM_DIN4_NUM_V 0x00000003U -#define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN5_NUM 0x00000003U -#define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) -#define SPI_SMEM_DIN5_NUM_V 0x00000003U -#define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN6_NUM 0x00000003U -#define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) -#define SPI_SMEM_DIN6_NUM_V 0x00000003U -#define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN7_NUM 0x00000003U -#define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) -#define SPI_SMEM_DIN7_NUM_V 0x00000003U -#define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_NUM 0x00000003U -#define SPI_SMEM_DINS_NUM_M (SPI_SMEM_DINS_NUM_V << SPI_SMEM_DINS_NUM_S) -#define SPI_SMEM_DINS_NUM_V 0x00000003U -#define SPI_SMEM_DINS_NUM_S 16 - -/** SPI_SMEM_DOUT_MODE_REG register - * MSPI external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x19c) -/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) -#define SPI_SMEM_DOUT0_MODE_V 0x00000001U -#define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) -#define SPI_SMEM_DOUT1_MODE_V 0x00000001U -#define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) -#define SPI_SMEM_DOUT2_MODE_V 0x00000001U -#define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) -#define SPI_SMEM_DOUT3_MODE_V 0x00000001U -#define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) -#define SPI_SMEM_DOUT4_MODE_V 0x00000001U -#define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) -#define SPI_SMEM_DOUT5_MODE_V 0x00000001U -#define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) -#define SPI_SMEM_DOUT6_MODE_V 0x00000001U -#define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) -#define SPI_SMEM_DOUT7_MODE_V 0x00000001U -#define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_MODE_M (SPI_SMEM_DOUTS_MODE_V << SPI_SMEM_DOUTS_MODE_S) -#define SPI_SMEM_DOUTS_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_MODE_S 8 - -/** SPI_SMEM_AC_REG register - * MSPI external RAM ECC and SPI CS timing control register - */ -#define SPI_SMEM_AC_REG (DR_REG_SPI_BASE + 0x1a0) -/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ -#define SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) -#define SPI_SMEM_CS_SETUP_V 0x00000001U -#define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ -#define SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) -#define SPI_SMEM_CS_HOLD_V 0x00000001U -#define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ -#define SPI_SMEM_CS_SETUP_TIME 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) -#define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU -#define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ -#define SPI_SMEM_CS_HOLD_TIME 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) -#define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU -#define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ -#define SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) -#define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U -#define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U -#define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ -#define SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) -#define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U -#define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ -#define SPI_SMEM_CS_HOLD_DELAY 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) -#define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU -#define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ -#define SPI_SMEM_SPLIT_TRANS_EN (BIT(31)) -#define SPI_SMEM_SPLIT_TRANS_EN_M (SPI_SMEM_SPLIT_TRANS_EN_V << SPI_SMEM_SPLIT_TRANS_EN_S) -#define SPI_SMEM_SPLIT_TRANS_EN_V 0x00000001U -#define SPI_SMEM_SPLIT_TRANS_EN_S 31 - -/** SPI_SMEM_DIN_HEX_MODE_REG register - * MSPI 16x external RAM input timing delay mode control register - */ -#define SPI_SMEM_DIN_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1a4) -/** SPI_SMEM_DIN08_MODE : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN08_MODE 0x00000007U -#define SPI_SMEM_DIN08_MODE_M (SPI_SMEM_DIN08_MODE_V << SPI_SMEM_DIN08_MODE_S) -#define SPI_SMEM_DIN08_MODE_V 0x00000007U -#define SPI_SMEM_DIN08_MODE_S 0 -/** SPI_SMEM_DIN09_MODE : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN09_MODE 0x00000007U -#define SPI_SMEM_DIN09_MODE_M (SPI_SMEM_DIN09_MODE_V << SPI_SMEM_DIN09_MODE_S) -#define SPI_SMEM_DIN09_MODE_V 0x00000007U -#define SPI_SMEM_DIN09_MODE_S 3 -/** SPI_SMEM_DIN10_MODE : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN10_MODE 0x00000007U -#define SPI_SMEM_DIN10_MODE_M (SPI_SMEM_DIN10_MODE_V << SPI_SMEM_DIN10_MODE_S) -#define SPI_SMEM_DIN10_MODE_V 0x00000007U -#define SPI_SMEM_DIN10_MODE_S 6 -/** SPI_SMEM_DIN11_MODE : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN11_MODE 0x00000007U -#define SPI_SMEM_DIN11_MODE_M (SPI_SMEM_DIN11_MODE_V << SPI_SMEM_DIN11_MODE_S) -#define SPI_SMEM_DIN11_MODE_V 0x00000007U -#define SPI_SMEM_DIN11_MODE_S 9 -/** SPI_SMEM_DIN12_MODE : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN12_MODE 0x00000007U -#define SPI_SMEM_DIN12_MODE_M (SPI_SMEM_DIN12_MODE_V << SPI_SMEM_DIN12_MODE_S) -#define SPI_SMEM_DIN12_MODE_V 0x00000007U -#define SPI_SMEM_DIN12_MODE_S 12 -/** SPI_SMEM_DIN13_MODE : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN13_MODE 0x00000007U -#define SPI_SMEM_DIN13_MODE_M (SPI_SMEM_DIN13_MODE_V << SPI_SMEM_DIN13_MODE_S) -#define SPI_SMEM_DIN13_MODE_V 0x00000007U -#define SPI_SMEM_DIN13_MODE_S 15 -/** SPI_SMEM_DIN14_MODE : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN14_MODE 0x00000007U -#define SPI_SMEM_DIN14_MODE_M (SPI_SMEM_DIN14_MODE_V << SPI_SMEM_DIN14_MODE_S) -#define SPI_SMEM_DIN14_MODE_V 0x00000007U -#define SPI_SMEM_DIN14_MODE_S 18 -/** SPI_SMEM_DIN15_MODE : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DIN15_MODE 0x00000007U -#define SPI_SMEM_DIN15_MODE_M (SPI_SMEM_DIN15_MODE_V << SPI_SMEM_DIN15_MODE_S) -#define SPI_SMEM_DIN15_MODE_V 0x00000007U -#define SPI_SMEM_DIN15_MODE_S 21 -/** SPI_SMEM_DINS_HEX_MODE : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ -#define SPI_SMEM_DINS_HEX_MODE 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_M (SPI_SMEM_DINS_HEX_MODE_V << SPI_SMEM_DINS_HEX_MODE_S) -#define SPI_SMEM_DINS_HEX_MODE_V 0x00000007U -#define SPI_SMEM_DINS_HEX_MODE_S 24 - -/** SPI_SMEM_DIN_HEX_NUM_REG register - * MSPI 16x external RAM input timing delay number control register - */ -#define SPI_SMEM_DIN_HEX_NUM_REG (DR_REG_SPI_BASE + 0x1a8) -/** SPI_SMEM_DIN08_NUM : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN08_NUM 0x00000003U -#define SPI_SMEM_DIN08_NUM_M (SPI_SMEM_DIN08_NUM_V << SPI_SMEM_DIN08_NUM_S) -#define SPI_SMEM_DIN08_NUM_V 0x00000003U -#define SPI_SMEM_DIN08_NUM_S 0 -/** SPI_SMEM_DIN09_NUM : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN09_NUM 0x00000003U -#define SPI_SMEM_DIN09_NUM_M (SPI_SMEM_DIN09_NUM_V << SPI_SMEM_DIN09_NUM_S) -#define SPI_SMEM_DIN09_NUM_V 0x00000003U -#define SPI_SMEM_DIN09_NUM_S 2 -/** SPI_SMEM_DIN10_NUM : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN10_NUM 0x00000003U -#define SPI_SMEM_DIN10_NUM_M (SPI_SMEM_DIN10_NUM_V << SPI_SMEM_DIN10_NUM_S) -#define SPI_SMEM_DIN10_NUM_V 0x00000003U -#define SPI_SMEM_DIN10_NUM_S 4 -/** SPI_SMEM_DIN11_NUM : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN11_NUM 0x00000003U -#define SPI_SMEM_DIN11_NUM_M (SPI_SMEM_DIN11_NUM_V << SPI_SMEM_DIN11_NUM_S) -#define SPI_SMEM_DIN11_NUM_V 0x00000003U -#define SPI_SMEM_DIN11_NUM_S 6 -/** SPI_SMEM_DIN12_NUM : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN12_NUM 0x00000003U -#define SPI_SMEM_DIN12_NUM_M (SPI_SMEM_DIN12_NUM_V << SPI_SMEM_DIN12_NUM_S) -#define SPI_SMEM_DIN12_NUM_V 0x00000003U -#define SPI_SMEM_DIN12_NUM_S 8 -/** SPI_SMEM_DIN13_NUM : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN13_NUM 0x00000003U -#define SPI_SMEM_DIN13_NUM_M (SPI_SMEM_DIN13_NUM_V << SPI_SMEM_DIN13_NUM_S) -#define SPI_SMEM_DIN13_NUM_V 0x00000003U -#define SPI_SMEM_DIN13_NUM_S 10 -/** SPI_SMEM_DIN14_NUM : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN14_NUM 0x00000003U -#define SPI_SMEM_DIN14_NUM_M (SPI_SMEM_DIN14_NUM_V << SPI_SMEM_DIN14_NUM_S) -#define SPI_SMEM_DIN14_NUM_V 0x00000003U -#define SPI_SMEM_DIN14_NUM_S 12 -/** SPI_SMEM_DIN15_NUM : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DIN15_NUM 0x00000003U -#define SPI_SMEM_DIN15_NUM_M (SPI_SMEM_DIN15_NUM_V << SPI_SMEM_DIN15_NUM_S) -#define SPI_SMEM_DIN15_NUM_V 0x00000003U -#define SPI_SMEM_DIN15_NUM_S 14 -/** SPI_SMEM_DINS_HEX_NUM : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ -#define SPI_SMEM_DINS_HEX_NUM 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_M (SPI_SMEM_DINS_HEX_NUM_V << SPI_SMEM_DINS_HEX_NUM_S) -#define SPI_SMEM_DINS_HEX_NUM_V 0x00000003U -#define SPI_SMEM_DINS_HEX_NUM_S 16 - -/** SPI_SMEM_DOUT_HEX_MODE_REG register - * MSPI 16x external RAM output timing adjustment control register - */ -#define SPI_SMEM_DOUT_HEX_MODE_REG (DR_REG_SPI_BASE + 0x1ac) -/** SPI_SMEM_DOUT08_MODE : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT08_MODE (BIT(0)) -#define SPI_SMEM_DOUT08_MODE_M (SPI_SMEM_DOUT08_MODE_V << SPI_SMEM_DOUT08_MODE_S) -#define SPI_SMEM_DOUT08_MODE_V 0x00000001U -#define SPI_SMEM_DOUT08_MODE_S 0 -/** SPI_SMEM_DOUT09_MODE : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT09_MODE (BIT(1)) -#define SPI_SMEM_DOUT09_MODE_M (SPI_SMEM_DOUT09_MODE_V << SPI_SMEM_DOUT09_MODE_S) -#define SPI_SMEM_DOUT09_MODE_V 0x00000001U -#define SPI_SMEM_DOUT09_MODE_S 1 -/** SPI_SMEM_DOUT10_MODE : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT10_MODE (BIT(2)) -#define SPI_SMEM_DOUT10_MODE_M (SPI_SMEM_DOUT10_MODE_V << SPI_SMEM_DOUT10_MODE_S) -#define SPI_SMEM_DOUT10_MODE_V 0x00000001U -#define SPI_SMEM_DOUT10_MODE_S 2 -/** SPI_SMEM_DOUT11_MODE : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT11_MODE (BIT(3)) -#define SPI_SMEM_DOUT11_MODE_M (SPI_SMEM_DOUT11_MODE_V << SPI_SMEM_DOUT11_MODE_S) -#define SPI_SMEM_DOUT11_MODE_V 0x00000001U -#define SPI_SMEM_DOUT11_MODE_S 3 -/** SPI_SMEM_DOUT12_MODE : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT12_MODE (BIT(4)) -#define SPI_SMEM_DOUT12_MODE_M (SPI_SMEM_DOUT12_MODE_V << SPI_SMEM_DOUT12_MODE_S) -#define SPI_SMEM_DOUT12_MODE_V 0x00000001U -#define SPI_SMEM_DOUT12_MODE_S 4 -/** SPI_SMEM_DOUT13_MODE : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT13_MODE (BIT(5)) -#define SPI_SMEM_DOUT13_MODE_M (SPI_SMEM_DOUT13_MODE_V << SPI_SMEM_DOUT13_MODE_S) -#define SPI_SMEM_DOUT13_MODE_V 0x00000001U -#define SPI_SMEM_DOUT13_MODE_S 5 -/** SPI_SMEM_DOUT14_MODE : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT14_MODE (BIT(6)) -#define SPI_SMEM_DOUT14_MODE_M (SPI_SMEM_DOUT14_MODE_V << SPI_SMEM_DOUT14_MODE_S) -#define SPI_SMEM_DOUT14_MODE_V 0x00000001U -#define SPI_SMEM_DOUT14_MODE_S 6 -/** SPI_SMEM_DOUT15_MODE : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUT15_MODE (BIT(7)) -#define SPI_SMEM_DOUT15_MODE_M (SPI_SMEM_DOUT15_MODE_V << SPI_SMEM_DOUT15_MODE_S) -#define SPI_SMEM_DOUT15_MODE_V 0x00000001U -#define SPI_SMEM_DOUT15_MODE_S 7 -/** SPI_SMEM_DOUTS_HEX_MODE : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ -#define SPI_SMEM_DOUTS_HEX_MODE (BIT(8)) -#define SPI_SMEM_DOUTS_HEX_MODE_M (SPI_SMEM_DOUTS_HEX_MODE_V << SPI_SMEM_DOUTS_HEX_MODE_S) -#define SPI_SMEM_DOUTS_HEX_MODE_V 0x00000001U -#define SPI_SMEM_DOUTS_HEX_MODE_S 8 - -/** SPI_MEM_CLOCK_GATE_REG register - * SPI0 clock gate register - */ -#define SPI_MEM_CLOCK_GATE_REG (DR_REG_SPI_BASE + 0x200) -/** SPI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ -#define SPI_CLK_EN (BIT(0)) -#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_CLK_EN_V 0x00000001U -#define SPI_CLK_EN_S 0 -/** SPI_MSPI_CLK_FORCE_ON : HRO; bitpos: [1]; default: 1; - * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. - */ -#define SPI_MSPI_CLK_FORCE_ON (BIT(1)) -#define SPI_MSPI_CLK_FORCE_ON_M (SPI_MSPI_CLK_FORCE_ON_V << SPI_MSPI_CLK_FORCE_ON_S) -#define SPI_MSPI_CLK_FORCE_ON_V 0x00000001U -#define SPI_MSPI_CLK_FORCE_ON_S 1 - -/** SPI_MEM_NAND_FLASH_EN_REG register - * NAND FLASH control register - */ -#define SPI_MEM_NAND_FLASH_EN_REG (DR_REG_SPI_BASE + 0x204) -/** SPI_MEM_NAND_FLASH_EN : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ -#define SPI_MEM_NAND_FLASH_EN (BIT(0)) -#define SPI_MEM_NAND_FLASH_EN_M (SPI_MEM_NAND_FLASH_EN_V << SPI_MEM_NAND_FLASH_EN_S) -#define SPI_MEM_NAND_FLASH_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_EN_S 0 -/** SPI_MEM_NAND_FLASH_SEQ_HD_INDEX : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_M (SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V << SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S) -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_V 0x00007FFFU -#define SPI_MEM_NAND_FLASH_SEQ_HD_INDEX_S 1 -/** SPI_MEM_NAND_FLASH_SEQ_USR_TRIG : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG (BIT(16)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_M (SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V << SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_USR_TRIG_S 16 -/** SPI_MEM_NAND_FLASH_LUT_EN : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_LUT_EN (BIT(17)) -#define SPI_MEM_NAND_FLASH_LUT_EN_M (SPI_MEM_NAND_FLASH_LUT_EN_V << SPI_MEM_NAND_FLASH_LUT_EN_S) -#define SPI_MEM_NAND_FLASH_LUT_EN_V 0x00000001U -#define SPI_MEM_NAND_FLASH_LUT_EN_S 17 -/** SPI_MEM_NAND_FLASH_SEQ_USR_WEND : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to - * execute page execute. 1: write end 0: write in a page size. - */ -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND (BIT(18)) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_M (SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V << SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S) -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_USR_WEND_S 18 - -/** SPI_MEM_NAND_FLASH_SR_ADDR0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0_REG (DR_REG_SPI_BASE + 0x208) -/** SPI_MEM_NAND_FLASH_SR_ADDR0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_M (SPI_MEM_NAND_FLASH_SR_ADDR0_V << SPI_MEM_NAND_FLASH_SR_ADDR0_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR0_S 0 -/** SPI_MEM_NAND_FLASH_SR_ADDR1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_M (SPI_MEM_NAND_FLASH_SR_ADDR1_V << SPI_MEM_NAND_FLASH_SR_ADDR1_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR1_S 8 -/** SPI_MEM_NAND_FLASH_SR_ADDR2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_M (SPI_MEM_NAND_FLASH_SR_ADDR2_V << SPI_MEM_NAND_FLASH_SR_ADDR2_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR2_S 16 -/** SPI_MEM_NAND_FLASH_SR_ADDR3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ -#define SPI_MEM_NAND_FLASH_SR_ADDR3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR3_M (SPI_MEM_NAND_FLASH_SR_ADDR3_V << SPI_MEM_NAND_FLASH_SR_ADDR3_S) -#define SPI_MEM_NAND_FLASH_SR_ADDR3_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_ADDR3_S 24 - -/** SPI_MEM_NAND_FLASH_SR_DIN0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0_REG (DR_REG_SPI_BASE + 0x20c) -/** SPI_MEM_NAND_FLASH_SR_DIN0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN0 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_M (SPI_MEM_NAND_FLASH_SR_DIN0_V << SPI_MEM_NAND_FLASH_SR_DIN0_S) -#define SPI_MEM_NAND_FLASH_SR_DIN0_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN0_S 0 -/** SPI_MEM_NAND_FLASH_SR_DIN1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN1 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_M (SPI_MEM_NAND_FLASH_SR_DIN1_V << SPI_MEM_NAND_FLASH_SR_DIN1_S) -#define SPI_MEM_NAND_FLASH_SR_DIN1_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN1_S 8 -/** SPI_MEM_NAND_FLASH_SR_DIN2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN2 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_M (SPI_MEM_NAND_FLASH_SR_DIN2_V << SPI_MEM_NAND_FLASH_SR_DIN2_S) -#define SPI_MEM_NAND_FLASH_SR_DIN2_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN2_S 16 -/** SPI_MEM_NAND_FLASH_SR_DIN3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ -#define SPI_MEM_NAND_FLASH_SR_DIN3 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN3_M (SPI_MEM_NAND_FLASH_SR_DIN3_V << SPI_MEM_NAND_FLASH_SR_DIN3_S) -#define SPI_MEM_NAND_FLASH_SR_DIN3_V 0x000000FFU -#define SPI_MEM_NAND_FLASH_SR_DIN3_S 24 - -/** SPI_MEM_NAND_FLASH_CFG_DATA0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0_REG (DR_REG_SPI_BASE + 0x210) -/** SPI_MEM_NAND_FLASH_CFG_DATA0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_M (SPI_MEM_NAND_FLASH_CFG_DATA0_V << SPI_MEM_NAND_FLASH_CFG_DATA0_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA0_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA1_M (SPI_MEM_NAND_FLASH_CFG_DATA1_V << SPI_MEM_NAND_FLASH_CFG_DATA1_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA1_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA1_S 16 - -/** SPI_MEM_NAND_FLASH_CFG_DATA1_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA1_REG (DR_REG_SPI_BASE + 0x214) -/** SPI_MEM_NAND_FLASH_CFG_DATA2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_M (SPI_MEM_NAND_FLASH_CFG_DATA2_V << SPI_MEM_NAND_FLASH_CFG_DATA2_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA2_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA2_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA3 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA3_M (SPI_MEM_NAND_FLASH_CFG_DATA3_V << SPI_MEM_NAND_FLASH_CFG_DATA3_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA3_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA3_S 16 - -/** SPI_MEM_NAND_FLASH_CFG_DATA2_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA2_REG (DR_REG_SPI_BASE + 0x218) -/** SPI_MEM_NAND_FLASH_CFG_DATA4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA4 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_M (SPI_MEM_NAND_FLASH_CFG_DATA4_V << SPI_MEM_NAND_FLASH_CFG_DATA4_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA4_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA4_S 0 -/** SPI_MEM_NAND_FLASH_CFG_DATA5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ -#define SPI_MEM_NAND_FLASH_CFG_DATA5 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA5_M (SPI_MEM_NAND_FLASH_CFG_DATA5_V << SPI_MEM_NAND_FLASH_CFG_DATA5_S) -#define SPI_MEM_NAND_FLASH_CFG_DATA5_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_CFG_DATA5_S 16 - -/** SPI_MEM_NAND_FLASH_CMD_LUT0_REG register - * MSPI NAND FLASH CMD LUT control register - */ -#define SPI_MEM_NAND_FLASH_CMD_LUT0_REG (DR_REG_SPI_BASE + 0x240) -/** SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_M (SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V << SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_V 0x0000FFFFU -#define SPI_MEM_NAND_FLASH_LUT_CMD_VALUE0_S 0 -/** SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_M (SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V << SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_SFSM_ST_EN0_S 16 -/** SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_M (SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V << SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_CMD_LEN0_S 20 -/** SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_M (SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V << SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_LUT_ADDR_LEN0_S 24 -/** SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_M (SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V << SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S) -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_V 0x00000003U -#define SPI_MEM_NAND_FLASH_LUT_DATA_LEN0_S 28 -/** SPI_MEM_NAND_FLASH_LUT_BUS_EN0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0 (BIT(30)) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_M (SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V << SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S) -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_LUT_BUS_EN0_S 30 - -/** SPI_MEM_NAND_FLASH_SPI_SEQ0_REG register - * NAND FLASH SPI SEQ control register - */ -#define SPI_MEM_NAND_FLASH_SPI_SEQ0_REG (DR_REG_SPI_BASE + 0x280) -/** SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0 (BIT(0)) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_M (SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V << SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S) -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SEQ_TAIL_FLG0_S 0 -/** SPI_MEM_NAND_FLASH_SR_CHK_EN0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0 (BIT(1)) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_M (SPI_MEM_NAND_FLASH_SR_CHK_EN0_V << SPI_MEM_NAND_FLASH_SR_CHK_EN0_S) -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_SR_CHK_EN0_S 1 -/** SPI_MEM_NAND_FLASH_DIN_INDEX0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ -#define SPI_MEM_NAND_FLASH_DIN_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_M (SPI_MEM_NAND_FLASH_DIN_INDEX0_V << SPI_MEM_NAND_FLASH_DIN_INDEX0_S) -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_DIN_INDEX0_S 2 -/** SPI_MEM_NAND_FLASH_ADDR_INDEX0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_M (SPI_MEM_NAND_FLASH_ADDR_INDEX0_V << SPI_MEM_NAND_FLASH_ADDR_INDEX0_S) -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_ADDR_INDEX0_S 6 -/** SPI_MEM_NAND_FLASH_REQ_OR_CFG0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0 (BIT(10)) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_M (SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V << SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S) -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_V 0x00000001U -#define SPI_MEM_NAND_FLASH_REQ_OR_CFG0_S 10 -/** SPI_MEM_NAND_FLASH_CMD_INDEX0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ -#define SPI_MEM_NAND_FLASH_CMD_INDEX0 0x0000000FU -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_M (SPI_MEM_NAND_FLASH_CMD_INDEX0_V << SPI_MEM_NAND_FLASH_CMD_INDEX0_S) -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_V 0x0000000FU -#define SPI_MEM_NAND_FLASH_CMD_INDEX0_S 11 - -/** SPI_MEM_XTS_PLAIN_BASE_REG register - * The base address of the memory that stores plaintext in Manual Encryption - */ -#define SPI_MEM_XTS_PLAIN_BASE_REG (DR_REG_SPI_BASE + 0x300) -/** SPI_XTS_PLAIN : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ -#define SPI_XTS_PLAIN 0xFFFFFFFFU -#define SPI_XTS_PLAIN_M (SPI_XTS_PLAIN_V << SPI_XTS_PLAIN_S) -#define SPI_XTS_PLAIN_V 0xFFFFFFFFU -#define SPI_XTS_PLAIN_S 0 - -/** SPI_MEM_XTS_LINESIZE_REG register - * Manual Encryption Line-Size register - */ -#define SPI_MEM_XTS_LINESIZE_REG (DR_REG_SPI_BASE + 0x340) -/** SPI_XTS_LINESIZE : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ -#define SPI_XTS_LINESIZE 0x00000003U -#define SPI_XTS_LINESIZE_M (SPI_XTS_LINESIZE_V << SPI_XTS_LINESIZE_S) -#define SPI_XTS_LINESIZE_V 0x00000003U -#define SPI_XTS_LINESIZE_S 0 - -/** SPI_MEM_XTS_DESTINATION_REG register - * Manual Encryption destination register - */ -#define SPI_MEM_XTS_DESTINATION_REG (DR_REG_SPI_BASE + 0x344) -/** SPI_XTS_DESTINATION : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ -#define SPI_XTS_DESTINATION (BIT(0)) -#define SPI_XTS_DESTINATION_M (SPI_XTS_DESTINATION_V << SPI_XTS_DESTINATION_S) -#define SPI_XTS_DESTINATION_V 0x00000001U -#define SPI_XTS_DESTINATION_S 0 - -/** SPI_MEM_XTS_PHYSICAL_ADDRESS_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_PHYSICAL_ADDRESS_REG (DR_REG_SPI_BASE + 0x348) -/** SPI_XTS_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ -#define SPI_XTS_PHYSICAL_ADDRESS 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_M (SPI_XTS_PHYSICAL_ADDRESS_V << SPI_XTS_PHYSICAL_ADDRESS_S) -#define SPI_XTS_PHYSICAL_ADDRESS_V 0x3FFFFFFFU -#define SPI_XTS_PHYSICAL_ADDRESS_S 0 - -/** SPI_MEM_XTS_TRIGGER_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_TRIGGER_REG (DR_REG_SPI_BASE + 0x34c) -/** SPI_XTS_TRIGGER : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ -#define SPI_XTS_TRIGGER (BIT(0)) -#define SPI_XTS_TRIGGER_M (SPI_XTS_TRIGGER_V << SPI_XTS_TRIGGER_S) -#define SPI_XTS_TRIGGER_V 0x00000001U -#define SPI_XTS_TRIGGER_S 0 - -/** SPI_MEM_XTS_RELEASE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_RELEASE_REG (DR_REG_SPI_BASE + 0x350) -/** SPI_XTS_RELEASE : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ -#define SPI_XTS_RELEASE (BIT(0)) -#define SPI_XTS_RELEASE_M (SPI_XTS_RELEASE_V << SPI_XTS_RELEASE_S) -#define SPI_XTS_RELEASE_V 0x00000001U -#define SPI_XTS_RELEASE_S 0 - -/** SPI_MEM_XTS_DESTROY_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_DESTROY_REG (DR_REG_SPI_BASE + 0x354) -/** SPI_XTS_DESTROY : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ -#define SPI_XTS_DESTROY (BIT(0)) -#define SPI_XTS_DESTROY_M (SPI_XTS_DESTROY_V << SPI_XTS_DESTROY_S) -#define SPI_XTS_DESTROY_V 0x00000001U -#define SPI_XTS_DESTROY_S 0 - -/** SPI_MEM_XTS_STATE_REG register - * Manual Encryption physical address register - */ -#define SPI_MEM_XTS_STATE_REG (DR_REG_SPI_BASE + 0x358) -/** SPI_XTS_STATE : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ -#define SPI_XTS_STATE 0x00000003U -#define SPI_XTS_STATE_M (SPI_XTS_STATE_V << SPI_XTS_STATE_S) -#define SPI_XTS_STATE_V 0x00000003U -#define SPI_XTS_STATE_S 0 - -/** SPI_MEM_XTS_DATE_REG register - * Manual Encryption version register - */ -#define SPI_MEM_XTS_DATE_REG (DR_REG_SPI_BASE + 0x35c) -/** SPI_XTS_DATE : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ -#define SPI_XTS_DATE 0x3FFFFFFFU -#define SPI_XTS_DATE_M (SPI_XTS_DATE_V << SPI_XTS_DATE_S) -#define SPI_XTS_DATE_V 0x3FFFFFFFU -#define SPI_XTS_DATE_S 0 - -/** SPI_MEM_MMU_ITEM_CONTENT_REG register - * MSPI-MMU item content register - */ -#define SPI_MEM_MMU_ITEM_CONTENT_REG (DR_REG_SPI_BASE + 0x37c) -/** SPI_MMU_ITEM_CONTENT : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ -#define SPI_MMU_ITEM_CONTENT 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_M (SPI_MMU_ITEM_CONTENT_V << SPI_MMU_ITEM_CONTENT_S) -#define SPI_MMU_ITEM_CONTENT_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_CONTENT_S 0 - -/** SPI_MEM_MMU_ITEM_INDEX_REG register - * MSPI-MMU item index register - */ -#define SPI_MEM_MMU_ITEM_INDEX_REG (DR_REG_SPI_BASE + 0x380) -/** SPI_MMU_ITEM_INDEX : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ -#define SPI_MMU_ITEM_INDEX 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_M (SPI_MMU_ITEM_INDEX_V << SPI_MMU_ITEM_INDEX_S) -#define SPI_MMU_ITEM_INDEX_V 0xFFFFFFFFU -#define SPI_MMU_ITEM_INDEX_S 0 - -/** SPI_MEM_MMU_POWER_CTRL_REG register - * MSPI MMU power control register - */ -#define SPI_MEM_MMU_POWER_CTRL_REG (DR_REG_SPI_BASE + 0x384) -/** SPI_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ -#define SPI_MMU_MEM_FORCE_ON (BIT(0)) -#define SPI_MMU_MEM_FORCE_ON_M (SPI_MMU_MEM_FORCE_ON_V << SPI_MMU_MEM_FORCE_ON_S) -#define SPI_MMU_MEM_FORCE_ON_V 0x00000001U -#define SPI_MMU_MEM_FORCE_ON_S 0 -/** SPI_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * Set this bit to force mmu-memory powerdown - */ -#define SPI_MMU_MEM_FORCE_PD (BIT(1)) -#define SPI_MMU_MEM_FORCE_PD_M (SPI_MMU_MEM_FORCE_PD_V << SPI_MMU_MEM_FORCE_PD_S) -#define SPI_MMU_MEM_FORCE_PD_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PD_S 1 -/** SPI_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ -#define SPI_MMU_MEM_FORCE_PU (BIT(2)) -#define SPI_MMU_MEM_FORCE_PU_M (SPI_MMU_MEM_FORCE_PU_V << SPI_MMU_MEM_FORCE_PU_S) -#define SPI_MMU_MEM_FORCE_PU_V 0x00000001U -#define SPI_MMU_MEM_FORCE_PU_S 2 -/** SPI_MMU_PAGE_SIZE : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ -#define SPI_MMU_PAGE_SIZE 0x00000003U -#define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) -#define SPI_MMU_PAGE_SIZE_V 0x00000003U -#define SPI_MMU_PAGE_SIZE_S 3 -/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ -#define SPI_MEM_AUX_CTRL 0x00003FFFU -#define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) -#define SPI_MEM_AUX_CTRL_V 0x00003FFFU -#define SPI_MEM_AUX_CTRL_S 16 -/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_RDN_ENA (BIT(30)) -#define SPI_MEM_RDN_ENA_M (SPI_MEM_RDN_ENA_V << SPI_MEM_RDN_ENA_S) -#define SPI_MEM_RDN_ENA_V 0x00000001U -#define SPI_MEM_RDN_ENA_S 30 -/** SPI_MEM_RDN_RESULT : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_RDN_RESULT (BIT(31)) -#define SPI_MEM_RDN_RESULT_M (SPI_MEM_RDN_RESULT_V << SPI_MEM_RDN_RESULT_S) -#define SPI_MEM_RDN_RESULT_V 0x00000001U -#define SPI_MEM_RDN_RESULT_S 31 - -/** SPI_MEM_DPA_CTRL_REG register - * SPI memory cryption DPA register - */ -#define SPI_MEM_DPA_CTRL_REG (DR_REG_SPI_BASE + 0x388) -/** SPI_CRYPT_SECURITY_LEVEL : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ -#define SPI_CRYPT_SECURITY_LEVEL 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_M (SPI_CRYPT_SECURITY_LEVEL_V << SPI_CRYPT_SECURITY_LEVEL_S) -#define SPI_CRYPT_SECURITY_LEVEL_V 0x00000007U -#define SPI_CRYPT_SECURITY_LEVEL_S 0 -/** SPI_CRYPT_CALC_D_DPA_EN : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ -#define SPI_CRYPT_CALC_D_DPA_EN (BIT(3)) -#define SPI_CRYPT_CALC_D_DPA_EN_M (SPI_CRYPT_CALC_D_DPA_EN_V << SPI_CRYPT_CALC_D_DPA_EN_S) -#define SPI_CRYPT_CALC_D_DPA_EN_V 0x00000001U -#define SPI_CRYPT_CALC_D_DPA_EN_S 3 -/** SPI_CRYPT_DPA_SELECT_REGISTER : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ -#define SPI_CRYPT_DPA_SELECT_REGISTER (BIT(4)) -#define SPI_CRYPT_DPA_SELECT_REGISTER_M (SPI_CRYPT_DPA_SELECT_REGISTER_V << SPI_CRYPT_DPA_SELECT_REGISTER_S) -#define SPI_CRYPT_DPA_SELECT_REGISTER_V 0x00000001U -#define SPI_CRYPT_DPA_SELECT_REGISTER_S 4 - -/** SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG register - * SPI memory cryption PSEUDO register - */ -#define SPI_MEM_XTS_PSEUDO_ROUND_CONF_REG (DR_REG_SPI_BASE + 0x38c) -/** SPI_MEM_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ -#define SPI_MEM_MODE_PSEUDO 0x00000003U -#define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) -#define SPI_MEM_MODE_PSEUDO_V 0x00000003U -#define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be performed. - */ -#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) -#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U -#define SPI_MEM_PSEUDO_RNG_CNT_S 2 -/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be performed. - */ -#define SPI_MEM_PSEUDO_BASE 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) -#define SPI_MEM_PSEUDO_BASE_V 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_S 5 -/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be performed randomly between 0 & - * 2**(inc+1). - */ -#define SPI_MEM_PSEUDO_INC 0x00000003U -#define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) -#define SPI_MEM_PSEUDO_INC_V 0x00000003U -#define SPI_MEM_PSEUDO_INC_S 9 - -/** SPI_MEM_REGISTERRND_ECO_HIGH_REG register - * MSPI ECO high register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH_REG (DR_REG_SPI_BASE + 0x3f0) -/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; - * ECO high register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_REGISTERRND_ECO_HIGH 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_HIGH_M (SPI_MEM_REGISTERRND_ECO_HIGH_V << SPI_MEM_REGISTERRND_ECO_HIGH_S) -#define SPI_MEM_REGISTERRND_ECO_HIGH_V 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_HIGH_S 0 - -/** SPI_MEM_REGISTERRND_ECO_LOW_REG register - * MSPI ECO low register - * This register is only for internal debugging purposes. Do not use it in - * applications. - */ -#define SPI_MEM_REGISTERRND_ECO_LOW_REG (DR_REG_SPI_BASE + 0x3f4) -/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; - * ECO low register - * This field is only for internal debugging purposes. Do not use it in applications. - */ -#define SPI_MEM_REGISTERRND_ECO_LOW 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_LOW_M (SPI_MEM_REGISTERRND_ECO_LOW_V << SPI_MEM_REGISTERRND_ECO_LOW_S) -#define SPI_MEM_REGISTERRND_ECO_LOW_V 0xFFFFFFFFU -#define SPI_MEM_REGISTERRND_ECO_LOW_S 0 - -/** SPI_MEM_DATE_REG register - * SPI0 version control register - */ -#define SPI_MEM_DATE_REG (DR_REG_SPI_BASE + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37822512; - * SPI0 register version. - */ -#define SPI_MEM_DATE 0x0FFFFFFFU -#define SPI_MEM_DATE_M (SPI_MEM_DATE_V << SPI_MEM_DATE_S) -#define SPI_MEM_DATE_V 0x0FFFFFFFU -#define SPI_MEM_DATE_S 0 - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_struct.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h index 9d10a730c5..09eac698aa 100644 --- a/components/soc/esp32c5/register/soc/spi_mem_c_struct.h +++ b/components/soc/esp32c5/register/soc/spi_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,7 @@ typedef union { uint32_t mem_slv_st:4; uint32_t reserved_8:10; /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_AXI_REQ_EN is cleared. An operation + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ @@ -47,8 +47,8 @@ typedef union { struct { /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ uint32_t mem_axi_err_addr:29; uint32_t reserved_29:3; @@ -108,8 +108,8 @@ typedef union { uint32_t mem_fcmd_oct:1; uint32_t reserved_10:3; /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_FREAD_QIO, spi_mem_c_FREAD_DIO, spi_mem_c_FREAD_QOUT - * and spi_mem_c_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ uint32_t mem_fastrd_mode:1; /** mem_fread_dual : R/W; bitpos: [14]; default: 0; @@ -170,25 +170,20 @@ typedef union { * SPI clock is always on. */ uint32_t mem_clk_mode:2; - uint32_t reserved_2:19; - /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + uint32_t reserved_2:20; + /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : R/W; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_ECC_ERR_ADDR_REG. + * in SPI_MEM_ECC_ERR_ADDR_REG. */ uint32_t mem_rresp_ecc_err_en:1; /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; @@ -200,9 +195,9 @@ typedef union { */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -238,16 +233,16 @@ typedef union { struct { /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_CS_SETUP bit. + * SPI_MEM_CS_SETUP bit. */ uint32_t mem_cs_setup_time:5; /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_CS_HOLD bit. + * SPI_MEM_CS_HOLD bit. */ uint32_t mem_cs_hold_time:5; /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * spi_mem_c_CS_HOLD_TIME + spi_mem_c_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ uint32_t mem_ecc_cs_hold_time:3; @@ -270,7 +265,7 @@ typedef union { uint32_t mem_split_trans_en:1; /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t mem_cs_hold_delay:6; @@ -424,7 +419,7 @@ typedef union { uint32_t fmem_usr_ddr_dqs_thd:7; /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -471,16 +466,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -499,18 +494,18 @@ typedef union { typedef union { struct { /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N. + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk - * frequency is system/(spi_mem_c_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; @@ -534,7 +529,11 @@ typedef union { * Register clock gate enable signal. 1: Enable. 0: Disable. */ uint32_t clk_en:1; - uint32_t reserved_1:31; + /** mspi_clk_force_on : HRO; bitpos: [1]; default: 1; + * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. + */ + uint32_t mspi_clk_force_on:1; + uint32_t reserved_2:30; }; uint32_t val; } spi_mem_c_clock_gate_reg_t; @@ -557,7 +556,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -933,7 +932,7 @@ typedef union { uint32_t smem_usr_ddr_dqs_thd:7; /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ @@ -998,7 +997,7 @@ typedef union { */ uint32_t smem_cs_hold_time:5; /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * spi_smem_c_CS_HOLD_TIME + spi_smem_c_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; @@ -1015,7 +1014,7 @@ typedef union { uint32_t reserved_17:8; /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (spi_smem_c_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; @@ -1037,19 +1036,19 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - /** mem_flash_lock_en : R/W; bitpos: [12]; default: 0; + uint32_t mem_lock_delay_time:12; + /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. */ uint32_t mem_flash_lock_en:1; - /** mem_sram_lock_en : R/W; bitpos: [13]; default: 0; + /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. */ uint32_t mem_sram_lock_en:1; - uint32_t reserved_14:18; + uint32_t reserved_21:11; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -1063,48 +1062,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_ena:1; /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_ena:1; /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_ECC_ERR_INT interrupt. + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_ena:1; /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_ena:1; /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_ena:1; /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_ena:1; /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_ena:1; /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_ena:1; /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_ena:1; /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_ena:1; }; @@ -1118,48 +1117,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_clr:1; /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_clr:1; /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_ECC_ERR_INT interrupt. + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_clr:1; /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_clr:1; /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_clr:1; /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_clr:1; /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_clr:1; /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_clr:1; /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_clr:1; /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_clr:1; }; @@ -1173,67 +1172,67 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t mem_slv_st_end_int_raw:1; /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ uint32_t mem_mst_st_end_int_raw:1; /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_ECC_ERR_INT interrupt. When spi_fmem_c_ECC_ERR_INT_EN is set - * and spi_smem_c_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_ECC_ERR_INT_NUM. When - * spi_fmem_c_ECC_ERR_INT_EN is cleared and spi_smem_c_ECC_ERR_INT_EN is set, this bit is + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and - * spi_smem_c_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_ECC_ERR_INT_NUM. When spi_fmem_c_ECC_ERR_INT_EN and spi_smem_c_ECC_ERR_INT_EN + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ uint32_t mem_ecc_err_int_raw:1; /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ uint32_t mem_pms_reject_int_raw:1; /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_raddr_err_int_raw:1; /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ uint32_t mem_axi_wr_flash_err_int_raw:1; /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS1 is overflow. */ uint32_t mem_dqs0_afifo_ovf_int_raw:1; /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO * connected to SPI_DQS is overflow. */ uint32_t mem_dqs1_afifo_ovf_int_raw:1; /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is * underflow. */ uint32_t mem_bus_fifo1_udf_int_raw:1; /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is * underflow. */ uint32_t mem_bus_fifo0_udf_int_raw:1; @@ -1248,48 +1247,48 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_st:1; /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_st:1; /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_ECC_ERR_INT interrupt. + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_st:1; /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_st:1; /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_st:1; /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_st:1; /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; uint32_t reserved_10:18; /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for spi_mem_c_DQS0_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs0_afifo_ovf_int_st:1; /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for spi_mem_c_DQS1_AFIFO_OVF_INT interrupt. + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. */ uint32_t mem_dqs1_afifo_ovf_int_st:1; /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for spi_mem_c_BUS_FIFO1_UDF_INT interrupt. + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. */ uint32_t mem_bus_fifo1_udf_int_st:1; /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for spi_mem_c_BUS_FIFO0_UDF_INT interrupt. + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. */ uint32_t mem_bus_fifo0_udf_int_st:1; }; @@ -1313,8 +1312,8 @@ typedef union { uint32_t fmem_pmsn_wr_attr:1; /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers spi_fmem_c_PMSn_ADDR_REG and - * spi_fmem_c_PMSn_SIZE_REG. + * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and + * SPI_FMEM_PMSn_SIZE_REG. */ uint32_t fmem_pmsn_ecc:1; uint32_t reserved_3:29; @@ -1342,8 +1341,8 @@ typedef union { typedef union { struct { /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section n address region is (spi_fmem_c_PMSn_ADDR_S, - * spi_fmem_c_PMSn_ADDR_S + spi_fmem_c_PMSn_SIZE) + * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, + * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) */ uint32_t fmem_pmsn_size:17; uint32_t reserved_17:15; @@ -1366,8 +1365,8 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers spi_smem_c_PMSn_ADDR_REG and - * spi_smem_c_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; uint32_t reserved_3:29; @@ -1395,8 +1394,8 @@ typedef union { typedef union { struct { /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (spi_smem_c_PMSn_ADDR_S, - * spi_smem_c_PMSn_ADDR_S + spi_smem_c_PMSn_SIZE) + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) */ uint32_t smem_pmsn_size:17; uint32_t reserved_17:15; @@ -1416,22 +1415,22 @@ typedef union { uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; @@ -1445,7 +1444,7 @@ typedef union { struct { /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_reject_addr:29; uint32_t reserved_29:3; @@ -1463,11 +1462,11 @@ typedef union { uint32_t reserved_0:5; /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_ECC_ERR_INT interrupt. + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; @@ -1492,9 +1491,9 @@ typedef union { uint32_t mem_usr_ecc_addr_en:1; uint32_t reserved_23:1; /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_ECC_ERR_BITS and spi_mem_c_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_ECC_ERR_BITS and - * spi_mem_c_ECC_ERR_ADDR record the first ECC error information. + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; @@ -1513,7 +1512,7 @@ typedef union { struct { /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_addr:29; uint32_t reserved_29:3; @@ -1895,17 +1894,27 @@ typedef union { */ uint32_t smem_dll_timing_cali:1; uint32_t reserved_6:1; - /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; + /** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1; * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. */ uint32_t smem_dqs0_270_sel:2; - /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; + /** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1; * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, * 2'd2: 1.5ns 2'd3: 2.0ns. */ uint32_t smem_dqs0_90_sel:2; - uint32_t reserved_11:21; + /** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_270_sel:2; + /** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs1_90_sel:2; + uint32_t reserved_15:17; }; uint32_t val; } spi_smem_c_timing_cali_reg_t; @@ -2330,8 +2339,8 @@ typedef union { */ uint32_t mem_nand_flash_seq_hd_index:15; /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. spi_mem_c_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to spi_mem_c_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. + * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG + * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. */ uint32_t mem_nand_flash_seq_usr_trig:1; /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; @@ -2339,7 +2348,7 @@ typedef union { */ uint32_t mem_nand_flash_lut_en:1; /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; - * Used with spi_mem_c_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to + * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to * execute page execute. 1: write end 0: write in a page size. */ uint32_t mem_nand_flash_seq_usr_wend:1; @@ -2384,22 +2393,22 @@ typedef union { struct { /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din0:8; /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din1:8; /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din2:8; /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; * spi read state register data to this register for SPI SEQ need. - * spi_mem_c_NAND_FLASH_SR_DIN0_REG corresponds to spi_mem_c_NAND_FLASH_SR_ADDR0_REG. + * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. */ uint32_t mem_nand_flash_sr_din3:8; }; @@ -2492,7 +2501,7 @@ typedef union { /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the spi_mem_c_NAND_FLASH_CMD_LUT0_REG's + * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's * field. The number of CMD LUT entries can be defined by the user, but cannot exceed * 16 ) */ @@ -2518,12 +2527,12 @@ typedef union { uint32_t mem_nand_flash_sr_chk_en0:1; /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * spi_mem_c_NAND_FLASH_CFG_DATA + * SPI_MEM_NAND_FLASH_CFG_DATA */ uint32_t mem_nand_flash_din_index0:4; /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * spi_mem_c_NAND_FLASH_SR_ADDR + * SPI_MEM_NAND_FLASH_SR_ADDR */ uint32_t mem_nand_flash_addr_index0:4; /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; @@ -2534,7 +2543,7 @@ typedef union { /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in * CMD LUT.(Note these registers are described to indicate the - * spi_mem_c_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined + * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined * by the user, but cannot exceed 16 ) */ uint32_t mem_nand_flash_cmd_index0:4; @@ -2730,16 +2739,16 @@ typedef union { * Set this bit to enable mmu-memory clock force on */ uint32_t mmu_mem_force_on:1; - /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 1; + /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; * Set this bit to force mmu-memory powerdown */ uint32_t mmu_mem_force_pd:1; - /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 0; + /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; * Set this bit to force mmu-memory powerup, in this case, the power should also be * controlled by rtc. */ uint32_t mmu_mem_force_pu:1; - /** mmu_page_size : HRO; bitpos: [4:3]; default: 0; + /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 */ uint32_t mmu_page_size:2; @@ -2859,7 +2868,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36774400; + /** mem_date : R/W; bitpos: [27:0]; default: 37822512; * SPI0 register version. */ uint32_t mem_date:28; diff --git a/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h b/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h deleted file mode 100644 index 220deaf10b..0000000000 --- a/components/soc/esp32c5/register/soc/spi_mem_c_struct_eco2.h +++ /dev/null @@ -1,2982 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Status and state control register */ -/** Type of mem_cmd register - * SPI0 FSM status register - */ -typedef union { - struct { - /** mem_mst_st : RO; bitpos: [3:0]; default: 0; - * The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:SPI0_GRANT , - * 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent - * data is stored in SPI0 TX FIFO, 5: SPI0 write data state. - */ - uint32_t mem_mst_st:4; - /** mem_slv_st : RO; bitpos: [7:4]; default: 0; - * The current status of SPI0 slave FSM: mspi_st. 0: idle state, 1: preparation state, - * 2: send command state, 3: send address state, 4: wait state, 5: read data state, - * 6:write data state, 7: done state, 8: read data end state. - */ - uint32_t mem_slv_st:4; - uint32_t reserved_8:10; - /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation - * will be triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - uint32_t mem_usr:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_cmd_reg_t; - -/** Type of mem_axi_err_addr register - * SPI0 AXI request error address. - */ -typedef union { - struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, - * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. - */ - uint32_t mem_axi_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_axi_err_addr_reg_t; - - -/** Group: Flash Control and configuration registers */ -/** Type of mem_ctrl register - * SPI0 control register. - */ -typedef union { - struct { - /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_DQS is output by the MSPI controller. - */ - uint32_t mem_wdummy_dqs_always_out:1; - /** mem_wdummy_always_out : R/W; bitpos: [1]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to flash, the level - * of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t mem_wdummy_always_out:1; - /** mem_fdummy_rin : R/W; bitpos: [2]; default: 1; - * In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the first half part of dummy phase. It is used to - * mask invalid SPI_DQS in the half part of dummy phase. - */ - uint32_t mem_fdummy_rin:1; - /** mem_fdummy_wout : R/W; bitpos: [3]; default: 1; - * In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is - * output by the MSPI controller in the second half part of dummy phase. It is used to - * pre-drive flash. - */ - uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; - * Apply 8 signals during write-data phase 1:enable 0: disable - */ - uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; - * Apply 8 signals during read-data phase 1:enable 0: disable - */ - uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; - * Apply 8 signals during address phase 1:enable 0: disable - */ - uint32_t mem_faddr_oct:1; - uint32_t reserved_7:1; - /** mem_fcmd_quad : R/W; bitpos: [8]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; - * Apply 8 signals during command phase 1:enable 0: disable - */ - uint32_t mem_fcmd_oct:1; - uint32_t reserved_10:3; - /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT - * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. - */ - uint32_t mem_fastrd_mode:1; - /** mem_fread_dual : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_dual:1; - uint32_t reserved_15:3; - /** mem_q_pol : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low - */ - uint32_t mem_q_pol:1; - /** mem_d_pol : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low - */ - uint32_t mem_d_pol:1; - /** mem_fread_quad : R/W; bitpos: [20]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: disable. - */ - uint32_t mem_fread_quad:1; - /** mem_wp_reg : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output low. - */ - uint32_t mem_wp_reg:1; - uint32_t reserved_22:1; - /** mem_fread_dio : R/W; bitpos: [23]; default: 0; - * In the read operations address phase and read-data phase apply 2 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_dio:1; - /** mem_fread_qio : R/W; bitpos: [24]; default: 0; - * In the read operations address phase and read-data phase apply 4 signals. 1: enable - * 0: disable. - */ - uint32_t mem_fread_qio:1; - uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always - * 1. 0: Others. - */ - uint32_t mem_dqs_ie_always_on:1; - /** mem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are - * always 1. 0: Others. - */ - uint32_t mem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_ctrl_reg_t; - -/** Type of mem_ctrl1 register - * SPI0 control1 register. - */ -typedef union { - struct { - /** mem_clk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - */ - uint32_t mem_clk_mode:2; - uint32_t reserved_2:20; - /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; - * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply - * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; - * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. - */ - uint32_t aw_size0_1_support_en:1; - /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; - * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY - * when there is a ECC error in AXI read data. The ECC error information is recorded - * in SPI_MEM_ECC_ERR_ADDR_REG. - */ - uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; - * Set this bit to enable AXI Read Splice-transfer. - */ - uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; - * Set this bit to enable AXI Write Splice-transfer. - */ - uint32_t mem_aw_splice_en:1; - /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be - * accessed at the same time. - */ - uint32_t mem_ram0_en:1; - /** mem_dual_ram_en : HRO; bitpos: [28]; default: 0; - * Set this bit to enable DUAL-RAM mode, EXT_RAM0 and EXT_RAM1 will be accessed at the - * same time. - */ - uint32_t mem_dual_ram_en:1; - /** mem_fast_write_en : R/W; bitpos: [29]; default: 1; - * Set this bit to write data faster, do not wait write data has been stored in - * tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored - * in tx_bus_fifo_l2. - */ - uint32_t mem_fast_write_en:1; - /** mem_rxfifo_rst : WT; bitpos: [30]; default: 0; - * The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to - * receive signals from AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_rxfifo_rst:1; - /** mem_txfifo_rst : WT; bitpos: [31]; default: 0; - * The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to - * send signals to AXI. Set this bit to reset these FIFO. - */ - uint32_t mem_txfifo_rst:1; - }; - uint32_t val; -} spi_mem_ctrl1_reg_t; - -/** Type of mem_ctrl2 register - * SPI0 control2 register. - */ -typedef union { - struct { - /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; - * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * SPI_MEM_CS_SETUP bit. - */ - uint32_t mem_cs_setup_time:5; - /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; - * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * SPI_MEM_CS_HOLD bit. - */ - uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; - * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC - * mode when accessed flash. - */ - uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; - * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when - * accesses flash. - */ - uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses flash. - */ - uint32_t mem_ecc_16to18_byte_en:1; - uint32_t reserved_15:9; - /** mem_split_trans_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable SPI0 split one AXI read flash transfer into two SPI - * transfers when one transfer will cross flash or EXT_RAM page corner, valid no - * matter whether there is an ECC region or not. - */ - uint32_t mem_split_trans_en:1; - /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI - * core clock cycles. - */ - uint32_t mem_cs_hold_delay:6; - /** mem_sync_reset : WT; bitpos: [31]; default: 0; - * The spi0_mst_st and spi0_slv_st will be reset. - */ - uint32_t mem_sync_reset:1; - }; - uint32_t val; -} spi_mem_ctrl2_reg_t; - -/** Type of mem_misc register - * SPI0 misc register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_fsub_pin : HRO; bitpos: [7]; default: 0; - * For SPI0, flash is connected to SUBPINs. - */ - uint32_t mem_fsub_pin:1; - /** mem_ssub_pin : HRO; bitpos: [8]; default: 0; - * For SPI0, sram is connected to SUBPINs. - */ - uint32_t mem_ssub_pin:1; - /** mem_ck_idle_edge : R/W; bitpos: [9]; default: 0; - * 1: SPI_CLK line is high when idle 0: spi clk line is low when idle - */ - uint32_t mem_ck_idle_edge:1; - /** mem_cs_keep_active : R/W; bitpos: [10]; default: 0; - * SPI_CS line keep low when the bit is set. - */ - uint32_t mem_cs_keep_active:1; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_misc_reg_t; - -/** Type of mem_cache_fctrl register - * SPI0 bit mode control register. - */ -typedef union { - struct { - /** mem_axi_req_en : R/W; bitpos: [0]; default: 0; - * For SPI0, AXI master access enable, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_axi_req_en:1; - /** mem_cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; - * For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_usr_addr_4byte:1; - /** mem_cache_flash_usr_cmd : R/W; bitpos: [2]; default: 0; - * For SPI0, cache read flash for user define command, 1: enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_flash_usr_cmd:1; - /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; - * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdin_dual:1; - /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; - * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdout_dual:1; - /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; - * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_faddr_dual:1; - /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; - * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdin_quad:1; - /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; - * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_fdout_quad:1; - /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; - * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_fread_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_faddr_quad:1; - uint32_t reserved_9:21; - /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; - * Set this bit to check AXI read/write the same address region. - */ - uint32_t same_aw_ar_addr_chk_en:1; - /** close_axi_inf_en : R/W; bitpos: [31]; default: 1; - * Set this bit to close AXI read/write transfer to MSPI, which means that only - * SLV_ERR will be replied to BRESP/RRESP. - */ - uint32_t close_axi_inf_en:1; - }; - uint32_t val; -} spi_mem_cache_fctrl_reg_t; - -/** Type of mem_ddr register - * SPI0 flash DDR mode control register - */ -typedef union { - struct { - /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t fmem_ddr_en:1; - /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t fmem_var_dummy:1; - /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_rdat_swp:1; - /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t fmem_ddr_wdat_swp:1; - /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t fmem_ddr_cmd_dis:1; - /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the panda device. - */ - uint32_t fmem_outminbytelen:7; - /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to flash. - */ - uint32_t fmem_tx_ddr_msk_en:1; - /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to flash. - */ - uint32_t fmem_rx_ddr_msk_en:1; - /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t fmem_usr_ddr_dqs_thd:7; - /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t fmem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t fmem_clk_diff_en:1; - uint32_t reserved_25:1; - /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t fmem_dqs_ca_in:1; - /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t fmem_hyperbus_dummy_2x:1; - /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to flash. . - */ - uint32_t fmem_clk_diff_inv:1; - /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ - uint32_t fmem_octa_ram_addr:1; - /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to flash, which means - * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t fmem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_ddr_reg_t; - - -/** Group: Clock control and configuration registers */ -/** Type of mem_clock register - * SPI clock division control register. - */ -typedef union { - struct { - /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to SPI_MEM_CLKCNT_N. - */ - uint32_t mem_clkcnt_l:8; - /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). - */ - uint32_t mem_clkcnt_h:8; - /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(SPI_MEM_CLKCNT_N+1) - */ - uint32_t mem_clkcnt_n:8; - uint32_t reserved_24:7; - /** mem_clk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * 1: 1-division mode, the frequency of SPI bus clock equals to that of MSPI module - * clock. - */ - uint32_t mem_clk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_clock_reg_t; - -/** Type of mem_sram_clk register - * SPI0 external RAM clock control register - */ -typedef union { - struct { - /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_l:8; - /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_h:8; - /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(SPI_MEM_SCLKCNT_N+1) - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclkcnt_n:8; - uint32_t reserved_24:7; - /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk - * is divided from system clock. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclk_equ_sysclk:1; - }; - uint32_t val; -} spi_mem_sram_clk_reg_t; - -/** Type of mem_clock_gate register - * SPI0 clock gate register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 1; - * Register clock gate enable signal. 1: Enable. 0: Disable. - */ - uint32_t clk_en:1; - /** mspi_clk_force_on : HRO; bitpos: [1]; default: 1; - * MSPI lowpower function clock gate force on signal. 1: Enable. 0: Disable. - */ - uint32_t mspi_clk_force_on:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_clock_gate_reg_t; - - -/** Group: Flash User-defined control registers */ -/** Type of mem_user register - * SPI0 user register. - */ -typedef union { - struct { - uint32_t reserved_0:6; - /** mem_cs_hold : R/W; bitpos: [6]; default: 0; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t mem_cs_hold:1; - /** mem_cs_setup : R/W; bitpos: [7]; default: 0; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - */ - uint32_t mem_cs_setup:1; - uint32_t reserved_8:1; - /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. - */ - uint32_t mem_ck_out_edge:1; - uint32_t reserved_10:16; - /** mem_usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. - */ - uint32_t mem_usr_dummy_idle:1; - uint32_t reserved_27:2; - /** mem_usr_dummy : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. - */ - uint32_t mem_usr_dummy:1; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_user_reg_t; - -/** Type of mem_user1 register - * SPI0 user1 register. - */ -typedef union { - struct { - /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). - */ - uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; - * SPI0 USR_CMD read or write data byte length -1 - */ - uint32_t mem_usr_dbytelen:6; - uint32_t reserved_12:14; - /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; - * The length in bits of address phase. The register value shall be (bit_num-1). - */ - uint32_t mem_usr_addr_bitlen:6; - }; - uint32_t val; -} spi_mem_user1_reg_t; - -/** Type of mem_user2 register - * SPI0 user2 register. - */ -typedef union { - struct { - /** mem_usr_command_value : R/W; bitpos: [15:0]; default: 0; - * The value of command. - */ - uint32_t mem_usr_command_value:16; - uint32_t reserved_16:12; - /** mem_usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be (bit_num-1) - */ - uint32_t mem_usr_command_bitlen:4; - }; - uint32_t val; -} spi_mem_user2_reg_t; - -/** Type of mem_rd_status register - * SPI0 read control register. - */ -typedef union { - struct { - uint32_t reserved_0:16; - /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode:8; - /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; - * Mode bits length for flash fast read mode. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode_bitlen:3; - /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; - * Mode bits is valid while this bit is enable. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_wb_mode_en:1; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_rd_status_reg_t; - - -/** Group: External RAM Control and configuration registers */ -/** Type of mem_cache_sctrl register - * SPI0 external RAM control register - */ -typedef union { - struct { - /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; - * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: - * enable, 0:disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_usr_saddr_4byte:1; - /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; - * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_sram_dio:1; - /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; - * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_sram_qio:1; - /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_wr_sram_dummy:1; - /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; - * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read - * operations. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_usr_rd_sram_dummy:1; - /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; - * For SPI0, In the external RAM mode cache read external RAM for user define command. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rcmd:1; - /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_rdummy_cyclelen:6; - uint32_t reserved_12:2; - /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; - * For SPI0, In the external RAM mode, it is the length in bits of address phase. The - * register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_addr_bitlen:6; - /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; - * For SPI0, In the external RAM mode cache write sram for user define command - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wcmd:1; - /** mem_sram_oct : R/W; bitpos: [21]; default: 0; - * reserved - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_oct:1; - /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; - * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sram_wdummy_cyclelen:6; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_cache_sctrl_reg_t; - -/** Type of mem_sram_cmd register - * SPI0 external RAM mode control register - */ -typedef union { - struct { - /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed - * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: - * SPI clock is always on. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sclk_mode:2; - /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; - * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_fastrd_mode bit. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_swb_mode:8; - /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; - * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_dual:1; - /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; - * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_dual:1; - /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; - * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_dio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_dual:1; - uint32_t reserved_13:1; - /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; - * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_quad:1; - /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; - * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_quad:1; - /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_quad:1; - /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; - * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_usr_sram_qio. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_scmd_quad:1; - /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; - * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_oct:1; - /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; - * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_oct:1; - /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; - * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_saddr_oct:1; - /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; - * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_scmd_oct:1; - /** mem_sdummy_rin : R/W; bitpos: [22]; default: 1; - * In the dummy phase of a MSPI read data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdummy_rin:1; - /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; - * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the - * signal level of SPI bus is output by the MSPI controller. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdummy_wout:1; - /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_DQS is output by the MSPI controller. - */ - uint32_t smem_wdummy_dqs_always_out:1; - /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; - * In the dummy phase of an MSPI write data transfer when accesses to external RAM, - * the level of SPI_IO[7:0] is output by the MSPI controller. - */ - uint32_t smem_wdummy_always_out:1; - /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; - * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdin_hex:1; - /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; - * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_sdout_hex:1; - uint32_t reserved_28:2; - /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are - * always 1. 0: Others. - */ - uint32_t smem_dqs_ie_always_on:1; - /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; - * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] - * are always 1. 0: Others. - */ - uint32_t smem_data_ie_always_on:1; - }; - uint32_t val; -} spi_mem_sram_cmd_reg_t; - -/** Type of mem_sram_drd_cmd register - * SPI0 external RAM DDR read command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the read command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rd_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the length in bits of command phase for - * sram. The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_rd_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_drd_cmd_reg_t; - -/** Type of mem_sram_dwr_cmd register - * SPI0 external RAM DDR write command control register - */ -typedef union { - struct { - /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; - * For SPI0,When cache mode is enable it is the write command value of command phase - * for sram. - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wr_cmd_value:16; - uint32_t reserved_16:12; - /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; - * For SPI0,When cache mode is enable it is the in bits of command phase for sram. - * The register value shall be (bit_num-1). - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_cache_sram_usr_wr_cmd_bitlen:4; - }; - uint32_t val; -} spi_mem_sram_dwr_cmd_reg_t; - -/** Type of smem_ddr register - * SPI0 external RAM DDR mode control register - */ -typedef union { - struct { - /** smem_ddr_en : R/W; bitpos: [0]; default: 0; - * 1: in DDR mode, 0 in SDR mode - */ - uint32_t smem_ddr_en:1; - /** smem_var_dummy : R/W; bitpos: [1]; default: 0; - * Set the bit to enable variable dummy cycle in spi DDR mode. - */ - uint32_t smem_var_dummy:1; - /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; - * Set the bit to reorder rx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_rdat_swp:1; - /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; - * Set the bit to reorder tx data of the word in spi DDR mode. - */ - uint32_t smem_ddr_wdat_swp:1; - /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; - * the bit is used to disable dual edge in command phase when DDR mode. - */ - uint32_t smem_ddr_cmd_dis:1; - /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; - * It is the minimum output data length in the DDR psram. - */ - uint32_t smem_outminbytelen:7; - /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when - * accesses to external RAM. - */ - uint32_t smem_tx_ddr_msk_en:1; - /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; - * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when - * accesses to external RAM. - */ - uint32_t smem_rx_ddr_msk_en:1; - /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; - * The delay number of data strobe which from memory based on SPI clock. - */ - uint32_t smem_usr_ddr_dqs_thd:7; - /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; - * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or - * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and - * negative edge of SPI_DQS. - */ - uint32_t smem_ddr_dqs_loop:1; - uint32_t reserved_22:2; - /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; - * Set this bit to enable the differential SPI_CLK#. - */ - uint32_t smem_clk_diff_en:1; - uint32_t reserved_25:1; - /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; - * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. - */ - uint32_t smem_dqs_ca_in:1; - /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; - * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 - * accesses flash or SPI1 accesses flash or sram. - */ - uint32_t smem_hyperbus_dummy_2x:1; - /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; - * Set this bit to invert SPI_DIFF when accesses to external RAM. . - */ - uint32_t smem_clk_diff_inv:1; - /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; - * Set this bit to enable octa_ram address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], - * 1'b0}. - */ - uint32_t smem_octa_ram_addr:1; - /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; - * Set this bit to enable HyperRAM address out when accesses to external RAM, which - * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. - */ - uint32_t smem_hyperbus_ca:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_smem_ddr_reg_t; - -/** Type of smem_ac register - * MSPI external RAM ECC and SPI CS timing control register - */ -typedef union { - struct { - /** smem_cs_setup : R/W; bitpos: [0]; default: 0; - * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: - * disable. - */ - uint32_t smem_cs_setup:1; - /** smem_cs_hold : R/W; bitpos: [1]; default: 0; - * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. - */ - uint32_t smem_cs_hold:1; - /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; - * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_cs_setup bit. - */ - uint32_t smem_cs_setup_time:5; - /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; - * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_cs_hold bit. - */ - uint32_t smem_cs_hold_time:5; - /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; - * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold - * cycles in ECC mode when accessed external RAM. - */ - uint32_t smem_ecc_cs_hold_time:3; - /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; - * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when - * accesses external RAM. - */ - uint32_t smem_ecc_skip_page_corner:1; - /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; - * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when - * accesses external RAM. - */ - uint32_t smem_ecc_16to18_byte_en:1; - uint32_t reserved_17:8; - /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; - * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) - * MSPI core clock cycles. - */ - uint32_t smem_cs_hold_delay:6; - /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; - * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI - * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter - * whether there is an ECC region or not. - */ - uint32_t smem_split_trans_en:1; - }; - uint32_t val; -} spi_smem_ac_reg_t; - - -/** Group: State control register */ -/** Type of mem_fsm register - * SPI0 FSM status register - */ -typedef union { - struct { - uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; - * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. - */ - uint32_t mem_lock_delay_time:12; - /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; - * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_flash_lock_en:1; - /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; - * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. - */ - uint32_t mem_sram_lock_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_mem_fsm_reg_t; - - -/** Group: Interrupt registers */ -/** Type of mem_int_ena register - * SPI0 interrupt enable register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_ena:1; - /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_ena:1; - /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_ena:1; - /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; - * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_ena:1; - /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; - * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_ena:1; - /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_ena:1; - /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; - * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_ena:1; - }; - uint32_t val; -} spi_mem_int_ena_reg_t; - -/** Type of mem_int_clr register - * SPI0 interrupt clear register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_clr:1; - /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; - * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_clr:1; - /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_clr:1; - /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; - * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_clr:1; - /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; - * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_clr:1; - /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_clr:1; - /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; - * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_clr:1; - }; - uint32_t val; -} spi_mem_int_clr_reg_t; - -/** Type of mem_int_raw register - * SPI0 interrupt raw register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is - * changed from non idle state to idle state. It means that SPI_CS raises high. 0: - * Others - */ - uint32_t mem_slv_st_end_int_raw:1; - /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is - * changed from non idle state to idle state. 0: Others. - */ - uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is - * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times - * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN - * are cleared, this bit will not be triggered. - */ - uint32_t mem_ecc_err_int_raw:1; - /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is - * rejected. 0: Others. - */ - uint32_t mem_pms_reject_int_raw:1; - /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write - * flash request is received. 0: Others. - */ - uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write - * address is invalid by compared to MMU configuration. 0: Others. - */ - uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; - * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS1 is overflow. - */ - uint32_t mem_dqs0_afifo_ovf_int_raw:1; - /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; - * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO - * connected to SPI_DQS is overflow. - */ - uint32_t mem_dqs1_afifo_ovf_int_raw:1; - /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo1_udf_int_raw:1; - /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; - * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is - * underflow. - */ - uint32_t mem_bus_fifo0_udf_int_raw:1; - }; - uint32_t val; -} spi_mem_int_raw_reg_t; - -/** Type of mem_int_st register - * SPI0 interrupt status register - */ -typedef union { - struct { - uint32_t reserved_0:3; - /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. - */ - uint32_t mem_slv_st_end_int_st:1; - /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for SPI_MEM_MST_ST_END_INT interrupt. - */ - uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; - * The status bit for SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t mem_ecc_err_int_st:1; - /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. - */ - uint32_t mem_pms_reject_int_st:1; - /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; - * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. - */ - uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; - * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. - */ - uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:18; - /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; - * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs0_afifo_ovf_int_st:1; - /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; - * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. - */ - uint32_t mem_dqs1_afifo_ovf_int_st:1; - /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo1_udf_int_st:1; - /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; - * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. - */ - uint32_t mem_bus_fifo0_udf_int_st:1; - }; - uint32_t val; -} spi_mem_int_st_reg_t; - - -/** Group: PMS control and configuration registers */ -/** Type of fmem_pmsn_attr register - * SPI1 flash PMS section n attribute register - */ -typedef union { - struct { - /** fmem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 flash PMS section n read accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_rd_attr:1; - /** fmem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 flash PMS section n write accessible. 0: Not allowed. - */ - uint32_t fmem_pmsn_wr_attr:1; - /** fmem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 flash PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The flash PMS - * section n is configured by registers SPI_FMEM_PMSn_ADDR_REG and - * SPI_FMEM_PMSn_SIZE_REG. - */ - uint32_t fmem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_fmem_pmsn_attr_reg_t; - -/** Type of fmem_pmsn_addr register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 flash PMS section n start address value - */ - uint32_t fmem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_fmem_pmsn_addr_reg_t; - -/** Type of fmem_pmsn_size register - * SPI1 flash PMS section n start address register - */ -typedef union { - struct { - /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, - * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) - */ - uint32_t fmem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_fmem_pmsn_size_reg_t; - -/** Type of smem_pmsn_attr register - * SPI1 external RAM PMS section n attribute register - */ -typedef union { - struct { - /** smem_pmsn_rd_attr : R/W; bitpos: [0]; default: 1; - * 1: SPI1 external RAM PMS section n read accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_rd_attr:1; - /** smem_pmsn_wr_attr : R/W; bitpos: [1]; default: 1; - * 1: SPI1 external RAM PMS section n write accessible. 0: Not allowed. - */ - uint32_t smem_pmsn_wr_attr:1; - /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; - * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and - * SPI_SMEM_PMSn_SIZE_REG. - */ - uint32_t smem_pmsn_ecc:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} spi_smem_pmsn_attr_reg_t; - -/** Type of smem_pmsn_addr register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; - * SPI1 external RAM PMS section n start address value - */ - uint32_t smem_pmsn_addr_s:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_smem_pmsn_addr_reg_t; - -/** Type of smem_pmsn_size register - * SPI1 external RAM PMS section n start address register - */ -typedef union { - struct { - /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, - * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) - */ - uint32_t smem_pmsn_size:17; - uint32_t reserved_17:15; - }; - uint32_t val; -} spi_smem_pmsn_size_reg_t; - -/** Type of mem_pms_reject register - * SPI1 access reject register - */ -typedef union { - struct { - uint32_t reserved_0:27; - /** mem_pm_en : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI0/1 transfer permission control function. - */ - uint32_t mem_pm_en:1; - /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; - * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ld:1; - /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; - * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_st:1; - /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; - * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_multi_hit:1; - /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; - * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_pms_ivd:1; - }; - uint32_t val; -} spi_mem_pms_reject_reg_t; - -/** Type of mem_pms_reject_addr register - * SPI1 access reject addr register - */ -typedef union { - struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_reject_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_pms_reject_addr_reg_t; - - -/** Group: MSPI ECC registers */ -/** Type of mem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:5; - /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; - * This bits show the error times of MSPI ECC read. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_cnt:6; - /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. - */ - uint32_t fmem_ecc_err_int_num:6; - /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. - */ - uint32_t fmem_ecc_err_int_en:1; - /** fmem_page_size : R/W; bitpos: [19:18]; default: 0; - * Set the page size of the flash accessed by MSPI. 0: 256 bytes. 1: 512 bytes. 2: - * 1024 bytes. 3: 2048 bytes. - */ - uint32_t fmem_page_size:2; - uint32_t reserved_20:1; - /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit - * should be 0. Otherwise, this bit should be 1. - */ - uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; - * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. - */ - uint32_t mem_usr_ecc_addr_en:1; - uint32_t reserved_23:1; - /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; - * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and - * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. - */ - uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; - * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to - * byte 0 bit 0 to byte 15 bit 7) - */ - uint32_t mem_ecc_err_bits:7; - }; - uint32_t val; -} spi_mem_ecc_ctrl_reg_t; - -/** Type of mem_ecc_err_addr register - * MSPI ECC error address register - */ -typedef union { - struct { - /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; - * This bits show the first MSPI ECC error address. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - uint32_t mem_ecc_err_addr:29; - uint32_t reserved_29:3; - }; - uint32_t val; -} spi_mem_ecc_err_addr_reg_t; - -/** Type of smem_ecc_ctrl register - * MSPI ECC control register - */ -typedef union { - struct { - uint32_t reserved_0:17; - /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; - * Set this bit to calculate the error times of MSPI ECC read when accesses to - * external RAM. - */ - uint32_t smem_ecc_err_int_en:1; - /** smem_page_size : R/W; bitpos: [19:18]; default: 2; - * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. - * 2: 1024 bytes. 3: 2048 bytes. - */ - uint32_t smem_page_size:2; - /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; - * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the - * ECC region or non-ECC region of external RAM. If there is no ECC region in external - * RAM, this bit should be 0. Otherwise, this bit should be 1. - */ - uint32_t smem_ecc_addr_en:1; - uint32_t reserved_21:11; - }; - uint32_t val; -} spi_smem_ecc_ctrl_reg_t; - - -/** Group: Status and state control registers */ -/** Type of smem_axi_addr_ctrl register - * SPI0 AXI address control register - */ -typedef union { - struct { - uint32_t reserved_0:26; - /** mem_all_fifo_empty : RO; bitpos: [26]; default: 1; - * The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers - * and SPI0 transfers are done. 0: Others. - */ - uint32_t mem_all_fifo_empty:1; - /** rdata_afifo_rempty : RO; bitpos: [27]; default: 1; - * 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t rdata_afifo_rempty:1; - /** raddr_afifo_rempty : RO; bitpos: [28]; default: 1; - * 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending. - */ - uint32_t raddr_afifo_rempty:1; - /** wdata_afifo_rempty : RO; bitpos: [29]; default: 1; - * 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wdata_afifo_rempty:1; - /** wblen_afifo_rempty : RO; bitpos: [30]; default: 1; - * 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending. - */ - uint32_t wblen_afifo_rempty:1; - /** all_axi_trans_afifo_empty : RO; bitpos: [31]; default: 1; - * This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and - * RDATA_AFIFO are empty and spi0_mst_st is IDLE. - */ - uint32_t all_axi_trans_afifo_empty:1; - }; - uint32_t val; -} spi_smem_axi_addr_ctrl_reg_t; - -/** Type of mem_axi_err_resp_en register - * SPI0 AXI error response enable register - */ -typedef union { - struct { - /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; - * Set this bit to enable AXI response function for axi flash err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; - * Set this bit to enable AXI response function for mmu sens in err axi write trans. - */ - uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; - * Set this bit to enable AXI response function for axi wstrb err in axi write trans. - */ - uint32_t mem_aw_resp_en_axi_wstrb:1; - /** mem_ar_resp_en_mmu_vld : R/W; bitpos: [7]; default: 0; - * Set this bit to enable AXI response function for mmu valid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_vld:1; - /** mem_ar_resp_en_mmu_gid : R/W; bitpos: [8]; default: 0; - * Set this bit to enable AXI response function for mmu gid err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_gid:1; - /** mem_ar_resp_en_mmu_ecc : R/W; bitpos: [9]; default: 0; - * Set this bit to enable AXI response function for mmu ecc err in axi read trans. - */ - uint32_t mem_ar_resp_en_mmu_ecc:1; - /** mem_ar_resp_en_mmu_sens : R/W; bitpos: [10]; default: 0; - * Set this bit to enable AXI response function for mmu sensitive err in axi read - * trans. - */ - uint32_t mem_ar_resp_en_mmu_sens:1; - /** mem_ar_resp_en_axi_size : R/W; bitpos: [11]; default: 0; - * Set this bit to enable AXI response function for axi size err in axi read trans. - */ - uint32_t mem_ar_resp_en_axi_size:1; - uint32_t reserved_12:20; - }; - uint32_t val; -} spi_mem_axi_err_resp_en_reg_t; - - -/** Group: Flash timing registers */ -/** Type of mem_timing_cali register - * SPI0 flash timing calibration register - */ -typedef union { - struct { - /** mem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * The bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t mem_timing_clk_ena:1; - /** mem_timing_cali : R/W; bitpos: [1]; default: 0; - * The bit is used to enable timing auto-calibration for all reading operations. - */ - uint32_t mem_timing_cali:1; - /** mem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * flash. - */ - uint32_t mem_dll_timing_cali:1; - /** mem_timing_cali_update : WT; bitpos: [6]; default: 0; - * Set this bit to update delay mode, delay num and extra dummy in MSPI. - */ - uint32_t mem_timing_cali_update:1; - uint32_t reserved_7:25; - }; - uint32_t val; -} spi_mem_timing_cali_reg_t; - -/** Type of mem_din_mode register - * MSPI flash input timing delay mode control register - */ -typedef union { - struct { - /** mem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din0_mode:3; - /** mem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din1_mode:3; - /** mem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din2_mode:3; - /** mem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t mem_din3_mode:3; - /** mem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din4_mode:3; - /** mem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din5_mode:3; - /** mem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din6_mode:3; - /** mem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_din7_mode:3; - /** mem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the spi_clk - */ - uint32_t mem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_mem_din_mode_reg_t; - -/** Type of mem_din_num register - * MSPI flash input timing delay number control register - */ -typedef union { - struct { - /** mem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din0_num:2; - /** mem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din1_num:2; - /** mem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din2_num:2; - /** mem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din3_num:2; - /** mem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din4_num:2; - /** mem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din5_num:2; - /** mem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din6_num:2; - /** mem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_din7_num:2; - /** mem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t mem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_mem_din_num_reg_t; - -/** Type of mem_dout_mode register - * MSPI flash output timing adjustment control register - */ -typedef union { - struct { - /** mem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout0_mode:1; - /** mem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout1_mode:1; - /** mem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout2_mode:1; - /** mem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t mem_dout3_mode:1; - /** mem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout4_mode:1; - /** mem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout5_mode:1; - /** mem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout6_mode:1; - /** mem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_dout7_mode:1; - /** mem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the spi_clk - */ - uint32_t mem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_mem_dout_mode_reg_t; - - -/** Group: External RAM timing registers */ -/** Type of smem_timing_cali register - * MSPI external RAM timing calibration register - */ -typedef union { - struct { - /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; - * For sram, the bit is used to enable timing adjust clock for all reading operations. - */ - uint32_t smem_timing_clk_ena:1; - /** smem_timing_cali : R/W; bitpos: [1]; default: 0; - * For sram, the bit is used to enable timing auto-calibration for all reading - * operations. - */ - uint32_t smem_timing_cali:1; - /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; - * For sram, add extra dummy spi clock cycle length for spi clock calibration. - */ - uint32_t smem_extra_dummy_cyclelen:3; - /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; - * Set this bit to enable DLL for timing calibration in DDR mode when accessed to - * EXT_RAM. - */ - uint32_t smem_dll_timing_cali:1; - uint32_t reserved_6:1; - /** smem_dqs0_270_sel : HRO; bitpos: [8:7]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_270_sel:2; - /** smem_dqs0_90_sel : HRO; bitpos: [10:9]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs0_90_sel:2; - /** smem_dqs1_270_sel : HRO; bitpos: [12:11]; default: 1; - * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. - * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs1_270_sel:2; - /** smem_dqs1_90_sel : HRO; bitpos: [14:13]; default: 1; - * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, - * 2'd2: 1.5ns 2'd3: 2.0ns. - */ - uint32_t smem_dqs1_90_sel:2; - uint32_t reserved_15:17; - }; - uint32_t val; -} spi_smem_timing_cali_reg_t; - -/** Type of smem_din_mode register - * MSPI external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din0_mode:3; - /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din1_mode:3; - /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din2_mode:3; - /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din3_mode:3; - /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din4_mode:3; - /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din5_mode:3; - /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din6_mode:3; - /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din7_mode:3; - /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_mode_reg_t; - -/** Type of smem_din_num register - * MSPI external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din0_num:2; - /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din1_num:2; - /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din2_num:2; - /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din3_num:2; - /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din4_num:2; - /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din5_num:2; - /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din6_num:2; - /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din7_num:2; - /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_num_reg_t; - -/** Type of smem_dout_mode register - * MSPI external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout0_mode:1; - /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout1_mode:1; - /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout2_mode:1; - /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout3_mode:1; - /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout4_mode:1; - /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout5_mode:1; - /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout6_mode:1; - /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout7_mode:1; - /** smem_douts_mode : R/W; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_mode_reg_t; - -/** Type of smem_din_hex_mode register - * MSPI 16x external RAM input timing delay mode control register - */ -typedef union { - struct { - /** smem_din08_mode : HRO; bitpos: [2:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din08_mode:3; - /** smem_din09_mode : HRO; bitpos: [5:3]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din09_mode:3; - /** smem_din10_mode : HRO; bitpos: [8:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din10_mode:3; - /** smem_din11_mode : HRO; bitpos: [11:9]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din11_mode:3; - /** smem_din12_mode : HRO; bitpos: [14:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din12_mode:3; - /** smem_din13_mode : HRO; bitpos: [17:15]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din13_mode:3; - /** smem_din14_mode : HRO; bitpos: [20:18]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din14_mode:3; - /** smem_din15_mode : HRO; bitpos: [23:21]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_din15_mode:3; - /** smem_dins_hex_mode : HRO; bitpos: [26:24]; default: 0; - * the input signals are delayed by system clock cycles, 0: input without delayed, 1: - * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input - * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the - * spi_clk high edge, 6: input with the spi_clk low edge - */ - uint32_t smem_dins_hex_mode:3; - uint32_t reserved_27:5; - }; - uint32_t val; -} spi_smem_din_hex_mode_reg_t; - -/** Type of smem_din_hex_num register - * MSPI 16x external RAM input timing delay number control register - */ -typedef union { - struct { - /** smem_din08_num : HRO; bitpos: [1:0]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din08_num:2; - /** smem_din09_num : HRO; bitpos: [3:2]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din09_num:2; - /** smem_din10_num : HRO; bitpos: [5:4]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din10_num:2; - /** smem_din11_num : HRO; bitpos: [7:6]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din11_num:2; - /** smem_din12_num : HRO; bitpos: [9:8]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din12_num:2; - /** smem_din13_num : HRO; bitpos: [11:10]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din13_num:2; - /** smem_din14_num : HRO; bitpos: [13:12]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din14_num:2; - /** smem_din15_num : HRO; bitpos: [15:14]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_din15_num:2; - /** smem_dins_hex_num : HRO; bitpos: [17:16]; default: 0; - * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: - * delayed by 2 cycles,... - */ - uint32_t smem_dins_hex_num:2; - uint32_t reserved_18:14; - }; - uint32_t val; -} spi_smem_din_hex_num_reg_t; - -/** Type of smem_dout_hex_mode register - * MSPI 16x external RAM output timing adjustment control register - */ -typedef union { - struct { - /** smem_dout08_mode : HRO; bitpos: [0]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout08_mode:1; - /** smem_dout09_mode : HRO; bitpos: [1]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout09_mode:1; - /** smem_dout10_mode : HRO; bitpos: [2]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout10_mode:1; - /** smem_dout11_mode : HRO; bitpos: [3]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout11_mode:1; - /** smem_dout12_mode : HRO; bitpos: [4]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout12_mode:1; - /** smem_dout13_mode : HRO; bitpos: [5]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout13_mode:1; - /** smem_dout14_mode : HRO; bitpos: [6]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout14_mode:1; - /** smem_dout15_mode : HRO; bitpos: [7]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_dout15_mode:1; - /** smem_douts_hex_mode : HRO; bitpos: [8]; default: 0; - * the output signals are delayed by system clock cycles, 0: output without delayed, - * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: - * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output - * with the spi_clk high edge ,6: output with the spi_clk low edge - */ - uint32_t smem_douts_hex_mode:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} spi_smem_dout_hex_mode_reg_t; - - -/** Group: NAND FLASH control and status registers */ -/** Type of mem_nand_flash_en register - * NAND FLASH control register - */ -typedef union { - struct { - /** mem_nand_flash_en : HRO; bitpos: [0]; default: 0; - * NAND FLASH function enable signal. 1: Enable NAND FLASH, Disable NOR FLASH. 0: - * Disable NAND FLASH, Enable NOR FLASH. - */ - uint32_t mem_nand_flash_en:1; - /** mem_nand_flash_seq_hd_index : HRO; bitpos: [15:1]; default: 32767; - * NAND FLASH spi seq head index configure register. Every 5 bits represent the 1st - * index of a SPI CMD sequence.[14:10]:usr; [9:5]:axi_rd; [4:0]:axi_wr. - */ - uint32_t mem_nand_flash_seq_hd_index:15; - /** mem_nand_flash_seq_usr_trig : HRO; bitpos: [16]; default: 0; - * NAND FLASH spi seq user trigger configure register. SPI_MEM_NAND_FLASH_SEQ_USR_TRIG - * is corresponds to SPI_MEM_NAND_FLASH_SEQ_HD_INDEX[14:10].1: enable 0: disable. - */ - uint32_t mem_nand_flash_seq_usr_trig:1; - /** mem_nand_flash_lut_en : HRO; bitpos: [17]; default: 0; - * NAND FLASH spi seq & cmd lut cfg en. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_lut_en:1; - /** mem_nand_flash_seq_usr_wend : HRO; bitpos: [18]; default: 0; - * Used with SPI_MEM_NAND_FLASH_SEQ_USR_TRIG to indicate the last page program ,and to - * execute page execute. 1: write end 0: write in a page size. - */ - uint32_t mem_nand_flash_seq_usr_wend:1; - uint32_t reserved_19:13; - }; - uint32_t val; -} spi_mem_nand_flash_en_reg_t; - -/** Type of mem_nand_flash_sr_addr0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_addr0 : HRO; bitpos: [7:0]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr0:8; - /** mem_nand_flash_sr_addr1 : HRO; bitpos: [15:8]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr1:8; - /** mem_nand_flash_sr_addr2 : HRO; bitpos: [23:16]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr2:8; - /** mem_nand_flash_sr_addr3 : HRO; bitpos: [31:24]; default: 0; - * configure state register address for SPI SEQ need. If OIP is in address C0H , user - * could configure C0H into this register - */ - uint32_t mem_nand_flash_sr_addr3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_addr0_reg_t; - -/** Type of mem_nand_flash_sr_din0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_sr_din0 : RO; bitpos: [7:0]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din0:8; - /** mem_nand_flash_sr_din1 : RO; bitpos: [15:8]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din1:8; - /** mem_nand_flash_sr_din2 : RO; bitpos: [23:16]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din2:8; - /** mem_nand_flash_sr_din3 : RO; bitpos: [31:24]; default: 0; - * spi read state register data to this register for SPI SEQ need. - * SPI_MEM_NAND_FLASH_SR_DIN0_REG corresponds to SPI_MEM_NAND_FLASH_SR_ADDR0_REG. - */ - uint32_t mem_nand_flash_sr_din3:8; - }; - uint32_t val; -} spi_mem_nand_flash_sr_din0_reg_t; - -/** Type of mem_nand_flash_cfg_data0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data0 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data0:16; - /** mem_nand_flash_cfg_data1 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data1:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data0_reg_t; - -/** Type of mem_nand_flash_cfg_data1 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data2 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data2:16; - /** mem_nand_flash_cfg_data3 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data3:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data1_reg_t; - -/** Type of mem_nand_flash_cfg_data2 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_cfg_data4 : HRO; bitpos: [15:0]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data4:16; - /** mem_nand_flash_cfg_data5 : HRO; bitpos: [31:16]; default: 0; - * configure data for SPI SEQ din/dout need. The data could be use to configure NAND - * FLASH or compare read data - */ - uint32_t mem_nand_flash_cfg_data5:16; - }; - uint32_t val; -} spi_mem_nand_flash_cfg_data2_reg_t; - -/** Type of mem_nand_flash_cmd_lut0 register - * MSPI NAND FLASH CMD LUT control register - */ -typedef union { - struct { - /** mem_nand_flash_lut_cmd_value0 : HRO; bitpos: [15:0]; default: 0; - * MSPI NAND FLASH config cmd value at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_value0:16; - /** mem_nand_flash_lut_sfsm_st_en0 : HRO; bitpos: [19:16]; default: 0; - * MSPI NAND FLASH config sfsm_st_en at cmd lut address 0.[3]-ADDR period enable; - * [2]-DUMMY period enable; [1]-DIN period; [0]-DOUT period. - */ - uint32_t mem_nand_flash_lut_sfsm_st_en0:4; - /** mem_nand_flash_lut_cmd_len0 : HRO; bitpos: [23:20]; default: 0; - * MSPI NAND FLASH config cmd length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_cmd_len0:4; - /** mem_nand_flash_lut_addr_len0 : HRO; bitpos: [27:24]; default: 0; - * MSPI NAND FLASH config address length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_addr_len0:4; - /** mem_nand_flash_lut_data_len0 : HRO; bitpos: [29:28]; default: 0; - * MSPI NAND FLASH config data length at cmd lut address 0. - */ - uint32_t mem_nand_flash_lut_data_len0:2; - /** mem_nand_flash_lut_bus_en0 : HRO; bitpos: [30]; default: 0; - * MSPI NAND FLASH config spi_bus_en at cmd lut address 0,SPI could use DUAL/QUAD mode - * while enable, SPI could use SINGLE mode while disable.1:Enable. 0:Disable.(Note - * these registers are described to indicate the SPI_MEM_NAND_FLASH_CMD_LUT0_REG's - * field. The number of CMD LUT entries can be defined by the user, but cannot exceed - * 16 ) - */ - uint32_t mem_nand_flash_lut_bus_en0:1; - uint32_t reserved_31:1; - }; - uint32_t val; -} spi_mem_nand_flash_cmd_lut0_reg_t; - -/** Type of mem_nand_flash_spi_seq0 register - * NAND FLASH SPI SEQ control register - */ -typedef union { - struct { - /** mem_nand_flash_seq_tail_flg0 : HRO; bitpos: [0]; default: 0; - * MSPI NAND FLASH config seq_tail_flg at spi seq index 0.1: The last index for - * sequence. 0: Not the last index. - */ - uint32_t mem_nand_flash_seq_tail_flg0:1; - /** mem_nand_flash_sr_chk_en0 : HRO; bitpos: [1]; default: 0; - * MSPI NAND FLASH config sr_chk_en at spi seq index 0. 1: enable 0: disable. - */ - uint32_t mem_nand_flash_sr_chk_en0:1; - /** mem_nand_flash_din_index0 : HRO; bitpos: [5:2]; default: 0; - * MSPI NAND FLASH config din_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_CFG_DATA - */ - uint32_t mem_nand_flash_din_index0:4; - /** mem_nand_flash_addr_index0 : HRO; bitpos: [9:6]; default: 0; - * MSPI NAND FLASH config addr_index at spi seq index 0. Use with - * SPI_MEM_NAND_FLASH_SR_ADDR - */ - uint32_t mem_nand_flash_addr_index0:4; - /** mem_nand_flash_req_or_cfg0 : HRO; bitpos: [10]; default: 0; - * MSPI NAND FLASH config reg_or_cfg at spi seq index 0. 1: AXI/APB request 0: SPI - * SEQ configuration. - */ - uint32_t mem_nand_flash_req_or_cfg0:1; - /** mem_nand_flash_cmd_index0 : HRO; bitpos: [14:11]; default: 0; - * MSPI NAND FLASH config spi_cmd_index at spi seq index 0. Use to find SPI command in - * CMD LUT.(Note these registers are described to indicate the - * SPI_MEM_NAND_FLASH_SPI_SEQ_REG' fieldd The number of CMD LUT entries can be defined - * by the user, but cannot exceed 16 ) - */ - uint32_t mem_nand_flash_cmd_index0:4; - uint32_t reserved_15:17; - }; - uint32_t val; -} spi_mem_nand_flash_spi_seq0_reg_t; - - -/** Group: Manual Encryption plaintext Memory */ -/** Type of mem_xts_plain_base register - * The base address of the memory that stores plaintext in Manual Encryption - */ -typedef union { - struct { - /** xts_plain : R/W; bitpos: [31:0]; default: 0; - * This field is only used to generate include file in c case. This field is useless. - * Please do not use this field. - */ - uint32_t xts_plain:32; - }; - uint32_t val; -} spi_mem_xts_plain_base_reg_t; - - -/** Group: Manual Encryption configuration registers */ -/** Type of mem_xts_linesize register - * Manual Encryption Line-Size register - */ -typedef union { - struct { - /** xts_linesize : R/W; bitpos: [1:0]; default: 0; - * This bits stores the line-size parameter which will be used in manual encryption - * calculation. It decides how many bytes will be encrypted one time. 0: 16-bytes, 1: - * 32-bytes, 2: 64-bytes, 3:reserved. - */ - uint32_t xts_linesize:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_linesize_reg_t; - -/** Type of mem_xts_destination register - * Manual Encryption destination register - */ -typedef union { - struct { - /** xts_destination : R/W; bitpos: [0]; default: 0; - * This bit stores the destination parameter which will be used in manual encryption - * calculation. 0: flash(default), 1: psram(reserved). Only default value can be used. - */ - uint32_t xts_destination:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destination_reg_t; - -/** Type of mem_xts_physical_address register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_physical_address : R/W; bitpos: [29:0]; default: 0; - * This bits stores the physical-address parameter which will be used in manual - * encryption calculation. This value should aligned with byte number decided by - * line-size parameter. - */ - uint32_t xts_physical_address:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_physical_address_reg_t; - - -/** Group: Manual Encryption control and status registers */ -/** Type of mem_xts_trigger register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_trigger : WT; bitpos: [0]; default: 0; - * Set this bit to trigger the process of manual encryption calculation. This action - * should only be asserted when manual encryption status is 0. After this action, - * manual encryption status becomes 1. After calculation is done, manual encryption - * status becomes 2. - */ - uint32_t xts_trigger:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_trigger_reg_t; - -/** Type of mem_xts_release register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_release : WT; bitpos: [0]; default: 0; - * Set this bit to release encrypted result to mspi. This action should only be - * asserted when manual encryption status is 2. After this action, manual encryption - * status will become 3. - */ - uint32_t xts_release:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_release_reg_t; - -/** Type of mem_xts_destroy register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_destroy : WT; bitpos: [0]; default: 0; - * Set this bit to destroy encrypted result. This action should be asserted only when - * manual encryption status is 3. After this action, manual encryption status will - * become 0. - */ - uint32_t xts_destroy:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} spi_mem_xts_destroy_reg_t; - -/** Type of mem_xts_state register - * Manual Encryption physical address register - */ -typedef union { - struct { - /** xts_state : RO; bitpos: [1:0]; default: 0; - * This bits stores the status of manual encryption. 0: idle, 1: busy of encryption - * calculation, 2: encryption calculation is done but the encrypted result is - * invisible to mspi, 3: the encrypted result is visible to mspi. - */ - uint32_t xts_state:2; - uint32_t reserved_2:30; - }; - uint32_t val; -} spi_mem_xts_state_reg_t; - - -/** Group: Manual Encryption version control register */ -/** Type of mem_xts_date register - * Manual Encryption version register - */ -typedef union { - struct { - /** xts_date : R/W; bitpos: [29:0]; default: 539035911; - * This bits stores the last modified-time of manual encryption feature. - */ - uint32_t xts_date:30; - uint32_t reserved_30:2; - }; - uint32_t val; -} spi_mem_xts_date_reg_t; - - -/** Group: MMU access registers */ -/** Type of mem_mmu_item_content register - * MSPI-MMU item content register - */ -typedef union { - struct { - /** mmu_item_content : R/W; bitpos: [31:0]; default: 892; - * MSPI-MMU item content - */ - uint32_t mmu_item_content:32; - }; - uint32_t val; -} spi_mem_mmu_item_content_reg_t; - -/** Type of mem_mmu_item_index register - * MSPI-MMU item index register - */ -typedef union { - struct { - /** mmu_item_index : R/W; bitpos: [31:0]; default: 0; - * MSPI-MMU item index - */ - uint32_t mmu_item_index:32; - }; - uint32_t val; -} spi_mem_mmu_item_index_reg_t; - - -/** Group: MMU power control and configuration registers */ -/** Type of mem_mmu_power_ctrl register - * MSPI MMU power control register - */ -typedef union { - struct { - /** mmu_mem_force_on : R/W; bitpos: [0]; default: 0; - * Set this bit to enable mmu-memory clock force on - */ - uint32_t mmu_mem_force_on:1; - /** mmu_mem_force_pd : R/W; bitpos: [1]; default: 0; - * Set this bit to force mmu-memory powerdown - */ - uint32_t mmu_mem_force_pd:1; - /** mmu_mem_force_pu : R/W; bitpos: [2]; default: 1; - * Set this bit to force mmu-memory powerup, in this case, the power should also be - * controlled by rtc. - */ - uint32_t mmu_mem_force_pu:1; - /** mmu_page_size : R/W; bitpos: [4:3]; default: 0; - * 0: Max page size , 1: Max page size/2 , 2: Max page size/4, 3: Max page size/8 - */ - uint32_t mmu_page_size:2; - uint32_t reserved_5:11; - /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; - * MMU PSRAM aux control register - */ - uint32_t mem_aux_ctrl:14; - /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; - * ECO register enable bit - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_rdn_ena:1; - /** mem_rdn_result : RO; bitpos: [31]; default: 0; - * MSPI module clock domain and AXI clock domain ECO register result register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_rdn_result:1; - }; - uint32_t val; -} spi_mem_mmu_power_ctrl_reg_t; - - -/** Group: External mem cryption DPA registers */ -/** Type of mem_dpa_ctrl register - * SPI memory cryption DPA register - */ -typedef union { - struct { - /** crypt_security_level : R/W; bitpos: [2:0]; default: 7; - * Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: - * The bigger the number is, the more secure the cryption is. (Note that the - * performance of cryption will decrease together with this number increasing) - */ - uint32_t crypt_security_level:3; - /** crypt_calc_d_dpa_en : R/W; bitpos: [3]; default: 1; - * Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the - * calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that - * using key 1. - */ - uint32_t crypt_calc_d_dpa_en:1; - /** crypt_dpa_select_register : R/W; bitpos: [4]; default: 0; - * 1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and - * SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits. - */ - uint32_t crypt_dpa_select_register:1; - uint32_t reserved_5:27; - }; - uint32_t val; -} spi_mem_dpa_ctrl_reg_t; - - -/** Group: External mem cryption PSEUDO registers */ -/** Type of mem_xts_pseudo_round_conf register - * SPI memory cryption PSEUDO register - */ -typedef union { - struct { - /** mem_mode_pseudo : R/W; bitpos: [1:0]; default: 0; - * Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo - * and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. - * 2'b11: crypto with pseudo. - */ - uint32_t mem_mode_pseudo:2; - /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; - * xts aes peseudo function base round that must be performed. - */ - uint32_t mem_pseudo_rng_cnt:3; - /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; - * xts aes peseudo function base round that must be performed. - */ - uint32_t mem_pseudo_base:4; - /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; - * xts aes peseudo function increment round that will be performed randomly between 0 & - * 2**(inc+1). - */ - uint32_t mem_pseudo_inc:2; - uint32_t reserved_11:21; - }; - uint32_t val; -} spi_mem_xts_pseudo_round_conf_reg_t; - - -/** Group: ECO registers */ -/** Type of mem_registerrnd_eco_high register - * MSPI ECO high register - */ -typedef union { - struct { - /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; - * ECO high register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_registerrnd_eco_high:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_high_reg_t; - -/** Type of mem_registerrnd_eco_low register - * MSPI ECO low register - */ -typedef union { - struct { - /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; - * ECO low register - * This field is only for internal debugging purposes. Do not use it in applications. - */ - uint32_t mem_registerrnd_eco_low:32; - }; - uint32_t val; -} spi_mem_registerrnd_eco_low_reg_t; - - -/** Group: Version control register */ -/** Type of mem_date register - * SPI0 version control register - */ -typedef union { - struct { - /** mem_date : R/W; bitpos: [27:0]; default: 37822512; - * SPI0 register version. - */ - uint32_t mem_date:28; - uint32_t reserved_28:4; - }; - uint32_t val; -} spi_mem_date_reg_t; - - -typedef struct { - volatile spi_mem_cmd_reg_t mem_cmd; - uint32_t reserved_004; - volatile spi_mem_ctrl_reg_t mem_ctrl; - volatile spi_mem_ctrl1_reg_t mem_ctrl1; - volatile spi_mem_ctrl2_reg_t mem_ctrl2; - volatile spi_mem_clock_reg_t mem_clock; - volatile spi_mem_user_reg_t mem_user; - volatile spi_mem_user1_reg_t mem_user1; - volatile spi_mem_user2_reg_t mem_user2; - uint32_t reserved_024[2]; - volatile spi_mem_rd_status_reg_t mem_rd_status; - uint32_t reserved_030; - volatile spi_mem_misc_reg_t mem_misc; - uint32_t reserved_038; - volatile spi_mem_cache_fctrl_reg_t mem_cache_fctrl; - volatile spi_mem_cache_sctrl_reg_t mem_cache_sctrl; - volatile spi_mem_sram_cmd_reg_t mem_sram_cmd; - volatile spi_mem_sram_drd_cmd_reg_t mem_sram_drd_cmd; - volatile spi_mem_sram_dwr_cmd_reg_t mem_sram_dwr_cmd; - volatile spi_mem_sram_clk_reg_t mem_sram_clk; - volatile spi_mem_fsm_reg_t mem_fsm; - uint32_t reserved_058[26]; - volatile spi_mem_int_ena_reg_t mem_int_ena; - volatile spi_mem_int_clr_reg_t mem_int_clr; - volatile spi_mem_int_raw_reg_t mem_int_raw; - volatile spi_mem_int_st_reg_t mem_int_st; - uint32_t reserved_0d0; - volatile spi_mem_ddr_reg_t mem_ddr; - volatile spi_smem_ddr_reg_t smem_ddr; - uint32_t reserved_0dc[9]; - volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; - volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; - volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; - volatile spi_mem_pms_reject_reg_t mem_pms_reject; - volatile spi_mem_pms_reject_addr_reg_t mem_pms_reject_addr; - volatile spi_mem_ecc_ctrl_reg_t mem_ecc_ctrl; - volatile spi_mem_ecc_err_addr_reg_t mem_ecc_err_addr; - volatile spi_mem_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; - volatile spi_mem_axi_err_resp_en_reg_t mem_axi_err_resp_en; - volatile spi_mem_timing_cali_reg_t mem_timing_cali; - volatile spi_mem_din_mode_reg_t mem_din_mode; - volatile spi_mem_din_num_reg_t mem_din_num; - volatile spi_mem_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_din_mode_reg_t smem_din_mode; - volatile spi_smem_din_num_reg_t smem_din_num; - volatile spi_smem_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_ac_reg_t smem_ac; - volatile spi_smem_din_hex_mode_reg_t smem_din_hex_mode; - volatile spi_smem_din_hex_num_reg_t smem_din_hex_num; - volatile spi_smem_dout_hex_mode_reg_t smem_dout_hex_mode; - uint32_t reserved_1b0[20]; - volatile spi_mem_clock_gate_reg_t mem_clock_gate; - volatile spi_mem_nand_flash_en_reg_t mem_nand_flash_en; - volatile spi_mem_nand_flash_sr_addr0_reg_t mem_nand_flash_sr_addr0; - volatile spi_mem_nand_flash_sr_din0_reg_t mem_nand_flash_sr_din0; - volatile spi_mem_nand_flash_cfg_data0_reg_t mem_nand_flash_cfg_data0; - volatile spi_mem_nand_flash_cfg_data1_reg_t mem_nand_flash_cfg_data1; - volatile spi_mem_nand_flash_cfg_data2_reg_t mem_nand_flash_cfg_data2; - uint32_t reserved_21c[9]; - volatile spi_mem_nand_flash_cmd_lut0_reg_t mem_nand_flash_cmd_lut0; - uint32_t reserved_244[15]; - volatile spi_mem_nand_flash_spi_seq0_reg_t mem_nand_flash_spi_seq0; - uint32_t reserved_284[31]; - volatile spi_mem_xts_plain_base_reg_t mem_xts_plain_base; - uint32_t reserved_304[15]; - volatile spi_mem_xts_linesize_reg_t mem_xts_linesize; - volatile spi_mem_xts_destination_reg_t mem_xts_destination; - volatile spi_mem_xts_physical_address_reg_t mem_xts_physical_address; - volatile spi_mem_xts_trigger_reg_t mem_xts_trigger; - volatile spi_mem_xts_release_reg_t mem_xts_release; - volatile spi_mem_xts_destroy_reg_t mem_xts_destroy; - volatile spi_mem_xts_state_reg_t mem_xts_state; - volatile spi_mem_xts_date_reg_t mem_xts_date; - uint32_t reserved_360[7]; - volatile spi_mem_mmu_item_content_reg_t mem_mmu_item_content; - volatile spi_mem_mmu_item_index_reg_t mem_mmu_item_index; - volatile spi_mem_mmu_power_ctrl_reg_t mem_mmu_power_ctrl; - volatile spi_mem_dpa_ctrl_reg_t mem_dpa_ctrl; - volatile spi_mem_xts_pseudo_round_conf_reg_t mem_xts_pseudo_round_conf; - uint32_t reserved_390[24]; - volatile spi_mem_registerrnd_eco_high_reg_t mem_registerrnd_eco_high; - volatile spi_mem_registerrnd_eco_low_reg_t mem_registerrnd_eco_low; - uint32_t reserved_3f8; - volatile spi_mem_date_reg_t mem_date; -} spi_dev_t; - -extern spi_dev_t SPIMEM0; - -#ifndef __cplusplus -_Static_assert(sizeof(spi_dev_t) == 0x400, "Invalid size of spi_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32c5/register/soc/tee_reg.h b/components/soc/esp32c5/register/soc/tee_reg.h index 48caf26c3d..398d4bc235 100644 --- a/components/soc/esp32c5/register/soc/tee_reg.h +++ b/components/soc/esp32c5/register/soc/tee_reg.h @@ -12,22 +12,24 @@ extern "C" { #endif /** TEE_M0_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M0_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x0) /** TEE_M0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M0 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 0. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M0_MODE 0x00000003U #define TEE_M0_MODE_M (TEE_M0_MODE_V << TEE_M0_MODE_S) #define TEE_M0_MODE_V 0x00000003U #define TEE_M0_MODE_S 0 /** TEE_M0_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M0_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M0_LOCK (BIT(2)) #define TEE_M0_LOCK_M (TEE_M0_LOCK_V << TEE_M0_LOCK_S) @@ -35,22 +37,24 @@ extern "C" { #define TEE_M0_LOCK_S 2 /** TEE_M1_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M1_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4) /** TEE_M1_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M1 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 1. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M1_MODE 0x00000003U #define TEE_M1_MODE_M (TEE_M1_MODE_V << TEE_M1_MODE_S) #define TEE_M1_MODE_V 0x00000003U #define TEE_M1_MODE_S 0 /** TEE_M1_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M1_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M1_LOCK (BIT(2)) #define TEE_M1_LOCK_M (TEE_M1_LOCK_V << TEE_M1_LOCK_S) @@ -58,22 +62,24 @@ extern "C" { #define TEE_M1_LOCK_S 2 /** TEE_M2_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M2_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x8) /** TEE_M2_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M2 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 2. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M2_MODE 0x00000003U #define TEE_M2_MODE_M (TEE_M2_MODE_V << TEE_M2_MODE_S) #define TEE_M2_MODE_V 0x00000003U #define TEE_M2_MODE_S 0 /** TEE_M2_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M2_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M2_LOCK (BIT(2)) #define TEE_M2_LOCK_M (TEE_M2_LOCK_V << TEE_M2_LOCK_S) @@ -81,22 +87,24 @@ extern "C" { #define TEE_M2_LOCK_S 2 /** TEE_M3_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M3_MODE_CTRL_REG (DR_REG_TEE_BASE + 0xc) /** TEE_M3_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M3 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 3. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M3_MODE 0x00000003U #define TEE_M3_MODE_M (TEE_M3_MODE_V << TEE_M3_MODE_S) #define TEE_M3_MODE_V 0x00000003U #define TEE_M3_MODE_S 0 /** TEE_M3_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M3_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M3_LOCK (BIT(2)) #define TEE_M3_LOCK_M (TEE_M3_LOCK_V << TEE_M3_LOCK_S) @@ -104,22 +112,24 @@ extern "C" { #define TEE_M3_LOCK_S 2 /** TEE_M4_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M4_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x10) /** TEE_M4_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M4 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 4. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M4_MODE 0x00000003U #define TEE_M4_MODE_M (TEE_M4_MODE_V << TEE_M4_MODE_S) #define TEE_M4_MODE_V 0x00000003U #define TEE_M4_MODE_S 0 /** TEE_M4_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M4_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M4_LOCK (BIT(2)) #define TEE_M4_LOCK_M (TEE_M4_LOCK_V << TEE_M4_LOCK_S) @@ -127,22 +137,24 @@ extern "C" { #define TEE_M4_LOCK_S 2 /** TEE_M5_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M5_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x14) /** TEE_M5_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M5 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 5. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M5_MODE 0x00000003U #define TEE_M5_MODE_M (TEE_M5_MODE_V << TEE_M5_MODE_S) #define TEE_M5_MODE_V 0x00000003U #define TEE_M5_MODE_S 0 /** TEE_M5_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M5_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M5_LOCK (BIT(2)) #define TEE_M5_LOCK_M (TEE_M5_LOCK_V << TEE_M5_LOCK_S) @@ -150,22 +162,24 @@ extern "C" { #define TEE_M5_LOCK_S 2 /** TEE_M6_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M6_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x18) /** TEE_M6_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M6 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 6. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M6_MODE 0x00000003U #define TEE_M6_MODE_M (TEE_M6_MODE_V << TEE_M6_MODE_S) #define TEE_M6_MODE_V 0x00000003U #define TEE_M6_MODE_S 0 /** TEE_M6_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M6_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M6_LOCK (BIT(2)) #define TEE_M6_LOCK_M (TEE_M6_LOCK_V << TEE_M6_LOCK_S) @@ -173,22 +187,24 @@ extern "C" { #define TEE_M6_LOCK_S 2 /** TEE_M7_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M7_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x1c) /** TEE_M7_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M7 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 7. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M7_MODE 0x00000003U #define TEE_M7_MODE_M (TEE_M7_MODE_V << TEE_M7_MODE_S) #define TEE_M7_MODE_V 0x00000003U #define TEE_M7_MODE_S 0 /** TEE_M7_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M7_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M7_LOCK (BIT(2)) #define TEE_M7_LOCK_M (TEE_M7_LOCK_V << TEE_M7_LOCK_S) @@ -196,22 +212,24 @@ extern "C" { #define TEE_M7_LOCK_S 2 /** TEE_M8_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M8_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x20) /** TEE_M8_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M8 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 8. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M8_MODE 0x00000003U #define TEE_M8_MODE_M (TEE_M8_MODE_V << TEE_M8_MODE_S) #define TEE_M8_MODE_V 0x00000003U #define TEE_M8_MODE_S 0 /** TEE_M8_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M8_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M8_LOCK (BIT(2)) #define TEE_M8_LOCK_M (TEE_M8_LOCK_V << TEE_M8_LOCK_S) @@ -219,22 +237,24 @@ extern "C" { #define TEE_M8_LOCK_S 2 /** TEE_M9_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M9_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x24) /** TEE_M9_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M9 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 9. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M9_MODE 0x00000003U #define TEE_M9_MODE_M (TEE_M9_MODE_V << TEE_M9_MODE_S) #define TEE_M9_MODE_V 0x00000003U #define TEE_M9_MODE_S 0 /** TEE_M9_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M9_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M9_LOCK (BIT(2)) #define TEE_M9_LOCK_M (TEE_M9_LOCK_V << TEE_M9_LOCK_S) @@ -242,22 +262,24 @@ extern "C" { #define TEE_M9_LOCK_S 2 /** TEE_M10_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M10_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x28) /** TEE_M10_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M10 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 10. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M10_MODE 0x00000003U #define TEE_M10_MODE_M (TEE_M10_MODE_V << TEE_M10_MODE_S) #define TEE_M10_MODE_V 0x00000003U #define TEE_M10_MODE_S 0 /** TEE_M10_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M10_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M10_LOCK (BIT(2)) #define TEE_M10_LOCK_M (TEE_M10_LOCK_V << TEE_M10_LOCK_S) @@ -265,22 +287,24 @@ extern "C" { #define TEE_M10_LOCK_S 2 /** TEE_M11_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M11_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x2c) /** TEE_M11_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M11 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 11. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M11_MODE 0x00000003U #define TEE_M11_MODE_M (TEE_M11_MODE_V << TEE_M11_MODE_S) #define TEE_M11_MODE_V 0x00000003U #define TEE_M11_MODE_S 0 /** TEE_M11_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M11_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M11_LOCK (BIT(2)) #define TEE_M11_LOCK_M (TEE_M11_LOCK_V << TEE_M11_LOCK_S) @@ -288,22 +312,24 @@ extern "C" { #define TEE_M11_LOCK_S 2 /** TEE_M12_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M12_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x30) /** TEE_M12_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M12 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 12. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M12_MODE 0x00000003U #define TEE_M12_MODE_M (TEE_M12_MODE_V << TEE_M12_MODE_S) #define TEE_M12_MODE_V 0x00000003U #define TEE_M12_MODE_S 0 /** TEE_M12_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M12_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M12_LOCK (BIT(2)) #define TEE_M12_LOCK_M (TEE_M12_LOCK_V << TEE_M12_LOCK_S) @@ -311,22 +337,24 @@ extern "C" { #define TEE_M12_LOCK_S 2 /** TEE_M13_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M13_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x34) /** TEE_M13_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M13 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 13. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M13_MODE 0x00000003U #define TEE_M13_MODE_M (TEE_M13_MODE_V << TEE_M13_MODE_S) #define TEE_M13_MODE_V 0x00000003U #define TEE_M13_MODE_S 0 /** TEE_M13_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M13_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M13_LOCK (BIT(2)) #define TEE_M13_LOCK_M (TEE_M13_LOCK_V << TEE_M13_LOCK_S) @@ -334,22 +362,24 @@ extern "C" { #define TEE_M13_LOCK_S 2 /** TEE_M14_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M14_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x38) /** TEE_M14_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M14 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 14. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M14_MODE 0x00000003U #define TEE_M14_MODE_M (TEE_M14_MODE_V << TEE_M14_MODE_S) #define TEE_M14_MODE_V 0x00000003U #define TEE_M14_MODE_S 0 /** TEE_M14_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M14_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M14_LOCK (BIT(2)) #define TEE_M14_LOCK_M (TEE_M14_LOCK_V << TEE_M14_LOCK_S) @@ -357,22 +387,24 @@ extern "C" { #define TEE_M14_LOCK_S 2 /** TEE_M15_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M15_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x3c) /** TEE_M15_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M15 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 15. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M15_MODE 0x00000003U #define TEE_M15_MODE_M (TEE_M15_MODE_V << TEE_M15_MODE_S) #define TEE_M15_MODE_V 0x00000003U #define TEE_M15_MODE_S 0 /** TEE_M15_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M15_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M15_LOCK (BIT(2)) #define TEE_M15_LOCK_M (TEE_M15_LOCK_V << TEE_M15_LOCK_S) @@ -380,22 +412,24 @@ extern "C" { #define TEE_M15_LOCK_S 2 /** TEE_M16_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M16_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x40) /** TEE_M16_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M16 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 16. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M16_MODE 0x00000003U #define TEE_M16_MODE_M (TEE_M16_MODE_V << TEE_M16_MODE_S) #define TEE_M16_MODE_V 0x00000003U #define TEE_M16_MODE_S 0 /** TEE_M16_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M16_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M16_LOCK (BIT(2)) #define TEE_M16_LOCK_M (TEE_M16_LOCK_V << TEE_M16_LOCK_S) @@ -403,22 +437,24 @@ extern "C" { #define TEE_M16_LOCK_S 2 /** TEE_M17_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M17_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x44) /** TEE_M17_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M17 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 17. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M17_MODE 0x00000003U #define TEE_M17_MODE_M (TEE_M17_MODE_V << TEE_M17_MODE_S) #define TEE_M17_MODE_V 0x00000003U #define TEE_M17_MODE_S 0 /** TEE_M17_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M17_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M17_LOCK (BIT(2)) #define TEE_M17_LOCK_M (TEE_M17_LOCK_V << TEE_M17_LOCK_S) @@ -426,22 +462,24 @@ extern "C" { #define TEE_M17_LOCK_S 2 /** TEE_M18_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M18_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x48) /** TEE_M18_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M18 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 18. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M18_MODE 0x00000003U #define TEE_M18_MODE_M (TEE_M18_MODE_V << TEE_M18_MODE_S) #define TEE_M18_MODE_V 0x00000003U #define TEE_M18_MODE_S 0 /** TEE_M18_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M18_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M18_LOCK (BIT(2)) #define TEE_M18_LOCK_M (TEE_M18_LOCK_V << TEE_M18_LOCK_S) @@ -449,22 +487,24 @@ extern "C" { #define TEE_M18_LOCK_S 2 /** TEE_M19_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M19_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x4c) /** TEE_M19_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M19 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 19. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M19_MODE 0x00000003U #define TEE_M19_MODE_M (TEE_M19_MODE_V << TEE_M19_MODE_S) #define TEE_M19_MODE_V 0x00000003U #define TEE_M19_MODE_S 0 /** TEE_M19_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M19_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M19_LOCK (BIT(2)) #define TEE_M19_LOCK_M (TEE_M19_LOCK_V << TEE_M19_LOCK_S) @@ -472,22 +512,24 @@ extern "C" { #define TEE_M19_LOCK_S 2 /** TEE_M20_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M20_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x50) /** TEE_M20_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M20 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 20. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M20_MODE 0x00000003U #define TEE_M20_MODE_M (TEE_M20_MODE_V << TEE_M20_MODE_S) #define TEE_M20_MODE_V 0x00000003U #define TEE_M20_MODE_S 0 /** TEE_M20_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M20_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M20_LOCK (BIT(2)) #define TEE_M20_LOCK_M (TEE_M20_LOCK_V << TEE_M20_LOCK_S) @@ -495,22 +537,24 @@ extern "C" { #define TEE_M20_LOCK_S 2 /** TEE_M21_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M21_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x54) /** TEE_M21_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M21 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 21. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M21_MODE 0x00000003U #define TEE_M21_MODE_M (TEE_M21_MODE_V << TEE_M21_MODE_S) #define TEE_M21_MODE_V 0x00000003U #define TEE_M21_MODE_S 0 /** TEE_M21_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M21_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M21_LOCK (BIT(2)) #define TEE_M21_LOCK_M (TEE_M21_LOCK_V << TEE_M21_LOCK_S) @@ -518,22 +562,24 @@ extern "C" { #define TEE_M21_LOCK_S 2 /** TEE_M22_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M22_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x58) /** TEE_M22_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M22 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 22. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M22_MODE 0x00000003U #define TEE_M22_MODE_M (TEE_M22_MODE_V << TEE_M22_MODE_S) #define TEE_M22_MODE_V 0x00000003U #define TEE_M22_MODE_S 0 /** TEE_M22_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M22_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M22_LOCK (BIT(2)) #define TEE_M22_LOCK_M (TEE_M22_LOCK_V << TEE_M22_LOCK_S) @@ -541,22 +587,24 @@ extern "C" { #define TEE_M22_LOCK_S 2 /** TEE_M23_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M23_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x5c) /** TEE_M23_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M23 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 23. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M23_MODE 0x00000003U #define TEE_M23_MODE_M (TEE_M23_MODE_V << TEE_M23_MODE_S) #define TEE_M23_MODE_V 0x00000003U #define TEE_M23_MODE_S 0 /** TEE_M23_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M23_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M23_LOCK (BIT(2)) #define TEE_M23_LOCK_M (TEE_M23_LOCK_V << TEE_M23_LOCK_S) @@ -564,22 +612,24 @@ extern "C" { #define TEE_M23_LOCK_S 2 /** TEE_M24_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M24_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x60) /** TEE_M24_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M24 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 24. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M24_MODE 0x00000003U #define TEE_M24_MODE_M (TEE_M24_MODE_V << TEE_M24_MODE_S) #define TEE_M24_MODE_V 0x00000003U #define TEE_M24_MODE_S 0 /** TEE_M24_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M24_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M24_LOCK (BIT(2)) #define TEE_M24_LOCK_M (TEE_M24_LOCK_V << TEE_M24_LOCK_S) @@ -587,22 +637,24 @@ extern "C" { #define TEE_M24_LOCK_S 2 /** TEE_M25_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M25_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x64) /** TEE_M25_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M25 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 25. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M25_MODE 0x00000003U #define TEE_M25_MODE_M (TEE_M25_MODE_V << TEE_M25_MODE_S) #define TEE_M25_MODE_V 0x00000003U #define TEE_M25_MODE_S 0 /** TEE_M25_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M25_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M25_LOCK (BIT(2)) #define TEE_M25_LOCK_M (TEE_M25_LOCK_V << TEE_M25_LOCK_S) @@ -610,22 +662,24 @@ extern "C" { #define TEE_M25_LOCK_S 2 /** TEE_M26_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M26_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x68) /** TEE_M26_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M26 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 26. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M26_MODE 0x00000003U #define TEE_M26_MODE_M (TEE_M26_MODE_V << TEE_M26_MODE_S) #define TEE_M26_MODE_V 0x00000003U #define TEE_M26_MODE_S 0 /** TEE_M26_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M26_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M26_LOCK (BIT(2)) #define TEE_M26_LOCK_M (TEE_M26_LOCK_V << TEE_M26_LOCK_S) @@ -633,22 +687,24 @@ extern "C" { #define TEE_M26_LOCK_S 2 /** TEE_M27_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M27_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x6c) /** TEE_M27_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M27 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 27. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M27_MODE 0x00000003U #define TEE_M27_MODE_M (TEE_M27_MODE_V << TEE_M27_MODE_S) #define TEE_M27_MODE_V 0x00000003U #define TEE_M27_MODE_S 0 /** TEE_M27_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M27_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M27_LOCK (BIT(2)) #define TEE_M27_LOCK_M (TEE_M27_LOCK_V << TEE_M27_LOCK_S) @@ -656,22 +712,24 @@ extern "C" { #define TEE_M27_LOCK_S 2 /** TEE_M28_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M28_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x70) /** TEE_M28_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M28 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 28. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M28_MODE 0x00000003U #define TEE_M28_MODE_M (TEE_M28_MODE_V << TEE_M28_MODE_S) #define TEE_M28_MODE_V 0x00000003U #define TEE_M28_MODE_S 0 /** TEE_M28_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M28_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M28_LOCK (BIT(2)) #define TEE_M28_LOCK_M (TEE_M28_LOCK_V << TEE_M28_LOCK_S) @@ -679,22 +737,24 @@ extern "C" { #define TEE_M28_LOCK_S 2 /** TEE_M29_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M29_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x74) /** TEE_M29_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M29 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 29. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M29_MODE 0x00000003U #define TEE_M29_MODE_M (TEE_M29_MODE_V << TEE_M29_MODE_S) #define TEE_M29_MODE_V 0x00000003U #define TEE_M29_MODE_S 0 /** TEE_M29_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M29_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M29_LOCK (BIT(2)) #define TEE_M29_LOCK_M (TEE_M29_LOCK_V << TEE_M29_LOCK_S) @@ -702,22 +762,24 @@ extern "C" { #define TEE_M29_LOCK_S 2 /** TEE_M30_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M30_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x78) /** TEE_M30_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M30 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 30. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M30_MODE 0x00000003U #define TEE_M30_MODE_M (TEE_M30_MODE_V << TEE_M30_MODE_S) #define TEE_M30_MODE_V 0x00000003U #define TEE_M30_MODE_S 0 /** TEE_M30_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M30_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M30_LOCK (BIT(2)) #define TEE_M30_LOCK_M (TEE_M30_LOCK_V << TEE_M30_LOCK_S) @@ -725,22 +787,24 @@ extern "C" { #define TEE_M30_LOCK_S 2 /** TEE_M31_MODE_CTRL_REG register - * TEE mode control register + * Security mode configuration register */ #define TEE_M31_MODE_CTRL_REG (DR_REG_TEE_BASE + 0x7c) /** TEE_M31_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures M31 security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master 31. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ #define TEE_M31_MODE 0x00000003U #define TEE_M31_MODE_M (TEE_M31_MODE_V << TEE_M31_MODE_S) #define TEE_M31_MODE_V 0x00000003U #define TEE_M31_MODE_S 0 /** TEE_M31_LOCK : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_M31_MODE. + * 0: Do not lock + * 1: Lock */ #define TEE_M31_LOCK (BIT(2)) #define TEE_M31_LOCK_M (TEE_M31_LOCK_V << TEE_M31_LOCK_S) @@ -748,7 +812,7 @@ extern "C" { #define TEE_M31_LOCK_S 2 /** TEE_UART0_CTRL_REG register - * uart0 read/write control register + * UART0 read/write control register */ #define TEE_UART0_CTRL_REG (DR_REG_TEE_BASE + 0x88) /** TEE_READ_TEE_UART0 : R/W; bitpos: [0]; default: 1; @@ -825,7 +889,7 @@ extern "C" { #define TEE_WRITE_REE2_UART0_S 7 /** TEE_UART1_CTRL_REG register - * uart1 read/write control register + * UART1 read/write control register */ #define TEE_UART1_CTRL_REG (DR_REG_TEE_BASE + 0x8c) /** TEE_READ_TEE_UART1 : R/W; bitpos: [0]; default: 1; @@ -902,7 +966,7 @@ extern "C" { #define TEE_WRITE_REE2_UART1_S 7 /** TEE_UHCI0_CTRL_REG register - * uhci0 read/write control register + * UHCI read/write control register */ #define TEE_UHCI0_CTRL_REG (DR_REG_TEE_BASE + 0x90) /** TEE_READ_TEE_UHCI0 : R/W; bitpos: [0]; default: 1; @@ -979,7 +1043,7 @@ extern "C" { #define TEE_WRITE_REE2_UHCI0_S 7 /** TEE_I2C_EXT0_CTRL_REG register - * i2c_ext0 read/write control register + * I2C read/write control register */ #define TEE_I2C_EXT0_CTRL_REG (DR_REG_TEE_BASE + 0x94) /** TEE_READ_TEE_I2C_EXT0 : R/W; bitpos: [0]; default: 1; @@ -1056,7 +1120,7 @@ extern "C" { #define TEE_WRITE_REE2_I2C_EXT0_S 7 /** TEE_I2S_CTRL_REG register - * i2s read/write control register + * I2S read/write control register */ #define TEE_I2S_CTRL_REG (DR_REG_TEE_BASE + 0x9c) /** TEE_READ_TEE_I2S : R/W; bitpos: [0]; default: 1; @@ -1133,7 +1197,7 @@ extern "C" { #define TEE_WRITE_REE2_I2S_S 7 /** TEE_PARL_IO_CTRL_REG register - * parl_io read/write control register + * PARL_IO read/write control register */ #define TEE_PARL_IO_CTRL_REG (DR_REG_TEE_BASE + 0xa0) /** TEE_READ_TEE_PARL_IO : R/W; bitpos: [0]; default: 1; @@ -1210,7 +1274,7 @@ extern "C" { #define TEE_WRITE_REE2_PARL_IO_S 7 /** TEE_PWM_CTRL_REG register - * pwm read/write control register + * MCPWM read/write control register */ #define TEE_PWM_CTRL_REG (DR_REG_TEE_BASE + 0xa4) /** TEE_READ_TEE_PWM : R/W; bitpos: [0]; default: 1; @@ -1287,7 +1351,7 @@ extern "C" { #define TEE_WRITE_REE2_PWM_S 7 /** TEE_LEDC_CTRL_REG register - * ledc read/write control register + * LEDC read/write control register */ #define TEE_LEDC_CTRL_REG (DR_REG_TEE_BASE + 0xac) /** TEE_READ_TEE_LEDC : R/W; bitpos: [0]; default: 1; @@ -1363,162 +1427,162 @@ extern "C" { #define TEE_WRITE_REE2_LEDC_V 0x00000001U #define TEE_WRITE_REE2_LEDC_S 7 -/** TEE_CAN0_CTRL_REG register - * can read/write control register +/** TEE_TWAI0_CTRL_REG register + * TWAI0 read/write control register */ -#define TEE_CAN0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) -/** TEE_READ_TEE_CAN0 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI0_CTRL_REG (DR_REG_TEE_BASE + 0xb0) +/** TEE_READ_TEE_TWAI0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN0 (BIT(0)) -#define TEE_READ_TEE_CAN0_M (TEE_READ_TEE_CAN0_V << TEE_READ_TEE_CAN0_S) -#define TEE_READ_TEE_CAN0_V 0x00000001U -#define TEE_READ_TEE_CAN0_S 0 -/** TEE_READ_REE0_CAN0 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI0 (BIT(0)) +#define TEE_READ_TEE_TWAI0_M (TEE_READ_TEE_TWAI0_V << TEE_READ_TEE_TWAI0_S) +#define TEE_READ_TEE_TWAI0_V 0x00000001U +#define TEE_READ_TEE_TWAI0_S 0 +/** TEE_READ_REE0_TWAI0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN0 (BIT(1)) -#define TEE_READ_REE0_CAN0_M (TEE_READ_REE0_CAN0_V << TEE_READ_REE0_CAN0_S) -#define TEE_READ_REE0_CAN0_V 0x00000001U -#define TEE_READ_REE0_CAN0_S 1 -/** TEE_READ_REE1_CAN0 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI0 (BIT(1)) +#define TEE_READ_REE0_TWAI0_M (TEE_READ_REE0_TWAI0_V << TEE_READ_REE0_TWAI0_S) +#define TEE_READ_REE0_TWAI0_V 0x00000001U +#define TEE_READ_REE0_TWAI0_S 1 +/** TEE_READ_REE1_TWAI0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN0 (BIT(2)) -#define TEE_READ_REE1_CAN0_M (TEE_READ_REE1_CAN0_V << TEE_READ_REE1_CAN0_S) -#define TEE_READ_REE1_CAN0_V 0x00000001U -#define TEE_READ_REE1_CAN0_S 2 -/** TEE_READ_REE2_CAN0 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI0 (BIT(2)) +#define TEE_READ_REE1_TWAI0_M (TEE_READ_REE1_TWAI0_V << TEE_READ_REE1_TWAI0_S) +#define TEE_READ_REE1_TWAI0_V 0x00000001U +#define TEE_READ_REE1_TWAI0_S 2 +/** TEE_READ_REE2_TWAI0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN0 (BIT(3)) -#define TEE_READ_REE2_CAN0_M (TEE_READ_REE2_CAN0_V << TEE_READ_REE2_CAN0_S) -#define TEE_READ_REE2_CAN0_V 0x00000001U -#define TEE_READ_REE2_CAN0_S 3 -/** TEE_WRITE_TEE_CAN0 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI0 (BIT(3)) +#define TEE_READ_REE2_TWAI0_M (TEE_READ_REE2_TWAI0_V << TEE_READ_REE2_TWAI0_S) +#define TEE_READ_REE2_TWAI0_V 0x00000001U +#define TEE_READ_REE2_TWAI0_S 3 +/** TEE_WRITE_TEE_TWAI0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN0 (BIT(4)) -#define TEE_WRITE_TEE_CAN0_M (TEE_WRITE_TEE_CAN0_V << TEE_WRITE_TEE_CAN0_S) -#define TEE_WRITE_TEE_CAN0_V 0x00000001U -#define TEE_WRITE_TEE_CAN0_S 4 -/** TEE_WRITE_REE0_CAN0 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI0 (BIT(4)) +#define TEE_WRITE_TEE_TWAI0_M (TEE_WRITE_TEE_TWAI0_V << TEE_WRITE_TEE_TWAI0_S) +#define TEE_WRITE_TEE_TWAI0_V 0x00000001U +#define TEE_WRITE_TEE_TWAI0_S 4 +/** TEE_WRITE_REE0_TWAI0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN0 (BIT(5)) -#define TEE_WRITE_REE0_CAN0_M (TEE_WRITE_REE0_CAN0_V << TEE_WRITE_REE0_CAN0_S) -#define TEE_WRITE_REE0_CAN0_V 0x00000001U -#define TEE_WRITE_REE0_CAN0_S 5 -/** TEE_WRITE_REE1_CAN0 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI0 (BIT(5)) +#define TEE_WRITE_REE0_TWAI0_M (TEE_WRITE_REE0_TWAI0_V << TEE_WRITE_REE0_TWAI0_S) +#define TEE_WRITE_REE0_TWAI0_V 0x00000001U +#define TEE_WRITE_REE0_TWAI0_S 5 +/** TEE_WRITE_REE1_TWAI0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN0 (BIT(6)) -#define TEE_WRITE_REE1_CAN0_M (TEE_WRITE_REE1_CAN0_V << TEE_WRITE_REE1_CAN0_S) -#define TEE_WRITE_REE1_CAN0_V 0x00000001U -#define TEE_WRITE_REE1_CAN0_S 6 -/** TEE_WRITE_REE2_CAN0 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI0 (BIT(6)) +#define TEE_WRITE_REE1_TWAI0_M (TEE_WRITE_REE1_TWAI0_V << TEE_WRITE_REE1_TWAI0_S) +#define TEE_WRITE_REE1_TWAI0_V 0x00000001U +#define TEE_WRITE_REE1_TWAI0_S 6 +/** TEE_WRITE_REE2_TWAI0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN0 (BIT(7)) -#define TEE_WRITE_REE2_CAN0_M (TEE_WRITE_REE2_CAN0_V << TEE_WRITE_REE2_CAN0_S) -#define TEE_WRITE_REE2_CAN0_V 0x00000001U -#define TEE_WRITE_REE2_CAN0_S 7 +#define TEE_WRITE_REE2_TWAI0 (BIT(7)) +#define TEE_WRITE_REE2_TWAI0_M (TEE_WRITE_REE2_TWAI0_V << TEE_WRITE_REE2_TWAI0_S) +#define TEE_WRITE_REE2_TWAI0_V 0x00000001U +#define TEE_WRITE_REE2_TWAI0_S 7 -/** TEE_USB_DEVICE_CTRL_REG register - * usb_device read/write control register +/** TEE_USB_SERIAL_JTAG_CTRL_REG register + * USB_SERIAL_JTAG read/write control register */ -#define TEE_USB_DEVICE_CTRL_REG (DR_REG_TEE_BASE + 0xb4) -/** TEE_READ_TEE_USB_DEVICE : R/W; bitpos: [0]; default: 1; +#define TEE_USB_SERIAL_JTAG_CTRL_REG (DR_REG_TEE_BASE + 0xb4) +/** TEE_READ_TEE_USB_SERIAL_JTAG : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_USB_DEVICE (BIT(0)) -#define TEE_READ_TEE_USB_DEVICE_M (TEE_READ_TEE_USB_DEVICE_V << TEE_READ_TEE_USB_DEVICE_S) -#define TEE_READ_TEE_USB_DEVICE_V 0x00000001U -#define TEE_READ_TEE_USB_DEVICE_S 0 -/** TEE_READ_REE0_USB_DEVICE : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_USB_SERIAL_JTAG (BIT(0)) +#define TEE_READ_TEE_USB_SERIAL_JTAG_M (TEE_READ_TEE_USB_SERIAL_JTAG_V << TEE_READ_TEE_USB_SERIAL_JTAG_S) +#define TEE_READ_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_TEE_USB_SERIAL_JTAG_S 0 +/** TEE_READ_REE0_USB_SERIAL_JTAG : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_USB_DEVICE (BIT(1)) -#define TEE_READ_REE0_USB_DEVICE_M (TEE_READ_REE0_USB_DEVICE_V << TEE_READ_REE0_USB_DEVICE_S) -#define TEE_READ_REE0_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE0_USB_DEVICE_S 1 -/** TEE_READ_REE1_USB_DEVICE : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_USB_SERIAL_JTAG (BIT(1)) +#define TEE_READ_REE0_USB_SERIAL_JTAG_M (TEE_READ_REE0_USB_SERIAL_JTAG_V << TEE_READ_REE0_USB_SERIAL_JTAG_S) +#define TEE_READ_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE0_USB_SERIAL_JTAG_S 1 +/** TEE_READ_REE1_USB_SERIAL_JTAG : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_USB_DEVICE (BIT(2)) -#define TEE_READ_REE1_USB_DEVICE_M (TEE_READ_REE1_USB_DEVICE_V << TEE_READ_REE1_USB_DEVICE_S) -#define TEE_READ_REE1_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE1_USB_DEVICE_S 2 -/** TEE_READ_REE2_USB_DEVICE : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_USB_SERIAL_JTAG (BIT(2)) +#define TEE_READ_REE1_USB_SERIAL_JTAG_M (TEE_READ_REE1_USB_SERIAL_JTAG_V << TEE_READ_REE1_USB_SERIAL_JTAG_S) +#define TEE_READ_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE1_USB_SERIAL_JTAG_S 2 +/** TEE_READ_REE2_USB_SERIAL_JTAG : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_USB_DEVICE (BIT(3)) -#define TEE_READ_REE2_USB_DEVICE_M (TEE_READ_REE2_USB_DEVICE_V << TEE_READ_REE2_USB_DEVICE_S) -#define TEE_READ_REE2_USB_DEVICE_V 0x00000001U -#define TEE_READ_REE2_USB_DEVICE_S 3 -/** TEE_WRITE_TEE_USB_DEVICE : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_USB_SERIAL_JTAG (BIT(3)) +#define TEE_READ_REE2_USB_SERIAL_JTAG_M (TEE_READ_REE2_USB_SERIAL_JTAG_V << TEE_READ_REE2_USB_SERIAL_JTAG_S) +#define TEE_READ_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_READ_REE2_USB_SERIAL_JTAG_S 3 +/** TEE_WRITE_TEE_USB_SERIAL_JTAG : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_USB_DEVICE (BIT(4)) -#define TEE_WRITE_TEE_USB_DEVICE_M (TEE_WRITE_TEE_USB_DEVICE_V << TEE_WRITE_TEE_USB_DEVICE_S) -#define TEE_WRITE_TEE_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_TEE_USB_DEVICE_S 4 -/** TEE_WRITE_REE0_USB_DEVICE : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_USB_SERIAL_JTAG (BIT(4)) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_M (TEE_WRITE_TEE_USB_SERIAL_JTAG_V << TEE_WRITE_TEE_USB_SERIAL_JTAG_S) +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_TEE_USB_SERIAL_JTAG_S 4 +/** TEE_WRITE_REE0_USB_SERIAL_JTAG : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_USB_DEVICE (BIT(5)) -#define TEE_WRITE_REE0_USB_DEVICE_M (TEE_WRITE_REE0_USB_DEVICE_V << TEE_WRITE_REE0_USB_DEVICE_S) -#define TEE_WRITE_REE0_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE0_USB_DEVICE_S 5 -/** TEE_WRITE_REE1_USB_DEVICE : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_USB_SERIAL_JTAG (BIT(5)) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_M (TEE_WRITE_REE0_USB_SERIAL_JTAG_V << TEE_WRITE_REE0_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE0_USB_SERIAL_JTAG_S 5 +/** TEE_WRITE_REE1_USB_SERIAL_JTAG : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_USB_DEVICE (BIT(6)) -#define TEE_WRITE_REE1_USB_DEVICE_M (TEE_WRITE_REE1_USB_DEVICE_V << TEE_WRITE_REE1_USB_DEVICE_S) -#define TEE_WRITE_REE1_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE1_USB_DEVICE_S 6 -/** TEE_WRITE_REE2_USB_DEVICE : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_USB_SERIAL_JTAG (BIT(6)) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_M (TEE_WRITE_REE1_USB_SERIAL_JTAG_V << TEE_WRITE_REE1_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE1_USB_SERIAL_JTAG_S 6 +/** TEE_WRITE_REE2_USB_SERIAL_JTAG : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_USB_DEVICE (BIT(7)) -#define TEE_WRITE_REE2_USB_DEVICE_M (TEE_WRITE_REE2_USB_DEVICE_V << TEE_WRITE_REE2_USB_DEVICE_S) -#define TEE_WRITE_REE2_USB_DEVICE_V 0x00000001U -#define TEE_WRITE_REE2_USB_DEVICE_S 7 +#define TEE_WRITE_REE2_USB_SERIAL_JTAG (BIT(7)) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_M (TEE_WRITE_REE2_USB_SERIAL_JTAG_V << TEE_WRITE_REE2_USB_SERIAL_JTAG_S) +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_V 0x00000001U +#define TEE_WRITE_REE2_USB_SERIAL_JTAG_S 7 /** TEE_RMT_CTRL_REG register - * rmt read/write control register + * RMT read/write control register */ #define TEE_RMT_CTRL_REG (DR_REG_TEE_BASE + 0xb8) /** TEE_READ_TEE_RMT : R/W; bitpos: [0]; default: 1; @@ -1595,7 +1659,7 @@ extern "C" { #define TEE_WRITE_REE2_RMT_S 7 /** TEE_GDMA_CTRL_REG register - * gdma read/write control register + * GDMA read/write control register */ #define TEE_GDMA_CTRL_REG (DR_REG_TEE_BASE + 0xbc) /** TEE_READ_TEE_GDMA : R/W; bitpos: [0]; default: 1; @@ -1671,85 +1735,8 @@ extern "C" { #define TEE_WRITE_REE2_GDMA_V 0x00000001U #define TEE_WRITE_REE2_GDMA_S 7 -/** TEE_REGDMA_CTRL_REG register - * regdma read/write control register - */ -#define TEE_REGDMA_CTRL_REG (DR_REG_TEE_BASE + 0xc0) -/** TEE_READ_TEE_REGDMA : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_REGDMA (BIT(0)) -#define TEE_READ_TEE_REGDMA_M (TEE_READ_TEE_REGDMA_V << TEE_READ_TEE_REGDMA_S) -#define TEE_READ_TEE_REGDMA_V 0x00000001U -#define TEE_READ_TEE_REGDMA_S 0 -/** TEE_READ_REE0_REGDMA : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_REGDMA (BIT(1)) -#define TEE_READ_REE0_REGDMA_M (TEE_READ_REE0_REGDMA_V << TEE_READ_REE0_REGDMA_S) -#define TEE_READ_REE0_REGDMA_V 0x00000001U -#define TEE_READ_REE0_REGDMA_S 1 -/** TEE_READ_REE1_REGDMA : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_REGDMA (BIT(2)) -#define TEE_READ_REE1_REGDMA_M (TEE_READ_REE1_REGDMA_V << TEE_READ_REE1_REGDMA_S) -#define TEE_READ_REE1_REGDMA_V 0x00000001U -#define TEE_READ_REE1_REGDMA_S 2 -/** TEE_READ_REE2_REGDMA : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_REGDMA (BIT(3)) -#define TEE_READ_REE2_REGDMA_M (TEE_READ_REE2_REGDMA_V << TEE_READ_REE2_REGDMA_S) -#define TEE_READ_REE2_REGDMA_V 0x00000001U -#define TEE_READ_REE2_REGDMA_S 3 -/** TEE_WRITE_TEE_REGDMA : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_REGDMA (BIT(4)) -#define TEE_WRITE_TEE_REGDMA_M (TEE_WRITE_TEE_REGDMA_V << TEE_WRITE_TEE_REGDMA_S) -#define TEE_WRITE_TEE_REGDMA_V 0x00000001U -#define TEE_WRITE_TEE_REGDMA_S 4 -/** TEE_WRITE_REE0_REGDMA : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_REGDMA (BIT(5)) -#define TEE_WRITE_REE0_REGDMA_M (TEE_WRITE_REE0_REGDMA_V << TEE_WRITE_REE0_REGDMA_S) -#define TEE_WRITE_REE0_REGDMA_V 0x00000001U -#define TEE_WRITE_REE0_REGDMA_S 5 -/** TEE_WRITE_REE1_REGDMA : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_REGDMA (BIT(6)) -#define TEE_WRITE_REE1_REGDMA_M (TEE_WRITE_REE1_REGDMA_V << TEE_WRITE_REE1_REGDMA_S) -#define TEE_WRITE_REE1_REGDMA_V 0x00000001U -#define TEE_WRITE_REE1_REGDMA_S 6 -/** TEE_WRITE_REE2_REGDMA : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_REGDMA (BIT(7)) -#define TEE_WRITE_REE2_REGDMA_M (TEE_WRITE_REE2_REGDMA_V << TEE_WRITE_REE2_REGDMA_S) -#define TEE_WRITE_REE2_REGDMA_V 0x00000001U -#define TEE_WRITE_REE2_REGDMA_S 7 - /** TEE_ETM_CTRL_REG register - * etm read/write control register + * SOC_ETM read/write control register */ #define TEE_ETM_CTRL_REG (DR_REG_TEE_BASE + 0xc4) /** TEE_READ_TEE_ETM : R/W; bitpos: [0]; default: 1; @@ -1826,7 +1813,7 @@ extern "C" { #define TEE_WRITE_REE2_ETM_S 7 /** TEE_INTMTX_CTRL_REG register - * intmtx read/write control register + * INTMTX read/write control register */ #define TEE_INTMTX_CTRL_REG (DR_REG_TEE_BASE + 0xc8) /** TEE_READ_TEE_INTMTX_CORE : R/W; bitpos: [0]; default: 1; @@ -1903,7 +1890,7 @@ extern "C" { #define TEE_WRITE_REE2_INTMTX_CORE_S 7 /** TEE_APB_ADC_CTRL_REG register - * apb_adc read/write control register + * SAR ADC read/write control register */ #define TEE_APB_ADC_CTRL_REG (DR_REG_TEE_BASE + 0xd0) /** TEE_READ_TEE_APB_ADC : R/W; bitpos: [0]; default: 1; @@ -1980,7 +1967,7 @@ extern "C" { #define TEE_WRITE_REE2_APB_ADC_S 7 /** TEE_TIMERGROUP0_CTRL_REG register - * timergroup0 read/write control register + * TIMG0 read/write control register */ #define TEE_TIMERGROUP0_CTRL_REG (DR_REG_TEE_BASE + 0xd4) /** TEE_READ_TEE_TIMERGROUP0 : R/W; bitpos: [0]; default: 1; @@ -2057,7 +2044,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP0_S 7 /** TEE_TIMERGROUP1_CTRL_REG register - * timergroup1 read/write control register + * TIMG1 read/write control register */ #define TEE_TIMERGROUP1_CTRL_REG (DR_REG_TEE_BASE + 0xd8) /** TEE_READ_TEE_TIMERGROUP1 : R/W; bitpos: [0]; default: 1; @@ -2134,7 +2121,7 @@ extern "C" { #define TEE_WRITE_REE2_TIMERGROUP1_S 7 /** TEE_SYSTIMER_CTRL_REG register - * systimer read/write control register + * SYSTIMER read/write control register */ #define TEE_SYSTIMER_CTRL_REG (DR_REG_TEE_BASE + 0xdc) /** TEE_READ_TEE_SYSTIMER : R/W; bitpos: [0]; default: 1; @@ -2210,162 +2197,8 @@ extern "C" { #define TEE_WRITE_REE2_SYSTIMER_V 0x00000001U #define TEE_WRITE_REE2_SYSTIMER_S 7 -/** TEE_MISC_CTRL_REG register - * misc read/write control register - */ -#define TEE_MISC_CTRL_REG (DR_REG_TEE_BASE + 0xe0) -/** TEE_READ_TEE_MISC : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MISC (BIT(0)) -#define TEE_READ_TEE_MISC_M (TEE_READ_TEE_MISC_V << TEE_READ_TEE_MISC_S) -#define TEE_READ_TEE_MISC_V 0x00000001U -#define TEE_READ_TEE_MISC_S 0 -/** TEE_READ_REE0_MISC : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MISC (BIT(1)) -#define TEE_READ_REE0_MISC_M (TEE_READ_REE0_MISC_V << TEE_READ_REE0_MISC_S) -#define TEE_READ_REE0_MISC_V 0x00000001U -#define TEE_READ_REE0_MISC_S 1 -/** TEE_READ_REE1_MISC : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MISC (BIT(2)) -#define TEE_READ_REE1_MISC_M (TEE_READ_REE1_MISC_V << TEE_READ_REE1_MISC_S) -#define TEE_READ_REE1_MISC_V 0x00000001U -#define TEE_READ_REE1_MISC_S 2 -/** TEE_READ_REE2_MISC : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MISC (BIT(3)) -#define TEE_READ_REE2_MISC_M (TEE_READ_REE2_MISC_V << TEE_READ_REE2_MISC_S) -#define TEE_READ_REE2_MISC_V 0x00000001U -#define TEE_READ_REE2_MISC_S 3 -/** TEE_WRITE_TEE_MISC : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MISC (BIT(4)) -#define TEE_WRITE_TEE_MISC_M (TEE_WRITE_TEE_MISC_V << TEE_WRITE_TEE_MISC_S) -#define TEE_WRITE_TEE_MISC_V 0x00000001U -#define TEE_WRITE_TEE_MISC_S 4 -/** TEE_WRITE_REE0_MISC : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MISC (BIT(5)) -#define TEE_WRITE_REE0_MISC_M (TEE_WRITE_REE0_MISC_V << TEE_WRITE_REE0_MISC_S) -#define TEE_WRITE_REE0_MISC_V 0x00000001U -#define TEE_WRITE_REE0_MISC_S 5 -/** TEE_WRITE_REE1_MISC : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MISC (BIT(6)) -#define TEE_WRITE_REE1_MISC_M (TEE_WRITE_REE1_MISC_V << TEE_WRITE_REE1_MISC_S) -#define TEE_WRITE_REE1_MISC_V 0x00000001U -#define TEE_WRITE_REE1_MISC_S 6 -/** TEE_WRITE_REE2_MISC : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MISC (BIT(7)) -#define TEE_WRITE_REE2_MISC_M (TEE_WRITE_REE2_MISC_V << TEE_WRITE_REE2_MISC_S) -#define TEE_WRITE_REE2_MISC_V 0x00000001U -#define TEE_WRITE_REE2_MISC_S 7 - -/** TEE_PVT_MONITOR_CTRL_REG register - * pvt_monitor read/write control register - */ -#define TEE_PVT_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xf0) -/** TEE_READ_TEE_PVT_MONITOR : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_PVT_MONITOR (BIT(0)) -#define TEE_READ_TEE_PVT_MONITOR_M (TEE_READ_TEE_PVT_MONITOR_V << TEE_READ_TEE_PVT_MONITOR_S) -#define TEE_READ_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_READ_TEE_PVT_MONITOR_S 0 -/** TEE_READ_REE0_PVT_MONITOR : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_PVT_MONITOR (BIT(1)) -#define TEE_READ_REE0_PVT_MONITOR_M (TEE_READ_REE0_PVT_MONITOR_V << TEE_READ_REE0_PVT_MONITOR_S) -#define TEE_READ_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE0_PVT_MONITOR_S 1 -/** TEE_READ_REE1_PVT_MONITOR : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_PVT_MONITOR (BIT(2)) -#define TEE_READ_REE1_PVT_MONITOR_M (TEE_READ_REE1_PVT_MONITOR_V << TEE_READ_REE1_PVT_MONITOR_S) -#define TEE_READ_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE1_PVT_MONITOR_S 2 -/** TEE_READ_REE2_PVT_MONITOR : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_PVT_MONITOR (BIT(3)) -#define TEE_READ_REE2_PVT_MONITOR_M (TEE_READ_REE2_PVT_MONITOR_V << TEE_READ_REE2_PVT_MONITOR_S) -#define TEE_READ_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_READ_REE2_PVT_MONITOR_S 3 -/** TEE_WRITE_TEE_PVT_MONITOR : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_PVT_MONITOR (BIT(4)) -#define TEE_WRITE_TEE_PVT_MONITOR_M (TEE_WRITE_TEE_PVT_MONITOR_V << TEE_WRITE_TEE_PVT_MONITOR_S) -#define TEE_WRITE_TEE_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_TEE_PVT_MONITOR_S 4 -/** TEE_WRITE_REE0_PVT_MONITOR : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_PVT_MONITOR (BIT(5)) -#define TEE_WRITE_REE0_PVT_MONITOR_M (TEE_WRITE_REE0_PVT_MONITOR_V << TEE_WRITE_REE0_PVT_MONITOR_S) -#define TEE_WRITE_REE0_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE0_PVT_MONITOR_S 5 -/** TEE_WRITE_REE1_PVT_MONITOR : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_PVT_MONITOR (BIT(6)) -#define TEE_WRITE_REE1_PVT_MONITOR_M (TEE_WRITE_REE1_PVT_MONITOR_V << TEE_WRITE_REE1_PVT_MONITOR_S) -#define TEE_WRITE_REE1_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE1_PVT_MONITOR_S 6 -/** TEE_WRITE_REE2_PVT_MONITOR : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_PVT_MONITOR (BIT(7)) -#define TEE_WRITE_REE2_PVT_MONITOR_M (TEE_WRITE_REE2_PVT_MONITOR_V << TEE_WRITE_REE2_PVT_MONITOR_S) -#define TEE_WRITE_REE2_PVT_MONITOR_V 0x00000001U -#define TEE_WRITE_REE2_PVT_MONITOR_S 7 - /** TEE_PCNT_CTRL_REG register - * pcnt read/write control register + * PCNT read/write control register */ #define TEE_PCNT_CTRL_REG (DR_REG_TEE_BASE + 0xf4) /** TEE_READ_TEE_PCNT : R/W; bitpos: [0]; default: 1; @@ -2442,7 +2275,7 @@ extern "C" { #define TEE_WRITE_REE2_PCNT_S 7 /** TEE_IOMUX_CTRL_REG register - * iomux read/write control register + * IO MUX read/write control register */ #define TEE_IOMUX_CTRL_REG (DR_REG_TEE_BASE + 0xf8) /** TEE_READ_TEE_IOMUX : R/W; bitpos: [0]; default: 1; @@ -2519,7 +2352,7 @@ extern "C" { #define TEE_WRITE_REE2_IOMUX_S 7 /** TEE_PSRAM_MEM_MONITOR_CTRL_REG register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ #define TEE_PSRAM_MEM_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0xfc) /** TEE_READ_TEE_PSRAM_MEM_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2596,7 +2429,7 @@ extern "C" { #define TEE_WRITE_REE2_PSRAM_MEM_MONITOR_S 7 /** TEE_MEM_ACS_MONITOR_CTRL_REG register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ #define TEE_MEM_ACS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x100) /** TEE_READ_TEE_MEM_ACS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -2673,7 +2506,7 @@ extern "C" { #define TEE_WRITE_REE2_MEM_ACS_MONITOR_S 7 /** TEE_HP_SYSTEM_REG_CTRL_REG register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ #define TEE_HP_SYSTEM_REG_CTRL_REG (DR_REG_TEE_BASE + 0x104) /** TEE_READ_TEE_HP_SYSTEM_REG : R/W; bitpos: [0]; default: 1; @@ -2750,7 +2583,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_SYSTEM_REG_S 7 /** TEE_PCR_REG_CTRL_REG register - * pcr_reg read/write control register + * PCR read/write control register */ #define TEE_PCR_REG_CTRL_REG (DR_REG_TEE_BASE + 0x108) /** TEE_READ_TEE_PCR_REG : R/W; bitpos: [0]; default: 1; @@ -2827,7 +2660,7 @@ extern "C" { #define TEE_WRITE_REE2_PCR_REG_S 7 /** TEE_MSPI_CTRL_REG register - * mspi read/write control register + * SPI01 read/write control register */ #define TEE_MSPI_CTRL_REG (DR_REG_TEE_BASE + 0x10c) /** TEE_READ_TEE_MSPI : R/W; bitpos: [0]; default: 1; @@ -2904,7 +2737,7 @@ extern "C" { #define TEE_WRITE_REE2_MSPI_S 7 /** TEE_HP_APM_CTRL_REG register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ #define TEE_HP_APM_CTRL_REG (DR_REG_TEE_BASE + 0x110) /** TEE_READ_TEE_HP_APM : R/W; bitpos: [0]; default: 1; @@ -2981,7 +2814,7 @@ extern "C" { #define TEE_WRITE_REE2_HP_APM_S 7 /** TEE_CPU_APM_CTRL_REG register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ #define TEE_CPU_APM_CTRL_REG (DR_REG_TEE_BASE + 0x114) /** TEE_READ_TEE_CPU_APM : R/W; bitpos: [0]; default: 1; @@ -3058,7 +2891,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_APM_S 7 /** TEE_TEE_CTRL_REG register - * tee read/write control register + * TEE read/write control register */ #define TEE_TEE_CTRL_REG (DR_REG_TEE_BASE + 0x118) /** TEE_READ_TEE_TEE : R/W; bitpos: [0]; default: 1; @@ -3135,7 +2968,8 @@ extern "C" { #define TEE_WRITE_REE2_TEE_S 7 /** TEE_CRYPT_CTRL_REG register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ #define TEE_CRYPT_CTRL_REG (DR_REG_TEE_BASE + 0x11c) /** TEE_READ_TEE_CRYPT : R/W; bitpos: [0]; default: 1; @@ -3212,7 +3046,7 @@ extern "C" { #define TEE_WRITE_REE2_CRYPT_S 7 /** TEE_TRACE_CTRL_REG register - * trace read/write control register + * TRACE read/write control register */ #define TEE_TRACE_CTRL_REG (DR_REG_TEE_BASE + 0x120) /** TEE_READ_TEE_TRACE : R/W; bitpos: [0]; default: 1; @@ -3289,7 +3123,7 @@ extern "C" { #define TEE_WRITE_REE2_TRACE_S 7 /** TEE_CPU_BUS_MONITOR_CTRL_REG register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ #define TEE_CPU_BUS_MONITOR_CTRL_REG (DR_REG_TEE_BASE + 0x128) /** TEE_READ_TEE_CPU_BUS_MONITOR : R/W; bitpos: [0]; default: 1; @@ -3366,7 +3200,7 @@ extern "C" { #define TEE_WRITE_REE2_CPU_BUS_MONITOR_S 7 /** TEE_INTPRI_REG_CTRL_REG register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ #define TEE_INTPRI_REG_CTRL_REG (DR_REG_TEE_BASE + 0x12c) /** TEE_READ_TEE_INTPRI_REG : R/W; bitpos: [0]; default: 1; @@ -3442,239 +3276,85 @@ extern "C" { #define TEE_WRITE_REE2_INTPRI_REG_V 0x00000001U #define TEE_WRITE_REE2_INTPRI_REG_S 7 -/** TEE_CACHE_CFG_CTRL_REG register - * cache_cfg read/write control register +/** TEE_TWAI1_CTRL_REG register + * TWAI1 read/write control register */ -#define TEE_CACHE_CFG_CTRL_REG (DR_REG_TEE_BASE + 0x130) -/** TEE_READ_TEE_CACHE_CFG : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_CACHE_CFG (BIT(0)) -#define TEE_READ_TEE_CACHE_CFG_M (TEE_READ_TEE_CACHE_CFG_V << TEE_READ_TEE_CACHE_CFG_S) -#define TEE_READ_TEE_CACHE_CFG_V 0x00000001U -#define TEE_READ_TEE_CACHE_CFG_S 0 -/** TEE_READ_REE0_CACHE_CFG : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_CACHE_CFG (BIT(1)) -#define TEE_READ_REE0_CACHE_CFG_M (TEE_READ_REE0_CACHE_CFG_V << TEE_READ_REE0_CACHE_CFG_S) -#define TEE_READ_REE0_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE0_CACHE_CFG_S 1 -/** TEE_READ_REE1_CACHE_CFG : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_CACHE_CFG (BIT(2)) -#define TEE_READ_REE1_CACHE_CFG_M (TEE_READ_REE1_CACHE_CFG_V << TEE_READ_REE1_CACHE_CFG_S) -#define TEE_READ_REE1_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE1_CACHE_CFG_S 2 -/** TEE_READ_REE2_CACHE_CFG : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_CACHE_CFG (BIT(3)) -#define TEE_READ_REE2_CACHE_CFG_M (TEE_READ_REE2_CACHE_CFG_V << TEE_READ_REE2_CACHE_CFG_S) -#define TEE_READ_REE2_CACHE_CFG_V 0x00000001U -#define TEE_READ_REE2_CACHE_CFG_S 3 -/** TEE_WRITE_TEE_CACHE_CFG : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_CACHE_CFG (BIT(4)) -#define TEE_WRITE_TEE_CACHE_CFG_M (TEE_WRITE_TEE_CACHE_CFG_V << TEE_WRITE_TEE_CACHE_CFG_S) -#define TEE_WRITE_TEE_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_TEE_CACHE_CFG_S 4 -/** TEE_WRITE_REE0_CACHE_CFG : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_CACHE_CFG (BIT(5)) -#define TEE_WRITE_REE0_CACHE_CFG_M (TEE_WRITE_REE0_CACHE_CFG_V << TEE_WRITE_REE0_CACHE_CFG_S) -#define TEE_WRITE_REE0_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE0_CACHE_CFG_S 5 -/** TEE_WRITE_REE1_CACHE_CFG : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_CACHE_CFG (BIT(6)) -#define TEE_WRITE_REE1_CACHE_CFG_M (TEE_WRITE_REE1_CACHE_CFG_V << TEE_WRITE_REE1_CACHE_CFG_S) -#define TEE_WRITE_REE1_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE1_CACHE_CFG_S 6 -/** TEE_WRITE_REE2_CACHE_CFG : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_CACHE_CFG (BIT(7)) -#define TEE_WRITE_REE2_CACHE_CFG_M (TEE_WRITE_REE2_CACHE_CFG_V << TEE_WRITE_REE2_CACHE_CFG_S) -#define TEE_WRITE_REE2_CACHE_CFG_V 0x00000001U -#define TEE_WRITE_REE2_CACHE_CFG_S 7 - -/** TEE_MODEM_CTRL_REG register - * modem read/write control register - */ -#define TEE_MODEM_CTRL_REG (DR_REG_TEE_BASE + 0x134) -/** TEE_READ_TEE_MODEM : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM (BIT(0)) -#define TEE_READ_TEE_MODEM_M (TEE_READ_TEE_MODEM_V << TEE_READ_TEE_MODEM_S) -#define TEE_READ_TEE_MODEM_V 0x00000001U -#define TEE_READ_TEE_MODEM_S 0 -/** TEE_READ_REE0_MODEM : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM (BIT(1)) -#define TEE_READ_REE0_MODEM_M (TEE_READ_REE0_MODEM_V << TEE_READ_REE0_MODEM_S) -#define TEE_READ_REE0_MODEM_V 0x00000001U -#define TEE_READ_REE0_MODEM_S 1 -/** TEE_READ_REE1_MODEM : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM (BIT(2)) -#define TEE_READ_REE1_MODEM_M (TEE_READ_REE1_MODEM_V << TEE_READ_REE1_MODEM_S) -#define TEE_READ_REE1_MODEM_V 0x00000001U -#define TEE_READ_REE1_MODEM_S 2 -/** TEE_READ_REE2_MODEM : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM (BIT(3)) -#define TEE_READ_REE2_MODEM_M (TEE_READ_REE2_MODEM_V << TEE_READ_REE2_MODEM_S) -#define TEE_READ_REE2_MODEM_V 0x00000001U -#define TEE_READ_REE2_MODEM_S 3 -/** TEE_WRITE_TEE_MODEM : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM (BIT(4)) -#define TEE_WRITE_TEE_MODEM_M (TEE_WRITE_TEE_MODEM_V << TEE_WRITE_TEE_MODEM_S) -#define TEE_WRITE_TEE_MODEM_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_S 4 -/** TEE_WRITE_REE0_MODEM : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM (BIT(5)) -#define TEE_WRITE_REE0_MODEM_M (TEE_WRITE_REE0_MODEM_V << TEE_WRITE_REE0_MODEM_S) -#define TEE_WRITE_REE0_MODEM_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_S 5 -/** TEE_WRITE_REE1_MODEM : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM (BIT(6)) -#define TEE_WRITE_REE1_MODEM_M (TEE_WRITE_REE1_MODEM_V << TEE_WRITE_REE1_MODEM_S) -#define TEE_WRITE_REE1_MODEM_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_S 6 -/** TEE_WRITE_REE2_MODEM : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM (BIT(7)) -#define TEE_WRITE_REE2_MODEM_M (TEE_WRITE_REE2_MODEM_V << TEE_WRITE_REE2_MODEM_S) -#define TEE_WRITE_REE2_MODEM_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_S 7 - -/** TEE_CAN1_CTRL_REG register - * can1 read/write control register - */ -#define TEE_CAN1_CTRL_REG (DR_REG_TEE_BASE + 0x138) -/** TEE_READ_TEE_CAN1 : R/W; bitpos: [0]; default: 1; +#define TEE_TWAI1_CTRL_REG (DR_REG_TEE_BASE + 0x138) +/** TEE_READ_TEE_TWAI1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_TEE_CAN1 (BIT(0)) -#define TEE_READ_TEE_CAN1_M (TEE_READ_TEE_CAN1_V << TEE_READ_TEE_CAN1_S) -#define TEE_READ_TEE_CAN1_V 0x00000001U -#define TEE_READ_TEE_CAN1_S 0 -/** TEE_READ_REE0_CAN1 : R/W; bitpos: [1]; default: 0; +#define TEE_READ_TEE_TWAI1 (BIT(0)) +#define TEE_READ_TEE_TWAI1_M (TEE_READ_TEE_TWAI1_V << TEE_READ_TEE_TWAI1_S) +#define TEE_READ_TEE_TWAI1_V 0x00000001U +#define TEE_READ_TEE_TWAI1_S 0 +/** TEE_READ_REE0_TWAI1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE0_CAN1 (BIT(1)) -#define TEE_READ_REE0_CAN1_M (TEE_READ_REE0_CAN1_V << TEE_READ_REE0_CAN1_S) -#define TEE_READ_REE0_CAN1_V 0x00000001U -#define TEE_READ_REE0_CAN1_S 1 -/** TEE_READ_REE1_CAN1 : R/W; bitpos: [2]; default: 0; +#define TEE_READ_REE0_TWAI1 (BIT(1)) +#define TEE_READ_REE0_TWAI1_M (TEE_READ_REE0_TWAI1_V << TEE_READ_REE0_TWAI1_S) +#define TEE_READ_REE0_TWAI1_V 0x00000001U +#define TEE_READ_REE0_TWAI1_S 1 +/** TEE_READ_REE1_TWAI1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE1_CAN1 (BIT(2)) -#define TEE_READ_REE1_CAN1_M (TEE_READ_REE1_CAN1_V << TEE_READ_REE1_CAN1_S) -#define TEE_READ_REE1_CAN1_V 0x00000001U -#define TEE_READ_REE1_CAN1_S 2 -/** TEE_READ_REE2_CAN1 : R/W; bitpos: [3]; default: 0; +#define TEE_READ_REE1_TWAI1 (BIT(2)) +#define TEE_READ_REE1_TWAI1_M (TEE_READ_REE1_TWAI1_V << TEE_READ_REE1_TWAI1_S) +#define TEE_READ_REE1_TWAI1_V 0x00000001U +#define TEE_READ_REE1_TWAI1_S 2 +/** TEE_READ_REE2_TWAI1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ -#define TEE_READ_REE2_CAN1 (BIT(3)) -#define TEE_READ_REE2_CAN1_M (TEE_READ_REE2_CAN1_V << TEE_READ_REE2_CAN1_S) -#define TEE_READ_REE2_CAN1_V 0x00000001U -#define TEE_READ_REE2_CAN1_S 3 -/** TEE_WRITE_TEE_CAN1 : R/W; bitpos: [4]; default: 1; +#define TEE_READ_REE2_TWAI1 (BIT(3)) +#define TEE_READ_REE2_TWAI1_M (TEE_READ_REE2_TWAI1_V << TEE_READ_REE2_TWAI1_S) +#define TEE_READ_REE2_TWAI1_V 0x00000001U +#define TEE_READ_REE2_TWAI1_S 3 +/** TEE_WRITE_TEE_TWAI1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_TEE_CAN1 (BIT(4)) -#define TEE_WRITE_TEE_CAN1_M (TEE_WRITE_TEE_CAN1_V << TEE_WRITE_TEE_CAN1_S) -#define TEE_WRITE_TEE_CAN1_V 0x00000001U -#define TEE_WRITE_TEE_CAN1_S 4 -/** TEE_WRITE_REE0_CAN1 : R/W; bitpos: [5]; default: 0; +#define TEE_WRITE_TEE_TWAI1 (BIT(4)) +#define TEE_WRITE_TEE_TWAI1_M (TEE_WRITE_TEE_TWAI1_V << TEE_WRITE_TEE_TWAI1_S) +#define TEE_WRITE_TEE_TWAI1_V 0x00000001U +#define TEE_WRITE_TEE_TWAI1_S 4 +/** TEE_WRITE_REE0_TWAI1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE0_CAN1 (BIT(5)) -#define TEE_WRITE_REE0_CAN1_M (TEE_WRITE_REE0_CAN1_V << TEE_WRITE_REE0_CAN1_S) -#define TEE_WRITE_REE0_CAN1_V 0x00000001U -#define TEE_WRITE_REE0_CAN1_S 5 -/** TEE_WRITE_REE1_CAN1 : R/W; bitpos: [6]; default: 0; +#define TEE_WRITE_REE0_TWAI1 (BIT(5)) +#define TEE_WRITE_REE0_TWAI1_M (TEE_WRITE_REE0_TWAI1_V << TEE_WRITE_REE0_TWAI1_S) +#define TEE_WRITE_REE0_TWAI1_V 0x00000001U +#define TEE_WRITE_REE0_TWAI1_S 5 +/** TEE_WRITE_REE1_TWAI1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE1_CAN1 (BIT(6)) -#define TEE_WRITE_REE1_CAN1_M (TEE_WRITE_REE1_CAN1_V << TEE_WRITE_REE1_CAN1_S) -#define TEE_WRITE_REE1_CAN1_V 0x00000001U -#define TEE_WRITE_REE1_CAN1_S 6 -/** TEE_WRITE_REE2_CAN1 : R/W; bitpos: [7]; default: 0; +#define TEE_WRITE_REE1_TWAI1 (BIT(6)) +#define TEE_WRITE_REE1_TWAI1_M (TEE_WRITE_REE1_TWAI1_V << TEE_WRITE_REE1_TWAI1_S) +#define TEE_WRITE_REE1_TWAI1_V 0x00000001U +#define TEE_WRITE_REE1_TWAI1_S 6 +/** TEE_WRITE_REE2_TWAI1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ -#define TEE_WRITE_REE2_CAN1 (BIT(7)) -#define TEE_WRITE_REE2_CAN1_M (TEE_WRITE_REE2_CAN1_V << TEE_WRITE_REE2_CAN1_S) -#define TEE_WRITE_REE2_CAN1_V 0x00000001U -#define TEE_WRITE_REE2_CAN1_S 7 +#define TEE_WRITE_REE2_TWAI1 (BIT(7)) +#define TEE_WRITE_REE2_TWAI1_M (TEE_WRITE_REE2_TWAI1_V << TEE_WRITE_REE2_TWAI1_S) +#define TEE_WRITE_REE2_TWAI1_V 0x00000001U +#define TEE_WRITE_REE2_TWAI1_S 7 /** TEE_SPI2_CTRL_REG register - * spi2 read/write control register + * SPI2 read/write control register */ #define TEE_SPI2_CTRL_REG (DR_REG_TEE_BASE + 0x13c) /** TEE_READ_TEE_SPI2 : R/W; bitpos: [0]; default: 1; @@ -3751,7 +3431,7 @@ extern "C" { #define TEE_WRITE_REE2_SPI2_S 7 /** TEE_BS_CTRL_REG register - * bs read/write control register + * BITSCRAMBLER read/write control register */ #define TEE_BS_CTRL_REG (DR_REG_TEE_BASE + 0x140) /** TEE_READ_TEE_BS : R/W; bitpos: [0]; default: 1; @@ -3827,399 +3507,14 @@ extern "C" { #define TEE_WRITE_REE2_BS_V 0x00000001U #define TEE_WRITE_REE2_BS_S 7 -/** TEE_KM_CTRL_REG register - * km read/write control register - */ -#define TEE_KM_CTRL_REG (DR_REG_TEE_BASE + 0x144) -/** TEE_READ_TEE_KM : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_KM (BIT(0)) -#define TEE_READ_TEE_KM_M (TEE_READ_TEE_KM_V << TEE_READ_TEE_KM_S) -#define TEE_READ_TEE_KM_V 0x00000001U -#define TEE_READ_TEE_KM_S 0 -/** TEE_READ_REE0_KM : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_KM (BIT(1)) -#define TEE_READ_REE0_KM_M (TEE_READ_REE0_KM_V << TEE_READ_REE0_KM_S) -#define TEE_READ_REE0_KM_V 0x00000001U -#define TEE_READ_REE0_KM_S 1 -/** TEE_READ_REE1_KM : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_KM (BIT(2)) -#define TEE_READ_REE1_KM_M (TEE_READ_REE1_KM_V << TEE_READ_REE1_KM_S) -#define TEE_READ_REE1_KM_V 0x00000001U -#define TEE_READ_REE1_KM_S 2 -/** TEE_READ_REE2_KM : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_KM (BIT(3)) -#define TEE_READ_REE2_KM_M (TEE_READ_REE2_KM_V << TEE_READ_REE2_KM_S) -#define TEE_READ_REE2_KM_V 0x00000001U -#define TEE_READ_REE2_KM_S 3 -/** TEE_WRITE_TEE_KM : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_KM (BIT(4)) -#define TEE_WRITE_TEE_KM_M (TEE_WRITE_TEE_KM_V << TEE_WRITE_TEE_KM_S) -#define TEE_WRITE_TEE_KM_V 0x00000001U -#define TEE_WRITE_TEE_KM_S 4 -/** TEE_WRITE_REE0_KM : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_KM (BIT(5)) -#define TEE_WRITE_REE0_KM_M (TEE_WRITE_REE0_KM_V << TEE_WRITE_REE0_KM_S) -#define TEE_WRITE_REE0_KM_V 0x00000001U -#define TEE_WRITE_REE0_KM_S 5 -/** TEE_WRITE_REE1_KM : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_KM (BIT(6)) -#define TEE_WRITE_REE1_KM_M (TEE_WRITE_REE1_KM_V << TEE_WRITE_REE1_KM_S) -#define TEE_WRITE_REE1_KM_V 0x00000001U -#define TEE_WRITE_REE1_KM_S 6 -/** TEE_WRITE_REE2_KM : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_KM (BIT(7)) -#define TEE_WRITE_REE2_KM_M (TEE_WRITE_REE2_KM_V << TEE_WRITE_REE2_KM_S) -#define TEE_WRITE_REE2_KM_V 0x00000001U -#define TEE_WRITE_REE2_KM_S 7 - -/** TEE_MODEM_PWR_CTRL_REG register - * modem_pwr read/write control register - */ -#define TEE_MODEM_PWR_CTRL_REG (DR_REG_TEE_BASE + 0x148) -/** TEE_READ_TEE_MODEM_PWR : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_MODEM_PWR (BIT(0)) -#define TEE_READ_TEE_MODEM_PWR_M (TEE_READ_TEE_MODEM_PWR_V << TEE_READ_TEE_MODEM_PWR_S) -#define TEE_READ_TEE_MODEM_PWR_V 0x00000001U -#define TEE_READ_TEE_MODEM_PWR_S 0 -/** TEE_READ_REE0_MODEM_PWR : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_MODEM_PWR (BIT(1)) -#define TEE_READ_REE0_MODEM_PWR_M (TEE_READ_REE0_MODEM_PWR_V << TEE_READ_REE0_MODEM_PWR_S) -#define TEE_READ_REE0_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE0_MODEM_PWR_S 1 -/** TEE_READ_REE1_MODEM_PWR : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_MODEM_PWR (BIT(2)) -#define TEE_READ_REE1_MODEM_PWR_M (TEE_READ_REE1_MODEM_PWR_V << TEE_READ_REE1_MODEM_PWR_S) -#define TEE_READ_REE1_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE1_MODEM_PWR_S 2 -/** TEE_READ_REE2_MODEM_PWR : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_MODEM_PWR (BIT(3)) -#define TEE_READ_REE2_MODEM_PWR_M (TEE_READ_REE2_MODEM_PWR_V << TEE_READ_REE2_MODEM_PWR_S) -#define TEE_READ_REE2_MODEM_PWR_V 0x00000001U -#define TEE_READ_REE2_MODEM_PWR_S 3 -/** TEE_WRITE_TEE_MODEM_PWR : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_MODEM_PWR (BIT(4)) -#define TEE_WRITE_TEE_MODEM_PWR_M (TEE_WRITE_TEE_MODEM_PWR_V << TEE_WRITE_TEE_MODEM_PWR_S) -#define TEE_WRITE_TEE_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_TEE_MODEM_PWR_S 4 -/** TEE_WRITE_REE0_MODEM_PWR : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_MODEM_PWR (BIT(5)) -#define TEE_WRITE_REE0_MODEM_PWR_M (TEE_WRITE_REE0_MODEM_PWR_V << TEE_WRITE_REE0_MODEM_PWR_S) -#define TEE_WRITE_REE0_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE0_MODEM_PWR_S 5 -/** TEE_WRITE_REE1_MODEM_PWR : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_MODEM_PWR (BIT(6)) -#define TEE_WRITE_REE1_MODEM_PWR_M (TEE_WRITE_REE1_MODEM_PWR_V << TEE_WRITE_REE1_MODEM_PWR_S) -#define TEE_WRITE_REE1_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE1_MODEM_PWR_S 6 -/** TEE_WRITE_REE2_MODEM_PWR : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_MODEM_PWR (BIT(7)) -#define TEE_WRITE_REE2_MODEM_PWR_M (TEE_WRITE_REE2_MODEM_PWR_V << TEE_WRITE_REE2_MODEM_PWR_S) -#define TEE_WRITE_REE2_MODEM_PWR_V 0x00000001U -#define TEE_WRITE_REE2_MODEM_PWR_S 7 - -/** TEE_HINF_CTRL_REG register - * hinf read/write control register - */ -#define TEE_HINF_CTRL_REG (DR_REG_TEE_BASE + 0x14c) -/** TEE_READ_TEE_HINF : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_HINF (BIT(0)) -#define TEE_READ_TEE_HINF_M (TEE_READ_TEE_HINF_V << TEE_READ_TEE_HINF_S) -#define TEE_READ_TEE_HINF_V 0x00000001U -#define TEE_READ_TEE_HINF_S 0 -/** TEE_READ_REE0_HINF : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_HINF (BIT(1)) -#define TEE_READ_REE0_HINF_M (TEE_READ_REE0_HINF_V << TEE_READ_REE0_HINF_S) -#define TEE_READ_REE0_HINF_V 0x00000001U -#define TEE_READ_REE0_HINF_S 1 -/** TEE_READ_REE1_HINF : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_HINF (BIT(2)) -#define TEE_READ_REE1_HINF_M (TEE_READ_REE1_HINF_V << TEE_READ_REE1_HINF_S) -#define TEE_READ_REE1_HINF_V 0x00000001U -#define TEE_READ_REE1_HINF_S 2 -/** TEE_READ_REE2_HINF : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_HINF (BIT(3)) -#define TEE_READ_REE2_HINF_M (TEE_READ_REE2_HINF_V << TEE_READ_REE2_HINF_S) -#define TEE_READ_REE2_HINF_V 0x00000001U -#define TEE_READ_REE2_HINF_S 3 -/** TEE_WRITE_TEE_HINF : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_HINF (BIT(4)) -#define TEE_WRITE_TEE_HINF_M (TEE_WRITE_TEE_HINF_V << TEE_WRITE_TEE_HINF_S) -#define TEE_WRITE_TEE_HINF_V 0x00000001U -#define TEE_WRITE_TEE_HINF_S 4 -/** TEE_WRITE_REE0_HINF : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_HINF (BIT(5)) -#define TEE_WRITE_REE0_HINF_M (TEE_WRITE_REE0_HINF_V << TEE_WRITE_REE0_HINF_S) -#define TEE_WRITE_REE0_HINF_V 0x00000001U -#define TEE_WRITE_REE0_HINF_S 5 -/** TEE_WRITE_REE1_HINF : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_HINF (BIT(6)) -#define TEE_WRITE_REE1_HINF_M (TEE_WRITE_REE1_HINF_V << TEE_WRITE_REE1_HINF_S) -#define TEE_WRITE_REE1_HINF_V 0x00000001U -#define TEE_WRITE_REE1_HINF_S 6 -/** TEE_WRITE_REE2_HINF : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_HINF (BIT(7)) -#define TEE_WRITE_REE2_HINF_M (TEE_WRITE_REE2_HINF_V << TEE_WRITE_REE2_HINF_S) -#define TEE_WRITE_REE2_HINF_V 0x00000001U -#define TEE_WRITE_REE2_HINF_S 7 - -/** TEE_SLC_CTRL_REG register - * slc read/write control register - */ -#define TEE_SLC_CTRL_REG (DR_REG_TEE_BASE + 0x150) -/** TEE_READ_TEE_SLC : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC (BIT(0)) -#define TEE_READ_TEE_SLC_M (TEE_READ_TEE_SLC_V << TEE_READ_TEE_SLC_S) -#define TEE_READ_TEE_SLC_V 0x00000001U -#define TEE_READ_TEE_SLC_S 0 -/** TEE_READ_REE0_SLC : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC (BIT(1)) -#define TEE_READ_REE0_SLC_M (TEE_READ_REE0_SLC_V << TEE_READ_REE0_SLC_S) -#define TEE_READ_REE0_SLC_V 0x00000001U -#define TEE_READ_REE0_SLC_S 1 -/** TEE_READ_REE1_SLC : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC (BIT(2)) -#define TEE_READ_REE1_SLC_M (TEE_READ_REE1_SLC_V << TEE_READ_REE1_SLC_S) -#define TEE_READ_REE1_SLC_V 0x00000001U -#define TEE_READ_REE1_SLC_S 2 -/** TEE_READ_REE2_SLC : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC (BIT(3)) -#define TEE_READ_REE2_SLC_M (TEE_READ_REE2_SLC_V << TEE_READ_REE2_SLC_S) -#define TEE_READ_REE2_SLC_V 0x00000001U -#define TEE_READ_REE2_SLC_S 3 -/** TEE_WRITE_TEE_SLC : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC (BIT(4)) -#define TEE_WRITE_TEE_SLC_M (TEE_WRITE_TEE_SLC_V << TEE_WRITE_TEE_SLC_S) -#define TEE_WRITE_TEE_SLC_V 0x00000001U -#define TEE_WRITE_TEE_SLC_S 4 -/** TEE_WRITE_REE0_SLC : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC (BIT(5)) -#define TEE_WRITE_REE0_SLC_M (TEE_WRITE_REE0_SLC_V << TEE_WRITE_REE0_SLC_S) -#define TEE_WRITE_REE0_SLC_V 0x00000001U -#define TEE_WRITE_REE0_SLC_S 5 -/** TEE_WRITE_REE1_SLC : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC (BIT(6)) -#define TEE_WRITE_REE1_SLC_M (TEE_WRITE_REE1_SLC_V << TEE_WRITE_REE1_SLC_S) -#define TEE_WRITE_REE1_SLC_V 0x00000001U -#define TEE_WRITE_REE1_SLC_S 6 -/** TEE_WRITE_REE2_SLC : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC (BIT(7)) -#define TEE_WRITE_REE2_SLC_M (TEE_WRITE_REE2_SLC_V << TEE_WRITE_REE2_SLC_S) -#define TEE_WRITE_REE2_SLC_V 0x00000001U -#define TEE_WRITE_REE2_SLC_S 7 - -/** TEE_SLC_HOST_CTRL_REG register - * slc_host read/write control register - */ -#define TEE_SLC_HOST_CTRL_REG (DR_REG_TEE_BASE + 0x158) -/** TEE_READ_TEE_SLC_HOST : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_TEE_SLC_HOST (BIT(0)) -#define TEE_READ_TEE_SLC_HOST_M (TEE_READ_TEE_SLC_HOST_V << TEE_READ_TEE_SLC_HOST_S) -#define TEE_READ_TEE_SLC_HOST_V 0x00000001U -#define TEE_READ_TEE_SLC_HOST_S 0 -/** TEE_READ_REE0_SLC_HOST : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE0_SLC_HOST (BIT(1)) -#define TEE_READ_REE0_SLC_HOST_M (TEE_READ_REE0_SLC_HOST_V << TEE_READ_REE0_SLC_HOST_S) -#define TEE_READ_REE0_SLC_HOST_V 0x00000001U -#define TEE_READ_REE0_SLC_HOST_S 1 -/** TEE_READ_REE1_SLC_HOST : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE1_SLC_HOST (BIT(2)) -#define TEE_READ_REE1_SLC_HOST_M (TEE_READ_REE1_SLC_HOST_V << TEE_READ_REE1_SLC_HOST_S) -#define TEE_READ_REE1_SLC_HOST_V 0x00000001U -#define TEE_READ_REE1_SLC_HOST_S 2 -/** TEE_READ_REE2_SLC_HOST : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ -#define TEE_READ_REE2_SLC_HOST (BIT(3)) -#define TEE_READ_REE2_SLC_HOST_M (TEE_READ_REE2_SLC_HOST_V << TEE_READ_REE2_SLC_HOST_S) -#define TEE_READ_REE2_SLC_HOST_V 0x00000001U -#define TEE_READ_REE2_SLC_HOST_S 3 -/** TEE_WRITE_TEE_SLC_HOST : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_TEE_SLC_HOST (BIT(4)) -#define TEE_WRITE_TEE_SLC_HOST_M (TEE_WRITE_TEE_SLC_HOST_V << TEE_WRITE_TEE_SLC_HOST_S) -#define TEE_WRITE_TEE_SLC_HOST_V 0x00000001U -#define TEE_WRITE_TEE_SLC_HOST_S 4 -/** TEE_WRITE_REE0_SLC_HOST : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE0_SLC_HOST (BIT(5)) -#define TEE_WRITE_REE0_SLC_HOST_M (TEE_WRITE_REE0_SLC_HOST_V << TEE_WRITE_REE0_SLC_HOST_S) -#define TEE_WRITE_REE0_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE0_SLC_HOST_S 5 -/** TEE_WRITE_REE1_SLC_HOST : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE1_SLC_HOST (BIT(6)) -#define TEE_WRITE_REE1_SLC_HOST_M (TEE_WRITE_REE1_SLC_HOST_V << TEE_WRITE_REE1_SLC_HOST_S) -#define TEE_WRITE_REE1_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE1_SLC_HOST_S 6 -/** TEE_WRITE_REE2_SLC_HOST : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ -#define TEE_WRITE_REE2_SLC_HOST (BIT(7)) -#define TEE_WRITE_REE2_SLC_HOST_M (TEE_WRITE_REE2_SLC_HOST_V << TEE_WRITE_REE2_SLC_HOST_S) -#define TEE_WRITE_REE2_SLC_HOST_V 0x00000001U -#define TEE_WRITE_REE2_SLC_HOST_S 7 - /** TEE_BUS_ERR_CONF_REG register - * Clock gating register + * Error message return configuration register */ #define TEE_BUS_ERR_CONF_REG (DR_REG_TEE_BASE + 0xff0) /** TEE_BUS_ERR_RESP_EN : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ #define TEE_BUS_ERR_RESP_EN (BIT(0)) #define TEE_BUS_ERR_RESP_EN_M (TEE_BUS_ERR_RESP_EN_V << TEE_BUS_ERR_RESP_EN_S) @@ -4232,8 +3527,8 @@ extern "C" { #define TEE_CLOCK_GATE_REG (DR_REG_TEE_BASE + 0xff8) /** TEE_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ #define TEE_CLK_EN (BIT(0)) #define TEE_CLK_EN_M (TEE_CLK_EN_V << TEE_CLK_EN_S) @@ -4245,7 +3540,7 @@ extern "C" { */ #define TEE_DATE_REG (DR_REG_TEE_BASE + 0xffc) /** TEE_DATE : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ #define TEE_DATE 0x0FFFFFFFU #define TEE_DATE_M (TEE_DATE_V << TEE_DATE_S) diff --git a/components/soc/esp32c5/register/soc/tee_struct.h b/components/soc/esp32c5/register/soc/tee_struct.h index 13f9c99d53..23e99d2768 100644 --- a/components/soc/esp32c5/register/soc/tee_struct.h +++ b/components/soc/esp32c5/register/soc/tee_struct.h @@ -10,22 +10,24 @@ extern "C" { #endif -/** Group: Tee mode control register */ +/** Group: Configuration Registers */ /** Type of mn_mode_ctrl register - * TEE mode control register + * Security mode configuration register */ typedef union { struct { /** mn_mode : R/W; bitpos: [1:0]; default: 0; - * Configures Mn security level mode. - * 0: tee_mode - * 1: ree_mode0 - * 2: ree_mode1 - * 3: ree_mode2 + * Configures the security mode for master n. + * 0: TEE + * 1: REE0 + * 2: REE1 + * 3: REE2 */ uint32_t mn_mode:2; /** mn_lock : R/W; bitpos: [2]; default: 0; - * Set 1 to lock m0 tee configuration + * Configures whether to lock the value of TEE_Mn_MODE. + * 0: Do not lock + * 1: Lock */ uint32_t mn_lock:1; uint32_t reserved_3:29; @@ -34,9 +36,9 @@ typedef union { } tee_mn_mode_ctrl_reg_t; -/** Group: read write control register */ +/** Group: Peripheral Read/Write Control Registers */ /** Type of uart0_ctrl register - * uart0 read/write control register + * UART0 read/write control register */ typedef union { struct { @@ -94,7 +96,7 @@ typedef union { } tee_uart0_ctrl_reg_t; /** Type of uart1_ctrl register - * uart1 read/write control register + * UART1 read/write control register */ typedef union { struct { @@ -152,7 +154,7 @@ typedef union { } tee_uart1_ctrl_reg_t; /** Type of uhci0_ctrl register - * uhci0 read/write control register + * UHCI read/write control register */ typedef union { struct { @@ -210,7 +212,7 @@ typedef union { } tee_uhci0_ctrl_reg_t; /** Type of i2c_ext0_ctrl register - * i2c_ext0 read/write control register + * I2C read/write control register */ typedef union { struct { @@ -268,7 +270,7 @@ typedef union { } tee_i2c_ext0_ctrl_reg_t; /** Type of i2s_ctrl register - * i2s read/write control register + * I2S read/write control register */ typedef union { struct { @@ -326,7 +328,7 @@ typedef union { } tee_i2s_ctrl_reg_t; /** Type of parl_io_ctrl register - * parl_io read/write control register + * PARL_IO read/write control register */ typedef union { struct { @@ -384,7 +386,7 @@ typedef union { } tee_parl_io_ctrl_reg_t; /** Type of pwm_ctrl register - * pwm read/write control register + * MCPWM read/write control register */ typedef union { struct { @@ -442,7 +444,7 @@ typedef union { } tee_pwm_ctrl_reg_t; /** Type of ledc_ctrl register - * ledc read/write control register + * LEDC read/write control register */ typedef union { struct { @@ -499,124 +501,124 @@ typedef union { uint32_t val; } tee_ledc_ctrl_reg_t; -/** Type of can0_ctrl register - * can read/write control register +/** Type of twai0_ctrl register + * TWAI0 read/write control register */ typedef union { struct { - /** read_tee_can0 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai0 : R/W; bitpos: [0]; default: 1; * Configures can0 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can0:1; - /** read_ree0_can0 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai0:1; + /** read_ree0_twai0 : R/W; bitpos: [1]; default: 0; * Configures can0 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can0:1; - /** read_ree1_can0 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai0:1; + /** read_ree1_twai0 : R/W; bitpos: [2]; default: 0; * Configures can0 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can0:1; - /** read_ree2_can0 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai0:1; + /** read_ree2_twai0 : R/W; bitpos: [3]; default: 0; * Configures can0 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can0:1; - /** write_tee_can0 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai0:1; + /** write_tee_twai0 : R/W; bitpos: [4]; default: 1; * Configures can0 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can0:1; - /** write_ree0_can0 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai0:1; + /** write_ree0_twai0 : R/W; bitpos: [5]; default: 0; * Configures can0 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can0:1; - /** write_ree1_can0 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai0:1; + /** write_ree1_twai0 : R/W; bitpos: [6]; default: 0; * Configures can0 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can0:1; - /** write_ree2_can0 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai0:1; + /** write_ree2_twai0 : R/W; bitpos: [7]; default: 0; * Configures can0 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can0:1; + uint32_t write_ree2_twai0:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can0_ctrl_reg_t; +} tee_twai0_ctrl_reg_t; -/** Type of usb_device_ctrl register - * usb_device read/write control register +/** Type of usb_serial_jtag_ctrl register + * USB_SERIAL_JTAG read/write control register */ typedef union { struct { - /** read_tee_usb_device : R/W; bitpos: [0]; default: 1; + /** read_tee_usb_serial_jtag : R/W; bitpos: [0]; default: 1; * Configures usb_device registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_usb_device:1; - /** read_ree0_usb_device : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_usb_serial_jtag:1; + /** read_ree0_usb_serial_jtag : R/W; bitpos: [1]; default: 0; * Configures usb_device registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_usb_device:1; - /** read_ree1_usb_device : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_usb_serial_jtag:1; + /** read_ree1_usb_serial_jtag : R/W; bitpos: [2]; default: 0; * Configures usb_device registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_usb_device:1; - /** read_ree2_usb_device : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_usb_serial_jtag:1; + /** read_ree2_usb_serial_jtag : R/W; bitpos: [3]; default: 0; * Configures usb_device registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_usb_device:1; - /** write_tee_usb_device : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_usb_serial_jtag:1; + /** write_tee_usb_serial_jtag : R/W; bitpos: [4]; default: 1; * Configures usb_device registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_usb_device:1; - /** write_ree0_usb_device : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_usb_serial_jtag:1; + /** write_ree0_usb_serial_jtag : R/W; bitpos: [5]; default: 0; * Configures usb_device registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_usb_device:1; - /** write_ree1_usb_device : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_usb_serial_jtag:1; + /** write_ree1_usb_serial_jtag : R/W; bitpos: [6]; default: 0; * Configures usb_device registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_usb_device:1; - /** write_ree2_usb_device : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_usb_serial_jtag:1; + /** write_ree2_usb_serial_jtag : R/W; bitpos: [7]; default: 0; * Configures usb_device registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_usb_device:1; + uint32_t write_ree2_usb_serial_jtag:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_usb_device_ctrl_reg_t; +} tee_usb_serial_jtag_ctrl_reg_t; /** Type of rmt_ctrl register - * rmt read/write control register + * RMT read/write control register */ typedef union { struct { @@ -674,7 +676,7 @@ typedef union { } tee_rmt_ctrl_reg_t; /** Type of gdma_ctrl register - * gdma read/write control register + * GDMA read/write control register */ typedef union { struct { @@ -731,66 +733,8 @@ typedef union { uint32_t val; } tee_gdma_ctrl_reg_t; -/** Type of regdma_ctrl register - * regdma read/write control register - */ -typedef union { - struct { - /** read_tee_regdma : R/W; bitpos: [0]; default: 1; - * Configures regdma registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_regdma:1; - /** read_ree0_regdma : R/W; bitpos: [1]; default: 0; - * Configures regdma registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_regdma:1; - /** read_ree1_regdma : R/W; bitpos: [2]; default: 0; - * Configures regdma registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_regdma:1; - /** read_ree2_regdma : R/W; bitpos: [3]; default: 0; - * Configures regdma registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_regdma:1; - /** write_tee_regdma : R/W; bitpos: [4]; default: 1; - * Configures regdma registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_regdma:1; - /** write_ree0_regdma : R/W; bitpos: [5]; default: 0; - * Configures regdma registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_regdma:1; - /** write_ree1_regdma : R/W; bitpos: [6]; default: 0; - * Configures regdma registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_regdma:1; - /** write_ree2_regdma : R/W; bitpos: [7]; default: 0; - * Configures regdma registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_regdma:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_regdma_ctrl_reg_t; - /** Type of etm_ctrl register - * etm read/write control register + * SOC_ETM read/write control register */ typedef union { struct { @@ -848,7 +792,7 @@ typedef union { } tee_etm_ctrl_reg_t; /** Type of intmtx_ctrl register - * intmtx read/write control register + * INTMTX read/write control register */ typedef union { struct { @@ -906,7 +850,7 @@ typedef union { } tee_intmtx_ctrl_reg_t; /** Type of apb_adc_ctrl register - * apb_adc read/write control register + * SAR ADC read/write control register */ typedef union { struct { @@ -964,7 +908,7 @@ typedef union { } tee_apb_adc_ctrl_reg_t; /** Type of timergroup0_ctrl register - * timergroup0 read/write control register + * TIMG0 read/write control register */ typedef union { struct { @@ -1022,7 +966,7 @@ typedef union { } tee_timergroup0_ctrl_reg_t; /** Type of timergroup1_ctrl register - * timergroup1 read/write control register + * TIMG1 read/write control register */ typedef union { struct { @@ -1080,7 +1024,7 @@ typedef union { } tee_timergroup1_ctrl_reg_t; /** Type of systimer_ctrl register - * systimer read/write control register + * SYSTIMER read/write control register */ typedef union { struct { @@ -1137,124 +1081,8 @@ typedef union { uint32_t val; } tee_systimer_ctrl_reg_t; -/** Type of misc_ctrl register - * misc read/write control register - */ -typedef union { - struct { - /** read_tee_misc : R/W; bitpos: [0]; default: 1; - * Configures misc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_misc:1; - /** read_ree0_misc : R/W; bitpos: [1]; default: 0; - * Configures misc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_misc:1; - /** read_ree1_misc : R/W; bitpos: [2]; default: 0; - * Configures misc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_misc:1; - /** read_ree2_misc : R/W; bitpos: [3]; default: 0; - * Configures misc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_misc:1; - /** write_tee_misc : R/W; bitpos: [4]; default: 1; - * Configures misc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_misc:1; - /** write_ree0_misc : R/W; bitpos: [5]; default: 0; - * Configures misc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_misc:1; - /** write_ree1_misc : R/W; bitpos: [6]; default: 0; - * Configures misc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_misc:1; - /** write_ree2_misc : R/W; bitpos: [7]; default: 0; - * Configures misc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_misc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_misc_ctrl_reg_t; - -/** Type of pvt_monitor_ctrl register - * pvt_monitor read/write control register - */ -typedef union { - struct { - /** read_tee_pvt_monitor : R/W; bitpos: [0]; default: 1; - * Configures pvt_monitor registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_pvt_monitor:1; - /** read_ree0_pvt_monitor : R/W; bitpos: [1]; default: 0; - * Configures pvt_monitor registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_pvt_monitor:1; - /** read_ree1_pvt_monitor : R/W; bitpos: [2]; default: 0; - * Configures pvt_monitor registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_pvt_monitor:1; - /** read_ree2_pvt_monitor : R/W; bitpos: [3]; default: 0; - * Configures pvt_monitor registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_pvt_monitor:1; - /** write_tee_pvt_monitor : R/W; bitpos: [4]; default: 1; - * Configures pvt_monitor registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_pvt_monitor:1; - /** write_ree0_pvt_monitor : R/W; bitpos: [5]; default: 0; - * Configures pvt_monitor registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_pvt_monitor:1; - /** write_ree1_pvt_monitor : R/W; bitpos: [6]; default: 0; - * Configures pvt_monitor registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_pvt_monitor:1; - /** write_ree2_pvt_monitor : R/W; bitpos: [7]; default: 0; - * Configures pvt_monitor registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_pvt_monitor:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_pvt_monitor_ctrl_reg_t; - /** Type of pcnt_ctrl register - * pcnt read/write control register + * PCNT read/write control register */ typedef union { struct { @@ -1312,7 +1140,7 @@ typedef union { } tee_pcnt_ctrl_reg_t; /** Type of iomux_ctrl register - * iomux read/write control register + * IO MUX read/write control register */ typedef union { struct { @@ -1370,7 +1198,7 @@ typedef union { } tee_iomux_ctrl_reg_t; /** Type of psram_mem_monitor_ctrl register - * psram_mem_monitor read/write control register + * PSRAM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1428,7 +1256,7 @@ typedef union { } tee_psram_mem_monitor_ctrl_reg_t; /** Type of mem_acs_monitor_ctrl register - * mem_acs_monitor read/write control register + * TCM_MEM_MONITOR read/write control register */ typedef union { struct { @@ -1486,7 +1314,7 @@ typedef union { } tee_mem_acs_monitor_ctrl_reg_t; /** Type of hp_system_reg_ctrl register - * hp_system_reg read/write control register + * HP_SYSREG read/write control register */ typedef union { struct { @@ -1544,7 +1372,7 @@ typedef union { } tee_hp_system_reg_ctrl_reg_t; /** Type of pcr_reg_ctrl register - * pcr_reg read/write control register + * PCR read/write control register */ typedef union { struct { @@ -1602,7 +1430,7 @@ typedef union { } tee_pcr_reg_ctrl_reg_t; /** Type of mspi_ctrl register - * mspi read/write control register + * SPI01 read/write control register */ typedef union { struct { @@ -1660,7 +1488,7 @@ typedef union { } tee_mspi_ctrl_reg_t; /** Type of hp_apm_ctrl register - * hp_apm read/write control register + * HP_APM and LP_APM0 read/write control register */ typedef union { struct { @@ -1718,7 +1546,7 @@ typedef union { } tee_hp_apm_ctrl_reg_t; /** Type of cpu_apm_ctrl register - * cpu_apm read/write control register + * CPU_APM_REG read/write control register */ typedef union { struct { @@ -1776,7 +1604,7 @@ typedef union { } tee_cpu_apm_ctrl_reg_t; /** Type of tee_ctrl register - * tee read/write control register + * TEE read/write control register */ typedef union { struct { @@ -1834,7 +1662,8 @@ typedef union { } tee_tee_ctrl_reg_t; /** Type of crypt_ctrl register - * crypt read/write control register + * CRYPT read/write control register, including security peripherals from AES to ECDSA + * address range */ typedef union { struct { @@ -1892,7 +1721,7 @@ typedef union { } tee_crypt_ctrl_reg_t; /** Type of trace_ctrl register - * trace read/write control register + * TRACE read/write control register */ typedef union { struct { @@ -1950,7 +1779,7 @@ typedef union { } tee_trace_ctrl_reg_t; /** Type of cpu_bus_monitor_ctrl register - * cpu_bus_monitor read/write control register + * BUS_MONITOR read/write control register */ typedef union { struct { @@ -2008,7 +1837,7 @@ typedef union { } tee_cpu_bus_monitor_ctrl_reg_t; /** Type of intpri_reg_ctrl register - * intpri_reg read/write control register + * INTPRI_REG read/write control register */ typedef union { struct { @@ -2065,182 +1894,66 @@ typedef union { uint32_t val; } tee_intpri_reg_ctrl_reg_t; -/** Type of cache_cfg_ctrl register - * cache_cfg read/write control register +/** Type of twai1_ctrl register + * TWAI1 read/write control register */ typedef union { struct { - /** read_tee_cache_cfg : R/W; bitpos: [0]; default: 1; - * Configures cache_cfg registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_cache_cfg:1; - /** read_ree0_cache_cfg : R/W; bitpos: [1]; default: 0; - * Configures cache_cfg registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_cache_cfg:1; - /** read_ree1_cache_cfg : R/W; bitpos: [2]; default: 0; - * Configures cache_cfg registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_cache_cfg:1; - /** read_ree2_cache_cfg : R/W; bitpos: [3]; default: 0; - * Configures cache_cfg registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_cache_cfg:1; - /** write_tee_cache_cfg : R/W; bitpos: [4]; default: 1; - * Configures cache_cfg registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_cache_cfg:1; - /** write_ree0_cache_cfg : R/W; bitpos: [5]; default: 0; - * Configures cache_cfg registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_cache_cfg:1; - /** write_ree1_cache_cfg : R/W; bitpos: [6]; default: 0; - * Configures cache_cfg registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_cache_cfg:1; - /** write_ree2_cache_cfg : R/W; bitpos: [7]; default: 0; - * Configures cache_cfg registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_cache_cfg:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_cache_cfg_ctrl_reg_t; - -/** Type of modem_ctrl register - * modem read/write control register - */ -typedef union { - struct { - /** read_tee_modem : R/W; bitpos: [0]; default: 1; - * Configures modem registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem:1; - /** read_ree0_modem : R/W; bitpos: [1]; default: 0; - * Configures modem registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem:1; - /** read_ree1_modem : R/W; bitpos: [2]; default: 0; - * Configures modem registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem:1; - /** read_ree2_modem : R/W; bitpos: [3]; default: 0; - * Configures modem registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem:1; - /** write_tee_modem : R/W; bitpos: [4]; default: 1; - * Configures modem registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem:1; - /** write_ree0_modem : R/W; bitpos: [5]; default: 0; - * Configures modem registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem:1; - /** write_ree1_modem : R/W; bitpos: [6]; default: 0; - * Configures modem registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem:1; - /** write_ree2_modem : R/W; bitpos: [7]; default: 0; - * Configures modem registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_ctrl_reg_t; - -/** Type of can1_ctrl register - * can1 read/write control register - */ -typedef union { - struct { - /** read_tee_can1 : R/W; bitpos: [0]; default: 1; + /** read_tee_twai1 : R/W; bitpos: [0]; default: 1; * Configures can1 registers read permission in tee mode. * 0: can not be read * 1: can be read */ - uint32_t read_tee_can1:1; - /** read_ree0_can1 : R/W; bitpos: [1]; default: 0; + uint32_t read_tee_twai1:1; + /** read_ree0_twai1 : R/W; bitpos: [1]; default: 0; * Configures can1 registers read permission in ree0 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree0_can1:1; - /** read_ree1_can1 : R/W; bitpos: [2]; default: 0; + uint32_t read_ree0_twai1:1; + /** read_ree1_twai1 : R/W; bitpos: [2]; default: 0; * Configures can1 registers read permission in ree1 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree1_can1:1; - /** read_ree2_can1 : R/W; bitpos: [3]; default: 0; + uint32_t read_ree1_twai1:1; + /** read_ree2_twai1 : R/W; bitpos: [3]; default: 0; * Configures can1 registers read permission in ree2 mode. * 0: can not be read * 1: can be read */ - uint32_t read_ree2_can1:1; - /** write_tee_can1 : R/W; bitpos: [4]; default: 1; + uint32_t read_ree2_twai1:1; + /** write_tee_twai1 : R/W; bitpos: [4]; default: 1; * Configures can1 registers write permission in tee mode. * 0: can not be write * 1: can be write */ - uint32_t write_tee_can1:1; - /** write_ree0_can1 : R/W; bitpos: [5]; default: 0; + uint32_t write_tee_twai1:1; + /** write_ree0_twai1 : R/W; bitpos: [5]; default: 0; * Configures can1 registers write permission in ree0 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree0_can1:1; - /** write_ree1_can1 : R/W; bitpos: [6]; default: 0; + uint32_t write_ree0_twai1:1; + /** write_ree1_twai1 : R/W; bitpos: [6]; default: 0; * Configures can1 registers write permission in ree1 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree1_can1:1; - /** write_ree2_can1 : R/W; bitpos: [7]; default: 0; + uint32_t write_ree1_twai1:1; + /** write_ree2_twai1 : R/W; bitpos: [7]; default: 0; * Configures can1 registers write permission in ree2 mode. * 0: can not be write * 1: can be write */ - uint32_t write_ree2_can1:1; + uint32_t write_ree2_twai1:1; uint32_t reserved_8:24; }; uint32_t val; -} tee_can1_ctrl_reg_t; +} tee_twai1_ctrl_reg_t; /** Type of spi2_ctrl register - * spi2 read/write control register + * SPI2 read/write control register */ typedef union { struct { @@ -2298,7 +2011,7 @@ typedef union { } tee_spi2_ctrl_reg_t; /** Type of bs_ctrl register - * bs read/write control register + * BITSCRAMBLER read/write control register */ typedef union { struct { @@ -2355,307 +2068,15 @@ typedef union { uint32_t val; } tee_bs_ctrl_reg_t; -/** Type of km_ctrl register - * km read/write control register - */ -typedef union { - struct { - /** read_tee_km : R/W; bitpos: [0]; default: 1; - * Configures km registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_km:1; - /** read_ree0_km : R/W; bitpos: [1]; default: 0; - * Configures km registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_km:1; - /** read_ree1_km : R/W; bitpos: [2]; default: 0; - * Configures km registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_km:1; - /** read_ree2_km : R/W; bitpos: [3]; default: 0; - * Configures km registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_km:1; - /** write_tee_km : R/W; bitpos: [4]; default: 1; - * Configures km registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_km:1; - /** write_ree0_km : R/W; bitpos: [5]; default: 0; - * Configures km registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_km:1; - /** write_ree1_km : R/W; bitpos: [6]; default: 0; - * Configures km registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_km:1; - /** write_ree2_km : R/W; bitpos: [7]; default: 0; - * Configures km registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_km:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_km_ctrl_reg_t; - -/** Type of modem_pwr_ctrl register - * modem_pwr read/write control register - */ -typedef union { - struct { - /** read_tee_modem_pwr : R/W; bitpos: [0]; default: 1; - * Configures modem_pwr registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_modem_pwr:1; - /** read_ree0_modem_pwr : R/W; bitpos: [1]; default: 0; - * Configures modem_pwr registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_modem_pwr:1; - /** read_ree1_modem_pwr : R/W; bitpos: [2]; default: 0; - * Configures modem_pwr registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_modem_pwr:1; - /** read_ree2_modem_pwr : R/W; bitpos: [3]; default: 0; - * Configures modem_pwr registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_modem_pwr:1; - /** write_tee_modem_pwr : R/W; bitpos: [4]; default: 1; - * Configures modem_pwr registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_modem_pwr:1; - /** write_ree0_modem_pwr : R/W; bitpos: [5]; default: 0; - * Configures modem_pwr registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_modem_pwr:1; - /** write_ree1_modem_pwr : R/W; bitpos: [6]; default: 0; - * Configures modem_pwr registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_modem_pwr:1; - /** write_ree2_modem_pwr : R/W; bitpos: [7]; default: 0; - * Configures modem_pwr registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_modem_pwr:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_modem_pwr_ctrl_reg_t; - -/** Type of hinf_ctrl register - * hinf read/write control register - */ -typedef union { - struct { - /** read_tee_hinf : R/W; bitpos: [0]; default: 1; - * Configures hinf registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_hinf:1; - /** read_ree0_hinf : R/W; bitpos: [1]; default: 0; - * Configures hinf registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_hinf:1; - /** read_ree1_hinf : R/W; bitpos: [2]; default: 0; - * Configures hinf registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_hinf:1; - /** read_ree2_hinf : R/W; bitpos: [3]; default: 0; - * Configures hinf registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_hinf:1; - /** write_tee_hinf : R/W; bitpos: [4]; default: 1; - * Configures hinf registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_hinf:1; - /** write_ree0_hinf : R/W; bitpos: [5]; default: 0; - * Configures hinf registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_hinf:1; - /** write_ree1_hinf : R/W; bitpos: [6]; default: 0; - * Configures hinf registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_hinf:1; - /** write_ree2_hinf : R/W; bitpos: [7]; default: 0; - * Configures hinf registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_hinf:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_hinf_ctrl_reg_t; - -/** Type of slc_ctrl register - * slc read/write control register - */ -typedef union { - struct { - /** read_tee_slc : R/W; bitpos: [0]; default: 1; - * Configures slc registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc:1; - /** read_ree0_slc : R/W; bitpos: [1]; default: 0; - * Configures slc registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc:1; - /** read_ree1_slc : R/W; bitpos: [2]; default: 0; - * Configures slc registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc:1; - /** read_ree2_slc : R/W; bitpos: [3]; default: 0; - * Configures slc registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc:1; - /** write_tee_slc : R/W; bitpos: [4]; default: 1; - * Configures slc registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc:1; - /** write_ree0_slc : R/W; bitpos: [5]; default: 0; - * Configures slc registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc:1; - /** write_ree1_slc : R/W; bitpos: [6]; default: 0; - * Configures slc registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc:1; - /** write_ree2_slc : R/W; bitpos: [7]; default: 0; - * Configures slc registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_ctrl_reg_t; - -/** Type of slc_host_ctrl register - * slc_host read/write control register - */ -typedef union { - struct { - /** read_tee_slc_host : R/W; bitpos: [0]; default: 1; - * Configures slc_host registers read permission in tee mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_tee_slc_host:1; - /** read_ree0_slc_host : R/W; bitpos: [1]; default: 0; - * Configures slc_host registers read permission in ree0 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree0_slc_host:1; - /** read_ree1_slc_host : R/W; bitpos: [2]; default: 0; - * Configures slc_host registers read permission in ree1 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree1_slc_host:1; - /** read_ree2_slc_host : R/W; bitpos: [3]; default: 0; - * Configures slc_host registers read permission in ree2 mode. - * 0: can not be read - * 1: can be read - */ - uint32_t read_ree2_slc_host:1; - /** write_tee_slc_host : R/W; bitpos: [4]; default: 1; - * Configures slc_host registers write permission in tee mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_tee_slc_host:1; - /** write_ree0_slc_host : R/W; bitpos: [5]; default: 0; - * Configures slc_host registers write permission in ree0 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree0_slc_host:1; - /** write_ree1_slc_host : R/W; bitpos: [6]; default: 0; - * Configures slc_host registers write permission in ree1 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree1_slc_host:1; - /** write_ree2_slc_host : R/W; bitpos: [7]; default: 0; - * Configures slc_host registers write permission in ree2 mode. - * 0: can not be write - * 1: can be write - */ - uint32_t write_ree2_slc_host:1; - uint32_t reserved_8:24; - }; - uint32_t val; -} tee_slc_host_ctrl_reg_t; - - -/** Group: config register */ /** Type of bus_err_conf register - * Clock gating register + * Error message return configuration register */ typedef union { struct { /** bus_err_resp_en : R/W; bitpos: [0]; default: 0; - * Configures whether return error response to cpu when access blocked - * 0: disable error response - * 1: enable error response + * Configures whether to return error message to CPU when access is blocked. + * 0: Disable + * 1: Enable */ uint32_t bus_err_resp_en:1; uint32_t reserved_1:31; @@ -2672,8 +2093,8 @@ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; * Configures whether to keep the clock always on. - * 0: enable automatic clock gating - * 1: keep the clock always on + * 0: Enable automatic clock gating + * 1: Keep the clock always on */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -2682,14 +2103,14 @@ typedef union { } tee_clock_gate_reg_t; -/** Group: Version control register */ +/** Group: Version Control Registers */ /** Type of date register * Version control register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 37773824; - * Version control register + * Version control register. */ uint32_t date:28; uint32_t reserved_28:4; @@ -2711,11 +2132,11 @@ typedef struct { volatile tee_pwm_ctrl_reg_t pwm_ctrl; uint32_t reserved_0a8; volatile tee_ledc_ctrl_reg_t ledc_ctrl; - volatile tee_can0_ctrl_reg_t can0_ctrl; - volatile tee_usb_device_ctrl_reg_t usb_device_ctrl; + volatile tee_twai0_ctrl_reg_t twai0_ctrl; + volatile tee_usb_serial_jtag_ctrl_reg_t usb_serial_jtag_ctrl; volatile tee_rmt_ctrl_reg_t rmt_ctrl; volatile tee_gdma_ctrl_reg_t gdma_ctrl; - volatile tee_regdma_ctrl_reg_t regdma_ctrl; + uint32_t reserved_0c0; volatile tee_etm_ctrl_reg_t etm_ctrl; volatile tee_intmtx_ctrl_reg_t intmtx_ctrl; uint32_t reserved_0cc; @@ -2723,9 +2144,7 @@ typedef struct { volatile tee_timergroup0_ctrl_reg_t timergroup0_ctrl; volatile tee_timergroup1_ctrl_reg_t timergroup1_ctrl; volatile tee_systimer_ctrl_reg_t systimer_ctrl; - volatile tee_misc_ctrl_reg_t misc_ctrl; - uint32_t reserved_0e4[3]; - volatile tee_pvt_monitor_ctrl_reg_t pvt_monitor_ctrl; + uint32_t reserved_0e0[5]; volatile tee_pcnt_ctrl_reg_t pcnt_ctrl; volatile tee_iomux_ctrl_reg_t iomux_ctrl; volatile tee_psram_mem_monitor_ctrl_reg_t psram_mem_monitor_ctrl; @@ -2741,18 +2160,11 @@ typedef struct { uint32_t reserved_124; volatile tee_cpu_bus_monitor_ctrl_reg_t cpu_bus_monitor_ctrl; volatile tee_intpri_reg_ctrl_reg_t intpri_reg_ctrl; - volatile tee_cache_cfg_ctrl_reg_t cache_cfg_ctrl; - volatile tee_modem_ctrl_reg_t modem_ctrl; - volatile tee_can1_ctrl_reg_t can1_ctrl; + uint32_t reserved_130[2]; + volatile tee_twai1_ctrl_reg_t twai1_ctrl; volatile tee_spi2_ctrl_reg_t spi2_ctrl; volatile tee_bs_ctrl_reg_t bs_ctrl; - volatile tee_km_ctrl_reg_t km_ctrl; - volatile tee_modem_pwr_ctrl_reg_t modem_pwr_ctrl; - volatile tee_hinf_ctrl_reg_t hinf_ctrl; - volatile tee_slc_ctrl_reg_t slc_ctrl; - uint32_t reserved_154; - volatile tee_slc_host_ctrl_reg_t slc_host_ctrl; - uint32_t reserved_15c[933]; + uint32_t reserved_144[939]; volatile tee_bus_err_conf_reg_t bus_err_conf; uint32_t reserved_ff4; volatile tee_clock_gate_reg_t clock_gate; diff --git a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in index 42894c67c7..c79c672f9e 100644 --- a/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c6/include/soc/Kconfig.soc_caps.in @@ -1299,6 +1299,10 @@ config SOC_APM_LP_APM0_SUPPORTED bool default y +config SOC_APM_SUPPORT_LP_TEE_CTRL + bool + default y + config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED bool default y diff --git a/components/soc/esp32c6/include/soc/apm_defs.h b/components/soc/esp32c6/include/soc/apm_defs.h new file mode 100644 index 0000000000..f1d0278238 --- /dev/null +++ b/components/soc/esp32c6/include/soc/apm_defs.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of paths for each supported APM controller */ +#define APM_CTRL_HP_APM_PATH_NUM (4) +#define APM_CTRL_LP_APM0_PATH_NUM (1) +#define APM_CTRL_LP_APM_PATH_NUM (2) +/* Number of regions for each supported APM controller */ +#define APM_CTRL_HP_APM_REGION_NUM (16) +#define APM_CTRL_LP_APM0_REGION_NUM (4) +#define APM_CTRL_LP_APM_REGION_NUM (4) + +/* Register offset for TEE mode control */ +#define APM_TEE_MODE_CTRL_OFFSET (0x04) +/* Register offset between region bound address registers */ +#define APM_REGION_ADDR_OFFSET (0x0C) +/* Register offset between region pms attribute registers */ +#define APM_REGION_PMS_ATTR_OFFSET (0x0C) +/* Register offset between exception info registers */ +#define APM_EXCP_INFO_OFFSET (0x10) + +/* Bit to clear exception status */ +#define APM_EXCP_STATUS_CLR_BIT (BIT(0)) + +/* APM controller masters mask */ +#define APM_MASTER_MASK_ALL (0x03CD007FU) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c6/include/soc/soc_caps.h b/components/soc/esp32c6/include/soc/soc_caps.h index 933801224c..34746417ea 100644 --- a/components/soc/esp32c6/include/soc/soc_caps.h +++ b/components/soc/esp32c6/include/soc/soc_caps.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -498,8 +498,9 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 /*-------------------------- APM CAPS ----------------------------------------*/ -#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ -#define SOC_APM_LP_APM0_SUPPORTED 1 /*!< Support for LP APM0 control filter */ +#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */ +#define SOC_APM_LP_APM0_SUPPORTED 1 /*!< Support for LP APM0 control filter */ +#define SOC_APM_SUPPORT_LP_TEE_CTRL 1 /*!< Support for LP TEE controller */ /*------------------------ Anti DPA (Security) CAPS --------------------------*/ #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 diff --git a/components/soc/esp32c61/gdma_periph.c b/components/soc/esp32c61/gdma_periph.c index 57f237677f..c6487bf660 100644 --- a/components/soc/esp32c61/gdma_periph.c +++ b/components/soc/esp32c61/gdma_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,8 +30,8 @@ const gdma_signal_conn_t gdma_periph_signals = { AHB_DMA_IN_CONF0_CH0_REG / AHB_DMA_IN_CONF1_CH0_REG / AHB_DMA_IN_LINK_CH0_REG / AHB_DMA_IN_PRI_CH0_REG AHB_DMA_OUT_CONF0_CH0_REG / AHB_DMA_OUT_CONF1_CH0_REG / AHB_DMA_OUT_LINK_CH0_REG / AHB_DMA_OUT_PRI_CH0_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH0_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH0_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH0_REG AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG @@ -40,7 +40,7 @@ const gdma_signal_conn_t gdma_periph_signals = { #define G0P0_RETENTION_REGS_CNT_0 13 #define G0P0_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH0_REG #define G0P0_RETENTION_REGS_CNT_1 12 -#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG +#define G0P0_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH0_REG static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0}; static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { @@ -68,8 +68,8 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { AHB_DMA_IN_CONF0_CH1_REG / AHB_DMA_IN_CONF1_CH1_REG / AHB_DMA_IN_LINK_CH1_REG / AHB_DMA_IN_PRI_CH1_REG AHB_DMA_OUT_CONF0_CH1_REG / AHB_DMA_OUT_CONF1_CH1_REG / AHB_DMA_OUT_LINK_CH1_REG / AHB_DMA_OUT_PRI_CH1_REG - AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG - AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG + AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_TX_ARB_WEIGHT_OPT_DIR_CH1_REG + AHB_DMA_RX_CH_ARB_WEIGHT_CH1_REG / AHB_DMA_RX_ARB_WEIGHT_OPT_DIR_CH1_REG AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG @@ -78,7 +78,7 @@ static const regdma_entries_config_t gdma_g0p0_regs_retention[] = { #define G0P1_RETENTION_REGS_CNT_0 13 #define G0P1_RETENTION_MAP_BASE_0 AHB_DMA_IN_INT_ENA_CH1_REG #define G0P1_RETENTION_REGS_CNT_1 12 -#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG +#define G0P1_RETENTION_MAP_BASE_1 AHB_DMA_TX_CH_ARB_WEIGHT_CH1_REG static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604}; static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0}; static const regdma_entries_config_t gdma_g0p1_regs_retention[] = { diff --git a/components/soc/esp32c61/gpio_periph.c b/components/soc/esp32c61/gpio_periph.c index 573c99dc07..7f34e53bf6 100644 --- a/components/soc/esp32c61/gpio_periph.c +++ b/components/soc/esp32c61/gpio_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,6 +32,11 @@ const uint32_t GPIO_HOLD_MASK[] = { BIT(22), //GPIO22 BIT(23), //GPIO23 BIT(24), //GPIO24 + BIT(25), //GPIO25 + BIT(26), //GPIO26 + BIT(27), //GPIO27 + BIT(28), //GPIO28 + BIT(29), //GPIO29 }; _Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK"); diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_reg.h b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h index 2e16b2e54c..5ef865e64f 100644 --- a/components/soc/esp32c61/include/modem/modem_lpcon_reg.h +++ b/components/soc/esp32c61/include/modem/modem_lpcon_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,366 +11,524 @@ extern "C" { #endif -#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) -/* MODEM_LPCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_TEST_CONF_REG register + * need_des + */ +#define MODEM_LPCON_TEST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x0) +/** MODEM_LPCON_CLK_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_EN (BIT(0)) -#define MODEM_LPCON_CLK_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_EN_V 0x1 +#define MODEM_LPCON_CLK_EN_M (MODEM_LPCON_CLK_EN_V << MODEM_LPCON_CLK_EN_S) +#define MODEM_LPCON_CLK_EN_V 0x00000001U #define MODEM_LPCON_CLK_EN_S 0 -#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) -/* MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M ((MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V)<<(MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S)) -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_LP_TIMER_CONF_REG register + * need_des + */ +#define MODEM_LPCON_LP_TIMER_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x4) +/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_M (MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V << MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_M (MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V << MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_LP_TIMER_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_M (MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V << MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S) +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_LP_TIMER_DIV_NUM_S 4 -#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) -/* MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M ((MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_COEX_LP_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_COEX_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x8) +/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_LP_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_COEX_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_M (MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V << MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_COEX_LP_DIV_NUM_S 4 -#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xC) -/* MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W ;bitpos:[15:4] ;default: 12'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M ((MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V)<<(MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0xFFF -#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (BIT(3)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (BIT(2)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (BIT(1)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x1 -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_WIFI_LP_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_WIFI_LP_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0xc) +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_SLOW_S 0 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST (BIT(1)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_OSC_FAST_S 1 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL (BIT(2)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL_S 2 +/** MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K (BIT(3)) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_M (MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V << MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_V 0x00000001U +#define MODEM_LPCON_CLK_WIFIPWR_LP_SEL_XTAL32K_S 3 +/** MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM : R/W; bitpos: [15:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_M (MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V << MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S) +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_V 0x00000FFFU +#define MODEM_LPCON_CLK_WIFIPWR_LP_DIV_NUM_S 4 -#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) -/* MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (BIT(2)) -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x1 -#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -/* MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003 -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M ((MODEM_LPCON_CLK_MODEM_AON_FORCE_V)<<(MODEM_LPCON_CLK_MODEM_AON_FORCE_S)) -#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x3 +/** MODEM_LPCON_MODEM_SRC_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MODEM_SRC_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x10) +/** MODEM_LPCON_CLK_MODEM_AON_FORCE : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_MODEM_AON_FORCE 0x00000003U +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_M (MODEM_LPCON_CLK_MODEM_AON_FORCE_V << MODEM_LPCON_CLK_MODEM_AON_FORCE_S) +#define MODEM_LPCON_CLK_MODEM_AON_FORCE_V 0x00000003U #define MODEM_LPCON_CLK_MODEM_AON_FORCE_S 0 +/** MODEM_LPCON_MODEM_PWR_CLK_SRC_FO : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO (BIT(2)) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_M (MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V << MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S) +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_V 0x00000001U +#define MODEM_LPCON_MODEM_PWR_CLK_SRC_FO_S 2 -#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) -/* MODEM_LPCON_CLK_MODEM_32K_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003 -#define MODEM_LPCON_CLK_MODEM_32K_SEL_M ((MODEM_LPCON_CLK_MODEM_32K_SEL_V)<<(MODEM_LPCON_CLK_MODEM_32K_SEL_S)) -#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x3 +/** MODEM_LPCON_MODEM_32K_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MODEM_32K_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x14) +/** MODEM_LPCON_CLK_MODEM_32K_SEL : R/W; bitpos: [1:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_MODEM_32K_SEL 0x00000003U +#define MODEM_LPCON_CLK_MODEM_32K_SEL_M (MODEM_LPCON_CLK_MODEM_32K_SEL_V << MODEM_LPCON_CLK_MODEM_32K_SEL_S) +#define MODEM_LPCON_CLK_MODEM_32K_SEL_V 0x00000003U #define MODEM_LPCON_CLK_MODEM_32K_SEL_S 0 -#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) -/* MODEM_LPCON_CLK_LP_TIMER_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -/* MODEM_LPCON_CLK_I2C_MST_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 -/* MODEM_LPCON_CLK_COEX_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_EN_V 0x1 -#define MODEM_LPCON_CLK_COEX_EN_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_CLK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x18) +/** MODEM_LPCON_CLK_WIFIPWR_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_EN (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_EN_M (MODEM_LPCON_CLK_WIFIPWR_EN_V << MODEM_LPCON_CLK_WIFIPWR_EN_S) +#define MODEM_LPCON_CLK_WIFIPWR_EN_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_EN_S 0 +/** MODEM_LPCON_CLK_COEX_EN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_EN (BIT(1)) +#define MODEM_LPCON_CLK_COEX_EN_M (MODEM_LPCON_CLK_COEX_EN_V << MODEM_LPCON_CLK_COEX_EN_S) +#define MODEM_LPCON_CLK_COEX_EN_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_EN_S 1 +/** MODEM_LPCON_CLK_I2C_MST_EN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_EN (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_EN_M (MODEM_LPCON_CLK_I2C_MST_EN_V << MODEM_LPCON_CLK_I2C_MST_EN_S) +#define MODEM_LPCON_CLK_I2C_MST_EN_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_EN_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_EN : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_EN (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_EN_M (MODEM_LPCON_CLK_LP_TIMER_EN_V << MODEM_LPCON_CLK_LP_TIMER_EN_S) +#define MODEM_LPCON_CLK_LP_TIMER_EN_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_EN_S 3 -#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1C) -/* MODEM_LPCON_CLK_FE_MEM_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_M (BIT(4)) -#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x1 -#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -/* MODEM_LPCON_CLK_LP_TIMER_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_M (BIT(3)) -#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x1 -#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 -/* MODEM_LPCON_CLK_I2C_MST_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_M (BIT(2)) -#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x1 -#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 -/* MODEM_LPCON_CLK_COEX_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_M (BIT(1)) -#define MODEM_LPCON_CLK_COEX_FO_V 0x1 -#define MODEM_LPCON_CLK_COEX_FO_S 1 -/* MODEM_LPCON_CLK_WIFIPWR_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_CLK_CONF_FORCE_ON_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_LPCON_BASE + 0x1c) +/** MODEM_LPCON_CLK_WIFIPWR_FO : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CLK_WIFIPWR_FO (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_M (BIT(0)) -#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x1 +#define MODEM_LPCON_CLK_WIFIPWR_FO_M (MODEM_LPCON_CLK_WIFIPWR_FO_V << MODEM_LPCON_CLK_WIFIPWR_FO_S) +#define MODEM_LPCON_CLK_WIFIPWR_FO_V 0x00000001U #define MODEM_LPCON_CLK_WIFIPWR_FO_S 0 +/** MODEM_LPCON_CLK_COEX_FO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_FO (BIT(1)) +#define MODEM_LPCON_CLK_COEX_FO_M (MODEM_LPCON_CLK_COEX_FO_V << MODEM_LPCON_CLK_COEX_FO_S) +#define MODEM_LPCON_CLK_COEX_FO_V 0x00000001U +#define MODEM_LPCON_CLK_COEX_FO_S 1 +/** MODEM_LPCON_CLK_I2C_MST_FO : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_FO (BIT(2)) +#define MODEM_LPCON_CLK_I2C_MST_FO_M (MODEM_LPCON_CLK_I2C_MST_FO_V << MODEM_LPCON_CLK_I2C_MST_FO_S) +#define MODEM_LPCON_CLK_I2C_MST_FO_V 0x00000001U +#define MODEM_LPCON_CLK_I2C_MST_FO_S 2 +/** MODEM_LPCON_CLK_LP_TIMER_FO : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_TIMER_FO (BIT(3)) +#define MODEM_LPCON_CLK_LP_TIMER_FO_M (MODEM_LPCON_CLK_LP_TIMER_FO_V << MODEM_LPCON_CLK_LP_TIMER_FO_S) +#define MODEM_LPCON_CLK_LP_TIMER_FO_V 0x00000001U +#define MODEM_LPCON_CLK_LP_TIMER_FO_S 3 +/** MODEM_LPCON_CLK_FE_MEM_FO : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_FE_MEM_FO (BIT(4)) +#define MODEM_LPCON_CLK_FE_MEM_FO_M (MODEM_LPCON_CLK_FE_MEM_FO_V << MODEM_LPCON_CLK_FE_MEM_FO_S) +#define MODEM_LPCON_CLK_FE_MEM_FO_V 0x00000001U +#define MODEM_LPCON_CLK_FE_MEM_FO_S 4 -#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) -/* MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M ((MODEM_LPCON_CLK_LP_APB_ST_MAP_V)<<(MODEM_LPCON_CLK_LP_APB_ST_MAP_S)) -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -/* MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M ((MODEM_LPCON_CLK_I2C_MST_ST_MAP_V)<<(MODEM_LPCON_CLK_I2C_MST_ST_MAP_S)) -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 -/* MODEM_LPCON_CLK_COEX_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_COEX_ST_MAP_M ((MODEM_LPCON_CLK_COEX_ST_MAP_V)<<(MODEM_LPCON_CLK_COEX_ST_MAP_S)) -#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0xF -#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 -/* MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000F -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M ((MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V)<<(MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S)) -#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0xF +/** MODEM_LPCON_CLK_CONF_POWER_ST_REG register + * need_des + */ +#define MODEM_LPCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_LPCON_BASE + 0x20) +/** MODEM_LPCON_CLK_WIFIPWR_ST_MAP : R/W; bitpos: [19:16]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_M (MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V << MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S) +#define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_V 0x0000000FU #define MODEM_LPCON_CLK_WIFIPWR_ST_MAP_S 16 +/** MODEM_LPCON_CLK_COEX_ST_MAP : R/W; bitpos: [23:20]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_COEX_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_M (MODEM_LPCON_CLK_COEX_ST_MAP_V << MODEM_LPCON_CLK_COEX_ST_MAP_S) +#define MODEM_LPCON_CLK_COEX_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_COEX_ST_MAP_S 20 +/** MODEM_LPCON_CLK_I2C_MST_ST_MAP : R/W; bitpos: [27:24]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_M (MODEM_LPCON_CLK_I2C_MST_ST_MAP_V << MODEM_LPCON_CLK_I2C_MST_ST_MAP_S) +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_I2C_MST_ST_MAP_S 24 +/** MODEM_LPCON_CLK_LP_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; + * need_des + */ +#define MODEM_LPCON_CLK_LP_APB_ST_MAP 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_M (MODEM_LPCON_CLK_LP_APB_ST_MAP_V << MODEM_LPCON_CLK_LP_APB_ST_MAP_S) +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_V 0x0000000FU +#define MODEM_LPCON_CLK_LP_APB_ST_MAP_S 28 -#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) -/* MODEM_LPCON_RST_LP_TIMER : WO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_M (BIT(3)) -#define MODEM_LPCON_RST_LP_TIMER_V 0x1 -#define MODEM_LPCON_RST_LP_TIMER_S 3 -/* MODEM_LPCON_RST_I2C_MST : WO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_I2C_MST (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_M (BIT(2)) -#define MODEM_LPCON_RST_I2C_MST_V 0x1 -#define MODEM_LPCON_RST_I2C_MST_S 2 -/* MODEM_LPCON_RST_COEX : WO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_RST_COEX (BIT(1)) -#define MODEM_LPCON_RST_COEX_M (BIT(1)) -#define MODEM_LPCON_RST_COEX_V 0x1 -#define MODEM_LPCON_RST_COEX_S 1 -/* MODEM_LPCON_RST_WIFIPWR : WO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_RST_CONF_REG register + * need_des + */ +#define MODEM_LPCON_RST_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x24) +/** MODEM_LPCON_RST_WIFIPWR : WO; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_RST_WIFIPWR (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_M (BIT(0)) -#define MODEM_LPCON_RST_WIFIPWR_V 0x1 +#define MODEM_LPCON_RST_WIFIPWR_M (MODEM_LPCON_RST_WIFIPWR_V << MODEM_LPCON_RST_WIFIPWR_S) +#define MODEM_LPCON_RST_WIFIPWR_V 0x00000001U #define MODEM_LPCON_RST_WIFIPWR_S 0 +/** MODEM_LPCON_RST_COEX : WO; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_COEX (BIT(1)) +#define MODEM_LPCON_RST_COEX_M (MODEM_LPCON_RST_COEX_V << MODEM_LPCON_RST_COEX_S) +#define MODEM_LPCON_RST_COEX_V 0x00000001U +#define MODEM_LPCON_RST_COEX_S 1 +/** MODEM_LPCON_RST_I2C_MST : WO; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_I2C_MST (BIT(2)) +#define MODEM_LPCON_RST_I2C_MST_M (MODEM_LPCON_RST_I2C_MST_V << MODEM_LPCON_RST_I2C_MST_S) +#define MODEM_LPCON_RST_I2C_MST_V 0x00000001U +#define MODEM_LPCON_RST_I2C_MST_S 2 +/** MODEM_LPCON_RST_LP_TIMER : WO; bitpos: [3]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_LP_TIMER (BIT(3)) +#define MODEM_LPCON_RST_LP_TIMER_M (MODEM_LPCON_RST_LP_TIMER_V << MODEM_LPCON_RST_LP_TIMER_S) +#define MODEM_LPCON_RST_LP_TIMER_V 0x00000001U +#define MODEM_LPCON_RST_LP_TIMER_S 3 +/** MODEM_LPCON_RST_DCMEM : WO; bitpos: [4]; default: 0; + * need_des + */ +#define MODEM_LPCON_RST_DCMEM (BIT(4)) +#define MODEM_LPCON_RST_DCMEM_M (MODEM_LPCON_RST_DCMEM_V << MODEM_LPCON_RST_DCMEM_S) +#define MODEM_LPCON_RST_DCMEM_V 0x00000001U +#define MODEM_LPCON_RST_DCMEM_S 4 -#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) -/* MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W ;bitpos:[5:0] ;default: 6'd39 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003F -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M ((MODEM_LPCON_MODEM_PWR_TICK_TARGET_V)<<(MODEM_LPCON_MODEM_PWR_TICK_TARGET_S)) -#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x3F +/** MODEM_LPCON_TICK_CONF_REG register + * need_des + */ +#define MODEM_LPCON_TICK_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x28) +/** MODEM_LPCON_MODEM_PWR_TICK_TARGET : R/W; bitpos: [5:0]; default: 39; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET 0x0000003FU +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_M (MODEM_LPCON_MODEM_PWR_TICK_TARGET_V << MODEM_LPCON_MODEM_PWR_TICK_TARGET_S) +#define MODEM_LPCON_MODEM_PWR_TICK_TARGET_V 0x0000003FU #define MODEM_LPCON_MODEM_PWR_TICK_TARGET_S 0 -#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2C) -/* MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W ;bitpos:[23] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (BIT(23)) -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x1 -#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -/* MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M ((MODEM_LPCON_CHAN_FREQ_MEM_MODE_V)<<(MODEM_LPCON_CHAN_FREQ_MEM_MODE_S)) -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x7 -#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 -/* MODEM_LPCON_I2C_MST_MEM_FORCE : R/W ;bitpos:[19] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (BIT(19)) -#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x1 -#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 -/* MODEM_LPCON_I2C_MST_MEM_MODE : R/W ;bitpos:[18:16] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007 -#define MODEM_LPCON_I2C_MST_MEM_MODE_M ((MODEM_LPCON_I2C_MST_MEM_MODE_V)<<(MODEM_LPCON_I2C_MST_MEM_MODE_S)) -#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x7 -#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 -/* MODEM_LPCON_BC_MEM_FORCE : R/W ;bitpos:[15] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_M (BIT(15)) -#define MODEM_LPCON_BC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_BC_MEM_FORCE_S 15 -/* MODEM_LPCON_BC_MEM_MODE : R/W ;bitpos:[14:12] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_BC_MEM_MODE 0x00000007 -#define MODEM_LPCON_BC_MEM_MODE_M ((MODEM_LPCON_BC_MEM_MODE_V)<<(MODEM_LPCON_BC_MEM_MODE_S)) -#define MODEM_LPCON_BC_MEM_MODE_V 0x7 -#define MODEM_LPCON_BC_MEM_MODE_S 12 -/* MODEM_LPCON_PBUS_MEM_FORCE : R/W ;bitpos:[11] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_M (BIT(11)) -#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x1 -#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 -/* MODEM_LPCON_PBUS_MEM_MODE : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007 -#define MODEM_LPCON_PBUS_MEM_MODE_M ((MODEM_LPCON_PBUS_MEM_MODE_V)<<(MODEM_LPCON_PBUS_MEM_MODE_S)) -#define MODEM_LPCON_PBUS_MEM_MODE_V 0x7 -#define MODEM_LPCON_PBUS_MEM_MODE_S 8 -/* MODEM_LPCON_AGC_MEM_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_M (BIT(7)) -#define MODEM_LPCON_AGC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_AGC_MEM_FORCE_S 7 -/* MODEM_LPCON_AGC_MEM_MODE : R/W ;bitpos:[6:4] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_MODE 0x00000007 -#define MODEM_LPCON_AGC_MEM_MODE_M ((MODEM_LPCON_AGC_MEM_MODE_V)<<(MODEM_LPCON_AGC_MEM_MODE_S)) -#define MODEM_LPCON_AGC_MEM_MODE_V 0x7 -#define MODEM_LPCON_AGC_MEM_MODE_S 4 -/* MODEM_LPCON_DC_MEM_FORCE : R/W ;bitpos:[3] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_M (BIT(3)) -#define MODEM_LPCON_DC_MEM_FORCE_V 0x1 -#define MODEM_LPCON_DC_MEM_FORCE_S 3 -/* MODEM_LPCON_DC_MEM_MODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_DC_MEM_MODE 0x00000007 -#define MODEM_LPCON_DC_MEM_MODE_M ((MODEM_LPCON_DC_MEM_MODE_V)<<(MODEM_LPCON_DC_MEM_MODE_S)) -#define MODEM_LPCON_DC_MEM_MODE_V 0x7 +/** MODEM_LPCON_MEM_CONF_REG register + * need_des + */ +#define MODEM_LPCON_MEM_CONF_REG (DR_REG_MODEM_LPCON_BASE + 0x2c) +/** MODEM_LPCON_DC_MEM_MODE : R/W; bitpos: [2:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_DC_MEM_MODE 0x00000007U +#define MODEM_LPCON_DC_MEM_MODE_M (MODEM_LPCON_DC_MEM_MODE_V << MODEM_LPCON_DC_MEM_MODE_S) +#define MODEM_LPCON_DC_MEM_MODE_V 0x00000007U #define MODEM_LPCON_DC_MEM_MODE_S 0 +/** MODEM_LPCON_DC_MEM_FORCE : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define MODEM_LPCON_DC_MEM_FORCE (BIT(3)) +#define MODEM_LPCON_DC_MEM_FORCE_M (MODEM_LPCON_DC_MEM_FORCE_V << MODEM_LPCON_DC_MEM_FORCE_S) +#define MODEM_LPCON_DC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_DC_MEM_FORCE_S 3 +/** MODEM_LPCON_AGC_MEM_MODE : R/W; bitpos: [6:4]; default: 0; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_MODE 0x00000007U +#define MODEM_LPCON_AGC_MEM_MODE_M (MODEM_LPCON_AGC_MEM_MODE_V << MODEM_LPCON_AGC_MEM_MODE_S) +#define MODEM_LPCON_AGC_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_AGC_MEM_MODE_S 4 +/** MODEM_LPCON_AGC_MEM_FORCE : R/W; bitpos: [7]; default: 1; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_FORCE (BIT(7)) +#define MODEM_LPCON_AGC_MEM_FORCE_M (MODEM_LPCON_AGC_MEM_FORCE_V << MODEM_LPCON_AGC_MEM_FORCE_S) +#define MODEM_LPCON_AGC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_FORCE_S 7 +/** MODEM_LPCON_PBUS_MEM_MODE : R/W; bitpos: [10:8]; default: 0; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_MODE 0x00000007U +#define MODEM_LPCON_PBUS_MEM_MODE_M (MODEM_LPCON_PBUS_MEM_MODE_V << MODEM_LPCON_PBUS_MEM_MODE_S) +#define MODEM_LPCON_PBUS_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_PBUS_MEM_MODE_S 8 +/** MODEM_LPCON_PBUS_MEM_FORCE : R/W; bitpos: [11]; default: 1; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_FORCE (BIT(11)) +#define MODEM_LPCON_PBUS_MEM_FORCE_M (MODEM_LPCON_PBUS_MEM_FORCE_V << MODEM_LPCON_PBUS_MEM_FORCE_S) +#define MODEM_LPCON_PBUS_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_FORCE_S 11 +/** MODEM_LPCON_BC_MEM_MODE : R/W; bitpos: [14:12]; default: 0; + * need_des + */ +#define MODEM_LPCON_BC_MEM_MODE 0x00000007U +#define MODEM_LPCON_BC_MEM_MODE_M (MODEM_LPCON_BC_MEM_MODE_V << MODEM_LPCON_BC_MEM_MODE_S) +#define MODEM_LPCON_BC_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_BC_MEM_MODE_S 12 +/** MODEM_LPCON_BC_MEM_FORCE : R/W; bitpos: [15]; default: 1; + * need_des + */ +#define MODEM_LPCON_BC_MEM_FORCE (BIT(15)) +#define MODEM_LPCON_BC_MEM_FORCE_M (MODEM_LPCON_BC_MEM_FORCE_V << MODEM_LPCON_BC_MEM_FORCE_S) +#define MODEM_LPCON_BC_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_BC_MEM_FORCE_S 15 +/** MODEM_LPCON_I2C_MST_MEM_MODE : R/W; bitpos: [18:16]; default: 0; + * need_des + */ +#define MODEM_LPCON_I2C_MST_MEM_MODE 0x00000007U +#define MODEM_LPCON_I2C_MST_MEM_MODE_M (MODEM_LPCON_I2C_MST_MEM_MODE_V << MODEM_LPCON_I2C_MST_MEM_MODE_S) +#define MODEM_LPCON_I2C_MST_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_I2C_MST_MEM_MODE_S 16 +/** MODEM_LPCON_I2C_MST_MEM_FORCE : R/W; bitpos: [19]; default: 1; + * need_des + */ +#define MODEM_LPCON_I2C_MST_MEM_FORCE (BIT(19)) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_M (MODEM_LPCON_I2C_MST_MEM_FORCE_V << MODEM_LPCON_I2C_MST_MEM_FORCE_S) +#define MODEM_LPCON_I2C_MST_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_I2C_MST_MEM_FORCE_S 19 +/** MODEM_LPCON_CHAN_FREQ_MEM_MODE : R/W; bitpos: [22:20]; default: 0; + * need_des + */ +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE 0x00000007U +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_M (MODEM_LPCON_CHAN_FREQ_MEM_MODE_V << MODEM_LPCON_CHAN_FREQ_MEM_MODE_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_V 0x00000007U +#define MODEM_LPCON_CHAN_FREQ_MEM_MODE_S 20 +/** MODEM_LPCON_CHAN_FREQ_MEM_FORCE : R/W; bitpos: [23]; default: 1; + * need_des + */ +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE (BIT(23)) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_M (MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V << MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_V 0x00000001U +#define MODEM_LPCON_CHAN_FREQ_MEM_FORCE_S 23 -#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) -/* MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_LPCON_MEM_RF1_AUX_CTRL_REG register + * need_des + */ +#define MODEM_LPCON_MEM_RF1_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x30) +/** MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL 0xFFFFFFFFU +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S) +#define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_LPCON_MODEM_PWR_RF1_AUX_CTRL_S 0 -#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) -/* MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFF -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M ((MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V)<<(MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S)) -#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_LPCON_MEM_RF2_AUX_CTRL_REG register + * need_des + */ +#define MODEM_LPCON_MEM_RF2_AUX_CTRL_REG (DR_REG_MODEM_LPCON_BASE + 0x34) +/** MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL 0xFFFFFFFFU +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_M (MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V << MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S) +#define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_LPCON_MODEM_PWR_RF2_AUX_CTRL_S 0 -#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) -/* MODEM_LPCON_AGC_MEM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_M (BIT(2)) -#define MODEM_LPCON_AGC_MEM_EN_V 0x1 -#define MODEM_LPCON_AGC_MEM_EN_S 2 -/* MODEM_LPCON_PBUS_MEM_EN : R/W ;bitpos:[1] ;default: 'b0 ; */ -/*description: .*/ -#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_M (BIT(1)) -#define MODEM_LPCON_PBUS_MEM_EN_V 0x1 -#define MODEM_LPCON_PBUS_MEM_EN_S 1 -/* MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_LPCON_APB_MEM_SEL_REG register + * need_des + */ +#define MODEM_LPCON_APB_MEM_SEL_REG (DR_REG_MODEM_LPCON_BASE + 0x38) +/** MODEM_LPCON_CHAN_FREQ_MEM_EN : R/W; bitpos: [0]; default: 0; + * need_des + */ #define MODEM_LPCON_CHAN_FREQ_MEM_EN (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (BIT(0)) -#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x1 +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_M (MODEM_LPCON_CHAN_FREQ_MEM_EN_V << MODEM_LPCON_CHAN_FREQ_MEM_EN_S) +#define MODEM_LPCON_CHAN_FREQ_MEM_EN_V 0x00000001U #define MODEM_LPCON_CHAN_FREQ_MEM_EN_S 0 +/** MODEM_LPCON_PBUS_MEM_EN : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define MODEM_LPCON_PBUS_MEM_EN (BIT(1)) +#define MODEM_LPCON_PBUS_MEM_EN_M (MODEM_LPCON_PBUS_MEM_EN_V << MODEM_LPCON_PBUS_MEM_EN_S) +#define MODEM_LPCON_PBUS_MEM_EN_V 0x00000001U +#define MODEM_LPCON_PBUS_MEM_EN_S 1 +/** MODEM_LPCON_AGC_MEM_EN : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define MODEM_LPCON_AGC_MEM_EN (BIT(2)) +#define MODEM_LPCON_AGC_MEM_EN_M (MODEM_LPCON_AGC_MEM_EN_V << MODEM_LPCON_AGC_MEM_EN_S) +#define MODEM_LPCON_AGC_MEM_EN_V 0x00000001U +#define MODEM_LPCON_AGC_MEM_EN_S 2 -#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x3C) -/* MODEM_LPCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2311220 ; */ -/*description: .*/ -#define MODEM_LPCON_DATE 0x0FFFFFFF -#define MODEM_LPCON_DATE_M ((MODEM_LPCON_DATE_V)<<(MODEM_LPCON_DATE_S)) -#define MODEM_LPCON_DATE_V 0xFFFFFFF +/** MODEM_LPCON_DCMEM_VALID_0_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_0_REG (DR_REG_MODEM_LPCON_BASE + 0x3c) +/** MODEM_LPCON__DCMEM_VALID_0 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_0 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_0_M (MODEM_LPCON__DCMEM_VALID_0_V << MODEM_LPCON__DCMEM_VALID_0_S) +#define MODEM_LPCON__DCMEM_VALID_0_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_0_S 0 + +/** MODEM_LPCON_DCMEM_VALID_1_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_1_REG (DR_REG_MODEM_LPCON_BASE + 0x40) +/** MODEM_LPCON__DCMEM_VALID_1 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_1 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_1_M (MODEM_LPCON__DCMEM_VALID_1_V << MODEM_LPCON__DCMEM_VALID_1_S) +#define MODEM_LPCON__DCMEM_VALID_1_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_1_S 0 + +/** MODEM_LPCON_DCMEM_VALID_2_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_2_REG (DR_REG_MODEM_LPCON_BASE + 0x44) +/** MODEM_LPCON__DCMEM_VALID_2 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_2 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_2_M (MODEM_LPCON__DCMEM_VALID_2_V << MODEM_LPCON__DCMEM_VALID_2_S) +#define MODEM_LPCON__DCMEM_VALID_2_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_2_S 0 + +/** MODEM_LPCON_DCMEM_VALID_3_REG register + * need_des + */ +#define MODEM_LPCON_DCMEM_VALID_3_REG (DR_REG_MODEM_LPCON_BASE + 0x48) +/** MODEM_LPCON__DCMEM_VALID_3 : RO; bitpos: [31:0]; default: 0; + * need_des + */ +#define MODEM_LPCON__DCMEM_VALID_3 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_3_M (MODEM_LPCON__DCMEM_VALID_3_V << MODEM_LPCON__DCMEM_VALID_3_S) +#define MODEM_LPCON__DCMEM_VALID_3_V 0xFFFFFFFFU +#define MODEM_LPCON__DCMEM_VALID_3_S 0 + +/** MODEM_LPCON_DATE_REG register + * need_des + */ +#define MODEM_LPCON_DATE_REG (DR_REG_MODEM_LPCON_BASE + 0x4c) +/** MODEM_LPCON_DATE : R/W; bitpos: [27:0]; default: 37814640; + * need_des + */ +#define MODEM_LPCON_DATE 0x0FFFFFFFU +#define MODEM_LPCON_DATE_M (MODEM_LPCON_DATE_V << MODEM_LPCON_DATE_S) +#define MODEM_LPCON_DATE_V 0x0FFFFFFFU #define MODEM_LPCON_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_lpcon_struct.h b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h index 6c695e5413..98d722fcf7 100644 --- a/components/soc/esp32c61/include/modem/modem_lpcon_struct.h +++ b/components/soc/esp32c61/include/modem/modem_lpcon_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,240 +10,228 @@ extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t clk_en : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 30; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t clk_lp_timer_sel_osc_slow : 1; - uint32_t clk_lp_timer_sel_osc_fast : 1; - uint32_t clk_lp_timer_sel_xtal : 1; - uint32_t clk_lp_timer_sel_xtal32k : 1; - uint32_t clk_lp_timer_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } lp_timer_conf; - union { - struct { - uint32_t clk_coex_lp_sel_osc_slow : 1; - uint32_t clk_coex_lp_sel_osc_fast : 1; - uint32_t clk_coex_lp_sel_xtal : 1; - uint32_t clk_coex_lp_sel_xtal32k : 1; - uint32_t clk_coex_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } coex_lp_clk_conf; - union { - struct { - uint32_t clk_wifipwr_lp_sel_osc_slow: 1; - uint32_t clk_wifipwr_lp_sel_osc_fast: 1; - uint32_t clk_wifipwr_lp_sel_xtal : 1; - uint32_t clk_wifipwr_lp_sel_xtal32k: 1; - uint32_t clk_wifipwr_lp_div_num : 12; - uint32_t reserved16 : 16; - }; - uint32_t val; - } wifi_lp_clk_conf; - union { - struct { - uint32_t clk_modem_aon_force : 2; - uint32_t modem_pwr_clk_src_fo : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } modem_src_clk_conf; - union { - struct { - uint32_t clk_modem_32k_sel : 2; - uint32_t reserved2 : 30; - }; - uint32_t val; - } modem_32k_clk_conf; - union { - struct { - uint32_t clk_wifipwr_en : 1; - uint32_t clk_coex_en : 1; - uint32_t clk_i2c_mst_en : 1; - uint32_t clk_lp_timer_en : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t clk_wifipwr_fo : 1; - uint32_t clk_coex_fo : 1; - uint32_t clk_i2c_mst_fo : 1; - uint32_t clk_lp_timer_fo : 1; - uint32_t clk_fe_mem_fo : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 16; - uint32_t clk_wifipwr_st_map : 4; - uint32_t clk_coex_st_map : 4; - uint32_t clk_i2c_mst_st_map : 4; - uint32_t clk_lp_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t rst_wifipwr : 1; - uint32_t rst_coex : 1; - uint32_t rst_i2c_mst : 1; - uint32_t rst_lp_timer : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t reserved8 : 1; - uint32_t reserved9 : 1; - uint32_t reserved10 : 1; - uint32_t reserved11 : 1; - uint32_t reserved12 : 1; - uint32_t reserved13 : 1; - uint32_t reserved14 : 1; - uint32_t reserved15 : 1; - uint32_t reserved16 : 1; - uint32_t reserved17 : 1; - uint32_t reserved18 : 1; - uint32_t reserved19 : 1; - uint32_t reserved20 : 1; - uint32_t reserved21 : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } rst_conf; - union { - struct { - uint32_t modem_pwr_tick_target : 6; - uint32_t reserved6 : 26; - }; - uint32_t val; - } tick_conf; - union { - struct { - uint32_t dc_mem_mode : 3; - uint32_t dc_mem_force : 1; - uint32_t agc_mem_mode : 3; - uint32_t agc_mem_force : 1; - uint32_t pbus_mem_mode : 3; - uint32_t pbus_mem_force : 1; - uint32_t bc_mem_mode : 3; - uint32_t bc_mem_force : 1; - uint32_t i2c_mst_mem_mode : 3; - uint32_t i2c_mst_mem_force : 1; - uint32_t chan_freq_mem_mode : 3; - uint32_t chan_freq_mem_force : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t reserved28 : 1; - uint32_t reserved29 : 1; - uint32_t reserved30 : 1; - uint32_t reserved31 : 1; - }; - uint32_t val; - } mem_conf; - uint32_t mem_rf1_aux_ctrl; - uint32_t mem_rf2_aux_ctrl; - union { - struct { - uint32_t chan_freq_mem_en : 1; - uint32_t pbus_mem_en : 1; - uint32_t agc_mem_en : 1; - uint32_t reserved3 : 29; - }; - uint32_t val; - } apb_mem_sel; - union { - struct { - uint32_t date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; +/** Group: configure_register */ +typedef union { + struct { + uint32_t clk_en: 1; + uint32_t reserved_1: 31; + }; + uint32_t val; +} modem_lpcon_test_conf_t; + +typedef union { + struct { + uint32_t clk_lp_timer_sel_osc_slow: 1; + uint32_t clk_lp_timer_sel_osc_fast: 1; + uint32_t clk_lp_timer_sel_xtal: 1; + uint32_t clk_lp_timer_sel_xtal32k: 1; + uint32_t clk_lp_timer_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_lp_timer_conf_t; + +typedef union { + struct { + uint32_t clk_coex_lp_sel_osc_slow: 1; + uint32_t clk_coex_lp_sel_osc_fast: 1; + uint32_t clk_coex_lp_sel_xtal: 1; + uint32_t clk_coex_lp_sel_xtal32k: 1; + uint32_t clk_coex_lp_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_coex_lp_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_lp_sel_osc_slow: 1; + uint32_t clk_wifipwr_lp_sel_osc_fast: 1; + uint32_t clk_wifipwr_lp_sel_xtal: 1; + uint32_t clk_wifipwr_lp_sel_xtal32k: 1; + uint32_t clk_wifipwr_lp_div_num: 12; + uint32_t reserved_16: 16; + }; + uint32_t val; +} modem_lpcon_wifi_lp_clk_conf_t; + +typedef union { + struct { + uint32_t clk_modem_aon_force: 2; + uint32_t modem_pwr_clk_src_fo: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} modem_lpcon_modem_src_clk_conf_t; + +typedef union { + struct { + uint32_t clk_modem_32k_sel: 2; + uint32_t reserved_2: 30; + }; + uint32_t val; +} modem_lpcon_modem_32k_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_en: 1; + uint32_t clk_coex_en: 1; + uint32_t clk_i2c_mst_en: 1; + uint32_t clk_lp_timer_en: 1; + uint32_t reserved_4: 28; + }; + uint32_t val; +} modem_lpcon_clk_conf_t; + +typedef union { + struct { + uint32_t clk_wifipwr_fo: 1; + uint32_t clk_coex_fo: 1; + uint32_t clk_i2c_mst_fo: 1; + uint32_t clk_lp_timer_fo: 1; + uint32_t clk_fe_mem_fo: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} modem_lpcon_clk_conf_force_on_t; + +typedef union { + struct { + uint32_t reserved_0: 16; + uint32_t clk_wifipwr_st_map: 4; + uint32_t clk_coex_st_map: 4; + uint32_t clk_i2c_mst_st_map: 4; + uint32_t clk_lp_apb_st_map: 4; + }; + uint32_t val; +} modem_lpcon_clk_conf_power_st_t; + +typedef union { + struct { + uint32_t rst_wifipwr: 1; + uint32_t rst_coex: 1; + uint32_t rst_i2c_mst: 1; + uint32_t rst_lp_timer: 1; + uint32_t rst_dcmem: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} modem_lpcon_rst_conf_t; + +typedef union { + struct { + uint32_t modem_pwr_tick_target: 6; + uint32_t reserved_6: 26; + }; + uint32_t val; +} modem_lpcon_tick_conf_t; + +typedef union { + struct { + uint32_t dc_mem_mode: 3; + uint32_t dc_mem_force: 1; + uint32_t agc_mem_mode: 3; + uint32_t agc_mem_force: 1; + uint32_t pbus_mem_mode: 3; + uint32_t pbus_mem_force: 1; + uint32_t bc_mem_mode: 3; + uint32_t bc_mem_force: 1; + uint32_t i2c_mst_mem_mode: 3; + uint32_t i2c_mst_mem_force: 1; + uint32_t chan_freq_mem_mode: 3; + uint32_t chan_freq_mem_force: 1; + uint32_t reserved_24: 8; + }; + uint32_t val; +} modem_lpcon_mem_conf_t; + +typedef union { + struct { + uint32_t modem_pwr_rf1_aux_ctrl: 32; + }; + uint32_t val; +} modem_lpcon_mem_rf1_aux_ctrl_t; + +typedef union { + struct { + uint32_t modem_pwr_rf2_aux_ctrl: 32; + }; + uint32_t val; +} modem_lpcon_mem_rf2_aux_ctrl_t; + +typedef union { + struct { + uint32_t chan_freq_mem_en: 1; + uint32_t pbus_mem_en: 1; + uint32_t agc_mem_en: 1; + uint32_t reserved_3: 29; + }; + uint32_t val; +} modem_lpcon_apb_mem_sel_t; + +typedef union { + struct { + uint32_t _dcmem_valid_0: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_0_t; + +typedef union { + struct { + uint32_t _dcmem_valid_1: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_1_t; + +typedef union { + struct { + uint32_t _dcmem_valid_2: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_2_t; + +typedef union { + struct { + uint32_t _dcmem_valid_3: 32; + }; + uint32_t val; +} modem_lpcon_dcmem_valid_3_t; + +typedef union { + struct { + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} modem_lpcon_date_t; + +typedef struct { + volatile modem_lpcon_test_conf_t test_conf; + volatile modem_lpcon_lp_timer_conf_t lp_timer_conf; + volatile modem_lpcon_coex_lp_clk_conf_t coex_lp_clk_conf; + volatile modem_lpcon_wifi_lp_clk_conf_t wifi_lp_clk_conf; + volatile modem_lpcon_modem_src_clk_conf_t modem_src_clk_conf; + volatile modem_lpcon_modem_32k_clk_conf_t modem_32k_clk_conf; + volatile modem_lpcon_clk_conf_t clk_conf; + volatile modem_lpcon_clk_conf_force_on_t clk_conf_force_on; + volatile modem_lpcon_clk_conf_power_st_t clk_conf_power_st; + volatile modem_lpcon_rst_conf_t rst_conf; + volatile modem_lpcon_tick_conf_t tick_conf; + volatile modem_lpcon_mem_conf_t mem_conf; + volatile modem_lpcon_mem_rf1_aux_ctrl_t mem_rf1_aux_ctrl; + volatile modem_lpcon_mem_rf2_aux_ctrl_t mem_rf2_aux_ctrl; + volatile modem_lpcon_apb_mem_sel_t apb_mem_sel; + volatile modem_lpcon_dcmem_valid_0_t dcmem_valid_0; + volatile modem_lpcon_dcmem_valid_1_t dcmem_valid_1; + volatile modem_lpcon_dcmem_valid_2_t dcmem_valid_2; + volatile modem_lpcon_dcmem_valid_3_t dcmem_valid_3; + volatile modem_lpcon_date_t date; } modem_lpcon_dev_t; extern modem_lpcon_dev_t MODEM_LPCON; #ifndef __cplusplus -_Static_assert(sizeof(modem_lpcon_dev_t) == 0x40, "Invalid size of modem_lpcon_dev_t structure"); +_Static_assert(sizeof(modem_lpcon_dev_t) == 0x50, "Invalid size of modem_lpcon_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_syscon_reg.h b/components/soc/esp32c61/include/modem/modem_syscon_reg.h index bf811fff09..f94698d8e7 100644 --- a/components/soc/esp32c61/include/modem/modem_syscon_reg.h +++ b/components/soc/esp32c61/include/modem/modem_syscon_reg.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -11,582 +11,507 @@ extern "C" { #endif -#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) -/* MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (BIT(9)) -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 -/* MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W ;bitpos:[8] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (BIT(8)) -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x1 -#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 -/* MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (BIT(7)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 -/* MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (BIT(6)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 -/* MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (BIT(5)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 -/* MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (BIT(4)) -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 -/* MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (BIT(3)) -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x1 -#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (BIT(2)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 -/* MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (BIT(1)) -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x1 -#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 -/* MODEM_SYSCON_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_TEST_CONF_REG register **/ +#define MODEM_SYSCON_TEST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x0) +/** MODEM_SYSCON_CLK_EN : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_EN (BIT(0)) -#define MODEM_SYSCON_CLK_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_EN_V 0x1 +#define MODEM_SYSCON_CLK_EN_M (MODEM_SYSCON_CLK_EN_V << MODEM_SYSCON_CLK_EN_S) +#define MODEM_SYSCON_CLK_EN_V 0x00000001U #define MODEM_SYSCON_CLK_EN_S 0 +/** MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT (BIT(1)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_M (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_V 0x00000001U +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_BT_S 1 +/** MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI (BIT(2)) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_M (MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V << MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S) +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_V 0x00000001U +#define MODEM_SYSCON_MODEM_ANT_FORCE_SEL_WIFI_S 2 +/** MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH (BIT(3)) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_M (MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V << MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLKSWITCH_S 3 +/** MODEM_SYSCON_FPGA_DEBUG_CLK80 : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK80 (BIT(4)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_M (MODEM_SYSCON_FPGA_DEBUG_CLK80_V << MODEM_SYSCON_FPGA_DEBUG_CLK80_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK80_S 4 +/** MODEM_SYSCON_FPGA_DEBUG_CLK40 : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK40 (BIT(5)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_M (MODEM_SYSCON_FPGA_DEBUG_CLK40_V << MODEM_SYSCON_FPGA_DEBUG_CLK40_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK40_S 5 +/** MODEM_SYSCON_FPGA_DEBUG_CLK20 : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK20 (BIT(6)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_M (MODEM_SYSCON_FPGA_DEBUG_CLK20_V << MODEM_SYSCON_FPGA_DEBUG_CLK20_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK20_S 6 +/** MODEM_SYSCON_FPGA_DEBUG_CLK10 : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_FPGA_DEBUG_CLK10 (BIT(7)) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_M (MODEM_SYSCON_FPGA_DEBUG_CLK10_V << MODEM_SYSCON_FPGA_DEBUG_CLK10_S) +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_V 0x00000001U +#define MODEM_SYSCON_FPGA_DEBUG_CLK10_S 7 +/** MODEM_SYSCON_MODEM_MEM_MODE_FORCE : R/W; bitpos: [8]; default: 1; **/ +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE (BIT(8)) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_M (MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V << MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S) +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_V 0x00000001U +#define MODEM_SYSCON_MODEM_MEM_MODE_FORCE_S 8 +/** MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE (BIT(9)) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_M (MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V << MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S) +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_V 0x00000001U +#define MODEM_SYSCON_MODEM_DIS_WIFI6_FORCE_S 9 -#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) -/* MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 -/* MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (BIT(28)) -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 -/* MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (BIT(27)) -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 -/* MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (BIT(26)) -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 -/* MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (BIT(25)) -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 -/* MODEM_SYSCON_CLK_ZBMAC_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_M (BIT(24)) -#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 -/* MODEM_SYSCON_CLK_ZB_APB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_M (BIT(23)) -#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 -/* MODEM_SYSCON_CLK_ETM_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_M (BIT(22)) -#define MODEM_SYSCON_CLK_ETM_EN_V 0x1 -#define MODEM_SYSCON_CLK_ETM_EN_S 22 -/* MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (BIT(21)) -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 -/* MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (BIT(12)) -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x1 -#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 -/* MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (BIT(11)) -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 -/* MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (BIT(10)) -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 -/* MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (BIT(9)) -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x1 -#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 -/* MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W ;bitpos:[8:1] ;default: 8'd1 ; */ -/*description: .*/ -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M ((MODEM_SYSCON_PWDET_CLK_DIV_NUM_V)<<(MODEM_SYSCON_PWDET_CLK_DIV_NUM_S)) -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0xFF -#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 -/* MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF_REG register **/ +#define MODEM_SYSCON_CLK_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x4) +/** MODEM_SYSCON_PWDET_SAR_CLOCK_ENA : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (BIT(0)) -#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x1 +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_M (MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V << MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S) +#define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_V 0x00000001U #define MODEM_SYSCON_PWDET_SAR_CLOCK_ENA_S 0 +/** MODEM_SYSCON_PWDET_CLK_DIV_NUM : R/W; bitpos: [8:1]; default: 1; **/ +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM 0x000000FFU +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_M (MODEM_SYSCON_PWDET_CLK_DIV_NUM_V << MODEM_SYSCON_PWDET_CLK_DIV_NUM_S) +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_V 0x000000FFU +#define MODEM_SYSCON_PWDET_CLK_DIV_NUM_S 1 +/** MODEM_SYSCON_CLK_TX_DAC_INV_ENA : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA (BIT(9)) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_M (MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V << MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S) +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_TX_DAC_INV_ENA_S 9 +/** MODEM_SYSCON_CLK_RX_ADC_INV_ENA : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA (BIT(10)) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_M (MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V << MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S) +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_RX_ADC_INV_ENA_S 10 +/** MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA (BIT(11)) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_M (MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V << MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S) +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_V 0x00000001U +#define MODEM_SYSCON_CLK_PWDET_ADC_INV_ENA_S 11 +/** MODEM_SYSCON_CLK_I2C_MST_SEL_160M : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M (BIT(12)) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_M (MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V << MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S) +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_V 0x00000001U +#define MODEM_SYSCON_CLK_I2C_MST_SEL_160M_S 12 +/** MODEM_SYSCON_CLK_DATA_DUMP_MUX : R/W; bitpos: [21]; default: 1; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX (BIT(21)) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_M (MODEM_SYSCON_CLK_DATA_DUMP_MUX_V << MODEM_SYSCON_CLK_DATA_DUMP_MUX_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_MUX_S 21 +/** MODEM_SYSCON_CLK_ETM_EN : R/W; bitpos: [22]; default: 0; **/ +#define MODEM_SYSCON_CLK_ETM_EN (BIT(22)) +#define MODEM_SYSCON_CLK_ETM_EN_M (MODEM_SYSCON_CLK_ETM_EN_V << MODEM_SYSCON_CLK_ETM_EN_S) +#define MODEM_SYSCON_CLK_ETM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_EN_S 22 +/** MODEM_SYSCON_CLK_ZB_APB_EN : R/W; bitpos: [23]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZB_APB_EN (BIT(23)) +#define MODEM_SYSCON_CLK_ZB_APB_EN_M (MODEM_SYSCON_CLK_ZB_APB_EN_V << MODEM_SYSCON_CLK_ZB_APB_EN_S) +#define MODEM_SYSCON_CLK_ZB_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZB_APB_EN_S 23 +/** MODEM_SYSCON_CLK_ZBMAC_EN : R/W; bitpos: [24]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_EN (BIT(24)) +#define MODEM_SYSCON_CLK_ZBMAC_EN_M (MODEM_SYSCON_CLK_ZBMAC_EN_V << MODEM_SYSCON_CLK_ZBMAC_EN_S) +#define MODEM_SYSCON_CLK_ZBMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_EN_S 24 +/** MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN : R/W; bitpos: [25]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN (BIT(25)) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_ECB_EN_S 25 +/** MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN : R/W; bitpos: [26]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN (BIT(26)) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_CCM_EN_S 26 +/** MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN : R/W; bitpos: [27]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN (BIT(27)) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_BAH_EN_S 27 +/** MODEM_SYSCON_CLK_MODEM_SEC_APB_EN : R/W; bitpos: [28]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN (BIT(28)) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_APB_EN_S 28 +/** MODEM_SYSCON_CLK_MODEM_SEC_EN : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_EN (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_M (MODEM_SYSCON_CLK_MODEM_SEC_EN_V << MODEM_SYSCON_CLK_MODEM_SEC_EN_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_EN_S 29 +/** MODEM_SYSCON_CLK_BLE_TIMER_EN : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_CLK_BLE_TIMER_EN (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_M (MODEM_SYSCON_CLK_BLE_TIMER_EN_V << MODEM_SYSCON_CLK_BLE_TIMER_EN_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_EN_S 30 +/** MODEM_SYSCON_CLK_DATA_DUMP_EN : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_EN (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_M (MODEM_SYSCON_CLK_DATA_DUMP_EN_V << MODEM_SYSCON_CLK_DATA_DUMP_EN_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_EN_S 31 -#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) -/* MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (BIT(31)) -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x1 -#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -/* MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (BIT(30)) -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x1 -#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 -/* MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (BIT(29)) -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x1 -#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 -/* MODEM_SYSCON_CLK_ETM_FO : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_M (BIT(28)) -#define MODEM_SYSCON_CLK_ETM_FO_V 0x1 -#define MODEM_SYSCON_CLK_ETM_FO_S 28 -/* MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (BIT(9)) -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 -/* MODEM_SYSCON_CLK_ZBMAC_FO : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_M (BIT(8)) -#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 -/* MODEM_SYSCON_CLK_BT_APB_FO : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_M (BIT(7)) -#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 -/* MODEM_SYSCON_CLK_BTMAC_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_M (BIT(6)) -#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 -/* MODEM_SYSCON_CLK_BTBB_FO : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_M (BIT(5)) -#define MODEM_SYSCON_CLK_BTBB_FO_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_FO_S 5 -/* MODEM_SYSCON_CLK_FE_APB_FO : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_M (BIT(4)) -#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 -/* MODEM_SYSCON_CLK_FE_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_M (BIT(3)) -#define MODEM_SYSCON_CLK_FE_FO_V 0x1 -#define MODEM_SYSCON_CLK_FE_FO_S 3 -/* MODEM_SYSCON_CLK_WIFI_APB_FO : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 -/* MODEM_SYSCON_CLK_WIFIMAC_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF_FORCE_ON_REG register **/ +#define MODEM_SYSCON_CLK_CONF_FORCE_ON_REG (DR_REG_MODEM_SYSCON_BASE + 0x8) +/** MODEM_SYSCON_CLK_WIFIBB_FO : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_WIFIBB_FO (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_FO_M (MODEM_SYSCON_CLK_WIFIBB_FO_V << MODEM_SYSCON_CLK_WIFIBB_FO_S) +#define MODEM_SYSCON_CLK_WIFIBB_FO_V 0x00000001U #define MODEM_SYSCON_CLK_WIFIBB_FO_S 0 +/** MODEM_SYSCON_CLK_WIFIMAC_FO : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIMAC_FO (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_M (MODEM_SYSCON_CLK_WIFIMAC_FO_V << MODEM_SYSCON_CLK_WIFIMAC_FO_S) +#define MODEM_SYSCON_CLK_WIFIMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_FO_S 1 +/** MODEM_SYSCON_CLK_WIFI_APB_FO : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_APB_FO (BIT(2)) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_M (MODEM_SYSCON_CLK_WIFI_APB_FO_V << MODEM_SYSCON_CLK_WIFI_APB_FO_S) +#define MODEM_SYSCON_CLK_WIFI_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_FO_S 2 +/** MODEM_SYSCON_CLK_FE_FO : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_FO (BIT(3)) +#define MODEM_SYSCON_CLK_FE_FO_M (MODEM_SYSCON_CLK_FE_FO_V << MODEM_SYSCON_CLK_FE_FO_S) +#define MODEM_SYSCON_CLK_FE_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_FO_S 3 +/** MODEM_SYSCON_CLK_FE_APB_FO : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_APB_FO (BIT(4)) +#define MODEM_SYSCON_CLK_FE_APB_FO_M (MODEM_SYSCON_CLK_FE_APB_FO_V << MODEM_SYSCON_CLK_FE_APB_FO_S) +#define MODEM_SYSCON_CLK_FE_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_FO_S 4 +/** MODEM_SYSCON_CLK_BTBB_FO : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTBB_FO (BIT(5)) +#define MODEM_SYSCON_CLK_BTBB_FO_M (MODEM_SYSCON_CLK_BTBB_FO_V << MODEM_SYSCON_CLK_BTBB_FO_S) +#define MODEM_SYSCON_CLK_BTBB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BTBB_FO_S 5 +/** MODEM_SYSCON_CLK_BTMAC_FO : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTMAC_FO (BIT(6)) +#define MODEM_SYSCON_CLK_BTMAC_FO_M (MODEM_SYSCON_CLK_BTMAC_FO_V << MODEM_SYSCON_CLK_BTMAC_FO_S) +#define MODEM_SYSCON_CLK_BTMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BTMAC_FO_S 6 +/** MODEM_SYSCON_CLK_BT_APB_FO : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_APB_FO (BIT(7)) +#define MODEM_SYSCON_CLK_BT_APB_FO_M (MODEM_SYSCON_CLK_BT_APB_FO_V << MODEM_SYSCON_CLK_BT_APB_FO_S) +#define MODEM_SYSCON_CLK_BT_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_FO_S 7 +/** MODEM_SYSCON_CLK_ZBMAC_FO : R/W; bitpos: [8]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_FO (BIT(8)) +#define MODEM_SYSCON_CLK_ZBMAC_FO_M (MODEM_SYSCON_CLK_ZBMAC_FO_V << MODEM_SYSCON_CLK_ZBMAC_FO_S) +#define MODEM_SYSCON_CLK_ZBMAC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_FO_S 8 +/** MODEM_SYSCON_CLK_ZBMAC_APB_FO : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO (BIT(9)) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_M (MODEM_SYSCON_CLK_ZBMAC_APB_FO_V << MODEM_SYSCON_CLK_ZBMAC_APB_FO_S) +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ZBMAC_APB_FO_S 9 +/** MODEM_SYSCON_CLK_ETM_FO : R/W; bitpos: [28]; default: 0; **/ +#define MODEM_SYSCON_CLK_ETM_FO (BIT(28)) +#define MODEM_SYSCON_CLK_ETM_FO_M (MODEM_SYSCON_CLK_ETM_FO_V << MODEM_SYSCON_CLK_ETM_FO_S) +#define MODEM_SYSCON_CLK_ETM_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_ETM_FO_S 28 +/** MODEM_SYSCON_CLK_MODEM_SEC_FO : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_SEC_FO (BIT(29)) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_M (MODEM_SYSCON_CLK_MODEM_SEC_FO_V << MODEM_SYSCON_CLK_MODEM_SEC_FO_S) +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_MODEM_SEC_FO_S 29 +/** MODEM_SYSCON_CLK_BLE_TIMER_FO : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_CLK_BLE_TIMER_FO (BIT(30)) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_M (MODEM_SYSCON_CLK_BLE_TIMER_FO_V << MODEM_SYSCON_CLK_BLE_TIMER_FO_S) +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_BLE_TIMER_FO_S 30 +/** MODEM_SYSCON_CLK_DATA_DUMP_FO : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_CLK_DATA_DUMP_FO (BIT(31)) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_M (MODEM_SYSCON_CLK_DATA_DUMP_FO_V << MODEM_SYSCON_CLK_DATA_DUMP_FO_S) +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_V 0x00000001U +#define MODEM_SYSCON_CLK_DATA_DUMP_FO_S 31 -#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xC) -/* MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -/* MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W ;bitpos:[27:24] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M ((MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V)<<(MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 -/* MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M ((MODEM_SYSCON_CLK_WIFI_ST_MAP_V)<<(MODEM_SYSCON_CLK_WIFI_ST_MAP_S)) -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 -/* MODEM_SYSCON_CLK_BT_ST_MAP : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_BT_ST_MAP_M ((MODEM_SYSCON_CLK_BT_ST_MAP_V)<<(MODEM_SYSCON_CLK_BT_ST_MAP_S)) -#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 -/* MODEM_SYSCON_CLK_FE_ST_MAP : R/W ;bitpos:[15:12] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_FE_ST_MAP_M ((MODEM_SYSCON_CLK_FE_ST_MAP_V)<<(MODEM_SYSCON_CLK_FE_ST_MAP_S)) -#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0xF -#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 -/* MODEM_SYSCON_CLK_ZB_ST_MAP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000F -#define MODEM_SYSCON_CLK_ZB_ST_MAP_M ((MODEM_SYSCON_CLK_ZB_ST_MAP_V)<<(MODEM_SYSCON_CLK_ZB_ST_MAP_S)) -#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0xF +/** MODEM_SYSCON_CLK_CONF_POWER_ST_REG register **/ +#define MODEM_SYSCON_CLK_CONF_POWER_ST_REG (DR_REG_MODEM_SYSCON_BASE + 0xc) +/** MODEM_SYSCON_CLK_ZB_ST_MAP : R/W; bitpos: [11:8]; default: 0; **/ +#define MODEM_SYSCON_CLK_ZB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_ZB_ST_MAP_M (MODEM_SYSCON_CLK_ZB_ST_MAP_V << MODEM_SYSCON_CLK_ZB_ST_MAP_S) +#define MODEM_SYSCON_CLK_ZB_ST_MAP_V 0x0000000FU #define MODEM_SYSCON_CLK_ZB_ST_MAP_S 8 +/** MODEM_SYSCON_CLK_FE_ST_MAP : R/W; bitpos: [15:12]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_M (MODEM_SYSCON_CLK_FE_ST_MAP_V << MODEM_SYSCON_CLK_FE_ST_MAP_S) +#define MODEM_SYSCON_CLK_FE_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_FE_ST_MAP_S 12 +/** MODEM_SYSCON_CLK_BT_ST_MAP : R/W; bitpos: [19:16]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_M (MODEM_SYSCON_CLK_BT_ST_MAP_V << MODEM_SYSCON_CLK_BT_ST_MAP_S) +#define MODEM_SYSCON_CLK_BT_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_BT_ST_MAP_S 16 +/** MODEM_SYSCON_CLK_WIFI_ST_MAP : R/W; bitpos: [23:20]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_M (MODEM_SYSCON_CLK_WIFI_ST_MAP_V << MODEM_SYSCON_CLK_WIFI_ST_MAP_S) +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_WIFI_ST_MAP_S 20 +/** MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP : R/W; bitpos: [27:24]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_PERI_ST_MAP_S 24 +/** MODEM_SYSCON_CLK_MODEM_APB_ST_MAP : R/W; bitpos: [31:28]; default: 0; **/ +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_M (MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V << MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S) +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_V 0x0000000FU +#define MODEM_SYSCON_CLK_MODEM_APB_ST_MAP_S 28 -#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) -/* MODEM_SYSCON_RST_DATA_DUMP : R/W ;bitpos:[31] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_M (BIT(31)) -#define MODEM_SYSCON_RST_DATA_DUMP_V 0x1 -#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -/* MODEM_SYSCON_RST_BLE_TIMER : R/W ;bitpos:[30] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_M (BIT(30)) -#define MODEM_SYSCON_RST_BLE_TIMER_V 0x1 -#define MODEM_SYSCON_RST_BLE_TIMER_S 30 -/* MODEM_SYSCON_RST_MODEM_SEC : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_M (BIT(29)) -#define MODEM_SYSCON_RST_MODEM_SEC_V 0x1 -#define MODEM_SYSCON_RST_MODEM_SEC_S 29 -/* MODEM_SYSCON_RST_MODEM_BAH : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_M (BIT(27)) -#define MODEM_SYSCON_RST_MODEM_BAH_V 0x1 -#define MODEM_SYSCON_RST_MODEM_BAH_S 27 -/* MODEM_SYSCON_RST_MODEM_CCM : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_M (BIT(26)) -#define MODEM_SYSCON_RST_MODEM_CCM_V 0x1 -#define MODEM_SYSCON_RST_MODEM_CCM_S 26 -/* MODEM_SYSCON_RST_MODEM_ECB : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_M (BIT(25)) -#define MODEM_SYSCON_RST_MODEM_ECB_V 0x1 -#define MODEM_SYSCON_RST_MODEM_ECB_S 25 -/* MODEM_SYSCON_RST_ZBMAC : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_M (BIT(24)) -#define MODEM_SYSCON_RST_ZBMAC_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_S 24 -/* MODEM_SYSCON_RST_ZBMAC_APB : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_M (BIT(23)) -#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 -/* MODEM_SYSCON_RST_ETM : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_ETM (BIT(22)) -#define MODEM_SYSCON_RST_ETM_M (BIT(22)) -#define MODEM_SYSCON_RST_ETM_V 0x1 -#define MODEM_SYSCON_RST_ETM_S 22 -/* MODEM_SYSCON_RST_BTBB : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_M (BIT(18)) -#define MODEM_SYSCON_RST_BTBB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_S 18 -/* MODEM_SYSCON_RST_BTBB_APB : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_M (BIT(17)) -#define MODEM_SYSCON_RST_BTBB_APB_V 0x1 -#define MODEM_SYSCON_RST_BTBB_APB_S 17 -/* MODEM_SYSCON_RST_BTMAC : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_M (BIT(16)) -#define MODEM_SYSCON_RST_BTMAC_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_S 16 -/* MODEM_SYSCON_RST_BTMAC_APB : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_M (BIT(15)) -#define MODEM_SYSCON_RST_BTMAC_APB_V 0x1 -#define MODEM_SYSCON_RST_BTMAC_APB_S 15 -/* MODEM_SYSCON_RST_FE : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE (BIT(14)) -#define MODEM_SYSCON_RST_FE_M (BIT(14)) -#define MODEM_SYSCON_RST_FE_V 0x1 -#define MODEM_SYSCON_RST_FE_S 14 -/* MODEM_SYSCON_RST_FE_AHB : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_M (BIT(13)) -#define MODEM_SYSCON_RST_FE_AHB_V 0x1 -#define MODEM_SYSCON_RST_FE_AHB_S 13 -/* MODEM_SYSCON_RST_FE_ADC : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_M (BIT(12)) -#define MODEM_SYSCON_RST_FE_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_ADC_S 12 -/* MODEM_SYSCON_RST_FE_DAC : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_M (BIT(11)) -#define MODEM_SYSCON_RST_FE_DAC_V 0x1 -#define MODEM_SYSCON_RST_FE_DAC_S 11 -/* MODEM_SYSCON_RST_FE_PWDET_ADC : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (BIT(10)) -#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x1 -#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 -/* MODEM_SYSCON_RST_WIFIMAC : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_M (BIT(9)) -#define MODEM_SYSCON_RST_WIFIMAC_V 0x1 -#define MODEM_SYSCON_RST_WIFIMAC_S 9 -/* MODEM_SYSCON_RST_WIFIBB : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_MODEM_RST_CONF_REG register **/ +#define MODEM_SYSCON_MODEM_RST_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x10) +/** MODEM_SYSCON_RST_WIFIBB : R/W; bitpos: [8]; default: 0; **/ #define MODEM_SYSCON_RST_WIFIBB (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_M (BIT(8)) -#define MODEM_SYSCON_RST_WIFIBB_V 0x1 +#define MODEM_SYSCON_RST_WIFIBB_M (MODEM_SYSCON_RST_WIFIBB_V << MODEM_SYSCON_RST_WIFIBB_S) +#define MODEM_SYSCON_RST_WIFIBB_V 0x00000001U #define MODEM_SYSCON_RST_WIFIBB_S 8 +/** MODEM_SYSCON_RST_WIFIMAC : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_RST_WIFIMAC (BIT(9)) +#define MODEM_SYSCON_RST_WIFIMAC_M (MODEM_SYSCON_RST_WIFIMAC_V << MODEM_SYSCON_RST_WIFIMAC_S) +#define MODEM_SYSCON_RST_WIFIMAC_V 0x00000001U +#define MODEM_SYSCON_RST_WIFIMAC_S 9 +/** MODEM_SYSCON_RST_FE_PWDET_ADC : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_PWDET_ADC (BIT(10)) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_M (MODEM_SYSCON_RST_FE_PWDET_ADC_V << MODEM_SYSCON_RST_FE_PWDET_ADC_S) +#define MODEM_SYSCON_RST_FE_PWDET_ADC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_PWDET_ADC_S 10 +/** MODEM_SYSCON_RST_FE_DAC : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_DAC (BIT(11)) +#define MODEM_SYSCON_RST_FE_DAC_M (MODEM_SYSCON_RST_FE_DAC_V << MODEM_SYSCON_RST_FE_DAC_S) +#define MODEM_SYSCON_RST_FE_DAC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_DAC_S 11 +/** MODEM_SYSCON_RST_FE_ADC : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_ADC (BIT(12)) +#define MODEM_SYSCON_RST_FE_ADC_M (MODEM_SYSCON_RST_FE_ADC_V << MODEM_SYSCON_RST_FE_ADC_S) +#define MODEM_SYSCON_RST_FE_ADC_V 0x00000001U +#define MODEM_SYSCON_RST_FE_ADC_S 12 +/** MODEM_SYSCON_RST_FE_AHB : R/W; bitpos: [13]; default: 0; **/ +#define MODEM_SYSCON_RST_FE_AHB (BIT(13)) +#define MODEM_SYSCON_RST_FE_AHB_M (MODEM_SYSCON_RST_FE_AHB_V << MODEM_SYSCON_RST_FE_AHB_S) +#define MODEM_SYSCON_RST_FE_AHB_V 0x00000001U +#define MODEM_SYSCON_RST_FE_AHB_S 13 +/** MODEM_SYSCON_RST_FE : R/W; bitpos: [14]; default: 0; **/ +#define MODEM_SYSCON_RST_FE (BIT(14)) +#define MODEM_SYSCON_RST_FE_M (MODEM_SYSCON_RST_FE_V << MODEM_SYSCON_RST_FE_S) +#define MODEM_SYSCON_RST_FE_V 0x00000001U +#define MODEM_SYSCON_RST_FE_S 14 +/** MODEM_SYSCON_RST_BTMAC_APB : R/W; bitpos: [15]; default: 0; **/ +#define MODEM_SYSCON_RST_BTMAC_APB (BIT(15)) +#define MODEM_SYSCON_RST_BTMAC_APB_M (MODEM_SYSCON_RST_BTMAC_APB_V << MODEM_SYSCON_RST_BTMAC_APB_S) +#define MODEM_SYSCON_RST_BTMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_APB_S 15 +/** MODEM_SYSCON_RST_BTMAC : R/W; bitpos: [16]; default: 0; **/ +#define MODEM_SYSCON_RST_BTMAC (BIT(16)) +#define MODEM_SYSCON_RST_BTMAC_M (MODEM_SYSCON_RST_BTMAC_V << MODEM_SYSCON_RST_BTMAC_S) +#define MODEM_SYSCON_RST_BTMAC_V 0x00000001U +#define MODEM_SYSCON_RST_BTMAC_S 16 +/** MODEM_SYSCON_RST_BTBB_APB : R/W; bitpos: [17]; default: 0; **/ +#define MODEM_SYSCON_RST_BTBB_APB (BIT(17)) +#define MODEM_SYSCON_RST_BTBB_APB_M (MODEM_SYSCON_RST_BTBB_APB_V << MODEM_SYSCON_RST_BTBB_APB_S) +#define MODEM_SYSCON_RST_BTBB_APB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_APB_S 17 +/** MODEM_SYSCON_RST_BTBB : R/W; bitpos: [18]; default: 0; **/ +#define MODEM_SYSCON_RST_BTBB (BIT(18)) +#define MODEM_SYSCON_RST_BTBB_M (MODEM_SYSCON_RST_BTBB_V << MODEM_SYSCON_RST_BTBB_S) +#define MODEM_SYSCON_RST_BTBB_V 0x00000001U +#define MODEM_SYSCON_RST_BTBB_S 18 +/** MODEM_SYSCON_RST_ETM : R/W; bitpos: [22]; default: 0; **/ +#define MODEM_SYSCON_RST_ETM (BIT(22)) +#define MODEM_SYSCON_RST_ETM_M (MODEM_SYSCON_RST_ETM_V << MODEM_SYSCON_RST_ETM_S) +#define MODEM_SYSCON_RST_ETM_V 0x00000001U +#define MODEM_SYSCON_RST_ETM_S 22 +/** MODEM_SYSCON_RST_ZBMAC_APB : R/W; bitpos: [23]; default: 0; **/ +#define MODEM_SYSCON_RST_ZBMAC_APB (BIT(23)) +#define MODEM_SYSCON_RST_ZBMAC_APB_M (MODEM_SYSCON_RST_ZBMAC_APB_V << MODEM_SYSCON_RST_ZBMAC_APB_S) +#define MODEM_SYSCON_RST_ZBMAC_APB_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_APB_S 23 +/** MODEM_SYSCON_RST_ZBMAC : R/W; bitpos: [24]; default: 0; **/ +#define MODEM_SYSCON_RST_ZBMAC (BIT(24)) +#define MODEM_SYSCON_RST_ZBMAC_M (MODEM_SYSCON_RST_ZBMAC_V << MODEM_SYSCON_RST_ZBMAC_S) +#define MODEM_SYSCON_RST_ZBMAC_V 0x00000001U +#define MODEM_SYSCON_RST_ZBMAC_S 24 +/** MODEM_SYSCON_RST_MODEM_ECB : R/W; bitpos: [25]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_ECB (BIT(25)) +#define MODEM_SYSCON_RST_MODEM_ECB_M (MODEM_SYSCON_RST_MODEM_ECB_V << MODEM_SYSCON_RST_MODEM_ECB_S) +#define MODEM_SYSCON_RST_MODEM_ECB_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_ECB_S 25 +/** MODEM_SYSCON_RST_MODEM_CCM : R/W; bitpos: [26]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_CCM (BIT(26)) +#define MODEM_SYSCON_RST_MODEM_CCM_M (MODEM_SYSCON_RST_MODEM_CCM_V << MODEM_SYSCON_RST_MODEM_CCM_S) +#define MODEM_SYSCON_RST_MODEM_CCM_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_CCM_S 26 +/** MODEM_SYSCON_RST_MODEM_BAH : R/W; bitpos: [27]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_BAH (BIT(27)) +#define MODEM_SYSCON_RST_MODEM_BAH_M (MODEM_SYSCON_RST_MODEM_BAH_V << MODEM_SYSCON_RST_MODEM_BAH_S) +#define MODEM_SYSCON_RST_MODEM_BAH_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_BAH_S 27 +/** MODEM_SYSCON_RST_MODEM_SEC : R/W; bitpos: [29]; default: 0; **/ +#define MODEM_SYSCON_RST_MODEM_SEC (BIT(29)) +#define MODEM_SYSCON_RST_MODEM_SEC_M (MODEM_SYSCON_RST_MODEM_SEC_V << MODEM_SYSCON_RST_MODEM_SEC_S) +#define MODEM_SYSCON_RST_MODEM_SEC_V 0x00000001U +#define MODEM_SYSCON_RST_MODEM_SEC_S 29 +/** MODEM_SYSCON_RST_BLE_TIMER : R/W; bitpos: [30]; default: 0; **/ +#define MODEM_SYSCON_RST_BLE_TIMER (BIT(30)) +#define MODEM_SYSCON_RST_BLE_TIMER_M (MODEM_SYSCON_RST_BLE_TIMER_V << MODEM_SYSCON_RST_BLE_TIMER_S) +#define MODEM_SYSCON_RST_BLE_TIMER_V 0x00000001U +#define MODEM_SYSCON_RST_BLE_TIMER_S 30 +/** MODEM_SYSCON_RST_DATA_DUMP : R/W; bitpos: [31]; default: 0; **/ +#define MODEM_SYSCON_RST_DATA_DUMP (BIT(31)) +#define MODEM_SYSCON_RST_DATA_DUMP_M (MODEM_SYSCON_RST_DATA_DUMP_V << MODEM_SYSCON_RST_DATA_DUMP_S) +#define MODEM_SYSCON_RST_DATA_DUMP_V 0x00000001U +#define MODEM_SYSCON_RST_DATA_DUMP_S 31 -#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) -/* MODEM_SYSCON_CLK_FE_DAC_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_M (BIT(21)) -#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -/* MODEM_SYSCON_CLK_FE_ADC_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_M (BIT(20)) -#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 -/* MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (BIT(19)) -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 -/* MODEM_SYSCON_CLK_BTMAC_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_M (BIT(18)) -#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 -/* MODEM_SYSCON_CLK_BTBB_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_M (BIT(17)) -#define MODEM_SYSCON_CLK_BTBB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BTBB_EN_S 17 -/* MODEM_SYSCON_CLK_BT_APB_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_M (BIT(16)) -#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 -/* MODEM_SYSCON_CLK_FE_APB_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_M (BIT(15)) -#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 -/* MODEM_SYSCON_CLK_FE_160M_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_M (BIT(14)) -#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 -/* MODEM_SYSCON_CLK_FE_80M_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_M (BIT(13)) -#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 -/* MODEM_SYSCON_CLK_FE_40M_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_M (BIT(12)) -#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 -/* MODEM_SYSCON_CLK_FE_20M_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_M (BIT(11)) -#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x1 -#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 -/* MODEM_SYSCON_CLK_WIFI_APB_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (BIT(10)) -#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 -/* MODEM_SYSCON_CLK_WIFIMAC_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (BIT(9)) -#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 -/* MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (BIT(8)) -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 -/* MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (BIT(7)) -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 -/* MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (BIT(6)) -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 -/* MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (BIT(5)) -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 -/* MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (BIT(4)) -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 -/* MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (BIT(3)) -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 -/* MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (BIT(2)) -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 -/* MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: .*/ -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (BIT(1)) -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x1 -#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 -/* MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: .*/ +/** MODEM_SYSCON_CLK_CONF1_REG register **/ +#define MODEM_SYSCON_CLK_CONF1_REG (DR_REG_MODEM_SYSCON_BASE + 0x14) +/** MODEM_SYSCON_CLK_WIFIBB_22M_EN : R/W; bitpos: [0]; default: 0; **/ #define MODEM_SYSCON_CLK_WIFIBB_22M_EN (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (BIT(0)) -#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x1 +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_M (MODEM_SYSCON_CLK_WIFIBB_22M_EN_V << MODEM_SYSCON_CLK_WIFIBB_22M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_22M_EN_V 0x00000001U #define MODEM_SYSCON_CLK_WIFIBB_22M_EN_S 0 +/** MODEM_SYSCON_CLK_WIFIBB_40M_EN : R/W; bitpos: [1]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN (BIT(1)) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_M (MODEM_SYSCON_CLK_WIFIBB_40M_EN_V << MODEM_SYSCON_CLK_WIFIBB_40M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40M_EN_S 1 +/** MODEM_SYSCON_CLK_WIFIBB_44M_EN : R/W; bitpos: [2]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN (BIT(2)) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_M (MODEM_SYSCON_CLK_WIFIBB_44M_EN_V << MODEM_SYSCON_CLK_WIFIBB_44M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_44M_EN_S 2 +/** MODEM_SYSCON_CLK_WIFIBB_80M_EN : R/W; bitpos: [3]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN (BIT(3)) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_M (MODEM_SYSCON_CLK_WIFIBB_80M_EN_V << MODEM_SYSCON_CLK_WIFIBB_80M_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80M_EN_S 3 +/** MODEM_SYSCON_CLK_WIFIBB_40X_EN : R/W; bitpos: [4]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN (BIT(4)) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X_EN_S 4 +/** MODEM_SYSCON_CLK_WIFIBB_80X_EN : R/W; bitpos: [5]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN (BIT(5)) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X_EN_S 5 +/** MODEM_SYSCON_CLK_WIFIBB_40X1_EN : R/W; bitpos: [6]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN (BIT(6)) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_40X1_EN_S 6 +/** MODEM_SYSCON_CLK_WIFIBB_80X1_EN : R/W; bitpos: [7]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN (BIT(7)) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_80X1_EN_S 7 +/** MODEM_SYSCON_CLK_WIFIBB_160X1_EN : R/W; bitpos: [8]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN (BIT(8)) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_M (MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V << MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S) +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIBB_160X1_EN_S 8 +/** MODEM_SYSCON_CLK_WIFIMAC_EN : R/W; bitpos: [9]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFIMAC_EN (BIT(9)) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_M (MODEM_SYSCON_CLK_WIFIMAC_EN_V << MODEM_SYSCON_CLK_WIFIMAC_EN_S) +#define MODEM_SYSCON_CLK_WIFIMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFIMAC_EN_S 9 +/** MODEM_SYSCON_CLK_WIFI_APB_EN : R/W; bitpos: [10]; default: 0; **/ +#define MODEM_SYSCON_CLK_WIFI_APB_EN (BIT(10)) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_M (MODEM_SYSCON_CLK_WIFI_APB_EN_V << MODEM_SYSCON_CLK_WIFI_APB_EN_S) +#define MODEM_SYSCON_CLK_WIFI_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_WIFI_APB_EN_S 10 +/** MODEM_SYSCON_CLK_FE_20M_EN : R/W; bitpos: [11]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_20M_EN (BIT(11)) +#define MODEM_SYSCON_CLK_FE_20M_EN_M (MODEM_SYSCON_CLK_FE_20M_EN_V << MODEM_SYSCON_CLK_FE_20M_EN_S) +#define MODEM_SYSCON_CLK_FE_20M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_20M_EN_S 11 +/** MODEM_SYSCON_CLK_FE_40M_EN : R/W; bitpos: [12]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_40M_EN (BIT(12)) +#define MODEM_SYSCON_CLK_FE_40M_EN_M (MODEM_SYSCON_CLK_FE_40M_EN_V << MODEM_SYSCON_CLK_FE_40M_EN_S) +#define MODEM_SYSCON_CLK_FE_40M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_40M_EN_S 12 +/** MODEM_SYSCON_CLK_FE_80M_EN : R/W; bitpos: [13]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_80M_EN (BIT(13)) +#define MODEM_SYSCON_CLK_FE_80M_EN_M (MODEM_SYSCON_CLK_FE_80M_EN_V << MODEM_SYSCON_CLK_FE_80M_EN_S) +#define MODEM_SYSCON_CLK_FE_80M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_80M_EN_S 13 +/** MODEM_SYSCON_CLK_FE_160M_EN : R/W; bitpos: [14]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_160M_EN (BIT(14)) +#define MODEM_SYSCON_CLK_FE_160M_EN_M (MODEM_SYSCON_CLK_FE_160M_EN_V << MODEM_SYSCON_CLK_FE_160M_EN_S) +#define MODEM_SYSCON_CLK_FE_160M_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_160M_EN_S 14 +/** MODEM_SYSCON_CLK_FE_APB_EN : R/W; bitpos: [15]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_APB_EN (BIT(15)) +#define MODEM_SYSCON_CLK_FE_APB_EN_M (MODEM_SYSCON_CLK_FE_APB_EN_V << MODEM_SYSCON_CLK_FE_APB_EN_S) +#define MODEM_SYSCON_CLK_FE_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_APB_EN_S 15 +/** MODEM_SYSCON_CLK_BT_APB_EN : R/W; bitpos: [16]; default: 0; **/ +#define MODEM_SYSCON_CLK_BT_APB_EN (BIT(16)) +#define MODEM_SYSCON_CLK_BT_APB_EN_M (MODEM_SYSCON_CLK_BT_APB_EN_V << MODEM_SYSCON_CLK_BT_APB_EN_S) +#define MODEM_SYSCON_CLK_BT_APB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BT_APB_EN_S 16 +/** MODEM_SYSCON_CLK_BTBB_EN : R/W; bitpos: [17]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTBB_EN (BIT(17)) +#define MODEM_SYSCON_CLK_BTBB_EN_M (MODEM_SYSCON_CLK_BTBB_EN_V << MODEM_SYSCON_CLK_BTBB_EN_S) +#define MODEM_SYSCON_CLK_BTBB_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BTBB_EN_S 17 +/** MODEM_SYSCON_CLK_BTMAC_EN : R/W; bitpos: [18]; default: 0; **/ +#define MODEM_SYSCON_CLK_BTMAC_EN (BIT(18)) +#define MODEM_SYSCON_CLK_BTMAC_EN_M (MODEM_SYSCON_CLK_BTMAC_EN_V << MODEM_SYSCON_CLK_BTMAC_EN_S) +#define MODEM_SYSCON_CLK_BTMAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_BTMAC_EN_S 18 +/** MODEM_SYSCON_CLK_FE_PWDET_ADC_EN : R/W; bitpos: [19]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN (BIT(19)) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_M (MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V << MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S) +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_PWDET_ADC_EN_S 19 +/** MODEM_SYSCON_CLK_FE_ADC_EN : R/W; bitpos: [20]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_ADC_EN (BIT(20)) +#define MODEM_SYSCON_CLK_FE_ADC_EN_M (MODEM_SYSCON_CLK_FE_ADC_EN_V << MODEM_SYSCON_CLK_FE_ADC_EN_S) +#define MODEM_SYSCON_CLK_FE_ADC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_ADC_EN_S 20 +/** MODEM_SYSCON_CLK_FE_DAC_EN : R/W; bitpos: [21]; default: 0; **/ +#define MODEM_SYSCON_CLK_FE_DAC_EN (BIT(21)) +#define MODEM_SYSCON_CLK_FE_DAC_EN_M (MODEM_SYSCON_CLK_FE_DAC_EN_V << MODEM_SYSCON_CLK_FE_DAC_EN_S) +#define MODEM_SYSCON_CLK_FE_DAC_EN_V 0x00000001U +#define MODEM_SYSCON_CLK_FE_DAC_EN_S 21 -#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) -/* MODEM_SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: .*/ -#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFF -#define MODEM_SYSCON_WIFI_BB_CFG_M ((MODEM_SYSCON_WIFI_BB_CFG_V)<<(MODEM_SYSCON_WIFI_BB_CFG_S)) -#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +/** MODEM_SYSCON_WIFI_BB_CFG_REG register **/ +#define MODEM_SYSCON_WIFI_BB_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x18) +/** MODEM_SYSCON_WIFI_BB_CFG : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_WIFI_BB_CFG 0xFFFFFFFFU +#define MODEM_SYSCON_WIFI_BB_CFG_M (MODEM_SYSCON_WIFI_BB_CFG_V << MODEM_SYSCON_WIFI_BB_CFG_S) +#define MODEM_SYSCON_WIFI_BB_CFG_V 0xFFFFFFFFU #define MODEM_SYSCON_WIFI_BB_CFG_S 0 -#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x1C) -/* MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00002070 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_SYSCON_FE_CFG_REG register **/ +#define MODEM_SYSCON_FE_CFG_REG (DR_REG_MODEM_SYSCON_BASE + 0x1c) +/** MODEM_SYSCON_FE_CFG : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_FE_CFG 0xFFFFFFFFU +#define MODEM_SYSCON_FE_CFG_M (MODEM_SYSCON_FE_CFG_V << MODEM_SYSCON_FE_CFG_S) +#define MODEM_SYSCON_FE_CFG_V 0xFFFFFFFFU +#define MODEM_SYSCON_FE_CFG_S 0 + +/** MODEM_SYSCON_MEM_RF1_CONF_REG register **/ +#define MODEM_SYSCON_MEM_RF1_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) +/** MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 8304; **/ +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL 0xFFFFFFFFU +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_M (MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S) +#define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_SYSCON_MODEM_RF1_MEM_AUX_CTRL_S 0 -#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x20) -/* MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W ;bitpos:[31:0] ;default: 32'h00000000 ; */ -/*description: .*/ -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFF -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M ((MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V)<<(MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S)) -#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFF +/** MODEM_SYSCON_MEM_RF2_CONF_REG register **/ +#define MODEM_SYSCON_MEM_RF2_CONF_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) +/** MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL : R/W; bitpos: [31:0]; default: 0; **/ +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL 0xFFFFFFFFU +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_M (MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V << MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S) +#define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_V 0xFFFFFFFFU #define MODEM_SYSCON_MODEM_RF2_MEM_AUX_CTRL_S 0 -#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x24) -/* MODEM_SYSCON_DATE : R/W ;bitpos:[27:0] ;default: 28'h2401180 ; */ -/*description: .*/ -#define MODEM_SYSCON_DATE 0x0FFFFFFF -#define MODEM_SYSCON_DATE_M ((MODEM_SYSCON_DATE_V)<<(MODEM_SYSCON_DATE_S)) -#define MODEM_SYSCON_DATE_V 0xFFFFFFF +/** MODEM_SYSCON_DATE_REG register **/ +#define MODEM_SYSCON_DATE_REG (DR_REG_MODEM_SYSCON_BASE + 0x28) +/** MODEM_SYSCON_DATE : R/W; bitpos: [27:0]; default: 37823072; **/ +#define MODEM_SYSCON_DATE 0x0FFFFFFFU +#define MODEM_SYSCON_DATE_M (MODEM_SYSCON_DATE_V << MODEM_SYSCON_DATE_S) +#define MODEM_SYSCON_DATE_V 0x0FFFFFFFU #define MODEM_SYSCON_DATE_S 0 #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/modem/modem_syscon_struct.h b/components/soc/esp32c61/include/modem/modem_syscon_struct.h index 101c41dd43..8e7d5f6d5a 100644 --- a/components/soc/esp32c61/include/modem/modem_syscon_struct.h +++ b/components/soc/esp32c61/include/modem/modem_syscon_struct.h @@ -1,7 +1,7 @@ -/* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -10,164 +10,194 @@ extern "C" { #endif -typedef volatile struct { - union { - struct { - uint32_t clk_en : 1; - uint32_t modem_ant_force_sel_bt : 1; - uint32_t modem_ant_force_sel_wifi : 1; - uint32_t fpga_debug_clkswitch : 1; - uint32_t fpga_debug_clk80 : 1; - uint32_t fpga_debug_clk40 : 1; - uint32_t fpga_debug_clk20 : 1; - uint32_t fpga_debug_clk10 : 1; - uint32_t modem_mem_mode_force : 1; - uint32_t modem_dis_wifi6_force : 1; - uint32_t reserved10 : 22; - }; - uint32_t val; - } test_conf; - union { - struct { - uint32_t pwdet_sar_clock_ena : 1; - uint32_t pwdet_clk_div_num : 8; - uint32_t clk_tx_dac_inv_ena : 1; - uint32_t clk_rx_adc_inv_ena : 1; - uint32_t clk_pwdet_adc_inv_ena : 1; - uint32_t clk_i2c_mst_sel_160m : 1; - uint32_t reserved13 : 8; - uint32_t clk_data_dump_mux : 1; - uint32_t clk_etm_en : 1; - uint32_t clk_zb_apb_en : 1; - uint32_t clk_zbmac_en : 1; - uint32_t clk_modem_sec_ecb_en : 1; - uint32_t clk_modem_sec_ccm_en : 1; - uint32_t clk_modem_sec_bah_en : 1; - uint32_t clk_modem_sec_apb_en : 1; - uint32_t clk_modem_sec_en : 1; - uint32_t clk_ble_timer_en : 1; - uint32_t clk_data_dump_en : 1; - }; - uint32_t val; - } clk_conf; - union { - struct { - uint32_t clk_wifibb_fo : 1; - uint32_t clk_wifimac_fo : 1; - uint32_t clk_wifi_apb_fo : 1; - uint32_t clk_fe_fo : 1; - uint32_t clk_fe_apb_fo : 1; - uint32_t clk_btbb_fo : 1; - uint32_t clk_btmac_fo : 1; - uint32_t clk_bt_apb_fo : 1; - uint32_t clk_zbmac_fo : 1; - uint32_t clk_zbmac_apb_fo : 1; - uint32_t reserved10 : 13; - uint32_t reserved23 : 1; - uint32_t reserved24 : 1; - uint32_t reserved25 : 1; - uint32_t reserved26 : 1; - uint32_t reserved27 : 1; - uint32_t clk_etm_fo : 1; - uint32_t clk_modem_sec_fo : 1; - uint32_t clk_ble_timer_fo : 1; - uint32_t clk_data_dump_fo : 1; - }; - uint32_t val; - } clk_conf_force_on; - union { - struct { - uint32_t reserved0 : 8; - uint32_t clk_zb_st_map : 4; - uint32_t clk_fe_st_map : 4; - uint32_t clk_bt_st_map : 4; - uint32_t clk_wifi_st_map : 4; - uint32_t clk_modem_peri_st_map : 4; - uint32_t clk_modem_apb_st_map : 4; - }; - uint32_t val; - } clk_conf_power_st; - union { - struct { - uint32_t reserved0 : 1; - uint32_t reserved1 : 1; - uint32_t reserved2 : 1; - uint32_t reserved3 : 1; - uint32_t reserved4 : 1; - uint32_t reserved5 : 1; - uint32_t reserved6 : 1; - uint32_t reserved7 : 1; - uint32_t rst_wifibb : 1; - uint32_t rst_wifimac : 1; - uint32_t rst_fe_pwdet_adc : 1; - uint32_t rst_fe_dac : 1; - uint32_t rst_fe_adc : 1; - uint32_t rst_fe_ahb : 1; - uint32_t rst_fe : 1; - uint32_t rst_btmac_apb : 1; - uint32_t rst_btmac : 1; - uint32_t rst_btbb_apb : 1; - uint32_t rst_btbb : 1; - uint32_t reserved19 : 3; - uint32_t rst_etm : 1; - uint32_t rst_zbmac_apb : 1; - uint32_t rst_zbmac : 1; - uint32_t rst_modem_ecb : 1; - uint32_t rst_modem_ccm : 1; - uint32_t rst_modem_bah : 1; - uint32_t reserved28 : 1; - uint32_t rst_modem_sec : 1; - uint32_t rst_ble_timer : 1; - uint32_t rst_data_dump : 1; - }; - uint32_t val; - } modem_rst_conf; - union { - struct { - uint32_t clk_wifibb_22m_en : 1; - uint32_t clk_wifibb_40m_en : 1; - uint32_t clk_wifibb_44m_en : 1; - uint32_t clk_wifibb_80m_en : 1; - uint32_t clk_wifibb_40x_en : 1; - uint32_t clk_wifibb_80x_en : 1; - uint32_t clk_wifibb_40x1_en : 1; - uint32_t clk_wifibb_80x1_en : 1; - uint32_t clk_wifibb_160x1_en : 1; - uint32_t clk_wifimac_en : 1; - uint32_t clk_wifi_apb_en : 1; - uint32_t clk_fe_20m_en : 1; - uint32_t clk_fe_40m_en : 1; - uint32_t clk_fe_80m_en : 1; - uint32_t clk_fe_160m_en : 1; - uint32_t clk_fe_apb_en : 1; - uint32_t clk_bt_apb_en : 1; - uint32_t clk_btbb_en : 1; - uint32_t clk_btmac_en : 1; - uint32_t clk_fe_pwdet_adc_en : 1; - uint32_t clk_fe_adc_en : 1; - uint32_t clk_fe_dac_en : 1; - uint32_t reserved22 : 1; - uint32_t reserved23 : 1; - uint32_t reserved24 : 8; - }; - uint32_t val; - } clk_conf1; - uint32_t wifi_bb_cfg; - uint32_t mem_rf1_conf; - uint32_t mem_rf2_conf; - union { - struct { - uint32_t date : 28; - uint32_t reserved28 : 4; - }; - uint32_t val; - } date; +/** Group: configure_register */ +typedef union { + struct { + uint32_t clk_en: 1; + uint32_t modem_ant_force_sel_bt: 1; + uint32_t modem_ant_force_sel_wifi: 1; + uint32_t fpga_debug_clkswitch: 1; + uint32_t fpga_debug_clk80: 1; + uint32_t fpga_debug_clk40: 1; + uint32_t fpga_debug_clk20: 1; + uint32_t fpga_debug_clk10: 1; + uint32_t modem_mem_mode_force: 1; + uint32_t modem_dis_wifi6_force: 1; + uint32_t reserved_10: 22; + }; + uint32_t val; +} modem_syscon_test_conf_reg_t; + +typedef union { + struct { + uint32_t pwdet_sar_clock_ena: 1; + uint32_t pwdet_clk_div_num: 8; + uint32_t clk_tx_dac_inv_ena: 1; + uint32_t clk_rx_adc_inv_ena: 1; + uint32_t clk_pwdet_adc_inv_ena: 1; + uint32_t clk_i2c_mst_sel_160m: 1; + uint32_t reserved_13: 8; + uint32_t clk_data_dump_mux: 1; + uint32_t clk_etm_en: 1; + uint32_t clk_zb_apb_en: 1; + uint32_t clk_zbmac_en: 1; + uint32_t clk_modem_sec_ecb_en: 1; + uint32_t clk_modem_sec_ccm_en: 1; + uint32_t clk_modem_sec_bah_en: 1; + uint32_t clk_modem_sec_apb_en: 1; + uint32_t clk_modem_sec_en: 1; + uint32_t clk_ble_timer_en: 1; + uint32_t clk_data_dump_en: 1; + }; + uint32_t val; +} modem_syscon_clk_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_fo: 1; + uint32_t clk_wifimac_fo: 1; + uint32_t clk_wifi_apb_fo: 1; + uint32_t clk_fe_fo: 1; + uint32_t clk_fe_apb_fo: 1; + uint32_t clk_btbb_fo: 1; + uint32_t clk_btmac_fo: 1; + uint32_t clk_bt_apb_fo: 1; + uint32_t clk_zbmac_fo: 1; + uint32_t clk_zbmac_apb_fo: 1; + uint32_t reserved_10: 18; + uint32_t clk_etm_fo: 1; + uint32_t clk_modem_sec_fo: 1; + uint32_t clk_ble_timer_fo: 1; + uint32_t clk_data_dump_fo: 1; + }; + uint32_t val; +} modem_syscon_clk_conf_force_on_reg_t; + +typedef union { + struct { + uint32_t reserved_0: 8; + uint32_t clk_zb_st_map: 4; + uint32_t clk_fe_st_map: 4; + uint32_t clk_bt_st_map: 4; + uint32_t clk_wifi_st_map: 4; + uint32_t clk_modem_peri_st_map: 4; + uint32_t clk_modem_apb_st_map: 4; + }; + uint32_t val; +} modem_syscon_clk_conf_power_st_reg_t; + +typedef union { + struct { + uint32_t reserved_0: 8; + uint32_t rst_wifibb: 1; + uint32_t rst_wifimac: 1; + uint32_t rst_fe_pwdet_adc: 1; + uint32_t rst_fe_dac: 1; + uint32_t rst_fe_adc: 1; + uint32_t rst_fe_ahb: 1; + uint32_t rst_fe: 1; + uint32_t rst_btmac_apb: 1; + uint32_t rst_btmac: 1; + uint32_t rst_btbb_apb: 1; + uint32_t rst_btbb: 1; + uint32_t reserved_19: 3; + uint32_t rst_etm: 1; + uint32_t rst_zbmac_apb: 1; + uint32_t rst_zbmac: 1; + uint32_t rst_modem_ecb: 1; + uint32_t rst_modem_ccm: 1; + uint32_t rst_modem_bah: 1; + uint32_t reserved_28: 1; + uint32_t rst_modem_sec: 1; + uint32_t rst_ble_timer: 1; + uint32_t rst_data_dump: 1; + }; + uint32_t val; +} modem_syscon_modem_rst_conf_reg_t; + +typedef union { + struct { + uint32_t clk_wifibb_22m_en: 1; + uint32_t clk_wifibb_40m_en: 1; + uint32_t clk_wifibb_44m_en: 1; + uint32_t clk_wifibb_80m_en: 1; + uint32_t clk_wifibb_40x_en: 1; + uint32_t clk_wifibb_80x_en: 1; + uint32_t clk_wifibb_40x1_en: 1; + uint32_t clk_wifibb_80x1_en: 1; + uint32_t clk_wifibb_160x1_en: 1; + uint32_t clk_wifimac_en: 1; + uint32_t clk_wifi_apb_en: 1; + uint32_t clk_fe_20m_en: 1; + uint32_t clk_fe_40m_en: 1; + uint32_t clk_fe_80m_en: 1; + uint32_t clk_fe_160m_en: 1; + uint32_t clk_fe_apb_en: 1; + uint32_t clk_bt_apb_en: 1; + uint32_t clk_btbb_en: 1; + uint32_t clk_btmac_en: 1; + uint32_t clk_fe_pwdet_adc_en: 1; + uint32_t clk_fe_adc_en: 1; + uint32_t clk_fe_dac_en: 1; + uint32_t reserved_22: 10; + }; + uint32_t val; +} modem_syscon_clk_conf1_reg_t; + +typedef union { + struct { + uint32_t wifi_bb_cfg: 32; + }; + uint32_t val; +} modem_syscon_wifi_bb_cfg_reg_t; + +typedef union { + struct { + uint32_t fe_cfg: 32; + }; + uint32_t val; +} modem_syscon_fe_cfg_reg_t; + +typedef union { + struct { + uint32_t modem_rf1_mem_aux_ctrl: 32; + }; + uint32_t val; +} modem_syscon_mem_rf1_conf_reg_t; + +typedef union { + struct { + uint32_t modem_rf2_mem_aux_ctrl: 32; + }; + uint32_t val; +} modem_syscon_mem_rf2_conf_reg_t; + +typedef union { + struct { + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} modem_syscon_date_reg_t; + +typedef struct { + volatile modem_syscon_test_conf_reg_t test_conf; + volatile modem_syscon_clk_conf_reg_t clk_conf; + volatile modem_syscon_clk_conf_force_on_reg_t clk_conf_force_on; + volatile modem_syscon_clk_conf_power_st_reg_t clk_conf_power_st; + volatile modem_syscon_modem_rst_conf_reg_t modem_rst_conf; + volatile modem_syscon_clk_conf1_reg_t clk_conf1; + volatile modem_syscon_wifi_bb_cfg_reg_t wifi_bb_cfg; + volatile modem_syscon_fe_cfg_reg_t fe_cfg; + volatile modem_syscon_mem_rf1_conf_reg_t mem_rf1_conf; + volatile modem_syscon_mem_rf2_conf_reg_t mem_rf2_conf; + volatile modem_syscon_date_reg_t date; } modem_syscon_dev_t; extern modem_syscon_dev_t MODEM_SYSCON; #ifndef __cplusplus -_Static_assert(sizeof(modem_syscon_dev_t) == 0x28, "Invalid size of modem_syscon_dev_t structure"); +_Static_assert(sizeof(modem_syscon_dev_t) == 0x2c, "Invalid size of modem_syscon_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in index b231b665ed..7bb74765ae 100644 --- a/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c61/include/soc/Kconfig.soc_caps.in @@ -379,6 +379,10 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION bool default y +config SOC_AHB_GDMA_SUPPORT_PSRAM + bool + default y + config SOC_ETM_GROUPS int default 1 @@ -397,7 +401,7 @@ config SOC_GPIO_PORT config SOC_GPIO_PIN_COUNT int - default 25 + default 30 config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER bool @@ -421,11 +425,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT config SOC_GPIO_IN_RANGE_MAX int - default 24 + default 29 config SOC_GPIO_OUT_RANGE_MAX int - default 24 + default 29 config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP bool @@ -441,7 +445,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK hex - default 0x1FFFF80 + default 0x3FFFFF80 config SOC_GPIO_SUPPORT_FORCE_HOLD bool @@ -791,6 +795,10 @@ config SOC_SPIRAM_XIP_SUPPORTED bool default y +config SOC_PSRAM_DMA_CAPABLE + bool + default y + config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE bool default y @@ -819,6 +827,10 @@ config SOC_SPI_MEM_SUPPORT_WRAP bool default y +config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + bool + default y + config SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED bool default y @@ -975,10 +987,26 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND bool default y +config SOC_RECOVERY_BOOTLOADER_SUPPORTED + bool + default y + +config SOC_BOOTLOADER_ANTI_ROLLBACK_SUPPORTED + bool + default y + config SOC_APM_CTRL_FILTER_SUPPORTED bool default y +config SOC_APM_CPU_APM_SUPPORTED + bool + default y + +config SOC_APM_SUPPORT_CTRL_CFG_LOCK + bool + default y + config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED bool default y @@ -1259,10 +1287,6 @@ config SOC_BLE_SUPPORTED bool default y -config SOC_BLE_MESH_SUPPORTED - bool - default y - config SOC_ESP_NIMBLE_CONTROLLER bool default y diff --git a/components/soc/esp32c61/include/soc/apm_defs.h b/components/soc/esp32c61/include/soc/apm_defs.h new file mode 100644 index 0000000000..96b45ea89a --- /dev/null +++ b/components/soc/esp32c61/include/soc/apm_defs.h @@ -0,0 +1,45 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of paths for each supported APM controller */ +#define APM_CTRL_HP_APM_PATH_NUM (4) +#define APM_CTRL_LP_APM_PATH_NUM (1) +#define APM_CTRL_CPU_APM_PATH_NUM (2) +/* Number of regions for each supported APM controller */ +#define APM_CTRL_HP_APM_REGION_NUM (16) +#define APM_CTRL_LP_APM_REGION_NUM (4) +#define APM_CTRL_CPU_APM_REGION_NUM (8) + +/* Register offset for TEE mode control */ +#define APM_TEE_MODE_CTRL_OFFSET (0x04) +/* Register offset between region bound address registers */ +#define APM_REGION_ADDR_OFFSET (0x0C) +/* Register offset between region pms attribute registers */ +#define APM_REGION_ATTR_OFFSET (0x0C) +/* Register offset between exception info registers */ +#define APM_EXCP_INFO_OFFSET (0x10) + +/* Bit to clear exception status */ +#define APM_EXCP_STATUS_CLR_BIT (BIT(0)) +/* Bit to lock TEE mode */ +#define APM_TEE_MODE_LOCK_BIT (BIT(2)) +/* Bit to lock region pms attributes */ +#define APM_REGION_LOCK_BIT (BIT(11)) + +/* APM controller masters mask */ +#define APM_MASTER_MASK_ALL (0x018E0175U) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/include/soc/gpio_num.h b/components/soc/esp32c61/include/soc/gpio_num.h index c92151b7f8..687a239b3a 100644 --- a/components/soc/esp32c61/include/soc/gpio_num.h +++ b/components/soc/esp32c61/include/soc/gpio_num.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -40,6 +40,11 @@ typedef enum { GPIO_NUM_22 = 22, /*!< GPIO22, input and output */ GPIO_NUM_23 = 23, /*!< GPIO23, input and output */ GPIO_NUM_24 = 24, /*!< GPIO24, input and output */ + GPIO_NUM_25 = 25, /*!< GPIO25, input and output */ + GPIO_NUM_26 = 26, /*!< GPIO26, input and output */ + GPIO_NUM_27 = 27, /*!< GPIO27, input and output */ + GPIO_NUM_28 = 28, /*!< GPIO28, input and output */ + GPIO_NUM_29 = 29, /*!< GPIO29, input and output */ GPIO_NUM_MAX, } gpio_num_t; diff --git a/components/soc/esp32c61/include/soc/gpio_pins.h b/components/soc/esp32c61/include/soc/gpio_pins.h index bb92733f65..c974250de0 100644 --- a/components/soc/esp32c61/include/soc/gpio_pins.h +++ b/components/soc/esp32c61/include/soc/gpio_pins.h @@ -10,8 +10,8 @@ extern "C" { #endif -#define GPIO_MATRIX_CONST_ONE_INPUT (0x20) -#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30) +#define GPIO_MATRIX_CONST_ONE_INPUT (0x40) +#define GPIO_MATRIX_CONST_ZERO_INPUT (0x60) #ifdef __cplusplus } diff --git a/components/soc/esp32c61/include/soc/gpio_sig_map.h b/components/soc/esp32c61/include/soc/gpio_sig_map.h index 10eb7cec7a..7eb822bffe 100644 --- a/components/soc/esp32c61/include/soc/gpio_sig_map.h +++ b/components/soc/esp32c61/include/soc/gpio_sig_map.h @@ -1,12 +1,11 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -// version date 2310090 #define EXT_ADC_START_IDX 0 #define LEDC_LS_SIG_OUT0_IDX 0 #define LEDC_LS_SIG_OUT1_IDX 1 @@ -141,6 +140,7 @@ #define GPIO_TASK_MATRIX_OUT2_IDX 120 #define GPIO_EVENT_MATRIX_IN3_IDX 121 #define GPIO_TASK_MATRIX_OUT3_IDX 121 +#define SDIO_TOHOST_INT_OUT_IDX 124 #define CLK_OUT_OUT1_IDX 126 #define CLK_OUT_OUT2_IDX 127 #define CLK_OUT_OUT3_IDX 128 @@ -176,5 +176,5 @@ #define MODEM_DIAG29_IDX 158 #define MODEM_DIAG30_IDX 159 #define MODEM_DIAG31_IDX 160 - +// version date 2310090 #define SIG_GPIO_OUT_IDX 256 diff --git a/components/soc/esp32c61/include/soc/interrupt_reg.h b/components/soc/esp32c61/include/soc/interrupt_reg.h index 7dffc583d0..d94be8a2ae 100644 --- a/components/soc/esp32c61/include/soc/interrupt_reg.h +++ b/components/soc/esp32c61/include/soc/interrupt_reg.h @@ -14,5 +14,3 @@ #define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG) #define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG - -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE diff --git a/components/soc/esp32c61/include/soc/interrupts.h b/components/soc/esp32c61/include/soc/interrupts.h index ab18526851..97a33ee181 100644 --- a/components/soc/esp32c61/include/soc/interrupts.h +++ b/components/soc/esp32c61/include/soc/interrupts.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,15 +35,15 @@ typedef enum { ETS_LP_WDT_INTR_SOURCE, ETS_LP_PERI_TIMEOUT_INTR_SOURCE, ETS_LP_APM_M0_INTR_SOURCE, - ETS_FROM_CPU_INTR0_SOURCE, - ETS_FROM_CPU_INTR1_SOURCE, - ETS_FROM_CPU_INTR2_SOURCE, - ETS_FROM_CPU_INTR3_SOURCE, + ETS_CPU_INTR_FROM_CPU_0_SOURCE, + ETS_CPU_INTR_FROM_CPU_1_SOURCE, + ETS_CPU_INTR_FROM_CPU_2_SOURCE, + ETS_CPU_INTR_FROM_CPU_3_SOURCE, ETS_ASSIST_DEBUG_INTR_SOURCE, ETS_TRACE_INTR_SOURCE, ETS_CACHE_INTR_SOURCE, ETS_CPU_PERI_TIMEOUT_INTR_SOURCE, - ETS_GPIO_INTR_SOURCE, + ETS_GPIO_INTERRUPT_PRO_SOURCE, ETS_GPIO_INTERRUPT_EXT_SOURCE, ETS_PAU_INTR_SOURCE, ETS_HP_PERI_TIMEOUT_INTR_SOURCE, @@ -52,6 +52,8 @@ typedef enum { ETS_HP_APM_M1_INTR_SOURCE, ETS_HP_APM_M2_INTR_SOURCE, ETS_HP_APM_M3_INTR_SOURCE, + ETS_CPU_APM_M0_INTR_SOURCE, + ETS_CPU_APM_M1_INTR_SOURCE, ETS_MSPI_INTR_SOURCE, ETS_I2S0_INTR_SOURCE, ETS_UART0_INTR_SOURCE, @@ -62,16 +64,18 @@ typedef enum { ETS_I2C_EXT0_INTR_SOURCE, ETS_TG0_T0_INTR_SOURCE, ETS_TG0_T1_INTR_SOURCE, - ETS_TG0_WDT_LEVEL_INTR_SOURCE, + ETS_TG0_WDT_INTR_SOURCE, ETS_TG1_T0_INTR_SOURCE, ETS_TG1_T1_INTR_SOURCE, - ETS_TG1_WDT_LEVEL_INTR_SOURCE, + ETS_TG1_WDT_INTR_SOURCE, ETS_SYSTIMER_TARGET0_INTR_SOURCE, ETS_SYSTIMER_TARGET1_INTR_SOURCE, ETS_SYSTIMER_TARGET2_INTR_SOURCE, - ETS_APB_ADC_INTR_SOURCE = 53, + ETS_APB_ADC_INTR_SOURCE, ETS_TEMPERATURE_SENSOR_INTR_SOURCE = ETS_APB_ADC_INTR_SOURCE, - ETS_DMA_IN_CH0_INTR_SOURCE = 54, + ETS_SLC0_INTR_SOURCE, + ETS_SLC1_INTR_SOURCE, + ETS_DMA_IN_CH0_INTR_SOURCE, ETS_DMA_IN_CH1_INTR_SOURCE, ETS_DMA_OUT_CH0_INTR_SOURCE, ETS_DMA_OUT_CH1_INTR_SOURCE, diff --git a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h index a71ee0a8da..7133c630e3 100644 --- a/components/soc/esp32c61/include/soc/pmu_icg_mapping.h +++ b/components/soc/esp32c61/include/soc/pmu_icg_mapping.h @@ -1,10 +1,11 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once + #define PMU_ICG_APB_ENA_SEC 0 #define PMU_ICG_APB_ENA_GDMA 1 #define PMU_ICG_APB_ENA_SPI2 2 @@ -35,6 +36,7 @@ #define PMU_ICG_FUNC_ENA_I2S_TX 7 #define PMU_ICG_FUNC_ENA_REGDMA 8 #define PMU_ICG_FUNC_ENA_MEM_MONITOR 10 +#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11 #define PMU_ICG_FUNC_ENA_TSENS 12 #define PMU_ICG_FUNC_ENA_TG1 13 #define PMU_ICG_FUNC_ENA_TG0 14 diff --git a/components/soc/esp32c61/include/soc/soc.h b/components/soc/esp32c61/include/soc/soc.h index bf56d907e3..a961fc8ff5 100644 --- a/components/soc/esp32c61/include/soc/soc.h +++ b/components/soc/esp32c61/include/soc/soc.h @@ -22,9 +22,7 @@ #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C61 #define REG_TIMG_BASE(i) (DR_REG_TIMG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_SPI_MEM_BASE(i) (DR_REG_MSPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 -#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C61 -#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE //Registers Operation {{ #define ETS_UNCACHED_ADDR(addr) (addr) diff --git a/components/soc/esp32c61/include/soc/soc_caps.h b/components/soc/esp32c61/include/soc/soc_caps.h index ce5c8596cd..0c2406df66 100644 --- a/components/soc/esp32c61/include/soc/soc_caps.h +++ b/components/soc/esp32c61/include/soc/soc_caps.h @@ -152,6 +152,7 @@ #define SOC_GDMA_PAIRS_PER_GROUP_MAX 2 #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 +#define SOC_AHB_GDMA_SUPPORT_PSRAM 1 /*-------------------------- ETM CAPS --------------------------------------*/ #define SOC_ETM_GROUPS 1U // Number of ETM groups @@ -161,7 +162,7 @@ /*-------------------------- GPIO CAPS ---------------------------------------*/ // ESP32-C61 has 1 GPIO peripheral #define SOC_GPIO_PORT 1U -#define SOC_GPIO_PIN_COUNT 25 +#define SOC_GPIO_PIN_COUNT 30 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1 @@ -178,16 +179,16 @@ #define SOC_GPIO_VALID_GPIO_MASK ((1ULL< +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** CPU_APM_REGION_FILTER_EN_REG register + * Region filter enable register + */ +#define CPU_APM_REGION_FILTER_EN_REG (DR_REG_CPU_APM_REG_BASE + 0x0) +/** CPU_APM_REGION_FILTER_EN : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ +#define CPU_APM_REGION_FILTER_EN 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_M (CPU_APM_REGION_FILTER_EN_V << CPU_APM_REGION_FILTER_EN_S) +#define CPU_APM_REGION_FILTER_EN_V 0x000000FFU +#define CPU_APM_REGION_FILTER_EN_S 0 + +/** CPU_APM_REGION0_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x4) +/** CPU_APM_REGION0_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_M (CPU_APM_REGION0_ADDR_START_L_V << CPU_APM_REGION0_ADDR_START_L_S) +#define CPU_APM_REGION0_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_START_L_S 0 +/** CPU_APM_REGION0_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_M (CPU_APM_REGION0_ADDR_START_V << CPU_APM_REGION0_ADDR_START_S) +#define CPU_APM_REGION0_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_START_S 12 +/** CPU_APM_REGION0_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 0. + */ +#define CPU_APM_REGION0_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_M (CPU_APM_REGION0_ADDR_START_H_V << CPU_APM_REGION0_ADDR_START_H_S) +#define CPU_APM_REGION0_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_START_H_S 19 + +/** CPU_APM_REGION0_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION0_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x8) +/** CPU_APM_REGION0_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_M (CPU_APM_REGION0_ADDR_END_L_V << CPU_APM_REGION0_ADDR_END_L_S) +#define CPU_APM_REGION0_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION0_ADDR_END_L_S 0 +/** CPU_APM_REGION0_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_M (CPU_APM_REGION0_ADDR_END_V << CPU_APM_REGION0_ADDR_END_S) +#define CPU_APM_REGION0_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION0_ADDR_END_S 12 +/** CPU_APM_REGION0_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 0. + */ +#define CPU_APM_REGION0_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_M (CPU_APM_REGION0_ADDR_END_H_V << CPU_APM_REGION0_ADDR_END_H_S) +#define CPU_APM_REGION0_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION0_ADDR_END_H_S 19 + +/** CPU_APM_REGION0_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION0_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0xc) +/** CPU_APM_REGION0_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_X (BIT(0)) +#define CPU_APM_REGION0_R0_X_M (CPU_APM_REGION0_R0_X_V << CPU_APM_REGION0_R0_X_S) +#define CPU_APM_REGION0_R0_X_V 0x00000001U +#define CPU_APM_REGION0_R0_X_S 0 +/** CPU_APM_REGION0_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_W (BIT(1)) +#define CPU_APM_REGION0_R0_W_M (CPU_APM_REGION0_R0_W_V << CPU_APM_REGION0_R0_W_S) +#define CPU_APM_REGION0_R0_W_V 0x00000001U +#define CPU_APM_REGION0_R0_W_S 1 +/** CPU_APM_REGION0_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 0. + */ +#define CPU_APM_REGION0_R0_R (BIT(2)) +#define CPU_APM_REGION0_R0_R_M (CPU_APM_REGION0_R0_R_V << CPU_APM_REGION0_R0_R_S) +#define CPU_APM_REGION0_R0_R_V 0x00000001U +#define CPU_APM_REGION0_R0_R_S 2 +/** CPU_APM_REGION0_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_X (BIT(4)) +#define CPU_APM_REGION0_R1_X_M (CPU_APM_REGION0_R1_X_V << CPU_APM_REGION0_R1_X_S) +#define CPU_APM_REGION0_R1_X_V 0x00000001U +#define CPU_APM_REGION0_R1_X_S 4 +/** CPU_APM_REGION0_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_W (BIT(5)) +#define CPU_APM_REGION0_R1_W_M (CPU_APM_REGION0_R1_W_V << CPU_APM_REGION0_R1_W_S) +#define CPU_APM_REGION0_R1_W_V 0x00000001U +#define CPU_APM_REGION0_R1_W_S 5 +/** CPU_APM_REGION0_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 0. + */ +#define CPU_APM_REGION0_R1_R (BIT(6)) +#define CPU_APM_REGION0_R1_R_M (CPU_APM_REGION0_R1_R_V << CPU_APM_REGION0_R1_R_S) +#define CPU_APM_REGION0_R1_R_V 0x00000001U +#define CPU_APM_REGION0_R1_R_S 6 +/** CPU_APM_REGION0_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_X (BIT(8)) +#define CPU_APM_REGION0_R2_X_M (CPU_APM_REGION0_R2_X_V << CPU_APM_REGION0_R2_X_S) +#define CPU_APM_REGION0_R2_X_V 0x00000001U +#define CPU_APM_REGION0_R2_X_S 8 +/** CPU_APM_REGION0_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_W (BIT(9)) +#define CPU_APM_REGION0_R2_W_M (CPU_APM_REGION0_R2_W_V << CPU_APM_REGION0_R2_W_S) +#define CPU_APM_REGION0_R2_W_V 0x00000001U +#define CPU_APM_REGION0_R2_W_S 9 +/** CPU_APM_REGION0_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 0. + */ +#define CPU_APM_REGION0_R2_R (BIT(10)) +#define CPU_APM_REGION0_R2_R_M (CPU_APM_REGION0_R2_R_V << CPU_APM_REGION0_R2_R_S) +#define CPU_APM_REGION0_R2_R_V 0x00000001U +#define CPU_APM_REGION0_R2_R_S 10 +/** CPU_APM_REGION0_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION0_LOCK (BIT(11)) +#define CPU_APM_REGION0_LOCK_M (CPU_APM_REGION0_LOCK_V << CPU_APM_REGION0_LOCK_S) +#define CPU_APM_REGION0_LOCK_V 0x00000001U +#define CPU_APM_REGION0_LOCK_S 11 + +/** CPU_APM_REGION1_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x10) +/** CPU_APM_REGION1_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_M (CPU_APM_REGION1_ADDR_START_L_V << CPU_APM_REGION1_ADDR_START_L_S) +#define CPU_APM_REGION1_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_START_L_S 0 +/** CPU_APM_REGION1_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_M (CPU_APM_REGION1_ADDR_START_V << CPU_APM_REGION1_ADDR_START_S) +#define CPU_APM_REGION1_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_START_S 12 +/** CPU_APM_REGION1_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 1. + */ +#define CPU_APM_REGION1_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_M (CPU_APM_REGION1_ADDR_START_H_V << CPU_APM_REGION1_ADDR_START_H_S) +#define CPU_APM_REGION1_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_START_H_S 19 + +/** CPU_APM_REGION1_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION1_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x14) +/** CPU_APM_REGION1_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_M (CPU_APM_REGION1_ADDR_END_L_V << CPU_APM_REGION1_ADDR_END_L_S) +#define CPU_APM_REGION1_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION1_ADDR_END_L_S 0 +/** CPU_APM_REGION1_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_M (CPU_APM_REGION1_ADDR_END_V << CPU_APM_REGION1_ADDR_END_S) +#define CPU_APM_REGION1_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION1_ADDR_END_S 12 +/** CPU_APM_REGION1_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 1. + */ +#define CPU_APM_REGION1_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_M (CPU_APM_REGION1_ADDR_END_H_V << CPU_APM_REGION1_ADDR_END_H_S) +#define CPU_APM_REGION1_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION1_ADDR_END_H_S 19 + +/** CPU_APM_REGION1_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION1_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x18) +/** CPU_APM_REGION1_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_X (BIT(0)) +#define CPU_APM_REGION1_R0_X_M (CPU_APM_REGION1_R0_X_V << CPU_APM_REGION1_R0_X_S) +#define CPU_APM_REGION1_R0_X_V 0x00000001U +#define CPU_APM_REGION1_R0_X_S 0 +/** CPU_APM_REGION1_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_W (BIT(1)) +#define CPU_APM_REGION1_R0_W_M (CPU_APM_REGION1_R0_W_V << CPU_APM_REGION1_R0_W_S) +#define CPU_APM_REGION1_R0_W_V 0x00000001U +#define CPU_APM_REGION1_R0_W_S 1 +/** CPU_APM_REGION1_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 1. + */ +#define CPU_APM_REGION1_R0_R (BIT(2)) +#define CPU_APM_REGION1_R0_R_M (CPU_APM_REGION1_R0_R_V << CPU_APM_REGION1_R0_R_S) +#define CPU_APM_REGION1_R0_R_V 0x00000001U +#define CPU_APM_REGION1_R0_R_S 2 +/** CPU_APM_REGION1_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_X (BIT(4)) +#define CPU_APM_REGION1_R1_X_M (CPU_APM_REGION1_R1_X_V << CPU_APM_REGION1_R1_X_S) +#define CPU_APM_REGION1_R1_X_V 0x00000001U +#define CPU_APM_REGION1_R1_X_S 4 +/** CPU_APM_REGION1_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_W (BIT(5)) +#define CPU_APM_REGION1_R1_W_M (CPU_APM_REGION1_R1_W_V << CPU_APM_REGION1_R1_W_S) +#define CPU_APM_REGION1_R1_W_V 0x00000001U +#define CPU_APM_REGION1_R1_W_S 5 +/** CPU_APM_REGION1_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 1. + */ +#define CPU_APM_REGION1_R1_R (BIT(6)) +#define CPU_APM_REGION1_R1_R_M (CPU_APM_REGION1_R1_R_V << CPU_APM_REGION1_R1_R_S) +#define CPU_APM_REGION1_R1_R_V 0x00000001U +#define CPU_APM_REGION1_R1_R_S 6 +/** CPU_APM_REGION1_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_X (BIT(8)) +#define CPU_APM_REGION1_R2_X_M (CPU_APM_REGION1_R2_X_V << CPU_APM_REGION1_R2_X_S) +#define CPU_APM_REGION1_R2_X_V 0x00000001U +#define CPU_APM_REGION1_R2_X_S 8 +/** CPU_APM_REGION1_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_W (BIT(9)) +#define CPU_APM_REGION1_R2_W_M (CPU_APM_REGION1_R2_W_V << CPU_APM_REGION1_R2_W_S) +#define CPU_APM_REGION1_R2_W_V 0x00000001U +#define CPU_APM_REGION1_R2_W_S 9 +/** CPU_APM_REGION1_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 1. + */ +#define CPU_APM_REGION1_R2_R (BIT(10)) +#define CPU_APM_REGION1_R2_R_M (CPU_APM_REGION1_R2_R_V << CPU_APM_REGION1_R2_R_S) +#define CPU_APM_REGION1_R2_R_V 0x00000001U +#define CPU_APM_REGION1_R2_R_S 10 +/** CPU_APM_REGION1_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION1_LOCK (BIT(11)) +#define CPU_APM_REGION1_LOCK_M (CPU_APM_REGION1_LOCK_V << CPU_APM_REGION1_LOCK_S) +#define CPU_APM_REGION1_LOCK_V 0x00000001U +#define CPU_APM_REGION1_LOCK_S 11 + +/** CPU_APM_REGION2_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x1c) +/** CPU_APM_REGION2_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_M (CPU_APM_REGION2_ADDR_START_L_V << CPU_APM_REGION2_ADDR_START_L_S) +#define CPU_APM_REGION2_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_START_L_S 0 +/** CPU_APM_REGION2_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_M (CPU_APM_REGION2_ADDR_START_V << CPU_APM_REGION2_ADDR_START_S) +#define CPU_APM_REGION2_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_START_S 12 +/** CPU_APM_REGION2_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 2. + */ +#define CPU_APM_REGION2_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_M (CPU_APM_REGION2_ADDR_START_H_V << CPU_APM_REGION2_ADDR_START_H_S) +#define CPU_APM_REGION2_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_START_H_S 19 + +/** CPU_APM_REGION2_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION2_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x20) +/** CPU_APM_REGION2_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_M (CPU_APM_REGION2_ADDR_END_L_V << CPU_APM_REGION2_ADDR_END_L_S) +#define CPU_APM_REGION2_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION2_ADDR_END_L_S 0 +/** CPU_APM_REGION2_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_M (CPU_APM_REGION2_ADDR_END_V << CPU_APM_REGION2_ADDR_END_S) +#define CPU_APM_REGION2_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION2_ADDR_END_S 12 +/** CPU_APM_REGION2_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 2. + */ +#define CPU_APM_REGION2_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_M (CPU_APM_REGION2_ADDR_END_H_V << CPU_APM_REGION2_ADDR_END_H_S) +#define CPU_APM_REGION2_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION2_ADDR_END_H_S 19 + +/** CPU_APM_REGION2_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION2_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x24) +/** CPU_APM_REGION2_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_X (BIT(0)) +#define CPU_APM_REGION2_R0_X_M (CPU_APM_REGION2_R0_X_V << CPU_APM_REGION2_R0_X_S) +#define CPU_APM_REGION2_R0_X_V 0x00000001U +#define CPU_APM_REGION2_R0_X_S 0 +/** CPU_APM_REGION2_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_W (BIT(1)) +#define CPU_APM_REGION2_R0_W_M (CPU_APM_REGION2_R0_W_V << CPU_APM_REGION2_R0_W_S) +#define CPU_APM_REGION2_R0_W_V 0x00000001U +#define CPU_APM_REGION2_R0_W_S 1 +/** CPU_APM_REGION2_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 2. + */ +#define CPU_APM_REGION2_R0_R (BIT(2)) +#define CPU_APM_REGION2_R0_R_M (CPU_APM_REGION2_R0_R_V << CPU_APM_REGION2_R0_R_S) +#define CPU_APM_REGION2_R0_R_V 0x00000001U +#define CPU_APM_REGION2_R0_R_S 2 +/** CPU_APM_REGION2_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_X (BIT(4)) +#define CPU_APM_REGION2_R1_X_M (CPU_APM_REGION2_R1_X_V << CPU_APM_REGION2_R1_X_S) +#define CPU_APM_REGION2_R1_X_V 0x00000001U +#define CPU_APM_REGION2_R1_X_S 4 +/** CPU_APM_REGION2_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_W (BIT(5)) +#define CPU_APM_REGION2_R1_W_M (CPU_APM_REGION2_R1_W_V << CPU_APM_REGION2_R1_W_S) +#define CPU_APM_REGION2_R1_W_V 0x00000001U +#define CPU_APM_REGION2_R1_W_S 5 +/** CPU_APM_REGION2_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 2. + */ +#define CPU_APM_REGION2_R1_R (BIT(6)) +#define CPU_APM_REGION2_R1_R_M (CPU_APM_REGION2_R1_R_V << CPU_APM_REGION2_R1_R_S) +#define CPU_APM_REGION2_R1_R_V 0x00000001U +#define CPU_APM_REGION2_R1_R_S 6 +/** CPU_APM_REGION2_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_X (BIT(8)) +#define CPU_APM_REGION2_R2_X_M (CPU_APM_REGION2_R2_X_V << CPU_APM_REGION2_R2_X_S) +#define CPU_APM_REGION2_R2_X_V 0x00000001U +#define CPU_APM_REGION2_R2_X_S 8 +/** CPU_APM_REGION2_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_W (BIT(9)) +#define CPU_APM_REGION2_R2_W_M (CPU_APM_REGION2_R2_W_V << CPU_APM_REGION2_R2_W_S) +#define CPU_APM_REGION2_R2_W_V 0x00000001U +#define CPU_APM_REGION2_R2_W_S 9 +/** CPU_APM_REGION2_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 2. + */ +#define CPU_APM_REGION2_R2_R (BIT(10)) +#define CPU_APM_REGION2_R2_R_M (CPU_APM_REGION2_R2_R_V << CPU_APM_REGION2_R2_R_S) +#define CPU_APM_REGION2_R2_R_V 0x00000001U +#define CPU_APM_REGION2_R2_R_S 10 +/** CPU_APM_REGION2_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION2_LOCK (BIT(11)) +#define CPU_APM_REGION2_LOCK_M (CPU_APM_REGION2_LOCK_V << CPU_APM_REGION2_LOCK_S) +#define CPU_APM_REGION2_LOCK_V 0x00000001U +#define CPU_APM_REGION2_LOCK_S 11 + +/** CPU_APM_REGION3_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x28) +/** CPU_APM_REGION3_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_M (CPU_APM_REGION3_ADDR_START_L_V << CPU_APM_REGION3_ADDR_START_L_S) +#define CPU_APM_REGION3_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_START_L_S 0 +/** CPU_APM_REGION3_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_M (CPU_APM_REGION3_ADDR_START_V << CPU_APM_REGION3_ADDR_START_S) +#define CPU_APM_REGION3_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_START_S 12 +/** CPU_APM_REGION3_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 3. + */ +#define CPU_APM_REGION3_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_M (CPU_APM_REGION3_ADDR_START_H_V << CPU_APM_REGION3_ADDR_START_H_S) +#define CPU_APM_REGION3_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_START_H_S 19 + +/** CPU_APM_REGION3_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION3_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x2c) +/** CPU_APM_REGION3_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_M (CPU_APM_REGION3_ADDR_END_L_V << CPU_APM_REGION3_ADDR_END_L_S) +#define CPU_APM_REGION3_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION3_ADDR_END_L_S 0 +/** CPU_APM_REGION3_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_M (CPU_APM_REGION3_ADDR_END_V << CPU_APM_REGION3_ADDR_END_S) +#define CPU_APM_REGION3_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION3_ADDR_END_S 12 +/** CPU_APM_REGION3_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 3. + */ +#define CPU_APM_REGION3_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_M (CPU_APM_REGION3_ADDR_END_H_V << CPU_APM_REGION3_ADDR_END_H_S) +#define CPU_APM_REGION3_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION3_ADDR_END_H_S 19 + +/** CPU_APM_REGION3_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION3_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x30) +/** CPU_APM_REGION3_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_X (BIT(0)) +#define CPU_APM_REGION3_R0_X_M (CPU_APM_REGION3_R0_X_V << CPU_APM_REGION3_R0_X_S) +#define CPU_APM_REGION3_R0_X_V 0x00000001U +#define CPU_APM_REGION3_R0_X_S 0 +/** CPU_APM_REGION3_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_W (BIT(1)) +#define CPU_APM_REGION3_R0_W_M (CPU_APM_REGION3_R0_W_V << CPU_APM_REGION3_R0_W_S) +#define CPU_APM_REGION3_R0_W_V 0x00000001U +#define CPU_APM_REGION3_R0_W_S 1 +/** CPU_APM_REGION3_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 3. + */ +#define CPU_APM_REGION3_R0_R (BIT(2)) +#define CPU_APM_REGION3_R0_R_M (CPU_APM_REGION3_R0_R_V << CPU_APM_REGION3_R0_R_S) +#define CPU_APM_REGION3_R0_R_V 0x00000001U +#define CPU_APM_REGION3_R0_R_S 2 +/** CPU_APM_REGION3_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_X (BIT(4)) +#define CPU_APM_REGION3_R1_X_M (CPU_APM_REGION3_R1_X_V << CPU_APM_REGION3_R1_X_S) +#define CPU_APM_REGION3_R1_X_V 0x00000001U +#define CPU_APM_REGION3_R1_X_S 4 +/** CPU_APM_REGION3_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_W (BIT(5)) +#define CPU_APM_REGION3_R1_W_M (CPU_APM_REGION3_R1_W_V << CPU_APM_REGION3_R1_W_S) +#define CPU_APM_REGION3_R1_W_V 0x00000001U +#define CPU_APM_REGION3_R1_W_S 5 +/** CPU_APM_REGION3_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 3. + */ +#define CPU_APM_REGION3_R1_R (BIT(6)) +#define CPU_APM_REGION3_R1_R_M (CPU_APM_REGION3_R1_R_V << CPU_APM_REGION3_R1_R_S) +#define CPU_APM_REGION3_R1_R_V 0x00000001U +#define CPU_APM_REGION3_R1_R_S 6 +/** CPU_APM_REGION3_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_X (BIT(8)) +#define CPU_APM_REGION3_R2_X_M (CPU_APM_REGION3_R2_X_V << CPU_APM_REGION3_R2_X_S) +#define CPU_APM_REGION3_R2_X_V 0x00000001U +#define CPU_APM_REGION3_R2_X_S 8 +/** CPU_APM_REGION3_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_W (BIT(9)) +#define CPU_APM_REGION3_R2_W_M (CPU_APM_REGION3_R2_W_V << CPU_APM_REGION3_R2_W_S) +#define CPU_APM_REGION3_R2_W_V 0x00000001U +#define CPU_APM_REGION3_R2_W_S 9 +/** CPU_APM_REGION3_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 3. + */ +#define CPU_APM_REGION3_R2_R (BIT(10)) +#define CPU_APM_REGION3_R2_R_M (CPU_APM_REGION3_R2_R_V << CPU_APM_REGION3_R2_R_S) +#define CPU_APM_REGION3_R2_R_V 0x00000001U +#define CPU_APM_REGION3_R2_R_S 10 +/** CPU_APM_REGION3_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION3_LOCK (BIT(11)) +#define CPU_APM_REGION3_LOCK_M (CPU_APM_REGION3_LOCK_V << CPU_APM_REGION3_LOCK_S) +#define CPU_APM_REGION3_LOCK_V 0x00000001U +#define CPU_APM_REGION3_LOCK_S 11 + +/** CPU_APM_REGION4_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x34) +/** CPU_APM_REGION4_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_M (CPU_APM_REGION4_ADDR_START_L_V << CPU_APM_REGION4_ADDR_START_L_S) +#define CPU_APM_REGION4_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_START_L_S 0 +/** CPU_APM_REGION4_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_M (CPU_APM_REGION4_ADDR_START_V << CPU_APM_REGION4_ADDR_START_S) +#define CPU_APM_REGION4_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_START_S 12 +/** CPU_APM_REGION4_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 4. + */ +#define CPU_APM_REGION4_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_M (CPU_APM_REGION4_ADDR_START_H_V << CPU_APM_REGION4_ADDR_START_H_S) +#define CPU_APM_REGION4_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_START_H_S 19 + +/** CPU_APM_REGION4_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION4_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x38) +/** CPU_APM_REGION4_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_M (CPU_APM_REGION4_ADDR_END_L_V << CPU_APM_REGION4_ADDR_END_L_S) +#define CPU_APM_REGION4_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION4_ADDR_END_L_S 0 +/** CPU_APM_REGION4_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_M (CPU_APM_REGION4_ADDR_END_V << CPU_APM_REGION4_ADDR_END_S) +#define CPU_APM_REGION4_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION4_ADDR_END_S 12 +/** CPU_APM_REGION4_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 4. + */ +#define CPU_APM_REGION4_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_M (CPU_APM_REGION4_ADDR_END_H_V << CPU_APM_REGION4_ADDR_END_H_S) +#define CPU_APM_REGION4_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION4_ADDR_END_H_S 19 + +/** CPU_APM_REGION4_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION4_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x3c) +/** CPU_APM_REGION4_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_X (BIT(0)) +#define CPU_APM_REGION4_R0_X_M (CPU_APM_REGION4_R0_X_V << CPU_APM_REGION4_R0_X_S) +#define CPU_APM_REGION4_R0_X_V 0x00000001U +#define CPU_APM_REGION4_R0_X_S 0 +/** CPU_APM_REGION4_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_W (BIT(1)) +#define CPU_APM_REGION4_R0_W_M (CPU_APM_REGION4_R0_W_V << CPU_APM_REGION4_R0_W_S) +#define CPU_APM_REGION4_R0_W_V 0x00000001U +#define CPU_APM_REGION4_R0_W_S 1 +/** CPU_APM_REGION4_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 4. + */ +#define CPU_APM_REGION4_R0_R (BIT(2)) +#define CPU_APM_REGION4_R0_R_M (CPU_APM_REGION4_R0_R_V << CPU_APM_REGION4_R0_R_S) +#define CPU_APM_REGION4_R0_R_V 0x00000001U +#define CPU_APM_REGION4_R0_R_S 2 +/** CPU_APM_REGION4_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_X (BIT(4)) +#define CPU_APM_REGION4_R1_X_M (CPU_APM_REGION4_R1_X_V << CPU_APM_REGION4_R1_X_S) +#define CPU_APM_REGION4_R1_X_V 0x00000001U +#define CPU_APM_REGION4_R1_X_S 4 +/** CPU_APM_REGION4_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_W (BIT(5)) +#define CPU_APM_REGION4_R1_W_M (CPU_APM_REGION4_R1_W_V << CPU_APM_REGION4_R1_W_S) +#define CPU_APM_REGION4_R1_W_V 0x00000001U +#define CPU_APM_REGION4_R1_W_S 5 +/** CPU_APM_REGION4_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 4. + */ +#define CPU_APM_REGION4_R1_R (BIT(6)) +#define CPU_APM_REGION4_R1_R_M (CPU_APM_REGION4_R1_R_V << CPU_APM_REGION4_R1_R_S) +#define CPU_APM_REGION4_R1_R_V 0x00000001U +#define CPU_APM_REGION4_R1_R_S 6 +/** CPU_APM_REGION4_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_X (BIT(8)) +#define CPU_APM_REGION4_R2_X_M (CPU_APM_REGION4_R2_X_V << CPU_APM_REGION4_R2_X_S) +#define CPU_APM_REGION4_R2_X_V 0x00000001U +#define CPU_APM_REGION4_R2_X_S 8 +/** CPU_APM_REGION4_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_W (BIT(9)) +#define CPU_APM_REGION4_R2_W_M (CPU_APM_REGION4_R2_W_V << CPU_APM_REGION4_R2_W_S) +#define CPU_APM_REGION4_R2_W_V 0x00000001U +#define CPU_APM_REGION4_R2_W_S 9 +/** CPU_APM_REGION4_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 4. + */ +#define CPU_APM_REGION4_R2_R (BIT(10)) +#define CPU_APM_REGION4_R2_R_M (CPU_APM_REGION4_R2_R_V << CPU_APM_REGION4_R2_R_S) +#define CPU_APM_REGION4_R2_R_V 0x00000001U +#define CPU_APM_REGION4_R2_R_S 10 +/** CPU_APM_REGION4_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION4_LOCK (BIT(11)) +#define CPU_APM_REGION4_LOCK_M (CPU_APM_REGION4_LOCK_V << CPU_APM_REGION4_LOCK_S) +#define CPU_APM_REGION4_LOCK_V 0x00000001U +#define CPU_APM_REGION4_LOCK_S 11 + +/** CPU_APM_REGION5_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x40) +/** CPU_APM_REGION5_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_M (CPU_APM_REGION5_ADDR_START_L_V << CPU_APM_REGION5_ADDR_START_L_S) +#define CPU_APM_REGION5_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_START_L_S 0 +/** CPU_APM_REGION5_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_M (CPU_APM_REGION5_ADDR_START_V << CPU_APM_REGION5_ADDR_START_S) +#define CPU_APM_REGION5_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_START_S 12 +/** CPU_APM_REGION5_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 5. + */ +#define CPU_APM_REGION5_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_M (CPU_APM_REGION5_ADDR_START_H_V << CPU_APM_REGION5_ADDR_START_H_S) +#define CPU_APM_REGION5_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_START_H_S 19 + +/** CPU_APM_REGION5_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION5_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x44) +/** CPU_APM_REGION5_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_M (CPU_APM_REGION5_ADDR_END_L_V << CPU_APM_REGION5_ADDR_END_L_S) +#define CPU_APM_REGION5_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION5_ADDR_END_L_S 0 +/** CPU_APM_REGION5_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_M (CPU_APM_REGION5_ADDR_END_V << CPU_APM_REGION5_ADDR_END_S) +#define CPU_APM_REGION5_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION5_ADDR_END_S 12 +/** CPU_APM_REGION5_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 5. + */ +#define CPU_APM_REGION5_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_M (CPU_APM_REGION5_ADDR_END_H_V << CPU_APM_REGION5_ADDR_END_H_S) +#define CPU_APM_REGION5_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION5_ADDR_END_H_S 19 + +/** CPU_APM_REGION5_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION5_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x48) +/** CPU_APM_REGION5_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_X (BIT(0)) +#define CPU_APM_REGION5_R0_X_M (CPU_APM_REGION5_R0_X_V << CPU_APM_REGION5_R0_X_S) +#define CPU_APM_REGION5_R0_X_V 0x00000001U +#define CPU_APM_REGION5_R0_X_S 0 +/** CPU_APM_REGION5_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_W (BIT(1)) +#define CPU_APM_REGION5_R0_W_M (CPU_APM_REGION5_R0_W_V << CPU_APM_REGION5_R0_W_S) +#define CPU_APM_REGION5_R0_W_V 0x00000001U +#define CPU_APM_REGION5_R0_W_S 1 +/** CPU_APM_REGION5_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 5. + */ +#define CPU_APM_REGION5_R0_R (BIT(2)) +#define CPU_APM_REGION5_R0_R_M (CPU_APM_REGION5_R0_R_V << CPU_APM_REGION5_R0_R_S) +#define CPU_APM_REGION5_R0_R_V 0x00000001U +#define CPU_APM_REGION5_R0_R_S 2 +/** CPU_APM_REGION5_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_X (BIT(4)) +#define CPU_APM_REGION5_R1_X_M (CPU_APM_REGION5_R1_X_V << CPU_APM_REGION5_R1_X_S) +#define CPU_APM_REGION5_R1_X_V 0x00000001U +#define CPU_APM_REGION5_R1_X_S 4 +/** CPU_APM_REGION5_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_W (BIT(5)) +#define CPU_APM_REGION5_R1_W_M (CPU_APM_REGION5_R1_W_V << CPU_APM_REGION5_R1_W_S) +#define CPU_APM_REGION5_R1_W_V 0x00000001U +#define CPU_APM_REGION5_R1_W_S 5 +/** CPU_APM_REGION5_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 5. + */ +#define CPU_APM_REGION5_R1_R (BIT(6)) +#define CPU_APM_REGION5_R1_R_M (CPU_APM_REGION5_R1_R_V << CPU_APM_REGION5_R1_R_S) +#define CPU_APM_REGION5_R1_R_V 0x00000001U +#define CPU_APM_REGION5_R1_R_S 6 +/** CPU_APM_REGION5_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_X (BIT(8)) +#define CPU_APM_REGION5_R2_X_M (CPU_APM_REGION5_R2_X_V << CPU_APM_REGION5_R2_X_S) +#define CPU_APM_REGION5_R2_X_V 0x00000001U +#define CPU_APM_REGION5_R2_X_S 8 +/** CPU_APM_REGION5_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_W (BIT(9)) +#define CPU_APM_REGION5_R2_W_M (CPU_APM_REGION5_R2_W_V << CPU_APM_REGION5_R2_W_S) +#define CPU_APM_REGION5_R2_W_V 0x00000001U +#define CPU_APM_REGION5_R2_W_S 9 +/** CPU_APM_REGION5_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 5. + */ +#define CPU_APM_REGION5_R2_R (BIT(10)) +#define CPU_APM_REGION5_R2_R_M (CPU_APM_REGION5_R2_R_V << CPU_APM_REGION5_R2_R_S) +#define CPU_APM_REGION5_R2_R_V 0x00000001U +#define CPU_APM_REGION5_R2_R_S 10 +/** CPU_APM_REGION5_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION5_LOCK (BIT(11)) +#define CPU_APM_REGION5_LOCK_M (CPU_APM_REGION5_LOCK_V << CPU_APM_REGION5_LOCK_S) +#define CPU_APM_REGION5_LOCK_V 0x00000001U +#define CPU_APM_REGION5_LOCK_S 11 + +/** CPU_APM_REGION6_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x4c) +/** CPU_APM_REGION6_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_M (CPU_APM_REGION6_ADDR_START_L_V << CPU_APM_REGION6_ADDR_START_L_S) +#define CPU_APM_REGION6_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_START_L_S 0 +/** CPU_APM_REGION6_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_M (CPU_APM_REGION6_ADDR_START_V << CPU_APM_REGION6_ADDR_START_S) +#define CPU_APM_REGION6_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_START_S 12 +/** CPU_APM_REGION6_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 6. + */ +#define CPU_APM_REGION6_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_M (CPU_APM_REGION6_ADDR_START_H_V << CPU_APM_REGION6_ADDR_START_H_S) +#define CPU_APM_REGION6_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_START_H_S 19 + +/** CPU_APM_REGION6_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION6_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x50) +/** CPU_APM_REGION6_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_M (CPU_APM_REGION6_ADDR_END_L_V << CPU_APM_REGION6_ADDR_END_L_S) +#define CPU_APM_REGION6_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION6_ADDR_END_L_S 0 +/** CPU_APM_REGION6_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_M (CPU_APM_REGION6_ADDR_END_V << CPU_APM_REGION6_ADDR_END_S) +#define CPU_APM_REGION6_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION6_ADDR_END_S 12 +/** CPU_APM_REGION6_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 6. + */ +#define CPU_APM_REGION6_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_M (CPU_APM_REGION6_ADDR_END_H_V << CPU_APM_REGION6_ADDR_END_H_S) +#define CPU_APM_REGION6_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION6_ADDR_END_H_S 19 + +/** CPU_APM_REGION6_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION6_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x54) +/** CPU_APM_REGION6_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_X (BIT(0)) +#define CPU_APM_REGION6_R0_X_M (CPU_APM_REGION6_R0_X_V << CPU_APM_REGION6_R0_X_S) +#define CPU_APM_REGION6_R0_X_V 0x00000001U +#define CPU_APM_REGION6_R0_X_S 0 +/** CPU_APM_REGION6_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_W (BIT(1)) +#define CPU_APM_REGION6_R0_W_M (CPU_APM_REGION6_R0_W_V << CPU_APM_REGION6_R0_W_S) +#define CPU_APM_REGION6_R0_W_V 0x00000001U +#define CPU_APM_REGION6_R0_W_S 1 +/** CPU_APM_REGION6_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 6. + */ +#define CPU_APM_REGION6_R0_R (BIT(2)) +#define CPU_APM_REGION6_R0_R_M (CPU_APM_REGION6_R0_R_V << CPU_APM_REGION6_R0_R_S) +#define CPU_APM_REGION6_R0_R_V 0x00000001U +#define CPU_APM_REGION6_R0_R_S 2 +/** CPU_APM_REGION6_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_X (BIT(4)) +#define CPU_APM_REGION6_R1_X_M (CPU_APM_REGION6_R1_X_V << CPU_APM_REGION6_R1_X_S) +#define CPU_APM_REGION6_R1_X_V 0x00000001U +#define CPU_APM_REGION6_R1_X_S 4 +/** CPU_APM_REGION6_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_W (BIT(5)) +#define CPU_APM_REGION6_R1_W_M (CPU_APM_REGION6_R1_W_V << CPU_APM_REGION6_R1_W_S) +#define CPU_APM_REGION6_R1_W_V 0x00000001U +#define CPU_APM_REGION6_R1_W_S 5 +/** CPU_APM_REGION6_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 6. + */ +#define CPU_APM_REGION6_R1_R (BIT(6)) +#define CPU_APM_REGION6_R1_R_M (CPU_APM_REGION6_R1_R_V << CPU_APM_REGION6_R1_R_S) +#define CPU_APM_REGION6_R1_R_V 0x00000001U +#define CPU_APM_REGION6_R1_R_S 6 +/** CPU_APM_REGION6_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_X (BIT(8)) +#define CPU_APM_REGION6_R2_X_M (CPU_APM_REGION6_R2_X_V << CPU_APM_REGION6_R2_X_S) +#define CPU_APM_REGION6_R2_X_V 0x00000001U +#define CPU_APM_REGION6_R2_X_S 8 +/** CPU_APM_REGION6_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_W (BIT(9)) +#define CPU_APM_REGION6_R2_W_M (CPU_APM_REGION6_R2_W_V << CPU_APM_REGION6_R2_W_S) +#define CPU_APM_REGION6_R2_W_V 0x00000001U +#define CPU_APM_REGION6_R2_W_S 9 +/** CPU_APM_REGION6_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 6. + */ +#define CPU_APM_REGION6_R2_R (BIT(10)) +#define CPU_APM_REGION6_R2_R_M (CPU_APM_REGION6_R2_R_V << CPU_APM_REGION6_R2_R_S) +#define CPU_APM_REGION6_R2_R_V 0x00000001U +#define CPU_APM_REGION6_R2_R_S 10 +/** CPU_APM_REGION6_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION6_LOCK (BIT(11)) +#define CPU_APM_REGION6_LOCK_M (CPU_APM_REGION6_LOCK_V << CPU_APM_REGION6_LOCK_S) +#define CPU_APM_REGION6_LOCK_V 0x00000001U +#define CPU_APM_REGION6_LOCK_S 11 + +/** CPU_APM_REGION7_ADDR_START_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_START_REG (DR_REG_CPU_APM_REG_BASE + 0x58) +/** CPU_APM_REGION7_ADDR_START_L : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_M (CPU_APM_REGION7_ADDR_START_L_V << CPU_APM_REGION7_ADDR_START_L_S) +#define CPU_APM_REGION7_ADDR_START_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_START_L_S 0 +/** CPU_APM_REGION7_ADDR_START : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_M (CPU_APM_REGION7_ADDR_START_V << CPU_APM_REGION7_ADDR_START_S) +#define CPU_APM_REGION7_ADDR_START_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_START_S 12 +/** CPU_APM_REGION7_ADDR_START_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region 7. + */ +#define CPU_APM_REGION7_ADDR_START_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_M (CPU_APM_REGION7_ADDR_START_H_V << CPU_APM_REGION7_ADDR_START_H_S) +#define CPU_APM_REGION7_ADDR_START_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_START_H_S 19 + +/** CPU_APM_REGION7_ADDR_END_REG register + * Region address register + */ +#define CPU_APM_REGION7_ADDR_END_REG (DR_REG_CPU_APM_REG_BASE + 0x5c) +/** CPU_APM_REGION7_ADDR_END_L : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_L 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_M (CPU_APM_REGION7_ADDR_END_L_V << CPU_APM_REGION7_ADDR_END_L_S) +#define CPU_APM_REGION7_ADDR_END_L_V 0x00000FFFU +#define CPU_APM_REGION7_ADDR_END_L_S 0 +/** CPU_APM_REGION7_ADDR_END : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_M (CPU_APM_REGION7_ADDR_END_V << CPU_APM_REGION7_ADDR_END_S) +#define CPU_APM_REGION7_ADDR_END_V 0x0000007FU +#define CPU_APM_REGION7_ADDR_END_S 12 +/** CPU_APM_REGION7_ADDR_END_H : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region 7. + */ +#define CPU_APM_REGION7_ADDR_END_H 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_M (CPU_APM_REGION7_ADDR_END_H_V << CPU_APM_REGION7_ADDR_END_H_S) +#define CPU_APM_REGION7_ADDR_END_H_V 0x00001FFFU +#define CPU_APM_REGION7_ADDR_END_H_S 19 + +/** CPU_APM_REGION7_ATTR_REG register + * Region access authority attribute register + */ +#define CPU_APM_REGION7_ATTR_REG (DR_REG_CPU_APM_REG_BASE + 0x60) +/** CPU_APM_REGION7_R0_X : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_X (BIT(0)) +#define CPU_APM_REGION7_R0_X_M (CPU_APM_REGION7_R0_X_V << CPU_APM_REGION7_R0_X_S) +#define CPU_APM_REGION7_R0_X_V 0x00000001U +#define CPU_APM_REGION7_R0_X_S 0 +/** CPU_APM_REGION7_R0_W : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_W (BIT(1)) +#define CPU_APM_REGION7_R0_W_M (CPU_APM_REGION7_R0_W_V << CPU_APM_REGION7_R0_W_S) +#define CPU_APM_REGION7_R0_W_V 0x00000001U +#define CPU_APM_REGION7_R0_W_S 1 +/** CPU_APM_REGION7_R0_R : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region 7. + */ +#define CPU_APM_REGION7_R0_R (BIT(2)) +#define CPU_APM_REGION7_R0_R_M (CPU_APM_REGION7_R0_R_V << CPU_APM_REGION7_R0_R_S) +#define CPU_APM_REGION7_R0_R_V 0x00000001U +#define CPU_APM_REGION7_R0_R_S 2 +/** CPU_APM_REGION7_R1_X : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_X (BIT(4)) +#define CPU_APM_REGION7_R1_X_M (CPU_APM_REGION7_R1_X_V << CPU_APM_REGION7_R1_X_S) +#define CPU_APM_REGION7_R1_X_V 0x00000001U +#define CPU_APM_REGION7_R1_X_S 4 +/** CPU_APM_REGION7_R1_W : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_W (BIT(5)) +#define CPU_APM_REGION7_R1_W_M (CPU_APM_REGION7_R1_W_V << CPU_APM_REGION7_R1_W_S) +#define CPU_APM_REGION7_R1_W_V 0x00000001U +#define CPU_APM_REGION7_R1_W_S 5 +/** CPU_APM_REGION7_R1_R : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region 7. + */ +#define CPU_APM_REGION7_R1_R (BIT(6)) +#define CPU_APM_REGION7_R1_R_M (CPU_APM_REGION7_R1_R_V << CPU_APM_REGION7_R1_R_S) +#define CPU_APM_REGION7_R1_R_V 0x00000001U +#define CPU_APM_REGION7_R1_R_S 6 +/** CPU_APM_REGION7_R2_X : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_X (BIT(8)) +#define CPU_APM_REGION7_R2_X_M (CPU_APM_REGION7_R2_X_V << CPU_APM_REGION7_R2_X_S) +#define CPU_APM_REGION7_R2_X_V 0x00000001U +#define CPU_APM_REGION7_R2_X_S 8 +/** CPU_APM_REGION7_R2_W : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_W (BIT(9)) +#define CPU_APM_REGION7_R2_W_M (CPU_APM_REGION7_R2_W_V << CPU_APM_REGION7_R2_W_S) +#define CPU_APM_REGION7_R2_W_V 0x00000001U +#define CPU_APM_REGION7_R2_W_S 9 +/** CPU_APM_REGION7_R2_R : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region 7. + */ +#define CPU_APM_REGION7_R2_R (BIT(10)) +#define CPU_APM_REGION7_R2_R_M (CPU_APM_REGION7_R2_R_V << CPU_APM_REGION7_R2_R_S) +#define CPU_APM_REGION7_R2_R_V 0x00000001U +#define CPU_APM_REGION7_R2_R_S 10 +/** CPU_APM_REGION7_LOCK : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ +#define CPU_APM_REGION7_LOCK (BIT(11)) +#define CPU_APM_REGION7_LOCK_M (CPU_APM_REGION7_LOCK_V << CPU_APM_REGION7_LOCK_S) +#define CPU_APM_REGION7_LOCK_V 0x00000001U +#define CPU_APM_REGION7_LOCK_S 11 + +/** CPU_APM_FUNC_CTRL_REG register + * APM function control register + */ +#define CPU_APM_FUNC_CTRL_REG (DR_REG_CPU_APM_REG_BASE + 0xc4) +/** CPU_APM_M0_FUNC_EN : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ +#define CPU_APM_M0_FUNC_EN (BIT(0)) +#define CPU_APM_M0_FUNC_EN_M (CPU_APM_M0_FUNC_EN_V << CPU_APM_M0_FUNC_EN_S) +#define CPU_APM_M0_FUNC_EN_V 0x00000001U +#define CPU_APM_M0_FUNC_EN_S 0 +/** CPU_APM_M1_FUNC_EN : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ +#define CPU_APM_M1_FUNC_EN (BIT(1)) +#define CPU_APM_M1_FUNC_EN_M (CPU_APM_M1_FUNC_EN_V << CPU_APM_M1_FUNC_EN_S) +#define CPU_APM_M1_FUNC_EN_V 0x00000001U +#define CPU_APM_M1_FUNC_EN_S 1 + +/** CPU_APM_M0_STATUS_REG register + * M0 status register + */ +#define CPU_APM_M0_STATUS_REG (DR_REG_CPU_APM_REG_BASE + 0xc8) +/** CPU_APM_M0_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M0_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_M (CPU_APM_M0_EXCEPTION_STATUS_V << CPU_APM_M0_EXCEPTION_STATUS_S) +#define CPU_APM_M0_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M0_STATUS_CLR_REG register + * M0 status clear register + */ +#define CPU_APM_M0_STATUS_CLR_REG (DR_REG_CPU_APM_REG_BASE + 0xcc) +/** CPU_APM_M0_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M0_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_M (CPU_APM_M0_EXCEPTION_STATUS_CLR_V << CPU_APM_M0_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M0_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M0_EXCEPTION_INFO0_REG register + * M0 exception_info0 register + */ +#define CPU_APM_M0_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_REG_BASE + 0xd0) +/** CPU_APM_M0_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M0_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_M (CPU_APM_M0_EXCEPTION_REGION_V << CPU_APM_M0_EXCEPTION_REGION_S) +#define CPU_APM_M0_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M0_EXCEPTION_REGION_S 0 +/** CPU_APM_M0_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M0_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_M (CPU_APM_M0_EXCEPTION_MODE_V << CPU_APM_M0_EXCEPTION_MODE_S) +#define CPU_APM_M0_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M0_EXCEPTION_MODE_S 16 +/** CPU_APM_M0_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M0_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_M (CPU_APM_M0_EXCEPTION_ID_V << CPU_APM_M0_EXCEPTION_ID_S) +#define CPU_APM_M0_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M0_EXCEPTION_ID_S 18 + +/** CPU_APM_M0_EXCEPTION_INFO1_REG register + * M0 exception_info1 register + */ +#define CPU_APM_M0_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_REG_BASE + 0xd4) +/** CPU_APM_M0_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M0_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_M (CPU_APM_M0_EXCEPTION_ADDR_V << CPU_APM_M0_EXCEPTION_ADDR_S) +#define CPU_APM_M0_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M0_EXCEPTION_ADDR_S 0 + +/** CPU_APM_M1_STATUS_REG register + * M1 status register + */ +#define CPU_APM_M1_STATUS_REG (DR_REG_CPU_APM_REG_BASE + 0xd8) +/** CPU_APM_M1_EXCEPTION_STATUS : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ +#define CPU_APM_M1_EXCEPTION_STATUS 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_M (CPU_APM_M1_EXCEPTION_STATUS_V << CPU_APM_M1_EXCEPTION_STATUS_S) +#define CPU_APM_M1_EXCEPTION_STATUS_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_STATUS_S 0 + +/** CPU_APM_M1_STATUS_CLR_REG register + * M1 status clear register + */ +#define CPU_APM_M1_STATUS_CLR_REG (DR_REG_CPU_APM_REG_BASE + 0xdc) +/** CPU_APM_M1_EXCEPTION_STATUS_CLR : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ +#define CPU_APM_M1_EXCEPTION_STATUS_CLR (BIT(0)) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_M (CPU_APM_M1_EXCEPTION_STATUS_CLR_V << CPU_APM_M1_EXCEPTION_STATUS_CLR_S) +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_V 0x00000001U +#define CPU_APM_M1_EXCEPTION_STATUS_CLR_S 0 + +/** CPU_APM_M1_EXCEPTION_INFO0_REG register + * M1 exception_info0 register + */ +#define CPU_APM_M1_EXCEPTION_INFO0_REG (DR_REG_CPU_APM_REG_BASE + 0xe0) +/** CPU_APM_M1_EXCEPTION_REGION : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ +#define CPU_APM_M1_EXCEPTION_REGION 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_M (CPU_APM_M1_EXCEPTION_REGION_V << CPU_APM_M1_EXCEPTION_REGION_S) +#define CPU_APM_M1_EXCEPTION_REGION_V 0x0000FFFFU +#define CPU_APM_M1_EXCEPTION_REGION_S 0 +/** CPU_APM_M1_EXCEPTION_MODE : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ +#define CPU_APM_M1_EXCEPTION_MODE 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_M (CPU_APM_M1_EXCEPTION_MODE_V << CPU_APM_M1_EXCEPTION_MODE_S) +#define CPU_APM_M1_EXCEPTION_MODE_V 0x00000003U +#define CPU_APM_M1_EXCEPTION_MODE_S 16 +/** CPU_APM_M1_EXCEPTION_ID : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ +#define CPU_APM_M1_EXCEPTION_ID 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_M (CPU_APM_M1_EXCEPTION_ID_V << CPU_APM_M1_EXCEPTION_ID_S) +#define CPU_APM_M1_EXCEPTION_ID_V 0x0000001FU +#define CPU_APM_M1_EXCEPTION_ID_S 18 + +/** CPU_APM_M1_EXCEPTION_INFO1_REG register + * M1 exception_info1 register + */ +#define CPU_APM_M1_EXCEPTION_INFO1_REG (DR_REG_CPU_APM_REG_BASE + 0xe4) +/** CPU_APM_M1_EXCEPTION_ADDR : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ +#define CPU_APM_M1_EXCEPTION_ADDR 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_M (CPU_APM_M1_EXCEPTION_ADDR_V << CPU_APM_M1_EXCEPTION_ADDR_S) +#define CPU_APM_M1_EXCEPTION_ADDR_V 0xFFFFFFFFU +#define CPU_APM_M1_EXCEPTION_ADDR_S 0 + +/** CPU_APM_INT_EN_REG register + * APM interrupt enable register + */ +#define CPU_APM_INT_EN_REG (DR_REG_CPU_APM_REG_BASE + 0x118) +/** CPU_APM_M0_APM_INT_EN : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M0_APM_INT_EN (BIT(0)) +#define CPU_APM_M0_APM_INT_EN_M (CPU_APM_M0_APM_INT_EN_V << CPU_APM_M0_APM_INT_EN_S) +#define CPU_APM_M0_APM_INT_EN_V 0x00000001U +#define CPU_APM_M0_APM_INT_EN_S 0 +/** CPU_APM_M1_APM_INT_EN : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ +#define CPU_APM_M1_APM_INT_EN (BIT(1)) +#define CPU_APM_M1_APM_INT_EN_M (CPU_APM_M1_APM_INT_EN_V << CPU_APM_M1_APM_INT_EN_S) +#define CPU_APM_M1_APM_INT_EN_V 0x00000001U +#define CPU_APM_M1_APM_INT_EN_S 1 + +/** CPU_APM_CLOCK_GATE_REG register + * Clock gating register + */ +#define CPU_APM_CLOCK_GATE_REG (DR_REG_CPU_APM_REG_BASE + 0x7f8) +/** CPU_APM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ +#define CPU_APM_CLK_EN (BIT(0)) +#define CPU_APM_CLK_EN_M (CPU_APM_CLK_EN_V << CPU_APM_CLK_EN_S) +#define CPU_APM_CLK_EN_V 0x00000001U +#define CPU_APM_CLK_EN_S 0 + +/** CPU_APM_DATE_REG register + * Version control register + */ +#define CPU_APM_DATE_REG (DR_REG_CPU_APM_REG_BASE + 0x7fc) +/** CPU_APM_DATE : R/W; bitpos: [27:0]; default: 37823248; + * Version control register. + */ +#define CPU_APM_DATE 0x0FFFFFFFU +#define CPU_APM_DATE_M (CPU_APM_DATE_V << CPU_APM_DATE_S) +#define CPU_APM_DATE_V 0x0FFFFFFFU +#define CPU_APM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/cpu_apm_struct.h b/components/soc/esp32c61/register/soc/cpu_apm_struct.h new file mode 100644 index 0000000000..8cb9219a85 --- /dev/null +++ b/components/soc/esp32c61/register/soc/cpu_apm_struct.h @@ -0,0 +1,403 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Region filter enable register */ +/** Type of apm_region_filter_en register + * Region filter enable register + */ +typedef union { + struct { + /** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1; + * Configure bit $n (0-7) to enable region $n. + * 0: disable + * 1: enable + */ + uint32_t apm_region_filter_en:8; + uint32_t reserved_8:24; + }; + uint32_t val; +} cpu_apm_region_filter_en_reg_t; + + +/** Group: Region address register */ +/** Type of apm_regionn_addr_start register + * Region address register + */ +typedef union { + struct { + /** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0; + * Low 12 bit, start address of region n. + */ + uint32_t apm_regionn_addr_start_l:12; + /** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0; + * Configures start address of region n. + */ + uint32_t apm_regionn_addr_start:7; + /** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, start address of region n. + */ + uint32_t apm_regionn_addr_start_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_start_reg_t; + +/** Type of apm_regionn_addr_end register + * Region address register + */ +typedef union { + struct { + /** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095; + * Low 12 bit, end address of region n. + */ + uint32_t apm_regionn_addr_end_l:12; + /** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127; + * Configures end address of region n. + */ + uint32_t apm_regionn_addr_end:7; + /** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064; + * High 13 bit, end address of region n. + */ + uint32_t apm_regionn_addr_end_h:13; + }; + uint32_t val; +} cpu_apm_regionn_addr_end_reg_t; + + +/** Group: Region access authority attribute register */ +/** Type of apm_regionn_attr register + * Region access authority attribute register + */ +typedef union { + struct { + /** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0; + * Configures the execution authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_x:1; + /** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0; + * Configures the write authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_w:1; + /** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0; + * Configures the read authority of REE_MODE 0 in region n. + */ + uint32_t apm_regionn_r0_r:1; + uint32_t reserved_3:1; + /** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0; + * Configures the execution authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_x:1; + /** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0; + * Configures the write authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_w:1; + /** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0; + * Configures the read authority of REE_MODE 1 in region n. + */ + uint32_t apm_regionn_r1_r:1; + uint32_t reserved_7:1; + /** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0; + * Configures the execution authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_x:1; + /** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0; + * Configures the write authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_w:1; + /** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0; + * Configures the read authority of REE_MODE 2 in region n. + */ + uint32_t apm_regionn_r2_r:1; + /** apm_regionn_lock : R/W; bitpos: [11]; default: 0; + * Set 1 to lock region0 configuration + */ + uint32_t apm_regionn_lock:1; + uint32_t reserved_12:20; + }; + uint32_t val; +} cpu_apm_regionn_attr_reg_t; + + +/** Group: function control register */ +/** Type of apm_func_ctrl register + * APM function control register + */ +typedef union { + struct { + /** apm_m0_func_en : R/W; bitpos: [0]; default: 1; + * PMS M0 function enable + */ + uint32_t apm_m0_func_en:1; + /** apm_m1_func_en : R/W; bitpos: [1]; default: 1; + * PMS M1 function enable + */ + uint32_t apm_m1_func_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_func_ctrl_reg_t; + + +/** Group: M0 status register */ +/** Type of apm_m0_status register + * M0 status register + */ +typedef union { + struct { + /** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t apm_m0_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m0_status_reg_t; + + +/** Group: M0 status clear register */ +/** Type of apm_m0_status_clr register + * M0 status clear register + */ +typedef union { + struct { + /** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t apm_m0_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m0_status_clr_reg_t; + + +/** Group: M0 exception_info0 register */ +/** Type of apm_m0_exception_info0 register + * M0 exception_info0 register + */ +typedef union { + struct { + /** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t apm_m0_exception_region:16; + /** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t apm_m0_exception_mode:2; + /** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t apm_m0_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m0_exception_info0_reg_t; + + +/** Group: M0 exception_info1 register */ +/** Type of apm_m0_exception_info1 register + * M0 exception_info1 register + */ +typedef union { + struct { + /** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t apm_m0_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m0_exception_info1_reg_t; + + +/** Group: M1 status register */ +/** Type of apm_m1_status register + * M1 status register + */ +typedef union { + struct { + /** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0; + * Represents exception status. + * bit0: 1 represents authority_exception + * bit1: 1 represents space_exception + */ + uint32_t apm_m1_exception_status:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_m1_status_reg_t; + + +/** Group: M1 status clear register */ +/** Type of apm_m1_status_clr register + * M1 status clear register + */ +typedef union { + struct { + /** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0; + * Configures to clear exception status. + */ + uint32_t apm_m1_exception_status_clr:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_m1_status_clr_reg_t; + + +/** Group: M1 exception_info0 register */ +/** Type of apm_m1_exception_info0 register + * M1 exception_info0 register + */ +typedef union { + struct { + /** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0; + * Represents exception region. + */ + uint32_t apm_m1_exception_region:16; + /** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0; + * Represents exception mode. + */ + uint32_t apm_m1_exception_mode:2; + /** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0; + * Represents exception id information. + */ + uint32_t apm_m1_exception_id:5; + uint32_t reserved_23:9; + }; + uint32_t val; +} cpu_apm_m1_exception_info0_reg_t; + + +/** Group: M1 exception_info1 register */ +/** Type of apm_m1_exception_info1 register + * M1 exception_info1 register + */ +typedef union { + struct { + /** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0; + * Represents exception addr. + */ + uint32_t apm_m1_exception_addr:32; + }; + uint32_t val; +} cpu_apm_m1_exception_info1_reg_t; + + +/** Group: APM interrupt enable register */ +/** Type of apm_int_en register + * APM interrupt enable register + */ +typedef union { + struct { + /** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0; + * Configures to enable APM M0 interrupt. + * 0: disable + * 1: enable + */ + uint32_t apm_m0_apm_int_en:1; + /** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0; + * Configures to enable APM M1 interrupt. + * 0: disable + * 1: enable + */ + uint32_t apm_m1_apm_int_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} cpu_apm_int_en_reg_t; + + +/** Group: Clock gating register */ +/** Type of apm_clock_gate register + * Clock gating register + */ +typedef union { + struct { + /** apm_clk_en : R/W; bitpos: [0]; default: 1; + * Configures whether to keep the clock always on. + * 0: enable automatic clock gating + * 1: keep the clock always on + */ + uint32_t apm_clk_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} cpu_apm_clock_gate_reg_t; + + +/** Group: Version control register */ +/** Type of apm_date register + * Version control register + */ +typedef union { + struct { + /** apm_date : R/W; bitpos: [27:0]; default: 37823248; + * Version control register. + */ + uint32_t apm_date:28; + uint32_t reserved_28:4; + }; + uint32_t val; +} cpu_apm_date_reg_t; + + +typedef struct { + volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en; + volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region0_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region1_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region2_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region3_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region4_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region5_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region6_attr; + volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start; + volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end; + volatile cpu_apm_regionn_attr_reg_t apm_region7_attr; + uint32_t reserved_064[24]; + volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl; + volatile cpu_apm_m0_status_reg_t apm_m0_status; + volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr; + volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0; + volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1; + volatile cpu_apm_m1_status_reg_t apm_m1_status; + volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr; + volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0; + volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1; + uint32_t reserved_0e8[12]; + volatile cpu_apm_int_en_reg_t apm_int_en; + uint32_t reserved_11c[439]; + volatile cpu_apm_clock_gate_reg_t apm_clock_gate; + volatile cpu_apm_date_reg_t apm_date; +} cpu_dev_t; + + +#ifndef __cplusplus +_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/efuse_reg.h b/components/soc/esp32c61/register/soc/efuse_reg.h index fa1866d023..1bf75495d7 100644 --- a/components/soc/esp32c61/register/soc/efuse_reg.h +++ b/components/soc/esp32c61/register/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -169,7 +169,7 @@ extern "C" { #define EFUSE_RD_DIS_V 0x0000007FU #define EFUSE_RD_DIS_S 0 /** EFUSE_DIS_ICACHE : RO; bitpos: [7]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled.\\ 1: Disabled\\ 0: Enabled.\\ */ #define EFUSE_DIS_ICACHE (BIT(7)) #define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) @@ -233,22 +233,24 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14 /** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ #define EFUSE_USB_DREFH 0x00000003U #define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) #define EFUSE_USB_DREFH_V 0x00000003U #define EFUSE_USB_DREFH_S 15 /** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ #define EFUSE_USB_DREFL 0x00000003U #define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) #define EFUSE_USB_DREFL_V 0x00000003U #define EFUSE_USB_DREFL_S 17 /** EFUSE_USB_EXCHG_PINS : RO; bitpos: [19]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.\\ 1: + * exchanged\\ 0: not exchanged\\ */ #define EFUSE_USB_EXCHG_PINS (BIT(19)) #define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) @@ -263,10 +265,8 @@ extern "C" { #define EFUSE_VDD_SPI_AS_GPIO_V 0x00000001U #define EFUSE_VDD_SPI_AS_GPIO_S 20 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [22:21]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ #define EFUSE_WDT_DELAY_SEL 0x00000003U #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) @@ -281,24 +281,24 @@ extern "C" { #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 23 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [26]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking first secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(26)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 26 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [27]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking second secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(27)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 27 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [28]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking third secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(28)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) @@ -366,15 +366,15 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 24 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [26]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. 1. Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_EN (BIT(26)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 26 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [27]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. 1. + * Enable\\ 0: Disable. */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(27)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) @@ -395,23 +395,22 @@ extern "C" { */ #define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE0_BASE + 0x38) /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + * Represents whether Download mode is disable or enable. 1. Disable\\ 0: Enable. */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 0 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: - * Enable\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable\\ 0: Enable. */ #define EFUSE_DIS_DIRECT_BOOT (BIT(1)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. - * Disable\\ 0: Enable\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable\\ + * 0: Enable. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) @@ -426,8 +425,7 @@ extern "C" { #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 3 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [4]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: - * Disable\\ + * Represents whether security download is enabled or disabled. 1: Enable\\ 0: Disable. */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(4)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) @@ -463,47 +461,46 @@ extern "C" { #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 24 /** EFUSE_HYS_EN_PAD : RO; bitpos: [25]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Set bits to enable hysteresis function of PAD0~27 */ #define EFUSE_HYS_EN_PAD (BIT(25)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 25 /** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [26]; default: 0; - * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: - * Disable\\ + * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: + * Disable.\\ */ #define EFUSE_XTS_DPA_CLK_ENABLE (BIT(26)) #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 26 /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [28:27]; default: 0; - * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: - * Low\\ 0: Decided by register configuration\\ + * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: + * Moderate 1. Low\\ 0: Disabled\\ */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 27 /** EFUSE_DIS_WIFI6 : RO; bitpos: [29]; default: 0; - * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is - * disable\\ 0: WiFi 6 is enabled.\\ + * Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable, 0: + * WIFI6 is enabled. */ #define EFUSE_DIS_WIFI6 (BIT(29)) #define EFUSE_DIS_WIFI6_M (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S) #define EFUSE_DIS_WIFI6_V 0x00000001U #define EFUSE_DIS_WIFI6_S 29 /** EFUSE_ECDSA_DISABLE_P192 : RO; bitpos: [30]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled. */ #define EFUSE_ECDSA_DISABLE_P192 (BIT(30)) #define EFUSE_ECDSA_DISABLE_P192_M (EFUSE_ECDSA_DISABLE_P192_V << EFUSE_ECDSA_DISABLE_P192_S) #define EFUSE_ECDSA_DISABLE_P192_V 0x00000001U #define EFUSE_ECDSA_DISABLE_P192_S 30 /** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [31]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. + * Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: + * Disable */ #define EFUSE_ECC_FORCE_CONST_TIME (BIT(31)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) @@ -514,25 +511,65 @@ extern "C" { * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE0_BASE + 0x3c) -/** EFUSE_RD_REPEAT_DATA3 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION : RO; bitpos: [3:0]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader. */ -#define EFUSE_RD_REPEAT_DATA3 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA3_M (EFUSE_RD_REPEAT_DATA3_V << EFUSE_RD_REPEAT_DATA3_S) -#define EFUSE_RD_REPEAT_DATA3_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA3_S 0 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [4]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(4)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 4 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [5]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader.\\1: Enable\\0: Disable\\ + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(5)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S 5 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR : RO; bitpos: [17:6]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S 6 +/** EFUSE_RD_RESERVE_0_146 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_146 0x00003FFFU +#define EFUSE_RD_RESERVE_0_146_M (EFUSE_RD_RESERVE_0_146_V << EFUSE_RD_RESERVE_0_146_S) +#define EFUSE_RD_RESERVE_0_146_V 0x00003FFFU +#define EFUSE_RD_RESERVE_0_146_S 18 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE0_BASE + 0x40) -/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [31:0]; default: 0; +/** EFUSE_RD_REPEAT_DATA4 : RO; bitpos: [23:0]; default: 0; * Reserved. */ -#define EFUSE_RD_REPEAT_DATA4 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4 0x00FFFFFFU #define EFUSE_RD_REPEAT_DATA4_M (EFUSE_RD_REPEAT_DATA4_V << EFUSE_RD_REPEAT_DATA4_S) -#define EFUSE_RD_REPEAT_DATA4_V 0xFFFFFFFFU +#define EFUSE_RD_REPEAT_DATA4_V 0x00FFFFFFU #define EFUSE_RD_REPEAT_DATA4_S 0 +/** EFUSE_RD_RESERVE_0_184 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ +#define EFUSE_RD_RESERVE_0_184 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_M (EFUSE_RD_RESERVE_0_184_V << EFUSE_RD_RESERVE_0_184_S) +#define EFUSE_RD_RESERVE_0_184_V 0x000000FFU +#define EFUSE_RD_RESERVE_0_184_S 24 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -653,32 +690,74 @@ extern "C" { #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) #define EFUSE_PKG_VERSION_V 0x00000007U #define EFUSE_PKG_VERSION_S 26 -/** EFUSE_RESERVED_1_93 : R; bitpos: [31:29]; default: 0; - * reserved +/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [31:29]; default: 0; + * Active HP DBIAS of fixed voltage */ -#define EFUSE_RESERVED_1_93 0x00000007U -#define EFUSE_RESERVED_1_93_M (EFUSE_RESERVED_1_93_V << EFUSE_RESERVED_1_93_S) -#define EFUSE_RESERVED_1_93_V 0x00000007U -#define EFUSE_RESERVED_1_93_S 29 +#define EFUSE_ACTIVE_HP_DBIAS 0x00000007U +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x00000007U +#define EFUSE_ACTIVE_HP_DBIAS_S 29 /** EFUSE_RD_MAC_SYS3_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE0_BASE + 0x50) -/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. +/** EFUSE_ACTIVE_HP_DBIAS_1 : R; bitpos: [0]; default: 0; + * Active HP DBIAS of fixed voltage */ -#define EFUSE_MAC_RESERVED_2 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) -#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU -#define EFUSE_MAC_RESERVED_2_S 0 -/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. +#define EFUSE_ACTIVE_HP_DBIAS_1 (BIT(0)) +#define EFUSE_ACTIVE_HP_DBIAS_1_M (EFUSE_ACTIVE_HP_DBIAS_1_V << EFUSE_ACTIVE_HP_DBIAS_1_S) +#define EFUSE_ACTIVE_HP_DBIAS_1_V 0x00000001U +#define EFUSE_ACTIVE_HP_DBIAS_1_S 0 +/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [4:1]; default: 0; + * Active LP DBIAS of fixed voltage */ -#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU -#define EFUSE_SYS_DATA_PART0_0_S 18 +#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_S 1 +/** EFUSE_LSLP_HP_DBG : R; bitpos: [6:5]; default: 0; + * LSLP HP DBG of fixed voltage + */ +#define EFUSE_LSLP_HP_DBG 0x00000003U +#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S) +#define EFUSE_LSLP_HP_DBG_V 0x00000003U +#define EFUSE_LSLP_HP_DBG_S 5 +/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [10:7]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ +#define EFUSE_LSLP_HP_DBIAS 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) +#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_S 7 +/** EFUSE_DSLP_LP_DBG : R; bitpos: [14:11]; default: 0; + * DSLP LP DBG of fixed voltage + */ +#define EFUSE_DSLP_LP_DBG 0x0000000FU +#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S) +#define EFUSE_DSLP_LP_DBG_V 0x0000000FU +#define EFUSE_DSLP_LP_DBG_S 11 +/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [19:15]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ +#define EFUSE_DSLP_LP_DBIAS 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) +#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_S 15 +/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [24:20]; default: 0; + * DBIAS gap between LP and HP + */ +#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S) +#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 20 +/** EFUSE_RESERVED_1_121 : R; bitpos: [31:25]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_121 0x0000007FU +#define EFUSE_RESERVED_1_121_M (EFUSE_RESERVED_1_121_V << EFUSE_RESERVED_1_121_S) +#define EFUSE_RESERVED_1_121_V 0x0000007FU +#define EFUSE_RESERVED_1_121_S 25 /** EFUSE_RD_MAC_SYS4_REG register * Represents rd_mac_sys @@ -2000,25 +2079,46 @@ extern "C" { * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_DATA_ERR3_REG (DR_REG_EFUSE0_BASE + 0x188) -/** EFUSE_RD_REPEAT_DATA_ERR3 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION */ -#define EFUSE_RD_REPEAT_DATA_ERR3 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR3_M (EFUSE_RD_REPEAT_DATA_ERR3_V << EFUSE_RD_REPEAT_DATA_ERR3_S) -#define EFUSE_RD_REPEAT_DATA_ERR3_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR3_S 0 +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_V 0x0000000FU +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_ERR_S 0 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR (BIT(4)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_ERR_S 4 +/** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR (BIT(5)) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S) +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_V 0x00000001U +#define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_ERR_S 5 +/** EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR : RO; bitpos: [17:6]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR + */ +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S) +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_V 0x00000FFFU +#define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_ERR_S 6 /** EFUSE_RD_REPEAT_DATA_ERR4_REG register * Represents rd_repeat_data_err */ #define EFUSE_RD_REPEAT_DATA_ERR4_REG (DR_REG_EFUSE0_BASE + 0x18c) -/** EFUSE_RD_REPEAT_DATA_ERR4 : RO; bitpos: [31:0]; default: 0; - * Reserved. +/** EFUSE_RD_REPEAT_DATA4_ERR : RO; bitpos: [23:0]; default: 0; + * Represents the programming error of EFUSE_RD_REPEAT_DATA4 */ -#define EFUSE_RD_REPEAT_DATA_ERR4 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR4_M (EFUSE_RD_REPEAT_DATA_ERR4_V << EFUSE_RD_REPEAT_DATA_ERR4_S) -#define EFUSE_RD_REPEAT_DATA_ERR4_V 0xFFFFFFFFU -#define EFUSE_RD_REPEAT_DATA_ERR4_S 0 +#define EFUSE_RD_REPEAT_DATA4_ERR 0x00FFFFFFU +#define EFUSE_RD_REPEAT_DATA4_ERR_M (EFUSE_RD_REPEAT_DATA4_ERR_V << EFUSE_RD_REPEAT_DATA4_ERR_S) +#define EFUSE_RD_REPEAT_DATA4_ERR_V 0x00FFFFFFU +#define EFUSE_RD_REPEAT_DATA4_ERR_S 0 /** EFUSE_RD_RS_DATA_ERR0_REG register * Represents rd_rs_data_err @@ -2204,7 +2304,7 @@ extern "C" { * eFuse version register. */ #define EFUSE_DATE_REG (DR_REG_EFUSE0_BASE + 0x198) -/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 37753088; +/** EFUSE_DATE : R/W; bitpos: [27:0]; default: 38801520; * Stores eFuse version. */ #define EFUSE_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/efuse_struct.h b/components/soc/esp32c61/register/soc/efuse_struct.h index 291d8b4565..2994dd8836 100644 --- a/components/soc/esp32c61/register/soc/efuse_struct.h +++ b/components/soc/esp32c61/register/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -183,7 +183,7 @@ typedef union { */ uint32_t rd_dis:7; /** dis_icache : RO; bitpos: [7]; default: 0; - * Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether cache is disabled.\\ 1: Disabled\\ 0: Enabled.\\ */ uint32_t dis_icache:1; /** dis_usb_jtag : RO; bitpos: [8]; default: 0; @@ -223,16 +223,18 @@ typedef union { */ uint32_t dis_download_manual_encrypt:1; /** usb_drefh : RO; bitpos: [16:15]; default: 0; - * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ uint32_t usb_drefh:2; /** usb_drefl : RO; bitpos: [18:17]; default: 0; - * Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV. + * Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY, 1.76 V to 2 + * V with step of 80 mV. */ uint32_t usb_drefl:2; /** usb_exchg_pins : RO; bitpos: [19]; default: 0; - * Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not - * exchanged\\ + * Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.\\ 1: + * exchanged\\ 0: not exchanged\\ */ uint32_t usb_exchg_pins:1; /** vdd_spi_as_gpio : RO; bitpos: [20]; default: 0; @@ -241,10 +243,8 @@ typedef union { */ uint32_t vdd_spi_as_gpio:1; /** wdt_delay_sel : RO; bitpos: [22:21]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * lp wdt timeout threshold at startup = initial timeout value * (2 ^ + * (EFUSE_WDT_DELAY_SEL + 1)) */ uint32_t wdt_delay_sel:2; /** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0; @@ -253,18 +253,18 @@ typedef union { */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking first secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking second secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Represents whether revoking third secure boot key is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_key_revoke2:1; /** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0; @@ -309,12 +309,12 @@ typedef union { */ uint32_t sec_dpa_level:2; /** secure_boot_en : RO; bitpos: [26]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. 1. Enable\\ 0: Disable. */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [27]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. 1. + * Enable\\ 0: Disable. */ uint32_t secure_boot_aggressive_revoke:1; /** flash_tpuw : RO; bitpos: [31:28]; default: 0; @@ -333,17 +333,16 @@ typedef union { typedef union { struct { /** dis_download_mode : RO; bitpos: [0]; default: 0; - * Represents whether Download mode is disable or enable.\\ 1. Disable\\ 0: Enable\\ + * Represents whether Download mode is disable or enable. 1. Disable\\ 0: Enable. */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [1]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1. Disable\\ 0: - * Enable\\ + * Represents whether direct boot mode is disabled or enabled. 1. Disable\\ 0: Enable. */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1. - * Disable\\ 0: Enable\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. 1. Disable\\ + * 0: Enable. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [3]; default: 0; @@ -352,8 +351,7 @@ typedef union { */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [4]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: - * Disable\\ + * Represents whether security download is enabled or disabled. 1: Enable\\ 0: Disable. */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [6:5]; default: 0; @@ -374,32 +372,31 @@ typedef union { */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [25]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Set bits to enable hysteresis function of PAD0~27 */ uint32_t hys_en_pad:1; /** xts_dpa_clk_enable : RO; bitpos: [26]; default: 0; - * Represents whether anti-dpa attack clock function is enabled.\\ 1. Enable\\ 0: - * Disable\\ + * Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: + * Disable.\\ */ uint32_t xts_dpa_clk_enable:1; /** xts_dpa_pseudo_level : RO; bitpos: [28:27]; default: 0; - * Represents the anti-dpa attack pseudo function level.\\ 3:High\\ 2: Moderate\\ 1: - * Low\\ 0: Decided by register configuration\\ + * Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: + * Moderate 1. Low\\ 0: Disabled\\ */ uint32_t xts_dpa_pseudo_level:2; /** dis_wifi6 : RO; bitpos: [29]; default: 0; - * Represents whether the WiFi 6 feature is enable or disable.\\ 1: WiFi 6 is - * disable\\ 0: WiFi 6 is enabled.\\ + * Represents whether the WIFI6 feature is enable or disabled. 1: WIFI6 is disable, 0: + * WIFI6 is enabled. */ uint32_t dis_wifi6:1; /** ecdsa_disable_p192 : RO; bitpos: [30]; default: 0; - * Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable. + * Represents whether to disable P192 curve in ECDSA. 1: Disabled. 0: Not disabled. */ uint32_t ecdsa_disable_p192:1; /** ecc_force_const_time : RO; bitpos: [31]; default: 0; - * Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. - * \\ 0: Disable. + * Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: + * Disable */ uint32_t ecc_force_const_time:1; }; @@ -411,10 +408,31 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data3 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** bootloader_anti_rollback_secure_version : RO; bitpos: [3:0]; default: 0; + * Represents the anti-rollback secure version of the 2nd stage bootloader used by the + * ROM bootloader. */ - uint32_t rd_repeat_data3:32; + uint32_t bootloader_anti_rollback_secure_version:4; + /** bootloader_anti_rollback_en : RO; bitpos: [4]; default: 0; + * Represents whether the ani-rollback check for the 2nd stage bootloader is + * enabled.\\1: Enabled\\0: Disabled\\ + */ + uint32_t bootloader_anti_rollback_en:1; + /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [5]; default: 0; + * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM + * bootloader.\\1: Enable\\0: Disable\\ + */ + uint32_t bootloader_anti_rollback_update_in_rom:1; + /** recovery_bootloader_flash_sector : RO; bitpos: [17:6]; default: 0; + * Represents the starting flash sector (flash sector size is 0x1000) of the recovery + * bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF + * - this feature is disabled. + */ + uint32_t recovery_bootloader_flash_sector:12; + /** rd_reserve_0_146 : RW; bitpos: [31:18]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_146:14; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -424,10 +442,14 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data4 : RO; bitpos: [31:0]; default: 0; + /** rd_repeat_data4 : RO; bitpos: [23:0]; default: 0; * Reserved. */ - uint32_t rd_repeat_data4:32; + uint32_t rd_repeat_data4:24; + /** rd_reserve_0_184 : RW; bitpos: [31:24]; default: 0; + * Reserved, it was created by set_missed_fields_in_regs func + */ + uint32_t rd_reserve_0_184:8; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -517,10 +539,10 @@ typedef union { * Package version */ uint32_t pkg_version:3; - /** reserved_1_93 : R; bitpos: [31:29]; default: 0; - * reserved + /** active_hp_dbias : R; bitpos: [31:29]; default: 0; + * Active HP DBIAS of fixed voltage */ - uint32_t reserved_1_93:3; + uint32_t active_hp_dbias:3; }; uint32_t val; } efuse_rd_mac_sys2_reg_t; @@ -530,14 +552,38 @@ typedef union { */ typedef union { struct { - /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; - * Reserved. + /** active_hp_dbias_1 : R; bitpos: [0]; default: 0; + * Active HP DBIAS of fixed voltage */ - uint32_t mac_reserved_2:18; - /** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0; - * Represents the first 14-bit of zeroth part of system data. + uint32_t active_hp_dbias_1:1; + /** active_lp_dbias : R; bitpos: [4:1]; default: 0; + * Active LP DBIAS of fixed voltage */ - uint32_t sys_data_part0_0:14; + uint32_t active_lp_dbias:4; + /** lslp_hp_dbg : R; bitpos: [6:5]; default: 0; + * LSLP HP DBG of fixed voltage + */ + uint32_t lslp_hp_dbg:2; + /** lslp_hp_dbias : R; bitpos: [10:7]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ + uint32_t lslp_hp_dbias:4; + /** dslp_lp_dbg : R; bitpos: [14:11]; default: 0; + * DSLP LP DBG of fixed voltage + */ + uint32_t dslp_lp_dbg:4; + /** dslp_lp_dbias : R; bitpos: [19:15]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ + uint32_t dslp_lp_dbias:5; + /** lp_hp_dbias_vol_gap : R; bitpos: [24:20]; default: 0; + * DBIAS gap between LP and HP + */ + uint32_t lp_hp_dbias_vol_gap:5; + /** reserved_1_121 : R; bitpos: [31:25]; default: 0; + * reserved + */ + uint32_t reserved_1_121:7; }; uint32_t val; } efuse_rd_mac_sys3_reg_t; @@ -1793,10 +1839,23 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data_err3 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** bootloader_anti_rollback_secure_version_err : RO; bitpos: [3:0]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION */ - uint32_t rd_repeat_data_err3:32; + uint32_t bootloader_anti_rollback_secure_version_err:4; + /** bootloader_anti_rollback_en_err : RO; bitpos: [4]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN + */ + uint32_t bootloader_anti_rollback_en_err:1; + /** bootloader_anti_rollback_update_in_rom_err : RO; bitpos: [5]; default: 0; + * Represents the programming error of EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM + */ + uint32_t bootloader_anti_rollback_update_in_rom_err:1; + /** recovery_bootloader_flash_sector_err : RO; bitpos: [17:6]; default: 0; + * Represents the programming error of EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR + */ + uint32_t recovery_bootloader_flash_sector_err:12; + uint32_t reserved_18:14; }; uint32_t val; } efuse_rd_repeat_data_err3_reg_t; @@ -1806,10 +1865,11 @@ typedef union { */ typedef union { struct { - /** rd_repeat_data_err4 : RO; bitpos: [31:0]; default: 0; - * Reserved. + /** rd_repeat_data4_err : RO; bitpos: [23:0]; default: 0; + * Represents the programming error of EFUSE_RD_REPEAT_DATA4 */ - uint32_t rd_repeat_data_err4:32; + uint32_t rd_repeat_data4_err:24; + uint32_t reserved_24:8; }; uint32_t val; } efuse_rd_repeat_data_err4_reg_t; @@ -1952,7 +2012,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753088; + /** date : R/W; bitpos: [27:0]; default: 38801520; * Stores eFuse version. */ uint32_t date:28; @@ -2010,6 +2070,122 @@ typedef union { uint32_t val; } efuse_conf_reg_t; +/** Type of dac_conf register + * Controls the eFuse programming voltage. + */ +typedef union { + struct { + /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; + * Controls the division factor of the rising clock of the programming voltage. + */ + uint32_t dac_clk_div:8; + /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + uint32_t dac_clk_pad_sel:1; + /** dac_num : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + uint32_t dac_num:8; + /** oe_clr : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + uint32_t oe_clr:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} efuse_dac_conf_reg_t; + +/** Type of rd_tim_conf register + * Configures read timing parameters. + */ +typedef union { + struct { + /** thr_a : R/W; bitpos: [7:0]; default: 1; + * Configures the read hold time. + */ + uint32_t thr_a:8; + /** trd : R/W; bitpos: [15:8]; default: 2; + * Configures the read time. + */ + uint32_t trd:8; + /** tsur_a : R/W; bitpos: [23:16]; default: 1; + * Configures the read setup time. + */ + uint32_t tsur_a:8; + /** read_init_num : R/W; bitpos: [31:24]; default: 18; + * Configures the waiting time of reading eFuse memory. + */ + uint32_t read_init_num:8; + }; + uint32_t val; +} efuse_rd_tim_conf_reg_t; + +/** Type of wr_tim_conf1 register + * Configurarion register 1 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** tsup_a : R/W; bitpos: [7:0]; default: 1; + * Configures the programming setup time. + */ + uint32_t tsup_a:8; + /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; + * Configures the power up time for VDDQ. + */ + uint32_t pwr_on_num:16; + /** thp_a : R/W; bitpos: [31:24]; default: 1; + * Configures the programming hold time. + */ + uint32_t thp_a:8; + }; + uint32_t val; +} efuse_wr_tim_conf1_reg_t; + +/** Type of wr_tim_conf2 register + * Configurarion register 2 of eFuse programming timing parameters. + */ +typedef union { + struct { + /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + uint32_t pwr_off_num:16; + /** tpgm : R/W; bitpos: [31:16]; default: 200; + * Configures the active programming time. + */ + uint32_t tpgm:16; + }; + uint32_t val; +} efuse_wr_tim_conf2_reg_t; + +/** Type of wr_tim_conf0_rs_bypass register + * Configurarion register0 of eFuse programming time parameters and rs bypass + * operation. + */ +typedef union { + struct { + /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; + * Set this bit to bypass reed solomon correction step. + */ + uint32_t bypass_rs_correction:1; + /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; + * Configures block number of programming twice operation. + */ + uint32_t bypass_rs_blk_num:11; + /** update : WT; bitpos: [12]; default: 0; + * Set this bit to update multi-bit register signals. + */ + uint32_t update:1; + /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; + * Configures the inactive programming time. + */ + uint32_t tpgm_inactive:8; + uint32_t reserved_21:11; + }; + uint32_t val; +} efuse_wr_tim_conf0_rs_bypass_reg_t; + /** Group: EFUSE Status Registers */ /** Type of status register @@ -2158,124 +2334,6 @@ typedef union { } efuse_int_clr_reg_t; -/** Group: EFUSE Configure Registers */ -/** Type of dac_conf register - * Controls the eFuse programming voltage. - */ -typedef union { - struct { - /** dac_clk_div : R/W; bitpos: [7:0]; default: 23; - * Controls the division factor of the rising clock of the programming voltage. - */ - uint32_t dac_clk_div:8; - /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - uint32_t dac_clk_pad_sel:1; - /** dac_num : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - uint32_t dac_num:8; - /** oe_clr : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - uint32_t oe_clr:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} efuse_dac_conf_reg_t; - -/** Type of rd_tim_conf register - * Configures read timing parameters. - */ -typedef union { - struct { - /** thr_a : R/W; bitpos: [7:0]; default: 1; - * Configures the read hold time. - */ - uint32_t thr_a:8; - /** trd : R/W; bitpos: [15:8]; default: 2; - * Configures the read time. - */ - uint32_t trd:8; - /** tsur_a : R/W; bitpos: [23:16]; default: 1; - * Configures the read setup time. - */ - uint32_t tsur_a:8; - /** read_init_num : R/W; bitpos: [31:24]; default: 18; - * Configures the waiting time of reading eFuse memory. - */ - uint32_t read_init_num:8; - }; - uint32_t val; -} efuse_rd_tim_conf_reg_t; - -/** Type of wr_tim_conf1 register - * Configurarion register 1 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** tsup_a : R/W; bitpos: [7:0]; default: 1; - * Configures the programming setup time. - */ - uint32_t tsup_a:8; - /** pwr_on_num : R/W; bitpos: [23:8]; default: 12288; - * Configures the power up time for VDDQ. - */ - uint32_t pwr_on_num:16; - /** thp_a : R/W; bitpos: [31:24]; default: 1; - * Configures the programming hold time. - */ - uint32_t thp_a:8; - }; - uint32_t val; -} efuse_wr_tim_conf1_reg_t; - -/** Type of wr_tim_conf2 register - * Configurarion register 2 of eFuse programming timing parameters. - */ -typedef union { - struct { - /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - uint32_t pwr_off_num:16; - /** tpgm : R/W; bitpos: [31:16]; default: 200; - * Configures the active programming time. - */ - uint32_t tpgm:16; - }; - uint32_t val; -} efuse_wr_tim_conf2_reg_t; - -/** Type of wr_tim_conf0_rs_bypass register - * Configurarion register0 of eFuse programming time parameters and rs bypass - * operation. - */ -typedef union { - struct { - /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Set this bit to bypass reed solomon correction step. - */ - uint32_t bypass_rs_correction:1; - /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; - * Configures block number of programming twice operation. - */ - uint32_t bypass_rs_blk_num:11; - /** update : WT; bitpos: [12]; default: 0; - * Set this bit to update multi-bit register signals. - */ - uint32_t update:1; - /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; - * Configures the inactive programming time. - */ - uint32_t tpgm_inactive:8; - uint32_t reserved_21:11; - }; - uint32_t val; -} efuse_wr_tim_conf0_rs_bypass_reg_t; - - /** Group: EFUSE_APB2OTP Block0 Write Disable Data */ /** Type of apb2otp_wr_dis register * eFuse apb2otp block0 data register1. @@ -2890,6 +2948,19 @@ typedef union { uint32_t val; } efuse_apb2otp_blk2_w11_reg_t; +/** Type of apb2otp_blk10_w11 register + * eFuse apb2otp block10 data register11. + */ +typedef union { + struct { + /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; + * Otp block10 word11 data. + */ + uint32_t apb2otp_block10_w11:32; + }; + uint32_t val; +} efuse_apb2otp_blk10_w11_reg_t; + /** Group: EFUSE_APB2OTP Block3 Word1 Data */ /** Type of apb2otp_blk3_w1 register @@ -4196,21 +4267,6 @@ typedef union { } efuse_apb2otp_blk10_w10_reg_t; -/** Group: EFUSE_APB2OTP Block2 Word11 Data */ -/** Type of apb2otp_blk10_w11 register - * eFuse apb2otp block10 data register11. - */ -typedef union { - struct { - /** apb2otp_block10_w11 : RO; bitpos: [31:0]; default: 0; - * Otp block10 word11 data. - */ - uint32_t apb2otp_block10_w11:32; - }; - uint32_t val; -} efuse_apb2otp_blk10_w11_reg_t; - - /** Group: EFUSE_APB2OTP Function Enable Signal */ /** Type of apb2otp_en register * eFuse apb2otp enable configuration register. diff --git a/components/soc/esp32c61/register/soc/gpio_ext_reg.h b/components/soc/esp32c61/register/soc/gpio_ext_reg.h index 2385576c33..ea6e3730e6 100644 --- a/components/soc/esp32c61/register/soc/gpio_ext_reg.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,48 +11,27 @@ extern "C" { #endif -/** GPIO_EXT_CLOCK_GATE_REG register - * Clock Gating Configure Register - */ -#define GPIO_EXT_CLOCK_GATE_REG (DR_REG_GPIO_EXT_BASE + 0x0) -/** GPIO_EXT_CLK_EN : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ -#define GPIO_EXT_CLK_EN (BIT(0)) -#define GPIO_EXT_CLK_EN_M (GPIO_EXT_CLK_EN_V << GPIO_EXT_CLK_EN_S) -#define GPIO_EXT_CLK_EN_V 0x00000001U -#define GPIO_EXT_CLK_EN_S 0 - /** GPIO_EXT_PAD_COMP_CONFIG_0_REG register - * Configuration register for zero-crossing detection + * PAD Compare configure Register */ -#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_EXT_BASE + 0x58) +#define GPIO_EXT_PAD_COMP_CONFIG_0_REG (DR_REG_GPIO_BASE + 0x58) /** GPIO_EXT_XPD_COMP_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pad compare enable bit. */ #define GPIO_EXT_XPD_COMP_0 (BIT(0)) #define GPIO_EXT_XPD_COMP_0_M (GPIO_EXT_XPD_COMP_0_V << GPIO_EXT_XPD_COMP_0_S) #define GPIO_EXT_XPD_COMP_0_V 0x00000001U #define GPIO_EXT_XPD_COMP_0_S 0 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * 1 to enable external reference from PAD[x]. 0 to enable internal reference, + * meanwhile PAD[x] can be used as a regular GPIO. */ #define GPIO_EXT_MODE_COMP_0 (BIT(1)) #define GPIO_EXT_MODE_COMP_0_M (GPIO_EXT_MODE_COMP_0_V << GPIO_EXT_MODE_COMP_0_S) #define GPIO_EXT_MODE_COMP_0_V 0x00000001U #define GPIO_EXT_MODE_COMP_0_S 1 /** GPIO_EXT_DREF_COMP_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * ......\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. */ #define GPIO_EXT_DREF_COMP_0 0x00000007U #define GPIO_EXT_DREF_COMP_0_M (GPIO_EXT_DREF_COMP_0_V << GPIO_EXT_DREF_COMP_0_S) @@ -60,13 +39,11 @@ extern "C" { #define GPIO_EXT_DREF_COMP_0_S 2 /** GPIO_EXT_PAD_COMP_FILTER_0_REG register - * Configuration register for interrupt source mask period of zero-crossing detection + * Zero Detect filter Register */ -#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_EXT_BASE + 0x5c) +#define GPIO_EXT_PAD_COMP_FILTER_0_REG (DR_REG_GPIO_BASE + 0x5c) /** GPIO_EXT_ZERO_DET_FILTER_CNT_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * Zero Detect filter cycle length */ #define GPIO_EXT_ZERO_DET_FILTER_CNT_0 0xFFFFFFFFU #define GPIO_EXT_ZERO_DET_FILTER_CNT_0_M (GPIO_EXT_ZERO_DET_FILTER_CNT_0_V << GPIO_EXT_ZERO_DET_FILTER_CNT_0_S) @@ -74,26 +51,18 @@ extern "C" { #define GPIO_EXT_ZERO_DET_FILTER_CNT_0_S 0 /** GPIO_EXT_ETM_EVENT_CH0_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel0 */ -#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x118) -/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH0_CFG_REG (DR_REG_GPIO_BASE + 0x118) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000001FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU #define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 /** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Etm event send enable bit. */ #define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) #define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) @@ -101,293 +70,207 @@ extern "C" { #define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH1_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel1 */ -#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x11c) -/** GPIO_EXT_ETM_CH1_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH1_CFG_REG (DR_REG_GPIO_BASE + 0x11c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH1_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH1_EVENT_SEL_M (GPIO_EXT_ETM_CH1_EVENT_SEL_V << GPIO_EXT_ETM_CH1_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH1_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH1_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH1_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH1_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH1_EVENT_EN_M (GPIO_EXT_ETM_CH1_EVENT_EN_V << GPIO_EXT_ETM_CH1_EVENT_EN_S) -#define GPIO_EXT_ETM_CH1_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH1_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH2_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel2 */ -#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x120) -/** GPIO_EXT_ETM_CH2_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH2_CFG_REG (DR_REG_GPIO_BASE + 0x120) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH2_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH2_EVENT_SEL_M (GPIO_EXT_ETM_CH2_EVENT_SEL_V << GPIO_EXT_ETM_CH2_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH2_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH2_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH2_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH2_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH2_EVENT_EN_M (GPIO_EXT_ETM_CH2_EVENT_EN_V << GPIO_EXT_ETM_CH2_EVENT_EN_S) -#define GPIO_EXT_ETM_CH2_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH2_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH3_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel3 */ -#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x124) -/** GPIO_EXT_ETM_CH3_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH3_CFG_REG (DR_REG_GPIO_BASE + 0x124) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH3_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH3_EVENT_SEL_M (GPIO_EXT_ETM_CH3_EVENT_SEL_V << GPIO_EXT_ETM_CH3_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH3_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH3_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH3_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH3_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH3_EVENT_EN_M (GPIO_EXT_ETM_CH3_EVENT_EN_V << GPIO_EXT_ETM_CH3_EVENT_EN_S) -#define GPIO_EXT_ETM_CH3_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH3_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH4_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel4 */ -#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x128) -/** GPIO_EXT_ETM_CH4_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH4_CFG_REG (DR_REG_GPIO_BASE + 0x128) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH4_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH4_EVENT_SEL_M (GPIO_EXT_ETM_CH4_EVENT_SEL_V << GPIO_EXT_ETM_CH4_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH4_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH4_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH4_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH4_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH4_EVENT_EN_M (GPIO_EXT_ETM_CH4_EVENT_EN_V << GPIO_EXT_ETM_CH4_EVENT_EN_S) -#define GPIO_EXT_ETM_CH4_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH4_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH5_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel5 */ -#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x12c) -/** GPIO_EXT_ETM_CH5_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH5_CFG_REG (DR_REG_GPIO_BASE + 0x12c) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH5_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH5_EVENT_SEL_M (GPIO_EXT_ETM_CH5_EVENT_SEL_V << GPIO_EXT_ETM_CH5_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH5_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH5_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH5_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH5_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH5_EVENT_EN_M (GPIO_EXT_ETM_CH5_EVENT_EN_V << GPIO_EXT_ETM_CH5_EVENT_EN_S) -#define GPIO_EXT_ETM_CH5_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH5_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH6_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel6 */ -#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x130) -/** GPIO_EXT_ETM_CH6_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH6_CFG_REG (DR_REG_GPIO_BASE + 0x130) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH6_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH6_EVENT_SEL_M (GPIO_EXT_ETM_CH6_EVENT_SEL_V << GPIO_EXT_ETM_CH6_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH6_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH6_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH6_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH6_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH6_EVENT_EN_M (GPIO_EXT_ETM_CH6_EVENT_EN_V << GPIO_EXT_ETM_CH6_EVENT_EN_S) -#define GPIO_EXT_ETM_CH6_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH6_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_EVENT_CH7_CFG_REG register - * ETM configuration register for channel 0 + * Etm Config register of Channel7 */ -#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x134) -/** GPIO_EXT_ETM_CH7_EVENT_SEL : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ +#define GPIO_EXT_ETM_EVENT_CH7_CFG_REG (DR_REG_GPIO_BASE + 0x134) +/** GPIO_EXT_ETM_CH0_EVENT_SEL : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ -#define GPIO_EXT_ETM_CH7_EVENT_SEL 0x0000001FU -#define GPIO_EXT_ETM_CH7_EVENT_SEL_M (GPIO_EXT_ETM_CH7_EVENT_SEL_V << GPIO_EXT_ETM_CH7_EVENT_SEL_S) -#define GPIO_EXT_ETM_CH7_EVENT_SEL_V 0x0000001FU -#define GPIO_EXT_ETM_CH7_EVENT_SEL_S 0 -/** GPIO_EXT_ETM_CH7_EVENT_EN : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ +#define GPIO_EXT_ETM_CH0_EVENT_SEL 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_M (GPIO_EXT_ETM_CH0_EVENT_SEL_V << GPIO_EXT_ETM_CH0_EVENT_SEL_S) +#define GPIO_EXT_ETM_CH0_EVENT_SEL_V 0x0000003FU +#define GPIO_EXT_ETM_CH0_EVENT_SEL_S 0 +/** GPIO_EXT_ETM_CH0_EVENT_EN : R/W; bitpos: [7]; default: 0; + * Etm event send enable bit. */ -#define GPIO_EXT_ETM_CH7_EVENT_EN (BIT(7)) -#define GPIO_EXT_ETM_CH7_EVENT_EN_M (GPIO_EXT_ETM_CH7_EVENT_EN_V << GPIO_EXT_ETM_CH7_EVENT_EN_S) -#define GPIO_EXT_ETM_CH7_EVENT_EN_V 0x00000001U -#define GPIO_EXT_ETM_CH7_EVENT_EN_S 7 +#define GPIO_EXT_ETM_CH0_EVENT_EN (BIT(7)) +#define GPIO_EXT_ETM_CH0_EVENT_EN_M (GPIO_EXT_ETM_CH0_EVENT_EN_V << GPIO_EXT_ETM_CH0_EVENT_EN_S) +#define GPIO_EXT_ETM_CH0_EVENT_EN_V 0x00000001U +#define GPIO_EXT_ETM_CH0_EVENT_EN_S 7 /** GPIO_EXT_ETM_TASK_P0_CFG_REG register - * GPIO selection register 0 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x158) +#define GPIO_EXT_ETM_TASK_P0_CFG_REG (DR_REG_GPIO_BASE + 0x158) /** GPIO_EXT_ETM_TASK_GPIO0_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO0.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO0_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_M (GPIO_EXT_ETM_TASK_GPIO0_SEL_V << GPIO_EXT_ETM_TASK_GPIO0_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO0_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO0_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO0_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO0 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO0_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO0_EN_M (GPIO_EXT_ETM_TASK_GPIO0_EN_V << GPIO_EXT_ETM_TASK_GPIO0_EN_S) #define GPIO_EXT_ETM_TASK_GPIO0_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO0_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO1_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO1.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO1_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_M (GPIO_EXT_ETM_TASK_GPIO1_SEL_V << GPIO_EXT_ETM_TASK_GPIO1_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO1_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO1_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO1_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO1 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO1_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO1_EN_M (GPIO_EXT_ETM_TASK_GPIO1_EN_V << GPIO_EXT_ETM_TASK_GPIO1_EN_S) #define GPIO_EXT_ETM_TASK_GPIO1_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO1_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO2_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO2.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO2_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_M (GPIO_EXT_ETM_TASK_GPIO2_SEL_V << GPIO_EXT_ETM_TASK_GPIO2_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO2_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO2_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO2_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO2 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO2_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO2_EN_M (GPIO_EXT_ETM_TASK_GPIO2_EN_V << GPIO_EXT_ETM_TASK_GPIO2_EN_S) #define GPIO_EXT_ETM_TASK_GPIO2_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO2_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO3_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO3.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO3_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_M (GPIO_EXT_ETM_TASK_GPIO3_SEL_V << GPIO_EXT_ETM_TASK_GPIO3_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO3_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO3_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO3_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO3 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO3_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO3_EN_M (GPIO_EXT_ETM_TASK_GPIO3_EN_V << GPIO_EXT_ETM_TASK_GPIO3_EN_S) #define GPIO_EXT_ETM_TASK_GPIO3_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO3_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO4_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO4.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO4_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_M (GPIO_EXT_ETM_TASK_GPIO4_SEL_V << GPIO_EXT_ETM_TASK_GPIO4_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO4_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO4_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO4_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO4 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO4_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO4_EN_M (GPIO_EXT_ETM_TASK_GPIO4_EN_V << GPIO_EXT_ETM_TASK_GPIO4_EN_S) @@ -395,104 +278,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO4_EN_S 29 /** GPIO_EXT_ETM_TASK_P1_CFG_REG register - * GPIO selection register 1 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x15c) +#define GPIO_EXT_ETM_TASK_P1_CFG_REG (DR_REG_GPIO_BASE + 0x15c) /** GPIO_EXT_ETM_TASK_GPIO5_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO5_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_M (GPIO_EXT_ETM_TASK_GPIO5_SEL_V << GPIO_EXT_ETM_TASK_GPIO5_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO5_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO5_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO5_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO5_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO5_EN_M (GPIO_EXT_ETM_TASK_GPIO5_EN_V << GPIO_EXT_ETM_TASK_GPIO5_EN_S) #define GPIO_EXT_ETM_TASK_GPIO5_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO5_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO6_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO6_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_M (GPIO_EXT_ETM_TASK_GPIO6_SEL_V << GPIO_EXT_ETM_TASK_GPIO6_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO6_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO6_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO6_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO6_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO6_EN_M (GPIO_EXT_ETM_TASK_GPIO6_EN_V << GPIO_EXT_ETM_TASK_GPIO6_EN_S) #define GPIO_EXT_ETM_TASK_GPIO6_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO6_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO7_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO7_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_M (GPIO_EXT_ETM_TASK_GPIO7_SEL_V << GPIO_EXT_ETM_TASK_GPIO7_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO7_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO7_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO7_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO7_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO7_EN_M (GPIO_EXT_ETM_TASK_GPIO7_EN_V << GPIO_EXT_ETM_TASK_GPIO7_EN_S) #define GPIO_EXT_ETM_TASK_GPIO7_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO7_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO8_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO8_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_M (GPIO_EXT_ETM_TASK_GPIO8_SEL_V << GPIO_EXT_ETM_TASK_GPIO8_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO8_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO8_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO8_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO8_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO8_EN_M (GPIO_EXT_ETM_TASK_GPIO8_EN_V << GPIO_EXT_ETM_TASK_GPIO8_EN_S) #define GPIO_EXT_ETM_TASK_GPIO8_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO8_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO9_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO9_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_M (GPIO_EXT_ETM_TASK_GPIO9_SEL_V << GPIO_EXT_ETM_TASK_GPIO9_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO9_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO9_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO9_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO9_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO9_EN_M (GPIO_EXT_ETM_TASK_GPIO9_EN_V << GPIO_EXT_ETM_TASK_GPIO9_EN_S) @@ -500,104 +353,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO9_EN_S 29 /** GPIO_EXT_ETM_TASK_P2_CFG_REG register - * GPIO selection register 2 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x160) +#define GPIO_EXT_ETM_TASK_P2_CFG_REG (DR_REG_GPIO_BASE + 0x160) /** GPIO_EXT_ETM_TASK_GPIO10_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO10_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_M (GPIO_EXT_ETM_TASK_GPIO10_SEL_V << GPIO_EXT_ETM_TASK_GPIO10_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO10_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO10_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO10_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO10_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO10_EN_M (GPIO_EXT_ETM_TASK_GPIO10_EN_V << GPIO_EXT_ETM_TASK_GPIO10_EN_S) #define GPIO_EXT_ETM_TASK_GPIO10_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO10_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO11_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO11_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_M (GPIO_EXT_ETM_TASK_GPIO11_SEL_V << GPIO_EXT_ETM_TASK_GPIO11_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO11_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO11_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO11_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO11_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO11_EN_M (GPIO_EXT_ETM_TASK_GPIO11_EN_V << GPIO_EXT_ETM_TASK_GPIO11_EN_S) #define GPIO_EXT_ETM_TASK_GPIO11_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO11_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO12_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO12_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_M (GPIO_EXT_ETM_TASK_GPIO12_SEL_V << GPIO_EXT_ETM_TASK_GPIO12_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO12_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO12_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO12_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO12_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO12_EN_M (GPIO_EXT_ETM_TASK_GPIO12_EN_V << GPIO_EXT_ETM_TASK_GPIO12_EN_S) #define GPIO_EXT_ETM_TASK_GPIO12_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO12_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO13_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO13_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_M (GPIO_EXT_ETM_TASK_GPIO13_SEL_V << GPIO_EXT_ETM_TASK_GPIO13_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO13_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO13_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO13_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO13_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO13_EN_M (GPIO_EXT_ETM_TASK_GPIO13_EN_V << GPIO_EXT_ETM_TASK_GPIO13_EN_S) #define GPIO_EXT_ETM_TASK_GPIO13_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO13_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO14_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO14_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_M (GPIO_EXT_ETM_TASK_GPIO14_SEL_V << GPIO_EXT_ETM_TASK_GPIO14_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO14_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO14_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO14_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO14_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO14_EN_M (GPIO_EXT_ETM_TASK_GPIO14_EN_V << GPIO_EXT_ETM_TASK_GPIO14_EN_S) @@ -605,104 +428,74 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO14_EN_S 29 /** GPIO_EXT_ETM_TASK_P3_CFG_REG register - * GPIO selection register 3 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x164) +#define GPIO_EXT_ETM_TASK_P3_CFG_REG (DR_REG_GPIO_BASE + 0x164) /** GPIO_EXT_ETM_TASK_GPIO15_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO15_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_M (GPIO_EXT_ETM_TASK_GPIO15_SEL_V << GPIO_EXT_ETM_TASK_GPIO15_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO15_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO15_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO15_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO15_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO15_EN_M (GPIO_EXT_ETM_TASK_GPIO15_EN_V << GPIO_EXT_ETM_TASK_GPIO15_EN_S) #define GPIO_EXT_ETM_TASK_GPIO15_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO15_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO16_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO16_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_M (GPIO_EXT_ETM_TASK_GPIO16_SEL_V << GPIO_EXT_ETM_TASK_GPIO16_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO16_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO16_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO16_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO16_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO16_EN_M (GPIO_EXT_ETM_TASK_GPIO16_EN_V << GPIO_EXT_ETM_TASK_GPIO16_EN_S) #define GPIO_EXT_ETM_TASK_GPIO16_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO16_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO17_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO17_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_M (GPIO_EXT_ETM_TASK_GPIO17_SEL_V << GPIO_EXT_ETM_TASK_GPIO17_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO17_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO17_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO17_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO17_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO17_EN_M (GPIO_EXT_ETM_TASK_GPIO17_EN_V << GPIO_EXT_ETM_TASK_GPIO17_EN_S) #define GPIO_EXT_ETM_TASK_GPIO17_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO17_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO18_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO18_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_M (GPIO_EXT_ETM_TASK_GPIO18_SEL_V << GPIO_EXT_ETM_TASK_GPIO18_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO18_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO18_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO18_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO18_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO18_EN_M (GPIO_EXT_ETM_TASK_GPIO18_EN_V << GPIO_EXT_ETM_TASK_GPIO18_EN_S) #define GPIO_EXT_ETM_TASK_GPIO18_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO18_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO19_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO19_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_M (GPIO_EXT_ETM_TASK_GPIO19_SEL_V << GPIO_EXT_ETM_TASK_GPIO19_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO19_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO19_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO19_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO19_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO19_EN_M (GPIO_EXT_ETM_TASK_GPIO19_EN_V << GPIO_EXT_ETM_TASK_GPIO19_EN_S) @@ -710,114 +503,159 @@ extern "C" { #define GPIO_EXT_ETM_TASK_GPIO19_EN_S 29 /** GPIO_EXT_ETM_TASK_P4_CFG_REG register - * GPIO selection register 4 for ETM + * Etm Configure Register to decide which GPIO been chosen */ -#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_EXT_BASE + 0x168) +#define GPIO_EXT_ETM_TASK_P4_CFG_REG (DR_REG_GPIO_BASE + 0x168) /** GPIO_EXT_ETM_TASK_GPIO20_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO20_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_M (GPIO_EXT_ETM_TASK_GPIO20_SEL_V << GPIO_EXT_ETM_TASK_GPIO20_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO20_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO20_SEL_S 0 /** GPIO_EXT_ETM_TASK_GPIO20_EN : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO20_EN (BIT(5)) #define GPIO_EXT_ETM_TASK_GPIO20_EN_M (GPIO_EXT_ETM_TASK_GPIO20_EN_V << GPIO_EXT_ETM_TASK_GPIO20_EN_S) #define GPIO_EXT_ETM_TASK_GPIO20_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO20_EN_S 5 /** GPIO_EXT_ETM_TASK_GPIO21_SEL : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO21_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_M (GPIO_EXT_ETM_TASK_GPIO21_SEL_V << GPIO_EXT_ETM_TASK_GPIO21_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO21_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO21_SEL_S 6 /** GPIO_EXT_ETM_TASK_GPIO21_EN : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO21_EN (BIT(11)) #define GPIO_EXT_ETM_TASK_GPIO21_EN_M (GPIO_EXT_ETM_TASK_GPIO21_EN_V << GPIO_EXT_ETM_TASK_GPIO21_EN_S) #define GPIO_EXT_ETM_TASK_GPIO21_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO21_EN_S 11 /** GPIO_EXT_ETM_TASK_GPIO22_SEL : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO22_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_M (GPIO_EXT_ETM_TASK_GPIO22_SEL_V << GPIO_EXT_ETM_TASK_GPIO22_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO22_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO22_SEL_S 12 /** GPIO_EXT_ETM_TASK_GPIO22_EN : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO22_EN (BIT(17)) #define GPIO_EXT_ETM_TASK_GPIO22_EN_M (GPIO_EXT_ETM_TASK_GPIO22_EN_V << GPIO_EXT_ETM_TASK_GPIO22_EN_S) #define GPIO_EXT_ETM_TASK_GPIO22_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO22_EN_S 17 /** GPIO_EXT_ETM_TASK_GPIO23_SEL : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO23_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_M (GPIO_EXT_ETM_TASK_GPIO23_SEL_V << GPIO_EXT_ETM_TASK_GPIO23_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO23_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO23_SEL_S 18 /** GPIO_EXT_ETM_TASK_GPIO23_EN : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO23_EN (BIT(23)) #define GPIO_EXT_ETM_TASK_GPIO23_EN_M (GPIO_EXT_ETM_TASK_GPIO23_EN_V << GPIO_EXT_ETM_TASK_GPIO23_EN_S) #define GPIO_EXT_ETM_TASK_GPIO23_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO23_EN_S 23 /** GPIO_EXT_ETM_TASK_GPIO24_SEL : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ #define GPIO_EXT_ETM_TASK_GPIO24_SEL 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_M (GPIO_EXT_ETM_TASK_GPIO24_SEL_V << GPIO_EXT_ETM_TASK_GPIO24_SEL_S) #define GPIO_EXT_ETM_TASK_GPIO24_SEL_V 0x00000007U #define GPIO_EXT_ETM_TASK_GPIO24_SEL_S 24 /** GPIO_EXT_ETM_TASK_GPIO24_EN : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ #define GPIO_EXT_ETM_TASK_GPIO24_EN (BIT(29)) #define GPIO_EXT_ETM_TASK_GPIO24_EN_M (GPIO_EXT_ETM_TASK_GPIO24_EN_V << GPIO_EXT_ETM_TASK_GPIO24_EN_S) #define GPIO_EXT_ETM_TASK_GPIO24_EN_V 0x00000001U #define GPIO_EXT_ETM_TASK_GPIO24_EN_S 29 +/** GPIO_EXT_ETM_TASK_P5_CFG_REG register + * Etm Configure Register to decide which GPIO been chosen + */ +#define GPIO_EXT_ETM_TASK_P5_CFG_REG (DR_REG_GPIO_BASE + 0x16c) +/** GPIO_EXT_ETM_TASK_GPIO25_SEL : R/W; bitpos: [2:0]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_M (GPIO_EXT_ETM_TASK_GPIO25_SEL_V << GPIO_EXT_ETM_TASK_GPIO25_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO25_SEL_S 0 +/** GPIO_EXT_ETM_TASK_GPIO25_EN : R/W; bitpos: [5]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO25_EN (BIT(5)) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_M (GPIO_EXT_ETM_TASK_GPIO25_EN_V << GPIO_EXT_ETM_TASK_GPIO25_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO25_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO25_EN_S 5 +/** GPIO_EXT_ETM_TASK_GPIO26_SEL : R/W; bitpos: [8:6]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_M (GPIO_EXT_ETM_TASK_GPIO26_SEL_V << GPIO_EXT_ETM_TASK_GPIO26_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO26_SEL_S 6 +/** GPIO_EXT_ETM_TASK_GPIO26_EN : R/W; bitpos: [11]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO26_EN (BIT(11)) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_M (GPIO_EXT_ETM_TASK_GPIO26_EN_V << GPIO_EXT_ETM_TASK_GPIO26_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO26_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO26_EN_S 11 +/** GPIO_EXT_ETM_TASK_GPIO27_SEL : R/W; bitpos: [14:12]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO27_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_M (GPIO_EXT_ETM_TASK_GPIO27_SEL_V << GPIO_EXT_ETM_TASK_GPIO27_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO27_SEL_S 12 +/** GPIO_EXT_ETM_TASK_GPIO27_EN : R/W; bitpos: [17]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO27_EN (BIT(17)) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_M (GPIO_EXT_ETM_TASK_GPIO27_EN_V << GPIO_EXT_ETM_TASK_GPIO27_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO27_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO27_EN_S 17 +/** GPIO_EXT_ETM_TASK_GPIO28_SEL : R/W; bitpos: [20:18]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO28_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_M (GPIO_EXT_ETM_TASK_GPIO28_SEL_V << GPIO_EXT_ETM_TASK_GPIO28_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO28_SEL_S 18 +/** GPIO_EXT_ETM_TASK_GPIO28_EN : R/W; bitpos: [23]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO28_EN (BIT(23)) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_M (GPIO_EXT_ETM_TASK_GPIO28_EN_V << GPIO_EXT_ETM_TASK_GPIO28_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO28_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO28_EN_S 23 +/** GPIO_EXT_ETM_TASK_GPIO29_SEL : R/W; bitpos: [26:24]; default: 0; + * GPIO choose a etm task channel. + */ +#define GPIO_EXT_ETM_TASK_GPIO29_SEL 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_M (GPIO_EXT_ETM_TASK_GPIO29_SEL_V << GPIO_EXT_ETM_TASK_GPIO29_SEL_S) +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_V 0x00000007U +#define GPIO_EXT_ETM_TASK_GPIO29_SEL_S 24 +/** GPIO_EXT_ETM_TASK_GPIO29_EN : R/W; bitpos: [29]; default: 0; + * Enable bit of GPIO response etm task. + */ +#define GPIO_EXT_ETM_TASK_GPIO29_EN (BIT(29)) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_M (GPIO_EXT_ETM_TASK_GPIO29_EN_V << GPIO_EXT_ETM_TASK_GPIO29_EN_S) +#define GPIO_EXT_ETM_TASK_GPIO29_EN_V 0x00000001U +#define GPIO_EXT_ETM_TASK_GPIO29_EN_S 29 + /** GPIO_EXT_INT_RAW_REG register * GPIO_EXT interrupt raw register */ -#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_EXT_BASE + 0x1d0) +#define GPIO_EXT_INT_RAW_REG (DR_REG_GPIO_BASE + 0x1d0) /** GPIO_EXT_COMP_NEG_0_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0; * analog comparator pos edge interrupt raw */ @@ -843,7 +681,7 @@ extern "C" { /** GPIO_EXT_INT_ST_REG register * GPIO_EXT interrupt masked register */ -#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_EXT_BASE + 0x1d4) +#define GPIO_EXT_INT_ST_REG (DR_REG_GPIO_BASE + 0x1d4) /** GPIO_EXT_COMP_NEG_0_INT_ST : RO; bitpos: [0]; default: 0; * analog comparator pos edge interrupt status */ @@ -869,7 +707,7 @@ extern "C" { /** GPIO_EXT_INT_ENA_REG register * GPIO_EXT interrupt enable register */ -#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_EXT_BASE + 0x1d8) +#define GPIO_EXT_INT_ENA_REG (DR_REG_GPIO_BASE + 0x1d8) /** GPIO_EXT_COMP_NEG_0_INT_ENA : R/W; bitpos: [0]; default: 1; * analog comparator pos edge interrupt enable */ @@ -895,7 +733,7 @@ extern "C" { /** GPIO_EXT_INT_CLR_REG register * GPIO_EXT interrupt clear register */ -#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_EXT_BASE + 0x1dc) +#define GPIO_EXT_INT_CLR_REG (DR_REG_GPIO_BASE + 0x1dc) /** GPIO_EXT_COMP_NEG_0_INT_CLR : WT; bitpos: [0]; default: 0; * analog comparator pos edge interrupt clear */ @@ -921,7 +759,7 @@ extern "C" { /** GPIO_EXT_PIN_CTRL_REG register * Clock Output Configuration Register */ -#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_EXT_BASE + 0x1e0) +#define GPIO_EXT_PIN_CTRL_REG (DR_REG_GPIO_BASE + 0x1e0) /** GPIO_EXT_CLK_OUT1 : R/W; bitpos: [4:0]; default: 0; * If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. * CLK_OUT_out1 can be found in peripheral output signals. @@ -948,10 +786,10 @@ extern "C" { #define GPIO_EXT_CLK_OUT3_S 10 /** GPIO_EXT_VERSION_REG register - * Version control register + * Version Control Register */ -#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_EXT_BASE + 0x1fc) -/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37753392; +#define GPIO_EXT_VERSION_REG (DR_REG_GPIO_BASE + 0x1fc) +/** GPIO_EXT_DATE : R/W; bitpos: [27:0]; default: 37823120; * Version control register. */ #define GPIO_EXT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/gpio_ext_struct.h b/components/soc/esp32c61/register/soc/gpio_ext_struct.h index 1f7f58950e..9886bf6295 100644 --- a/components/soc/esp32c61/register/soc/gpio_ext_struct.h +++ b/components/soc/esp32c61/register/soc/gpio_ext_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,48 +10,23 @@ extern "C" { #endif -/** Group: Clock gate Register */ -/** Type of clock_gate register - * Clock Gating Configure Register - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Clock enable bit of configuration registers for sigma delta modulation. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} gpio_ext_clock_gate_reg_t; - - /** Group: Configure Registers */ /** Type of pad_comp_config_0 register - * Configuration register for zero-crossing detection + * PAD Compare configure Register */ typedef union { struct { /** xpd_comp_0 : R/W; bitpos: [0]; default: 0; - * Configures whether to enable the function of analog PAD voltage comparator.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pad compare enable bit. */ uint32_t xpd_comp_0:1; /** mode_comp_0 : R/W; bitpos: [1]; default: 0; - * Configures the reference voltage for analog PAD voltage comparator.. \\ - * 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be - * used as a regular GPIO\\ - * 1: Reference voltage is the voltage on the GPIO8 PAD\\ + * 1 to enable external reference from PAD[x]. 0 to enable internal reference, + * meanwhile PAD[x] can be used as a regular GPIO. */ uint32_t mode_comp_0:1; /** dref_comp_0 : R/W; bitpos: [4:2]; default: 0; - * Configures the internal reference voltage for analog PAD voltage coparator. \\ - * 0: Internal reference voltage is 0 * VDDPST1\\ - * 1: Internal reference voltage is 0.1 * VDDPST1\\ - * ......\\ - * 6: Internal reference voltage is 0.6 * VDDPST1\\ - * 7: Internal reference voltage is 0.7 * VDDPST1\\ + * internal reference voltage tuning bit. 0V to 0.7*VDDPST step 0.1*VDDPST. */ uint32_t dref_comp_0:3; uint32_t reserved_5:27; @@ -60,14 +35,12 @@ typedef union { } gpio_ext_pad_comp_config_0_reg_t; /** Type of pad_comp_filter_0 register - * Configuration register for interrupt source mask period of zero-crossing detection + * Zero Detect filter Register */ typedef union { struct { /** zero_det_filter_cnt_0 : R/W; bitpos: [31:0]; default: 0; - * Configures the period of masking new interrupt source foe analog PAD voltage - * comparator.\\ - * Measurement unit: IO MUX operating clock cycle\\ + * Zero Detect filter cycle length */ uint32_t zero_det_filter_cnt_0:32; }; @@ -100,27 +73,19 @@ typedef union { } gpio_ext_pin_ctrl_reg_t; -/** Group: ETM Configuration Registers */ +/** Group: Etm Configure Registers */ /** Type of etm_event_chn_cfg register - * ETM configuration register for channel 0 + * Etm Config register of Channeln */ typedef union { struct { - /** etm_chn_event_sel : R/W; bitpos: [4:0]; default: 0; - * Configures to select GPIO for ETM event channel.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * 25 ~ 31: Reserved\\ + /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0; + * Etm event channel select gpio. */ - uint32_t etm_chn_event_sel:5; - uint32_t reserved_5:2; + uint32_t etm_chn_event_sel:6; + uint32_t reserved_6:1; /** etm_chn_event_en : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable ETM event send.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Etm event send enable bit. */ uint32_t etm_chn_event_en:1; uint32_t reserved_8:24; @@ -129,177 +94,108 @@ typedef union { } gpio_ext_etm_event_chn_cfg_reg_t; /** Type of etm_task_pn_cfg register - * GPIO selection register for ETM. - * This register is an abstraction of the following registers: - * gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t - */ -typedef union { - uint32_t val; -} gpio_ext_etm_task_pn_cfg_reg_t; - -/** Type of etm_task_p0_cfg register - * GPIO selection register 0 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio0_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO0.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio0_sel:3; uint32_t reserved_3:2; /** etm_task_gpio0_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO0 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio0_en:1; /** etm_task_gpio1_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO1.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio1_sel:3; uint32_t reserved_9:2; /** etm_task_gpio1_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO1 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio1_en:1; /** etm_task_gpio2_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO2.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio2_sel:3; uint32_t reserved_15:2; /** etm_task_gpio2_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO2 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio2_en:1; /** etm_task_gpio3_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO3.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio3_sel:3; uint32_t reserved_21:2; /** etm_task_gpio3_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO3 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio3_en:1; /** etm_task_gpio4_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO4.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio4_sel:3; uint32_t reserved_27:2; /** etm_task_gpio4_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO4 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio4_en:1; uint32_t reserved_30:2; }; uint32_t val; -} gpio_ext_etm_task_p0_cfg_reg_t; +} gpio_ext_etm_task_pn_cfg_reg_t; /** Type of etm_task_p1_cfg register - * GPIO selection register 1 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio5_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO5.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio5_sel:3; uint32_t reserved_3:2; /** etm_task_gpio5_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO5 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio5_en:1; /** etm_task_gpio6_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO6.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio6_sel:3; uint32_t reserved_9:2; /** etm_task_gpio6_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO6 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio6_en:1; /** etm_task_gpio7_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO7.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio7_sel:3; uint32_t reserved_15:2; /** etm_task_gpio7_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO7 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio7_en:1; /** etm_task_gpio8_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO8.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio8_sel:3; uint32_t reserved_21:2; /** etm_task_gpio8_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO8 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio8_en:1; /** etm_task_gpio9_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO9.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio9_sel:3; uint32_t reserved_27:2; /** etm_task_gpio9_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO9 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio9_en:1; uint32_t reserved_30:2; @@ -308,83 +204,53 @@ typedef union { } gpio_ext_etm_task_p1_cfg_reg_t; /** Type of etm_task_p2_cfg register - * GPIO selection register 2 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio10_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO10.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio10_sel:3; uint32_t reserved_3:2; /** etm_task_gpio10_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO10 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio10_en:1; /** etm_task_gpio11_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO11.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio11_sel:3; uint32_t reserved_9:2; /** etm_task_gpio11_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO11 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio11_en:1; /** etm_task_gpio12_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO12.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio12_sel:3; uint32_t reserved_15:2; /** etm_task_gpio12_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO12 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio12_en:1; /** etm_task_gpio13_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO13.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio13_sel:3; uint32_t reserved_21:2; /** etm_task_gpio13_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO13 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio13_en:1; /** etm_task_gpio14_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO14.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio14_sel:3; uint32_t reserved_27:2; /** etm_task_gpio14_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO14 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio14_en:1; uint32_t reserved_30:2; @@ -393,83 +259,53 @@ typedef union { } gpio_ext_etm_task_p2_cfg_reg_t; /** Type of etm_task_p3_cfg register - * GPIO selection register 3 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio15_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO15.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio15_sel:3; uint32_t reserved_3:2; /** etm_task_gpio15_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO15 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio15_en:1; /** etm_task_gpio16_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO16.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio16_sel:3; uint32_t reserved_9:2; /** etm_task_gpio16_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO16 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio16_en:1; /** etm_task_gpio17_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO17.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio17_sel:3; uint32_t reserved_15:2; /** etm_task_gpio17_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO17 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio17_en:1; /** etm_task_gpio18_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO18.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio18_sel:3; uint32_t reserved_21:2; /** etm_task_gpio18_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO18 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio18_en:1; /** etm_task_gpio19_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO19.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio19_sel:3; uint32_t reserved_27:2; /** etm_task_gpio19_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO19 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio19_en:1; uint32_t reserved_30:2; @@ -478,83 +314,53 @@ typedef union { } gpio_ext_etm_task_p3_cfg_reg_t; /** Type of etm_task_p4_cfg register - * GPIO selection register 4 for ETM + * Etm Configure Register to decide which GPIO been chosen */ typedef union { struct { /** etm_task_gpio20_sel : R/W; bitpos: [2:0]; default: 0; - * Configures to select an ETM task channel for GPIO20.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio20_sel:3; uint32_t reserved_3:2; /** etm_task_gpio20_en : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable GPIO20 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio20_en:1; /** etm_task_gpio21_sel : R/W; bitpos: [8:6]; default: 0; - * Configures to select an ETM task channel for GPIO21.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio21_sel:3; uint32_t reserved_9:2; /** etm_task_gpio21_en : R/W; bitpos: [11]; default: 0; - * Configures whether or not to enable GPIO21 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio21_en:1; /** etm_task_gpio22_sel : R/W; bitpos: [14:12]; default: 0; - * Configures to select an ETM task channel for GPIO22.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio22_sel:3; uint32_t reserved_15:2; /** etm_task_gpio22_en : R/W; bitpos: [17]; default: 0; - * Configures whether or not to enable GPIO22 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio22_en:1; /** etm_task_gpio23_sel : R/W; bitpos: [20:18]; default: 0; - * Configures to select an ETM task channel for GPIO23.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio23_sel:3; uint32_t reserved_21:2; /** etm_task_gpio23_en : R/W; bitpos: [23]; default: 0; - * Configures whether or not to enable GPIO23 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio23_en:1; /** etm_task_gpio24_sel : R/W; bitpos: [26:24]; default: 0; - * Configures to select an ETM task channel for GPIO24.\\ - * 0: Select channel 0\\ - * 1: Select channel 1\\ - * ......\\ - * 7: Select channel 7\\ + * GPIO choose a etm task channel. */ uint32_t etm_task_gpio24_sel:3; uint32_t reserved_27:2; /** etm_task_gpio24_en : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable GPIO24 to response ETM task.\\ - * 0: Not enable\\ - * 1: Enable\\ + * Enable bit of GPIO response etm task. */ uint32_t etm_task_gpio24_en:1; uint32_t reserved_30:2; @@ -562,6 +368,61 @@ typedef union { uint32_t val; } gpio_ext_etm_task_p4_cfg_reg_t; +/** Type of etm_task_p5_cfg register + * Etm Configure Register to decide which GPIO been chosen + */ +typedef union { + struct { + /** etm_task_gpio25_sel : R/W; bitpos: [2:0]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio25_sel:3; + uint32_t reserved_3:2; + /** etm_task_gpio25_en : R/W; bitpos: [5]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio25_en:1; + /** etm_task_gpio26_sel : R/W; bitpos: [8:6]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio26_sel:3; + uint32_t reserved_9:2; + /** etm_task_gpio26_en : R/W; bitpos: [11]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio26_en:1; + /** etm_task_gpio27_sel : R/W; bitpos: [14:12]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio27_sel:3; + uint32_t reserved_15:2; + /** etm_task_gpio27_en : R/W; bitpos: [17]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio27_en:1; + /** etm_task_gpio28_sel : R/W; bitpos: [20:18]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio28_sel:3; + uint32_t reserved_21:2; + /** etm_task_gpio28_en : R/W; bitpos: [23]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio28_en:1; + /** etm_task_gpio29_sel : R/W; bitpos: [26:24]; default: 0; + * GPIO choose a etm task channel. + */ + uint32_t etm_task_gpio29_sel:3; + uint32_t reserved_27:2; + /** etm_task_gpio29_en : R/W; bitpos: [29]; default: 0; + * Enable bit of GPIO response etm task. + */ + uint32_t etm_task_gpio29_en:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} gpio_ext_etm_task_p5_cfg_reg_t; + /** Group: Interrupt Registers */ /** Type of int_raw register @@ -655,11 +516,11 @@ typedef union { /** Group: Version Register */ /** Type of version register - * Version control register + * Version Control Register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753392; + /** date : R/W; bitpos: [27:0]; default: 37823120; * Version control register. */ uint32_t date:28; @@ -670,18 +531,17 @@ typedef union { typedef struct gpio_etm_dev_t { volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8]; - uint32_t reserved_138[8]; - volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5]; + uint32_t reserved_080[8]; + volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[6]; } gpio_etm_dev_t; typedef struct { - volatile gpio_ext_clock_gate_reg_t clock_gate; - uint32_t reserved_004[21]; + uint32_t reserved_000[22]; volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0; volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0; uint32_t reserved_060[46]; volatile gpio_etm_dev_t etm; - uint32_t reserved_16c[25]; + uint32_t reserved_170[24]; volatile gpio_ext_int_raw_reg_t int_raw; volatile gpio_ext_int_st_reg_t int_st; volatile gpio_ext_int_ena_reg_t int_ena; diff --git a/components/soc/esp32c61/register/soc/gpio_reg.h b/components/soc/esp32c61/register/soc/gpio_reg.h index f9eaeac424..af5013c93f 100644 --- a/components/soc/esp32c61/register/soc/gpio_reg.h +++ b/components/soc/esp32c61/register/soc/gpio_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,17 +12,11 @@ extern "C" { #endif /** GPIO_STRAP_REG register - * Strapping pin register + * pad strapping register */ #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0) /** GPIO_STRAPPING : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. - * - * - bit0 ~ bit1: invalid - * - bit2: GPIO8 - * - bit3: GPIO9 - * - bit4: GPIO7 - * - bit5 ~ bit15: invalid + * pad strapping register */ #define GPIO_STRAPPING 0x0000FFFFU #define GPIO_STRAPPING_M (GPIO_STRAPPING_V << GPIO_STRAPPING_S) @@ -30,281 +24,362 @@ extern "C" { #define GPIO_STRAPPING_S 0 /** GPIO_OUT_REG register - * GPIO output register + * GPIO output register for GPIO0-31 */ #define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) -/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [28:0]; default: 0; - * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ - * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 - * respectively. Bit25 ~ bit31 are invalid.\\ +/** GPIO_OUT_DATA_ORIG : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 */ -#define GPIO_OUT_DATA_ORIG 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG 0xFFFFFFFFU #define GPIO_OUT_DATA_ORIG_M (GPIO_OUT_DATA_ORIG_V << GPIO_OUT_DATA_ORIG_S) -#define GPIO_OUT_DATA_ORIG_V 0x1FFFFFFFU +#define GPIO_OUT_DATA_ORIG_V 0xFFFFFFFFU #define GPIO_OUT_DATA_ORIG_S 0 /** GPIO_OUT_W1TS_REG register - * GPIO output set register + * GPIO output set register for GPIO0-31 */ #define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) -/** GPIO_OUT_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ +/** GPIO_OUT_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 */ -#define GPIO_OUT_W1TS 0x1FFFFFFFU +#define GPIO_OUT_W1TS 0xFFFFFFFFU #define GPIO_OUT_W1TS_M (GPIO_OUT_W1TS_V << GPIO_OUT_W1TS_S) -#define GPIO_OUT_W1TS_V 0x1FFFFFFFU +#define GPIO_OUT_W1TS_V 0xFFFFFFFFU #define GPIO_OUT_W1TS_S 0 /** GPIO_OUT_W1TC_REG register - * GPIO output clear register + * GPIO output clear register for GPIO0-31 */ #define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) -/** GPIO_OUT_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ +/** GPIO_OUT_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 */ -#define GPIO_OUT_W1TC 0x1FFFFFFFU +#define GPIO_OUT_W1TC 0xFFFFFFFFU #define GPIO_OUT_W1TC_M (GPIO_OUT_W1TC_V << GPIO_OUT_W1TC_S) -#define GPIO_OUT_W1TC_V 0x1FFFFFFFU +#define GPIO_OUT_W1TC_V 0xFFFFFFFFU #define GPIO_OUT_W1TC_S 0 +/** GPIO_OUT1_REG register + * GPIO output register for GPIO32-33 + */ +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/** GPIO_OUT1_DATA_ORIG : R/W/SC/WTC; bitpos: [1:0]; default: 0; + * GPIO output register for GPIO32-33 + */ +#define GPIO_OUT1_DATA_ORIG 0x00000003U +#define GPIO_OUT1_DATA_ORIG_M (GPIO_OUT1_DATA_ORIG_V << GPIO_OUT1_DATA_ORIG_S) +#define GPIO_OUT1_DATA_ORIG_V 0x00000003U +#define GPIO_OUT1_DATA_ORIG_S 0 + +/** GPIO_OUT1_W1TS_REG register + * GPIO output set register for GPIO32-33 + */ +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/** GPIO_OUT1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO output set register for GPIO32-33 + */ +#define GPIO_OUT1_W1TS 0x00000003U +#define GPIO_OUT1_W1TS_M (GPIO_OUT1_W1TS_V << GPIO_OUT1_W1TS_S) +#define GPIO_OUT1_W1TS_V 0x00000003U +#define GPIO_OUT1_W1TS_S 0 + +/** GPIO_OUT1_W1TC_REG register + * GPIO output clear register for GPIO32-33 + */ +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/** GPIO_OUT1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO output clear register for GPIO32-33 + */ +#define GPIO_OUT1_W1TC 0x00000003U +#define GPIO_OUT1_W1TC_M (GPIO_OUT1_W1TC_V << GPIO_OUT1_W1TC_S) +#define GPIO_OUT1_W1TC_V 0x00000003U +#define GPIO_OUT1_W1TC_S 0 + /** GPIO_ENABLE_REG register - * GPIO output enable register + * GPIO output enable register for GPIO0-31 */ #define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x34) -/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [28:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ - * 0: Not enable\\ - * 1: Enable\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ +/** GPIO_ENABLE_DATA : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 */ -#define GPIO_ENABLE_DATA 0x1FFFFFFFU +#define GPIO_ENABLE_DATA 0xFFFFFFFFU #define GPIO_ENABLE_DATA_M (GPIO_ENABLE_DATA_V << GPIO_ENABLE_DATA_S) -#define GPIO_ENABLE_DATA_V 0x1FFFFFFFU +#define GPIO_ENABLE_DATA_V 0xFFFFFFFFU #define GPIO_ENABLE_DATA_S 0 /** GPIO_ENABLE_W1TS_REG register - * GPIO output enable set register + * GPIO output enable set register for GPIO0-31 */ #define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x38) -/** GPIO_ENABLE_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ +/** GPIO_ENABLE_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 */ -#define GPIO_ENABLE_W1TS 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_M (GPIO_ENABLE_W1TS_V << GPIO_ENABLE_W1TS_S) -#define GPIO_ENABLE_W1TS_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TS_S 0 /** GPIO_ENABLE_W1TC_REG register - * GPIO output enable clear register + * GPIO output enable clear register for GPIO0-31 */ #define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x3c) -/** GPIO_ENABLE_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ +/** GPIO_ENABLE_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 */ -#define GPIO_ENABLE_W1TC 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_M (GPIO_ENABLE_W1TC_V << GPIO_ENABLE_W1TC_S) -#define GPIO_ENABLE_W1TC_V 0x1FFFFFFFU +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFFU #define GPIO_ENABLE_W1TC_S 0 +/** GPIO_ENABLE1_REG register + * GPIO output enable register for GPIO32-33 + */ +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x40) +/** GPIO_ENABLE1_DATA : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO output enable register for GPIO32-33 + */ +#define GPIO_ENABLE1_DATA 0x00000003U +#define GPIO_ENABLE1_DATA_M (GPIO_ENABLE1_DATA_V << GPIO_ENABLE1_DATA_S) +#define GPIO_ENABLE1_DATA_V 0x00000003U +#define GPIO_ENABLE1_DATA_S 0 + +/** GPIO_ENABLE1_W1TS_REG register + * GPIO output enable set register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x44) +/** GPIO_ENABLE1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO output enable set register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TS 0x00000003U +#define GPIO_ENABLE1_W1TS_M (GPIO_ENABLE1_W1TS_V << GPIO_ENABLE1_W1TS_S) +#define GPIO_ENABLE1_W1TS_V 0x00000003U +#define GPIO_ENABLE1_W1TS_S 0 + +/** GPIO_ENABLE1_W1TC_REG register + * GPIO output enable clear register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x48) +/** GPIO_ENABLE1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO output enable clear register for GPIO32-33 + */ +#define GPIO_ENABLE1_W1TC 0x00000003U +#define GPIO_ENABLE1_W1TC_M (GPIO_ENABLE1_W1TC_V << GPIO_ENABLE1_W1TC_S) +#define GPIO_ENABLE1_W1TC_V 0x00000003U +#define GPIO_ENABLE1_W1TC_S 0 + /** GPIO_IN_REG register - * GPIO input register + * GPIO input register for GPIO0-31 */ #define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x64) -/** GPIO_IN_DATA_NEXT : RO; bitpos: [28:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ +/** GPIO_IN_DATA_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 */ -#define GPIO_IN_DATA_NEXT 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT 0xFFFFFFFFU #define GPIO_IN_DATA_NEXT_M (GPIO_IN_DATA_NEXT_V << GPIO_IN_DATA_NEXT_S) -#define GPIO_IN_DATA_NEXT_V 0x1FFFFFFFU +#define GPIO_IN_DATA_NEXT_V 0xFFFFFFFFU #define GPIO_IN_DATA_NEXT_S 0 +/** GPIO_IN1_REG register + * GPIO input register for GPIO32-33 + */ +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x68) +/** GPIO_IN1_DATA_NEXT : RO; bitpos: [1:0]; default: 0; + * GPIO input register for GPIO32-33 + */ +#define GPIO_IN1_DATA_NEXT 0x00000003U +#define GPIO_IN1_DATA_NEXT_M (GPIO_IN1_DATA_NEXT_V << GPIO_IN1_DATA_NEXT_S) +#define GPIO_IN1_DATA_NEXT_V 0x00000003U +#define GPIO_IN1_DATA_NEXT_S 0 + /** GPIO_STATUS_REG register - * GPIO interrupt status register + * GPIO interrupt status register for GPIO0-31 */ #define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x74) -/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [28:0]; default: 0; - * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - Each bit represents the status of its corresponding GPIO: - * - * - 0: Represents the GPIO does not generate the interrupt configured by - * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. - * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, - * or this bit is configured to 1 by the software. - * +/** GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 */ -#define GPIO_STATUS_INTERRUPT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_M (GPIO_STATUS_INTERRUPT_V << GPIO_STATUS_INTERRUPT_S) -#define GPIO_STATUS_INTERRUPT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_S 0 /** GPIO_STATUS_W1TS_REG register - * GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-31 */ #define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x78) -/** GPIO_STATUS_W1TS : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. +/** GPIO_STATUS_W1TS : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 */ -#define GPIO_STATUS_W1TS 0x1FFFFFFFU +#define GPIO_STATUS_W1TS 0xFFFFFFFFU #define GPIO_STATUS_W1TS_M (GPIO_STATUS_W1TS_V << GPIO_STATUS_W1TS_S) -#define GPIO_STATUS_W1TS_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TS_V 0xFFFFFFFFU #define GPIO_STATUS_W1TS_S 0 /** GPIO_STATUS_W1TC_REG register - * GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-31 */ #define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x7c) -/** GPIO_STATUS_W1TC : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. +/** GPIO_STATUS_W1TC : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 */ -#define GPIO_STATUS_W1TC 0x1FFFFFFFU +#define GPIO_STATUS_W1TC 0xFFFFFFFFU #define GPIO_STATUS_W1TC_M (GPIO_STATUS_W1TC_V << GPIO_STATUS_W1TC_S) -#define GPIO_STATUS_W1TC_V 0x1FFFFFFFU +#define GPIO_STATUS_W1TC_V 0xFFFFFFFFU #define GPIO_STATUS_W1TC_S 0 +/** GPIO_STATUS1_REG register + * GPIO interrupt status register for GPIO32-33 + */ +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x80) +/** GPIO_STATUS1_INTERRUPT : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO interrupt status register for GPIO32-33 + */ +#define GPIO_STATUS1_INTERRUPT 0x00000003U +#define GPIO_STATUS1_INTERRUPT_M (GPIO_STATUS1_INTERRUPT_V << GPIO_STATUS1_INTERRUPT_S) +#define GPIO_STATUS1_INTERRUPT_V 0x00000003U +#define GPIO_STATUS1_INTERRUPT_S 0 + +/** GPIO_STATUS1_W1TS_REG register + * GPIO interrupt status set register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x84) +/** GPIO_STATUS1_W1TS : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status set register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TS 0x00000003U +#define GPIO_STATUS1_W1TS_M (GPIO_STATUS1_W1TS_V << GPIO_STATUS1_W1TS_S) +#define GPIO_STATUS1_W1TS_V 0x00000003U +#define GPIO_STATUS1_W1TS_S 0 + +/** GPIO_STATUS1_W1TC_REG register + * GPIO interrupt status clear register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x88) +/** GPIO_STATUS1_W1TC : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-33 + */ +#define GPIO_STATUS1_W1TC 0x00000003U +#define GPIO_STATUS1_W1TC_M (GPIO_STATUS1_W1TC_V << GPIO_STATUS1_W1TC_S) +#define GPIO_STATUS1_W1TC_V 0x00000003U +#define GPIO_STATUS1_W1TC_S 0 + /** GPIO_PROCPU_INT_REG register - * CPU interrupt status register + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 */ #define GPIO_PROCPU_INT_REG (DR_REG_GPIO_BASE + 0xa4) -/** GPIO_PROCPU_INT : RO; bitpos: [28:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This - * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) - * enable signal (bit13 of GPIO_PIN$n_REG). \\ +/** GPIO_PROCPU_INT : RO; bitpos: [31:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 */ -#define GPIO_PROCPU_INT 0x1FFFFFFFU +#define GPIO_PROCPU_INT 0xFFFFFFFFU #define GPIO_PROCPU_INT_M (GPIO_PROCPU_INT_V << GPIO_PROCPU_INT_S) -#define GPIO_PROCPU_INT_V 0x1FFFFFFFU +#define GPIO_PROCPU_INT_V 0xFFFFFFFFU #define GPIO_PROCPU_INT_S 0 +/** GPIO_SDIO_INT_REG register + * GPIO_SDIO_INT interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT_REG (DR_REG_GPIO_BASE + 0xa8) +/** GPIO_SDIO_INT : RO; bitpos: [31:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO0-31 + */ +#define GPIO_SDIO_INT 0xFFFFFFFFU +#define GPIO_SDIO_INT_M (GPIO_SDIO_INT_V << GPIO_SDIO_INT_S) +#define GPIO_SDIO_INT_V 0xFFFFFFFFU +#define GPIO_SDIO_INT_S 0 + +/** GPIO_PROCPU_INT1_REG register + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +#define GPIO_PROCPU_INT1_REG (DR_REG_GPIO_BASE + 0xac) +/** GPIO_PROCPU_INT1 : RO; bitpos: [1:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +#define GPIO_PROCPU_INT1 0x00000003U +#define GPIO_PROCPU_INT1_M (GPIO_PROCPU_INT1_V << GPIO_PROCPU_INT1_S) +#define GPIO_PROCPU_INT1_V 0x00000003U +#define GPIO_PROCPU_INT1_S 0 + +/** GPIO_SDIO_INT1_REG register + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +#define GPIO_SDIO_INT1_REG (DR_REG_GPIO_BASE + 0xb0) +/** GPIO_SDIO_INT1 : RO; bitpos: [1:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +#define GPIO_SDIO_INT1 0x00000003U +#define GPIO_SDIO_INT1_M (GPIO_SDIO_INT1_V << GPIO_SDIO_INT1_S) +#define GPIO_SDIO_INT1_V 0x00000003U +#define GPIO_SDIO_INT1_S 0 + /** GPIO_STATUS_NEXT_REG register - * GPIO interrupt source register + * GPIO interrupt source register for GPIO0-31 */ -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xb4) -/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [28:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each - * bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0xc4) +/** GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 */ -#define GPIO_STATUS_INTERRUPT_NEXT 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_M (GPIO_STATUS_INTERRUPT_NEXT_V << GPIO_STATUS_INTERRUPT_NEXT_S) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0x1FFFFFFFU +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFFU #define GPIO_STATUS_INTERRUPT_NEXT_S 0 -/** GPIO_PIN0_REG register - * GPIO0 configuration register +/** GPIO_STATUS_NEXT1_REG register + * GPIO interrupt source register for GPIO32-33 */ -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xc4) +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0xc8) +/** GPIO_STATUS_INTERRUPT_NEXT1 : RO; bitpos: [1:0]; default: 0; + * GPIO interrupt source register for GPIO32-33 + */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x00000003U +#define GPIO_STATUS_INTERRUPT_NEXT1_M (GPIO_STATUS_INTERRUPT_NEXT1_V << GPIO_STATUS_INTERRUPT_NEXT1_S) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x00000003U +#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 + +/** GPIO_PIN0_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0xd4) /** GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN0_SYNC2_BYPASS 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_M (GPIO_PIN0_SYNC2_BYPASS_V << GPIO_PIN0_SYNC2_BYPASS_S) #define GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC2_BYPASS_S 0 /** GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN0_PAD_DRIVER (BIT(2)) #define GPIO_PIN0_PAD_DRIVER_M (GPIO_PIN0_PAD_DRIVER_V << GPIO_PIN0_PAD_DRIVER_S) #define GPIO_PIN0_PAD_DRIVER_V 0x00000001U #define GPIO_PIN0_PAD_DRIVER_S 2 /** GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN0_SYNC1_BYPASS 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_M (GPIO_PIN0_SYNC1_BYPASS_V << GPIO_PIN0_SYNC1_BYPASS_S) #define GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN0_SYNC1_BYPASS_S 3 /** GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN0_INT_TYPE 0x00000007U #define GPIO_PIN0_INT_TYPE_M (GPIO_PIN0_INT_TYPE_V << GPIO_PIN0_INT_TYPE_S) #define GPIO_PIN0_INT_TYPE_V 0x00000007U #define GPIO_PIN0_INT_TYPE_S 7 /** GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN0_WAKEUP_ENABLE_M (GPIO_PIN0_WAKEUP_ENABLE_V << GPIO_PIN0_WAKEUP_ENABLE_S) #define GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN0_WAKEUP_ENABLE_S 10 /** GPIO_PIN0_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN0_INT_ENA 0x0000001FU #define GPIO_PIN0_INT_ENA_M (GPIO_PIN0_INT_ENA_V << GPIO_PIN0_INT_ENA_S) @@ -312,72 +387,50 @@ extern "C" { #define GPIO_PIN0_INT_ENA_S 13 /** GPIO_PIN1_REG register - * GPIO1 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xc8) +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0xd8) /** GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN1_SYNC2_BYPASS 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_M (GPIO_PIN1_SYNC2_BYPASS_V << GPIO_PIN1_SYNC2_BYPASS_S) #define GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC2_BYPASS_S 0 /** GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN1_PAD_DRIVER (BIT(2)) #define GPIO_PIN1_PAD_DRIVER_M (GPIO_PIN1_PAD_DRIVER_V << GPIO_PIN1_PAD_DRIVER_S) #define GPIO_PIN1_PAD_DRIVER_V 0x00000001U #define GPIO_PIN1_PAD_DRIVER_S 2 /** GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN1_SYNC1_BYPASS 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_M (GPIO_PIN1_SYNC1_BYPASS_V << GPIO_PIN1_SYNC1_BYPASS_S) #define GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN1_SYNC1_BYPASS_S 3 /** GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN1_INT_TYPE 0x00000007U #define GPIO_PIN1_INT_TYPE_M (GPIO_PIN1_INT_TYPE_V << GPIO_PIN1_INT_TYPE_S) #define GPIO_PIN1_INT_TYPE_V 0x00000007U #define GPIO_PIN1_INT_TYPE_S 7 /** GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN1_WAKEUP_ENABLE_M (GPIO_PIN1_WAKEUP_ENABLE_V << GPIO_PIN1_WAKEUP_ENABLE_S) #define GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN1_WAKEUP_ENABLE_S 10 /** GPIO_PIN1_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN1_INT_ENA 0x0000001FU #define GPIO_PIN1_INT_ENA_M (GPIO_PIN1_INT_ENA_V << GPIO_PIN1_INT_ENA_S) @@ -385,72 +438,50 @@ extern "C" { #define GPIO_PIN1_INT_ENA_S 13 /** GPIO_PIN2_REG register - * GPIO2 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xcc) +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0xdc) /** GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN2_SYNC2_BYPASS 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_M (GPIO_PIN2_SYNC2_BYPASS_V << GPIO_PIN2_SYNC2_BYPASS_S) #define GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC2_BYPASS_S 0 /** GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN2_PAD_DRIVER (BIT(2)) #define GPIO_PIN2_PAD_DRIVER_M (GPIO_PIN2_PAD_DRIVER_V << GPIO_PIN2_PAD_DRIVER_S) #define GPIO_PIN2_PAD_DRIVER_V 0x00000001U #define GPIO_PIN2_PAD_DRIVER_S 2 /** GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN2_SYNC1_BYPASS 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_M (GPIO_PIN2_SYNC1_BYPASS_V << GPIO_PIN2_SYNC1_BYPASS_S) #define GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN2_SYNC1_BYPASS_S 3 /** GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN2_INT_TYPE 0x00000007U #define GPIO_PIN2_INT_TYPE_M (GPIO_PIN2_INT_TYPE_V << GPIO_PIN2_INT_TYPE_S) #define GPIO_PIN2_INT_TYPE_V 0x00000007U #define GPIO_PIN2_INT_TYPE_S 7 /** GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN2_WAKEUP_ENABLE_M (GPIO_PIN2_WAKEUP_ENABLE_V << GPIO_PIN2_WAKEUP_ENABLE_S) #define GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN2_WAKEUP_ENABLE_S 10 /** GPIO_PIN2_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN2_INT_ENA 0x0000001FU #define GPIO_PIN2_INT_ENA_M (GPIO_PIN2_INT_ENA_V << GPIO_PIN2_INT_ENA_S) @@ -458,72 +489,50 @@ extern "C" { #define GPIO_PIN2_INT_ENA_S 13 /** GPIO_PIN3_REG register - * GPIO3 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xd0) +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0xe0) /** GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN3_SYNC2_BYPASS 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_M (GPIO_PIN3_SYNC2_BYPASS_V << GPIO_PIN3_SYNC2_BYPASS_S) #define GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC2_BYPASS_S 0 /** GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN3_PAD_DRIVER (BIT(2)) #define GPIO_PIN3_PAD_DRIVER_M (GPIO_PIN3_PAD_DRIVER_V << GPIO_PIN3_PAD_DRIVER_S) #define GPIO_PIN3_PAD_DRIVER_V 0x00000001U #define GPIO_PIN3_PAD_DRIVER_S 2 /** GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN3_SYNC1_BYPASS 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_M (GPIO_PIN3_SYNC1_BYPASS_V << GPIO_PIN3_SYNC1_BYPASS_S) #define GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN3_SYNC1_BYPASS_S 3 /** GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN3_INT_TYPE 0x00000007U #define GPIO_PIN3_INT_TYPE_M (GPIO_PIN3_INT_TYPE_V << GPIO_PIN3_INT_TYPE_S) #define GPIO_PIN3_INT_TYPE_V 0x00000007U #define GPIO_PIN3_INT_TYPE_S 7 /** GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN3_WAKEUP_ENABLE_M (GPIO_PIN3_WAKEUP_ENABLE_V << GPIO_PIN3_WAKEUP_ENABLE_S) #define GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN3_WAKEUP_ENABLE_S 10 /** GPIO_PIN3_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN3_INT_ENA 0x0000001FU #define GPIO_PIN3_INT_ENA_M (GPIO_PIN3_INT_ENA_V << GPIO_PIN3_INT_ENA_S) @@ -531,72 +540,50 @@ extern "C" { #define GPIO_PIN3_INT_ENA_S 13 /** GPIO_PIN4_REG register - * GPIO4 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xd4) +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0xe4) /** GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN4_SYNC2_BYPASS 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_M (GPIO_PIN4_SYNC2_BYPASS_V << GPIO_PIN4_SYNC2_BYPASS_S) #define GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC2_BYPASS_S 0 /** GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN4_PAD_DRIVER (BIT(2)) #define GPIO_PIN4_PAD_DRIVER_M (GPIO_PIN4_PAD_DRIVER_V << GPIO_PIN4_PAD_DRIVER_S) #define GPIO_PIN4_PAD_DRIVER_V 0x00000001U #define GPIO_PIN4_PAD_DRIVER_S 2 /** GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN4_SYNC1_BYPASS 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_M (GPIO_PIN4_SYNC1_BYPASS_V << GPIO_PIN4_SYNC1_BYPASS_S) #define GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN4_SYNC1_BYPASS_S 3 /** GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN4_INT_TYPE 0x00000007U #define GPIO_PIN4_INT_TYPE_M (GPIO_PIN4_INT_TYPE_V << GPIO_PIN4_INT_TYPE_S) #define GPIO_PIN4_INT_TYPE_V 0x00000007U #define GPIO_PIN4_INT_TYPE_S 7 /** GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN4_WAKEUP_ENABLE_M (GPIO_PIN4_WAKEUP_ENABLE_V << GPIO_PIN4_WAKEUP_ENABLE_S) #define GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN4_WAKEUP_ENABLE_S 10 /** GPIO_PIN4_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN4_INT_ENA 0x0000001FU #define GPIO_PIN4_INT_ENA_M (GPIO_PIN4_INT_ENA_V << GPIO_PIN4_INT_ENA_S) @@ -604,72 +591,50 @@ extern "C" { #define GPIO_PIN4_INT_ENA_S 13 /** GPIO_PIN5_REG register - * GPIO5 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xd8) +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0xe8) /** GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN5_SYNC2_BYPASS 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_M (GPIO_PIN5_SYNC2_BYPASS_V << GPIO_PIN5_SYNC2_BYPASS_S) #define GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC2_BYPASS_S 0 /** GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN5_PAD_DRIVER (BIT(2)) #define GPIO_PIN5_PAD_DRIVER_M (GPIO_PIN5_PAD_DRIVER_V << GPIO_PIN5_PAD_DRIVER_S) #define GPIO_PIN5_PAD_DRIVER_V 0x00000001U #define GPIO_PIN5_PAD_DRIVER_S 2 /** GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN5_SYNC1_BYPASS 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_M (GPIO_PIN5_SYNC1_BYPASS_V << GPIO_PIN5_SYNC1_BYPASS_S) #define GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN5_SYNC1_BYPASS_S 3 /** GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN5_INT_TYPE 0x00000007U #define GPIO_PIN5_INT_TYPE_M (GPIO_PIN5_INT_TYPE_V << GPIO_PIN5_INT_TYPE_S) #define GPIO_PIN5_INT_TYPE_V 0x00000007U #define GPIO_PIN5_INT_TYPE_S 7 /** GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN5_WAKEUP_ENABLE_M (GPIO_PIN5_WAKEUP_ENABLE_V << GPIO_PIN5_WAKEUP_ENABLE_S) #define GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN5_WAKEUP_ENABLE_S 10 /** GPIO_PIN5_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN5_INT_ENA 0x0000001FU #define GPIO_PIN5_INT_ENA_M (GPIO_PIN5_INT_ENA_V << GPIO_PIN5_INT_ENA_S) @@ -677,72 +642,50 @@ extern "C" { #define GPIO_PIN5_INT_ENA_S 13 /** GPIO_PIN6_REG register - * GPIO6 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xdc) +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0xec) /** GPIO_PIN6_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN6_SYNC2_BYPASS 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_M (GPIO_PIN6_SYNC2_BYPASS_V << GPIO_PIN6_SYNC2_BYPASS_S) #define GPIO_PIN6_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC2_BYPASS_S 0 /** GPIO_PIN6_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN6_PAD_DRIVER (BIT(2)) #define GPIO_PIN6_PAD_DRIVER_M (GPIO_PIN6_PAD_DRIVER_V << GPIO_PIN6_PAD_DRIVER_S) #define GPIO_PIN6_PAD_DRIVER_V 0x00000001U #define GPIO_PIN6_PAD_DRIVER_S 2 /** GPIO_PIN6_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN6_SYNC1_BYPASS 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_M (GPIO_PIN6_SYNC1_BYPASS_V << GPIO_PIN6_SYNC1_BYPASS_S) #define GPIO_PIN6_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN6_SYNC1_BYPASS_S 3 /** GPIO_PIN6_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN6_INT_TYPE 0x00000007U #define GPIO_PIN6_INT_TYPE_M (GPIO_PIN6_INT_TYPE_V << GPIO_PIN6_INT_TYPE_S) #define GPIO_PIN6_INT_TYPE_V 0x00000007U #define GPIO_PIN6_INT_TYPE_S 7 /** GPIO_PIN6_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN6_WAKEUP_ENABLE_M (GPIO_PIN6_WAKEUP_ENABLE_V << GPIO_PIN6_WAKEUP_ENABLE_S) #define GPIO_PIN6_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN6_WAKEUP_ENABLE_S 10 /** GPIO_PIN6_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN6_INT_ENA 0x0000001FU #define GPIO_PIN6_INT_ENA_M (GPIO_PIN6_INT_ENA_V << GPIO_PIN6_INT_ENA_S) @@ -750,72 +693,50 @@ extern "C" { #define GPIO_PIN6_INT_ENA_S 13 /** GPIO_PIN7_REG register - * GPIO7 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xe0) +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0xf0) /** GPIO_PIN7_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN7_SYNC2_BYPASS 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_M (GPIO_PIN7_SYNC2_BYPASS_V << GPIO_PIN7_SYNC2_BYPASS_S) #define GPIO_PIN7_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC2_BYPASS_S 0 /** GPIO_PIN7_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN7_PAD_DRIVER (BIT(2)) #define GPIO_PIN7_PAD_DRIVER_M (GPIO_PIN7_PAD_DRIVER_V << GPIO_PIN7_PAD_DRIVER_S) #define GPIO_PIN7_PAD_DRIVER_V 0x00000001U #define GPIO_PIN7_PAD_DRIVER_S 2 /** GPIO_PIN7_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN7_SYNC1_BYPASS 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_M (GPIO_PIN7_SYNC1_BYPASS_V << GPIO_PIN7_SYNC1_BYPASS_S) #define GPIO_PIN7_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN7_SYNC1_BYPASS_S 3 /** GPIO_PIN7_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN7_INT_TYPE 0x00000007U #define GPIO_PIN7_INT_TYPE_M (GPIO_PIN7_INT_TYPE_V << GPIO_PIN7_INT_TYPE_S) #define GPIO_PIN7_INT_TYPE_V 0x00000007U #define GPIO_PIN7_INT_TYPE_S 7 /** GPIO_PIN7_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN7_WAKEUP_ENABLE_M (GPIO_PIN7_WAKEUP_ENABLE_V << GPIO_PIN7_WAKEUP_ENABLE_S) #define GPIO_PIN7_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN7_WAKEUP_ENABLE_S 10 /** GPIO_PIN7_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN7_INT_ENA 0x0000001FU #define GPIO_PIN7_INT_ENA_M (GPIO_PIN7_INT_ENA_V << GPIO_PIN7_INT_ENA_S) @@ -823,72 +744,50 @@ extern "C" { #define GPIO_PIN7_INT_ENA_S 13 /** GPIO_PIN8_REG register - * GPIO8 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xe4) +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0xf4) /** GPIO_PIN8_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN8_SYNC2_BYPASS 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_M (GPIO_PIN8_SYNC2_BYPASS_V << GPIO_PIN8_SYNC2_BYPASS_S) #define GPIO_PIN8_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC2_BYPASS_S 0 /** GPIO_PIN8_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN8_PAD_DRIVER (BIT(2)) #define GPIO_PIN8_PAD_DRIVER_M (GPIO_PIN8_PAD_DRIVER_V << GPIO_PIN8_PAD_DRIVER_S) #define GPIO_PIN8_PAD_DRIVER_V 0x00000001U #define GPIO_PIN8_PAD_DRIVER_S 2 /** GPIO_PIN8_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN8_SYNC1_BYPASS 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_M (GPIO_PIN8_SYNC1_BYPASS_V << GPIO_PIN8_SYNC1_BYPASS_S) #define GPIO_PIN8_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN8_SYNC1_BYPASS_S 3 /** GPIO_PIN8_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN8_INT_TYPE 0x00000007U #define GPIO_PIN8_INT_TYPE_M (GPIO_PIN8_INT_TYPE_V << GPIO_PIN8_INT_TYPE_S) #define GPIO_PIN8_INT_TYPE_V 0x00000007U #define GPIO_PIN8_INT_TYPE_S 7 /** GPIO_PIN8_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN8_WAKEUP_ENABLE_M (GPIO_PIN8_WAKEUP_ENABLE_V << GPIO_PIN8_WAKEUP_ENABLE_S) #define GPIO_PIN8_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN8_WAKEUP_ENABLE_S 10 /** GPIO_PIN8_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN8_INT_ENA 0x0000001FU #define GPIO_PIN8_INT_ENA_M (GPIO_PIN8_INT_ENA_V << GPIO_PIN8_INT_ENA_S) @@ -896,72 +795,50 @@ extern "C" { #define GPIO_PIN8_INT_ENA_S 13 /** GPIO_PIN9_REG register - * GPIO9 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xe8) +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0xf8) /** GPIO_PIN9_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN9_SYNC2_BYPASS 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_M (GPIO_PIN9_SYNC2_BYPASS_V << GPIO_PIN9_SYNC2_BYPASS_S) #define GPIO_PIN9_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC2_BYPASS_S 0 /** GPIO_PIN9_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN9_PAD_DRIVER (BIT(2)) #define GPIO_PIN9_PAD_DRIVER_M (GPIO_PIN9_PAD_DRIVER_V << GPIO_PIN9_PAD_DRIVER_S) #define GPIO_PIN9_PAD_DRIVER_V 0x00000001U #define GPIO_PIN9_PAD_DRIVER_S 2 /** GPIO_PIN9_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN9_SYNC1_BYPASS 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_M (GPIO_PIN9_SYNC1_BYPASS_V << GPIO_PIN9_SYNC1_BYPASS_S) #define GPIO_PIN9_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN9_SYNC1_BYPASS_S 3 /** GPIO_PIN9_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN9_INT_TYPE 0x00000007U #define GPIO_PIN9_INT_TYPE_M (GPIO_PIN9_INT_TYPE_V << GPIO_PIN9_INT_TYPE_S) #define GPIO_PIN9_INT_TYPE_V 0x00000007U #define GPIO_PIN9_INT_TYPE_S 7 /** GPIO_PIN9_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN9_WAKEUP_ENABLE_M (GPIO_PIN9_WAKEUP_ENABLE_V << GPIO_PIN9_WAKEUP_ENABLE_S) #define GPIO_PIN9_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN9_WAKEUP_ENABLE_S 10 /** GPIO_PIN9_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN9_INT_ENA 0x0000001FU #define GPIO_PIN9_INT_ENA_M (GPIO_PIN9_INT_ENA_V << GPIO_PIN9_INT_ENA_S) @@ -969,72 +846,50 @@ extern "C" { #define GPIO_PIN9_INT_ENA_S 13 /** GPIO_PIN10_REG register - * GPIO10 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xec) +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0xfc) /** GPIO_PIN10_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN10_SYNC2_BYPASS 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_M (GPIO_PIN10_SYNC2_BYPASS_V << GPIO_PIN10_SYNC2_BYPASS_S) #define GPIO_PIN10_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC2_BYPASS_S 0 /** GPIO_PIN10_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN10_PAD_DRIVER (BIT(2)) #define GPIO_PIN10_PAD_DRIVER_M (GPIO_PIN10_PAD_DRIVER_V << GPIO_PIN10_PAD_DRIVER_S) #define GPIO_PIN10_PAD_DRIVER_V 0x00000001U #define GPIO_PIN10_PAD_DRIVER_S 2 /** GPIO_PIN10_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN10_SYNC1_BYPASS 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_M (GPIO_PIN10_SYNC1_BYPASS_V << GPIO_PIN10_SYNC1_BYPASS_S) #define GPIO_PIN10_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN10_SYNC1_BYPASS_S 3 /** GPIO_PIN10_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN10_INT_TYPE 0x00000007U #define GPIO_PIN10_INT_TYPE_M (GPIO_PIN10_INT_TYPE_V << GPIO_PIN10_INT_TYPE_S) #define GPIO_PIN10_INT_TYPE_V 0x00000007U #define GPIO_PIN10_INT_TYPE_S 7 /** GPIO_PIN10_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN10_WAKEUP_ENABLE_M (GPIO_PIN10_WAKEUP_ENABLE_V << GPIO_PIN10_WAKEUP_ENABLE_S) #define GPIO_PIN10_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN10_WAKEUP_ENABLE_S 10 /** GPIO_PIN10_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN10_INT_ENA 0x0000001FU #define GPIO_PIN10_INT_ENA_M (GPIO_PIN10_INT_ENA_V << GPIO_PIN10_INT_ENA_S) @@ -1042,72 +897,50 @@ extern "C" { #define GPIO_PIN10_INT_ENA_S 13 /** GPIO_PIN11_REG register - * GPIO11 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xf0) +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0x100) /** GPIO_PIN11_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN11_SYNC2_BYPASS 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_M (GPIO_PIN11_SYNC2_BYPASS_V << GPIO_PIN11_SYNC2_BYPASS_S) #define GPIO_PIN11_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC2_BYPASS_S 0 /** GPIO_PIN11_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN11_PAD_DRIVER (BIT(2)) #define GPIO_PIN11_PAD_DRIVER_M (GPIO_PIN11_PAD_DRIVER_V << GPIO_PIN11_PAD_DRIVER_S) #define GPIO_PIN11_PAD_DRIVER_V 0x00000001U #define GPIO_PIN11_PAD_DRIVER_S 2 /** GPIO_PIN11_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN11_SYNC1_BYPASS 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_M (GPIO_PIN11_SYNC1_BYPASS_V << GPIO_PIN11_SYNC1_BYPASS_S) #define GPIO_PIN11_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN11_SYNC1_BYPASS_S 3 /** GPIO_PIN11_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN11_INT_TYPE 0x00000007U #define GPIO_PIN11_INT_TYPE_M (GPIO_PIN11_INT_TYPE_V << GPIO_PIN11_INT_TYPE_S) #define GPIO_PIN11_INT_TYPE_V 0x00000007U #define GPIO_PIN11_INT_TYPE_S 7 /** GPIO_PIN11_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN11_WAKEUP_ENABLE_M (GPIO_PIN11_WAKEUP_ENABLE_V << GPIO_PIN11_WAKEUP_ENABLE_S) #define GPIO_PIN11_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN11_WAKEUP_ENABLE_S 10 /** GPIO_PIN11_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN11_INT_ENA 0x0000001FU #define GPIO_PIN11_INT_ENA_M (GPIO_PIN11_INT_ENA_V << GPIO_PIN11_INT_ENA_S) @@ -1115,72 +948,50 @@ extern "C" { #define GPIO_PIN11_INT_ENA_S 13 /** GPIO_PIN12_REG register - * GPIO12 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xf4) +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0x104) /** GPIO_PIN12_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN12_SYNC2_BYPASS 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_M (GPIO_PIN12_SYNC2_BYPASS_V << GPIO_PIN12_SYNC2_BYPASS_S) #define GPIO_PIN12_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC2_BYPASS_S 0 /** GPIO_PIN12_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN12_PAD_DRIVER (BIT(2)) #define GPIO_PIN12_PAD_DRIVER_M (GPIO_PIN12_PAD_DRIVER_V << GPIO_PIN12_PAD_DRIVER_S) #define GPIO_PIN12_PAD_DRIVER_V 0x00000001U #define GPIO_PIN12_PAD_DRIVER_S 2 /** GPIO_PIN12_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN12_SYNC1_BYPASS 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_M (GPIO_PIN12_SYNC1_BYPASS_V << GPIO_PIN12_SYNC1_BYPASS_S) #define GPIO_PIN12_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN12_SYNC1_BYPASS_S 3 /** GPIO_PIN12_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN12_INT_TYPE 0x00000007U #define GPIO_PIN12_INT_TYPE_M (GPIO_PIN12_INT_TYPE_V << GPIO_PIN12_INT_TYPE_S) #define GPIO_PIN12_INT_TYPE_V 0x00000007U #define GPIO_PIN12_INT_TYPE_S 7 /** GPIO_PIN12_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN12_WAKEUP_ENABLE_M (GPIO_PIN12_WAKEUP_ENABLE_V << GPIO_PIN12_WAKEUP_ENABLE_S) #define GPIO_PIN12_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN12_WAKEUP_ENABLE_S 10 /** GPIO_PIN12_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN12_INT_ENA 0x0000001FU #define GPIO_PIN12_INT_ENA_M (GPIO_PIN12_INT_ENA_V << GPIO_PIN12_INT_ENA_S) @@ -1188,72 +999,50 @@ extern "C" { #define GPIO_PIN12_INT_ENA_S 13 /** GPIO_PIN13_REG register - * GPIO13 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xf8) +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0x108) /** GPIO_PIN13_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN13_SYNC2_BYPASS 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_M (GPIO_PIN13_SYNC2_BYPASS_V << GPIO_PIN13_SYNC2_BYPASS_S) #define GPIO_PIN13_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC2_BYPASS_S 0 /** GPIO_PIN13_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN13_PAD_DRIVER (BIT(2)) #define GPIO_PIN13_PAD_DRIVER_M (GPIO_PIN13_PAD_DRIVER_V << GPIO_PIN13_PAD_DRIVER_S) #define GPIO_PIN13_PAD_DRIVER_V 0x00000001U #define GPIO_PIN13_PAD_DRIVER_S 2 /** GPIO_PIN13_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN13_SYNC1_BYPASS 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_M (GPIO_PIN13_SYNC1_BYPASS_V << GPIO_PIN13_SYNC1_BYPASS_S) #define GPIO_PIN13_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN13_SYNC1_BYPASS_S 3 /** GPIO_PIN13_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN13_INT_TYPE 0x00000007U #define GPIO_PIN13_INT_TYPE_M (GPIO_PIN13_INT_TYPE_V << GPIO_PIN13_INT_TYPE_S) #define GPIO_PIN13_INT_TYPE_V 0x00000007U #define GPIO_PIN13_INT_TYPE_S 7 /** GPIO_PIN13_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN13_WAKEUP_ENABLE_M (GPIO_PIN13_WAKEUP_ENABLE_V << GPIO_PIN13_WAKEUP_ENABLE_S) #define GPIO_PIN13_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN13_WAKEUP_ENABLE_S 10 /** GPIO_PIN13_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN13_INT_ENA 0x0000001FU #define GPIO_PIN13_INT_ENA_M (GPIO_PIN13_INT_ENA_V << GPIO_PIN13_INT_ENA_S) @@ -1261,72 +1050,50 @@ extern "C" { #define GPIO_PIN13_INT_ENA_S 13 /** GPIO_PIN14_REG register - * GPIO14 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xfc) +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0x10c) /** GPIO_PIN14_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN14_SYNC2_BYPASS 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_M (GPIO_PIN14_SYNC2_BYPASS_V << GPIO_PIN14_SYNC2_BYPASS_S) #define GPIO_PIN14_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC2_BYPASS_S 0 /** GPIO_PIN14_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN14_PAD_DRIVER (BIT(2)) #define GPIO_PIN14_PAD_DRIVER_M (GPIO_PIN14_PAD_DRIVER_V << GPIO_PIN14_PAD_DRIVER_S) #define GPIO_PIN14_PAD_DRIVER_V 0x00000001U #define GPIO_PIN14_PAD_DRIVER_S 2 /** GPIO_PIN14_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN14_SYNC1_BYPASS 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_M (GPIO_PIN14_SYNC1_BYPASS_V << GPIO_PIN14_SYNC1_BYPASS_S) #define GPIO_PIN14_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN14_SYNC1_BYPASS_S 3 /** GPIO_PIN14_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN14_INT_TYPE 0x00000007U #define GPIO_PIN14_INT_TYPE_M (GPIO_PIN14_INT_TYPE_V << GPIO_PIN14_INT_TYPE_S) #define GPIO_PIN14_INT_TYPE_V 0x00000007U #define GPIO_PIN14_INT_TYPE_S 7 /** GPIO_PIN14_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN14_WAKEUP_ENABLE_M (GPIO_PIN14_WAKEUP_ENABLE_V << GPIO_PIN14_WAKEUP_ENABLE_S) #define GPIO_PIN14_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN14_WAKEUP_ENABLE_S 10 /** GPIO_PIN14_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN14_INT_ENA 0x0000001FU #define GPIO_PIN14_INT_ENA_M (GPIO_PIN14_INT_ENA_V << GPIO_PIN14_INT_ENA_S) @@ -1334,72 +1101,50 @@ extern "C" { #define GPIO_PIN14_INT_ENA_S 13 /** GPIO_PIN15_REG register - * GPIO15 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x100) +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0x110) /** GPIO_PIN15_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN15_SYNC2_BYPASS 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_M (GPIO_PIN15_SYNC2_BYPASS_V << GPIO_PIN15_SYNC2_BYPASS_S) #define GPIO_PIN15_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC2_BYPASS_S 0 /** GPIO_PIN15_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN15_PAD_DRIVER (BIT(2)) #define GPIO_PIN15_PAD_DRIVER_M (GPIO_PIN15_PAD_DRIVER_V << GPIO_PIN15_PAD_DRIVER_S) #define GPIO_PIN15_PAD_DRIVER_V 0x00000001U #define GPIO_PIN15_PAD_DRIVER_S 2 /** GPIO_PIN15_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN15_SYNC1_BYPASS 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_M (GPIO_PIN15_SYNC1_BYPASS_V << GPIO_PIN15_SYNC1_BYPASS_S) #define GPIO_PIN15_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN15_SYNC1_BYPASS_S 3 /** GPIO_PIN15_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN15_INT_TYPE 0x00000007U #define GPIO_PIN15_INT_TYPE_M (GPIO_PIN15_INT_TYPE_V << GPIO_PIN15_INT_TYPE_S) #define GPIO_PIN15_INT_TYPE_V 0x00000007U #define GPIO_PIN15_INT_TYPE_S 7 /** GPIO_PIN15_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN15_WAKEUP_ENABLE_M (GPIO_PIN15_WAKEUP_ENABLE_V << GPIO_PIN15_WAKEUP_ENABLE_S) #define GPIO_PIN15_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN15_WAKEUP_ENABLE_S 10 /** GPIO_PIN15_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN15_INT_ENA 0x0000001FU #define GPIO_PIN15_INT_ENA_M (GPIO_PIN15_INT_ENA_V << GPIO_PIN15_INT_ENA_S) @@ -1407,72 +1152,50 @@ extern "C" { #define GPIO_PIN15_INT_ENA_S 13 /** GPIO_PIN16_REG register - * GPIO16 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x104) +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0x114) /** GPIO_PIN16_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN16_SYNC2_BYPASS 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_M (GPIO_PIN16_SYNC2_BYPASS_V << GPIO_PIN16_SYNC2_BYPASS_S) #define GPIO_PIN16_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC2_BYPASS_S 0 /** GPIO_PIN16_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN16_PAD_DRIVER (BIT(2)) #define GPIO_PIN16_PAD_DRIVER_M (GPIO_PIN16_PAD_DRIVER_V << GPIO_PIN16_PAD_DRIVER_S) #define GPIO_PIN16_PAD_DRIVER_V 0x00000001U #define GPIO_PIN16_PAD_DRIVER_S 2 /** GPIO_PIN16_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN16_SYNC1_BYPASS 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_M (GPIO_PIN16_SYNC1_BYPASS_V << GPIO_PIN16_SYNC1_BYPASS_S) #define GPIO_PIN16_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN16_SYNC1_BYPASS_S 3 /** GPIO_PIN16_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN16_INT_TYPE 0x00000007U #define GPIO_PIN16_INT_TYPE_M (GPIO_PIN16_INT_TYPE_V << GPIO_PIN16_INT_TYPE_S) #define GPIO_PIN16_INT_TYPE_V 0x00000007U #define GPIO_PIN16_INT_TYPE_S 7 /** GPIO_PIN16_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN16_WAKEUP_ENABLE_M (GPIO_PIN16_WAKEUP_ENABLE_V << GPIO_PIN16_WAKEUP_ENABLE_S) #define GPIO_PIN16_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN16_WAKEUP_ENABLE_S 10 /** GPIO_PIN16_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN16_INT_ENA 0x0000001FU #define GPIO_PIN16_INT_ENA_M (GPIO_PIN16_INT_ENA_V << GPIO_PIN16_INT_ENA_S) @@ -1480,72 +1203,50 @@ extern "C" { #define GPIO_PIN16_INT_ENA_S 13 /** GPIO_PIN17_REG register - * GPIO17 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x108) +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0x118) /** GPIO_PIN17_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN17_SYNC2_BYPASS 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_M (GPIO_PIN17_SYNC2_BYPASS_V << GPIO_PIN17_SYNC2_BYPASS_S) #define GPIO_PIN17_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC2_BYPASS_S 0 /** GPIO_PIN17_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN17_PAD_DRIVER (BIT(2)) #define GPIO_PIN17_PAD_DRIVER_M (GPIO_PIN17_PAD_DRIVER_V << GPIO_PIN17_PAD_DRIVER_S) #define GPIO_PIN17_PAD_DRIVER_V 0x00000001U #define GPIO_PIN17_PAD_DRIVER_S 2 /** GPIO_PIN17_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN17_SYNC1_BYPASS 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_M (GPIO_PIN17_SYNC1_BYPASS_V << GPIO_PIN17_SYNC1_BYPASS_S) #define GPIO_PIN17_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN17_SYNC1_BYPASS_S 3 /** GPIO_PIN17_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN17_INT_TYPE 0x00000007U #define GPIO_PIN17_INT_TYPE_M (GPIO_PIN17_INT_TYPE_V << GPIO_PIN17_INT_TYPE_S) #define GPIO_PIN17_INT_TYPE_V 0x00000007U #define GPIO_PIN17_INT_TYPE_S 7 /** GPIO_PIN17_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN17_WAKEUP_ENABLE_M (GPIO_PIN17_WAKEUP_ENABLE_V << GPIO_PIN17_WAKEUP_ENABLE_S) #define GPIO_PIN17_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN17_WAKEUP_ENABLE_S 10 /** GPIO_PIN17_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN17_INT_ENA 0x0000001FU #define GPIO_PIN17_INT_ENA_M (GPIO_PIN17_INT_ENA_V << GPIO_PIN17_INT_ENA_S) @@ -1553,72 +1254,50 @@ extern "C" { #define GPIO_PIN17_INT_ENA_S 13 /** GPIO_PIN18_REG register - * GPIO18 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x10c) +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0x11c) /** GPIO_PIN18_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN18_SYNC2_BYPASS 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_M (GPIO_PIN18_SYNC2_BYPASS_V << GPIO_PIN18_SYNC2_BYPASS_S) #define GPIO_PIN18_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC2_BYPASS_S 0 /** GPIO_PIN18_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN18_PAD_DRIVER (BIT(2)) #define GPIO_PIN18_PAD_DRIVER_M (GPIO_PIN18_PAD_DRIVER_V << GPIO_PIN18_PAD_DRIVER_S) #define GPIO_PIN18_PAD_DRIVER_V 0x00000001U #define GPIO_PIN18_PAD_DRIVER_S 2 /** GPIO_PIN18_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN18_SYNC1_BYPASS 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_M (GPIO_PIN18_SYNC1_BYPASS_V << GPIO_PIN18_SYNC1_BYPASS_S) #define GPIO_PIN18_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN18_SYNC1_BYPASS_S 3 /** GPIO_PIN18_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN18_INT_TYPE 0x00000007U #define GPIO_PIN18_INT_TYPE_M (GPIO_PIN18_INT_TYPE_V << GPIO_PIN18_INT_TYPE_S) #define GPIO_PIN18_INT_TYPE_V 0x00000007U #define GPIO_PIN18_INT_TYPE_S 7 /** GPIO_PIN18_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN18_WAKEUP_ENABLE_M (GPIO_PIN18_WAKEUP_ENABLE_V << GPIO_PIN18_WAKEUP_ENABLE_S) #define GPIO_PIN18_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN18_WAKEUP_ENABLE_S 10 /** GPIO_PIN18_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN18_INT_ENA 0x0000001FU #define GPIO_PIN18_INT_ENA_M (GPIO_PIN18_INT_ENA_V << GPIO_PIN18_INT_ENA_S) @@ -1626,72 +1305,50 @@ extern "C" { #define GPIO_PIN18_INT_ENA_S 13 /** GPIO_PIN19_REG register - * GPIO19 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x110) +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0x120) /** GPIO_PIN19_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN19_SYNC2_BYPASS 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_M (GPIO_PIN19_SYNC2_BYPASS_V << GPIO_PIN19_SYNC2_BYPASS_S) #define GPIO_PIN19_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC2_BYPASS_S 0 /** GPIO_PIN19_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN19_PAD_DRIVER (BIT(2)) #define GPIO_PIN19_PAD_DRIVER_M (GPIO_PIN19_PAD_DRIVER_V << GPIO_PIN19_PAD_DRIVER_S) #define GPIO_PIN19_PAD_DRIVER_V 0x00000001U #define GPIO_PIN19_PAD_DRIVER_S 2 /** GPIO_PIN19_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN19_SYNC1_BYPASS 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_M (GPIO_PIN19_SYNC1_BYPASS_V << GPIO_PIN19_SYNC1_BYPASS_S) #define GPIO_PIN19_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN19_SYNC1_BYPASS_S 3 /** GPIO_PIN19_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN19_INT_TYPE 0x00000007U #define GPIO_PIN19_INT_TYPE_M (GPIO_PIN19_INT_TYPE_V << GPIO_PIN19_INT_TYPE_S) #define GPIO_PIN19_INT_TYPE_V 0x00000007U #define GPIO_PIN19_INT_TYPE_S 7 /** GPIO_PIN19_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN19_WAKEUP_ENABLE_M (GPIO_PIN19_WAKEUP_ENABLE_V << GPIO_PIN19_WAKEUP_ENABLE_S) #define GPIO_PIN19_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN19_WAKEUP_ENABLE_S 10 /** GPIO_PIN19_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN19_INT_ENA 0x0000001FU #define GPIO_PIN19_INT_ENA_M (GPIO_PIN19_INT_ENA_V << GPIO_PIN19_INT_ENA_S) @@ -1699,72 +1356,50 @@ extern "C" { #define GPIO_PIN19_INT_ENA_S 13 /** GPIO_PIN20_REG register - * GPIO20 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x114) +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0x124) /** GPIO_PIN20_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN20_SYNC2_BYPASS 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_M (GPIO_PIN20_SYNC2_BYPASS_V << GPIO_PIN20_SYNC2_BYPASS_S) #define GPIO_PIN20_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC2_BYPASS_S 0 /** GPIO_PIN20_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN20_PAD_DRIVER (BIT(2)) #define GPIO_PIN20_PAD_DRIVER_M (GPIO_PIN20_PAD_DRIVER_V << GPIO_PIN20_PAD_DRIVER_S) #define GPIO_PIN20_PAD_DRIVER_V 0x00000001U #define GPIO_PIN20_PAD_DRIVER_S 2 /** GPIO_PIN20_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN20_SYNC1_BYPASS 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_M (GPIO_PIN20_SYNC1_BYPASS_V << GPIO_PIN20_SYNC1_BYPASS_S) #define GPIO_PIN20_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN20_SYNC1_BYPASS_S 3 /** GPIO_PIN20_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN20_INT_TYPE 0x00000007U #define GPIO_PIN20_INT_TYPE_M (GPIO_PIN20_INT_TYPE_V << GPIO_PIN20_INT_TYPE_S) #define GPIO_PIN20_INT_TYPE_V 0x00000007U #define GPIO_PIN20_INT_TYPE_S 7 /** GPIO_PIN20_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN20_WAKEUP_ENABLE_M (GPIO_PIN20_WAKEUP_ENABLE_V << GPIO_PIN20_WAKEUP_ENABLE_S) #define GPIO_PIN20_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN20_WAKEUP_ENABLE_S 10 /** GPIO_PIN20_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN20_INT_ENA 0x0000001FU #define GPIO_PIN20_INT_ENA_M (GPIO_PIN20_INT_ENA_V << GPIO_PIN20_INT_ENA_S) @@ -1772,72 +1407,50 @@ extern "C" { #define GPIO_PIN20_INT_ENA_S 13 /** GPIO_PIN21_REG register - * GPIO21 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x118) +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0x128) /** GPIO_PIN21_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN21_SYNC2_BYPASS 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_M (GPIO_PIN21_SYNC2_BYPASS_V << GPIO_PIN21_SYNC2_BYPASS_S) #define GPIO_PIN21_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC2_BYPASS_S 0 /** GPIO_PIN21_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN21_PAD_DRIVER (BIT(2)) #define GPIO_PIN21_PAD_DRIVER_M (GPIO_PIN21_PAD_DRIVER_V << GPIO_PIN21_PAD_DRIVER_S) #define GPIO_PIN21_PAD_DRIVER_V 0x00000001U #define GPIO_PIN21_PAD_DRIVER_S 2 /** GPIO_PIN21_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN21_SYNC1_BYPASS 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_M (GPIO_PIN21_SYNC1_BYPASS_V << GPIO_PIN21_SYNC1_BYPASS_S) #define GPIO_PIN21_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN21_SYNC1_BYPASS_S 3 /** GPIO_PIN21_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN21_INT_TYPE 0x00000007U #define GPIO_PIN21_INT_TYPE_M (GPIO_PIN21_INT_TYPE_V << GPIO_PIN21_INT_TYPE_S) #define GPIO_PIN21_INT_TYPE_V 0x00000007U #define GPIO_PIN21_INT_TYPE_S 7 /** GPIO_PIN21_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN21_WAKEUP_ENABLE_M (GPIO_PIN21_WAKEUP_ENABLE_V << GPIO_PIN21_WAKEUP_ENABLE_S) #define GPIO_PIN21_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN21_WAKEUP_ENABLE_S 10 /** GPIO_PIN21_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN21_INT_ENA 0x0000001FU #define GPIO_PIN21_INT_ENA_M (GPIO_PIN21_INT_ENA_V << GPIO_PIN21_INT_ENA_S) @@ -1845,72 +1458,50 @@ extern "C" { #define GPIO_PIN21_INT_ENA_S 13 /** GPIO_PIN22_REG register - * GPIO22 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c) +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x12c) /** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN22_SYNC2_BYPASS 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S) #define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC2_BYPASS_S 0 /** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN22_PAD_DRIVER (BIT(2)) #define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S) #define GPIO_PIN22_PAD_DRIVER_V 0x00000001U #define GPIO_PIN22_PAD_DRIVER_S 2 /** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN22_SYNC1_BYPASS 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S) #define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN22_SYNC1_BYPASS_S 3 /** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN22_INT_TYPE 0x00000007U #define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S) #define GPIO_PIN22_INT_TYPE_V 0x00000007U #define GPIO_PIN22_INT_TYPE_S 7 /** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S) #define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN22_WAKEUP_ENABLE_S 10 /** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN22_INT_ENA 0x0000001FU #define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S) @@ -1918,72 +1509,50 @@ extern "C" { #define GPIO_PIN22_INT_ENA_S 13 /** GPIO_PIN23_REG register - * GPIO23 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120) +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x130) /** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN23_SYNC2_BYPASS 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S) #define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC2_BYPASS_S 0 /** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN23_PAD_DRIVER (BIT(2)) #define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S) #define GPIO_PIN23_PAD_DRIVER_V 0x00000001U #define GPIO_PIN23_PAD_DRIVER_S 2 /** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN23_SYNC1_BYPASS 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S) #define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN23_SYNC1_BYPASS_S 3 /** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN23_INT_TYPE 0x00000007U #define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S) #define GPIO_PIN23_INT_TYPE_V 0x00000007U #define GPIO_PIN23_INT_TYPE_S 7 /** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S) #define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN23_WAKEUP_ENABLE_S 10 /** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN23_INT_ENA 0x0000001FU #define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S) @@ -1991,1918 +1560,1787 @@ extern "C" { #define GPIO_PIN23_INT_ENA_S 13 /** GPIO_PIN24_REG register - * GPIO24 configuration register + * GPIO pin configuration register */ -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124) +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x134) /** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN24_SYNC2_BYPASS 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S) #define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC2_BYPASS_S 0 /** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ #define GPIO_PIN24_PAD_DRIVER (BIT(2)) #define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S) #define GPIO_PIN24_PAD_DRIVER_V 0x00000001U #define GPIO_PIN24_PAD_DRIVER_S 2 /** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ #define GPIO_PIN24_SYNC1_BYPASS 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S) #define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U #define GPIO_PIN24_SYNC1_BYPASS_S 3 /** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ #define GPIO_PIN24_INT_TYPE 0x00000007U #define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S) #define GPIO_PIN24_INT_TYPE_V 0x00000007U #define GPIO_PIN24_INT_TYPE_S 7 /** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ #define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) #define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S) #define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U #define GPIO_PIN24_WAKEUP_ENABLE_S 10 /** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ #define GPIO_PIN24_INT_ENA 0x0000001FU #define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S) #define GPIO_PIN24_INT_ENA_V 0x0000001FU #define GPIO_PIN24_INT_ENA_S 13 +/** GPIO_PIN25_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x138) +/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC2_BYPASS_S 0 +/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S) +#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN25_PAD_DRIVER_S 2 +/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN25_INT_TYPE 0x00000007U +#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S) +#define GPIO_PIN25_INT_TYPE_V 0x00000007U +#define GPIO_PIN25_INT_TYPE_S 7 +/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN25_INT_ENA 0x0000001FU +#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S) +#define GPIO_PIN25_INT_ENA_V 0x0000001FU +#define GPIO_PIN25_INT_ENA_S 13 + +/** GPIO_PIN26_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x13c) +/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC2_BYPASS_S 0 +/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S) +#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN26_PAD_DRIVER_S 2 +/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN26_INT_TYPE 0x00000007U +#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S) +#define GPIO_PIN26_INT_TYPE_V 0x00000007U +#define GPIO_PIN26_INT_TYPE_S 7 +/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN26_INT_ENA 0x0000001FU +#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S) +#define GPIO_PIN26_INT_ENA_V 0x0000001FU +#define GPIO_PIN26_INT_ENA_S 13 + +/** GPIO_PIN27_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x140) +/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC2_BYPASS_S 0 +/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S) +#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN27_PAD_DRIVER_S 2 +/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN27_INT_TYPE 0x00000007U +#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S) +#define GPIO_PIN27_INT_TYPE_V 0x00000007U +#define GPIO_PIN27_INT_TYPE_S 7 +/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN27_INT_ENA 0x0000001FU +#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S) +#define GPIO_PIN27_INT_ENA_V 0x0000001FU +#define GPIO_PIN27_INT_ENA_S 13 + +/** GPIO_PIN28_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x144) +/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC2_BYPASS_S 0 +/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S) +#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN28_PAD_DRIVER_S 2 +/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN28_INT_TYPE 0x00000007U +#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S) +#define GPIO_PIN28_INT_TYPE_V 0x00000007U +#define GPIO_PIN28_INT_TYPE_S 7 +/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN28_INT_ENA 0x0000001FU +#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S) +#define GPIO_PIN28_INT_ENA_V 0x0000001FU +#define GPIO_PIN28_INT_ENA_S 13 + +/** GPIO_PIN29_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0x148) +/** GPIO_PIN29_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_M (GPIO_PIN29_SYNC2_BYPASS_V << GPIO_PIN29_SYNC2_BYPASS_S) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC2_BYPASS_S 0 +/** GPIO_PIN29_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (GPIO_PIN29_PAD_DRIVER_V << GPIO_PIN29_PAD_DRIVER_S) +#define GPIO_PIN29_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN29_PAD_DRIVER_S 2 +/** GPIO_PIN29_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_M (GPIO_PIN29_SYNC1_BYPASS_V << GPIO_PIN29_SYNC1_BYPASS_S) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/** GPIO_PIN29_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN29_INT_TYPE 0x00000007U +#define GPIO_PIN29_INT_TYPE_M (GPIO_PIN29_INT_TYPE_V << GPIO_PIN29_INT_TYPE_S) +#define GPIO_PIN29_INT_TYPE_V 0x00000007U +#define GPIO_PIN29_INT_TYPE_S 7 +/** GPIO_PIN29_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (GPIO_PIN29_WAKEUP_ENABLE_V << GPIO_PIN29_WAKEUP_ENABLE_S) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/** GPIO_PIN29_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN29_INT_ENA 0x0000001FU +#define GPIO_PIN29_INT_ENA_M (GPIO_PIN29_INT_ENA_V << GPIO_PIN29_INT_ENA_S) +#define GPIO_PIN29_INT_ENA_V 0x0000001FU +#define GPIO_PIN29_INT_ENA_S 13 + +/** GPIO_PIN30_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0x14c) +/** GPIO_PIN30_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_M (GPIO_PIN30_SYNC2_BYPASS_V << GPIO_PIN30_SYNC2_BYPASS_S) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC2_BYPASS_S 0 +/** GPIO_PIN30_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (GPIO_PIN30_PAD_DRIVER_V << GPIO_PIN30_PAD_DRIVER_S) +#define GPIO_PIN30_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN30_PAD_DRIVER_S 2 +/** GPIO_PIN30_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_M (GPIO_PIN30_SYNC1_BYPASS_V << GPIO_PIN30_SYNC1_BYPASS_S) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/** GPIO_PIN30_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN30_INT_TYPE 0x00000007U +#define GPIO_PIN30_INT_TYPE_M (GPIO_PIN30_INT_TYPE_V << GPIO_PIN30_INT_TYPE_S) +#define GPIO_PIN30_INT_TYPE_V 0x00000007U +#define GPIO_PIN30_INT_TYPE_S 7 +/** GPIO_PIN30_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (GPIO_PIN30_WAKEUP_ENABLE_V << GPIO_PIN30_WAKEUP_ENABLE_S) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/** GPIO_PIN30_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN30_INT_ENA 0x0000001FU +#define GPIO_PIN30_INT_ENA_M (GPIO_PIN30_INT_ENA_V << GPIO_PIN30_INT_ENA_S) +#define GPIO_PIN30_INT_ENA_V 0x0000001FU +#define GPIO_PIN30_INT_ENA_S 13 + +/** GPIO_PIN31_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0x150) +/** GPIO_PIN31_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_M (GPIO_PIN31_SYNC2_BYPASS_V << GPIO_PIN31_SYNC2_BYPASS_S) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC2_BYPASS_S 0 +/** GPIO_PIN31_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (GPIO_PIN31_PAD_DRIVER_V << GPIO_PIN31_PAD_DRIVER_S) +#define GPIO_PIN31_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN31_PAD_DRIVER_S 2 +/** GPIO_PIN31_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_M (GPIO_PIN31_SYNC1_BYPASS_V << GPIO_PIN31_SYNC1_BYPASS_S) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/** GPIO_PIN31_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN31_INT_TYPE 0x00000007U +#define GPIO_PIN31_INT_TYPE_M (GPIO_PIN31_INT_TYPE_V << GPIO_PIN31_INT_TYPE_S) +#define GPIO_PIN31_INT_TYPE_V 0x00000007U +#define GPIO_PIN31_INT_TYPE_S 7 +/** GPIO_PIN31_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (GPIO_PIN31_WAKEUP_ENABLE_V << GPIO_PIN31_WAKEUP_ENABLE_S) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/** GPIO_PIN31_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN31_INT_ENA 0x0000001FU +#define GPIO_PIN31_INT_ENA_M (GPIO_PIN31_INT_ENA_V << GPIO_PIN31_INT_ENA_S) +#define GPIO_PIN31_INT_ENA_V 0x0000001FU +#define GPIO_PIN31_INT_ENA_S 13 + +/** GPIO_PIN32_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0x154) +/** GPIO_PIN32_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_M (GPIO_PIN32_SYNC2_BYPASS_V << GPIO_PIN32_SYNC2_BYPASS_S) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC2_BYPASS_S 0 +/** GPIO_PIN32_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (GPIO_PIN32_PAD_DRIVER_V << GPIO_PIN32_PAD_DRIVER_S) +#define GPIO_PIN32_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN32_PAD_DRIVER_S 2 +/** GPIO_PIN32_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_M (GPIO_PIN32_SYNC1_BYPASS_V << GPIO_PIN32_SYNC1_BYPASS_S) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/** GPIO_PIN32_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN32_INT_TYPE 0x00000007U +#define GPIO_PIN32_INT_TYPE_M (GPIO_PIN32_INT_TYPE_V << GPIO_PIN32_INT_TYPE_S) +#define GPIO_PIN32_INT_TYPE_V 0x00000007U +#define GPIO_PIN32_INT_TYPE_S 7 +/** GPIO_PIN32_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (GPIO_PIN32_WAKEUP_ENABLE_V << GPIO_PIN32_WAKEUP_ENABLE_S) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/** GPIO_PIN32_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN32_INT_ENA 0x0000001FU +#define GPIO_PIN32_INT_ENA_M (GPIO_PIN32_INT_ENA_V << GPIO_PIN32_INT_ENA_S) +#define GPIO_PIN32_INT_ENA_V 0x0000001FU +#define GPIO_PIN32_INT_ENA_S 13 + +/** GPIO_PIN33_REG register + * GPIO pin configuration register + */ +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0x158) +/** GPIO_PIN33_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0; + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_M (GPIO_PIN33_SYNC2_BYPASS_V << GPIO_PIN33_SYNC2_BYPASS_S) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC2_BYPASS_S 0 +/** GPIO_PIN33_PAD_DRIVER : R/W; bitpos: [2]; default: 0; + * set this bit to select pad driver. 1:open-drain. 0:normal. + */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (GPIO_PIN33_PAD_DRIVER_V << GPIO_PIN33_PAD_DRIVER_S) +#define GPIO_PIN33_PAD_DRIVER_V 0x00000001U +#define GPIO_PIN33_PAD_DRIVER_S 2 +/** GPIO_PIN33_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0; + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. + */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_M (GPIO_PIN33_SYNC1_BYPASS_V << GPIO_PIN33_SYNC1_BYPASS_S) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x00000003U +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/** GPIO_PIN33_INT_TYPE : R/W; bitpos: [9:7]; default: 0; + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level + */ +#define GPIO_PIN33_INT_TYPE 0x00000007U +#define GPIO_PIN33_INT_TYPE_M (GPIO_PIN33_INT_TYPE_V << GPIO_PIN33_INT_TYPE_S) +#define GPIO_PIN33_INT_TYPE_V 0x00000007U +#define GPIO_PIN33_INT_TYPE_S 7 +/** GPIO_PIN33_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0; + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) + */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (GPIO_PIN33_WAKEUP_ENABLE_V << GPIO_PIN33_WAKEUP_ENABLE_S) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x00000001U +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/** GPIO_PIN33_INT_ENA : R/W; bitpos: [17:13]; default: 0; + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. + */ +#define GPIO_PIN33_INT_ENA 0x0000001FU +#define GPIO_PIN33_INT_ENA_M (GPIO_PIN33_INT_ENA_V << GPIO_PIN33_INT_ENA_S) +#define GPIO_PIN33_INT_ENA_V 0x0000001FU +#define GPIO_PIN33_INT_ENA_S 13 + /** GPIO_FUNC0_IN_SEL_CFG_REG register - * Configuration register for input signal 0 + * GPIO input function configuration register */ -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) -/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) +/** GPIO_FUNC0_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC0_IN_SEL 0x0000003FU +#define GPIO_FUNC0_IN_SEL 0x0000007FU #define GPIO_FUNC0_IN_SEL_M (GPIO_FUNC0_IN_SEL_V << GPIO_FUNC0_IN_SEL_S) -#define GPIO_FUNC0_IN_SEL_V 0x0000003FU +#define GPIO_FUNC0_IN_SEL_V 0x0000007FU #define GPIO_FUNC0_IN_SEL_S 0 -/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC0_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL (BIT(7)) #define GPIO_FUNC0_IN_INV_SEL_M (GPIO_FUNC0_IN_INV_SEL_V << GPIO_FUNC0_IN_INV_SEL_S) #define GPIO_FUNC0_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC0_IN_INV_SEL_S 6 -/** GPIO_SIG0_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC0_IN_INV_SEL_S 7 +/** GPIO_SIG0_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL (BIT(8)) #define GPIO_SIG0_IN_SEL_M (GPIO_SIG0_IN_SEL_V << GPIO_SIG0_IN_SEL_S) #define GPIO_SIG0_IN_SEL_V 0x00000001U -#define GPIO_SIG0_IN_SEL_S 7 +#define GPIO_SIG0_IN_SEL_S 8 /** GPIO_FUNC6_IN_SEL_CFG_REG register - * Configuration register for input signal 6 + * GPIO input function configuration register */ -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) -/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 6.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) +/** GPIO_FUNC6_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC6_IN_SEL 0x0000003FU +#define GPIO_FUNC6_IN_SEL 0x0000007FU #define GPIO_FUNC6_IN_SEL_M (GPIO_FUNC6_IN_SEL_V << GPIO_FUNC6_IN_SEL_S) -#define GPIO_FUNC6_IN_SEL_V 0x0000003FU +#define GPIO_FUNC6_IN_SEL_V 0x0000007FU #define GPIO_FUNC6_IN_SEL_S 0 -/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC6_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL (BIT(7)) #define GPIO_FUNC6_IN_INV_SEL_M (GPIO_FUNC6_IN_INV_SEL_V << GPIO_FUNC6_IN_INV_SEL_S) #define GPIO_FUNC6_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC6_IN_INV_SEL_S 6 -/** GPIO_SIG6_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC6_IN_INV_SEL_S 7 +/** GPIO_SIG6_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL (BIT(8)) #define GPIO_SIG6_IN_SEL_M (GPIO_SIG6_IN_SEL_V << GPIO_SIG6_IN_SEL_S) #define GPIO_SIG6_IN_SEL_V 0x00000001U -#define GPIO_SIG6_IN_SEL_S 7 +#define GPIO_SIG6_IN_SEL_S 8 /** GPIO_FUNC7_IN_SEL_CFG_REG register - * Configuration register for input signal 7 + * GPIO input function configuration register */ -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) -/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 7.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) +/** GPIO_FUNC7_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC7_IN_SEL 0x0000003FU +#define GPIO_FUNC7_IN_SEL 0x0000007FU #define GPIO_FUNC7_IN_SEL_M (GPIO_FUNC7_IN_SEL_V << GPIO_FUNC7_IN_SEL_S) -#define GPIO_FUNC7_IN_SEL_V 0x0000003FU +#define GPIO_FUNC7_IN_SEL_V 0x0000007FU #define GPIO_FUNC7_IN_SEL_S 0 -/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC7_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL (BIT(7)) #define GPIO_FUNC7_IN_INV_SEL_M (GPIO_FUNC7_IN_INV_SEL_V << GPIO_FUNC7_IN_INV_SEL_S) #define GPIO_FUNC7_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC7_IN_INV_SEL_S 6 -/** GPIO_SIG7_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC7_IN_INV_SEL_S 7 +/** GPIO_SIG7_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL (BIT(8)) #define GPIO_SIG7_IN_SEL_M (GPIO_SIG7_IN_SEL_V << GPIO_SIG7_IN_SEL_S) #define GPIO_SIG7_IN_SEL_V 0x00000001U -#define GPIO_SIG7_IN_SEL_S 7 +#define GPIO_SIG7_IN_SEL_S 8 /** GPIO_FUNC8_IN_SEL_CFG_REG register - * Configuration register for input signal 8 + * GPIO input function configuration register */ -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) -/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 8.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) +/** GPIO_FUNC8_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC8_IN_SEL 0x0000003FU +#define GPIO_FUNC8_IN_SEL 0x0000007FU #define GPIO_FUNC8_IN_SEL_M (GPIO_FUNC8_IN_SEL_V << GPIO_FUNC8_IN_SEL_S) -#define GPIO_FUNC8_IN_SEL_V 0x0000003FU +#define GPIO_FUNC8_IN_SEL_V 0x0000007FU #define GPIO_FUNC8_IN_SEL_S 0 -/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC8_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL (BIT(7)) #define GPIO_FUNC8_IN_INV_SEL_M (GPIO_FUNC8_IN_INV_SEL_V << GPIO_FUNC8_IN_INV_SEL_S) #define GPIO_FUNC8_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC8_IN_INV_SEL_S 6 -/** GPIO_SIG8_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC8_IN_INV_SEL_S 7 +/** GPIO_SIG8_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL (BIT(8)) #define GPIO_SIG8_IN_SEL_M (GPIO_SIG8_IN_SEL_V << GPIO_SIG8_IN_SEL_S) #define GPIO_SIG8_IN_SEL_V 0x00000001U -#define GPIO_SIG8_IN_SEL_S 7 +#define GPIO_SIG8_IN_SEL_S 8 /** GPIO_FUNC9_IN_SEL_CFG_REG register - * Configuration register for input signal 9 + * GPIO input function configuration register */ -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) -/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 9.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) +/** GPIO_FUNC9_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC9_IN_SEL 0x0000003FU +#define GPIO_FUNC9_IN_SEL 0x0000007FU #define GPIO_FUNC9_IN_SEL_M (GPIO_FUNC9_IN_SEL_V << GPIO_FUNC9_IN_SEL_S) -#define GPIO_FUNC9_IN_SEL_V 0x0000003FU +#define GPIO_FUNC9_IN_SEL_V 0x0000007FU #define GPIO_FUNC9_IN_SEL_S 0 -/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC9_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL (BIT(7)) #define GPIO_FUNC9_IN_INV_SEL_M (GPIO_FUNC9_IN_INV_SEL_V << GPIO_FUNC9_IN_INV_SEL_S) #define GPIO_FUNC9_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC9_IN_INV_SEL_S 6 -/** GPIO_SIG9_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC9_IN_INV_SEL_S 7 +/** GPIO_SIG9_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL (BIT(8)) #define GPIO_SIG9_IN_SEL_M (GPIO_SIG9_IN_SEL_V << GPIO_SIG9_IN_SEL_S) #define GPIO_SIG9_IN_SEL_V 0x00000001U -#define GPIO_SIG9_IN_SEL_S 7 +#define GPIO_SIG9_IN_SEL_S 8 /** GPIO_FUNC10_IN_SEL_CFG_REG register - * Configuration register for input signal 10 + * GPIO input function configuration register */ -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) -/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 10.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) +/** GPIO_FUNC10_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC10_IN_SEL 0x0000003FU +#define GPIO_FUNC10_IN_SEL 0x0000007FU #define GPIO_FUNC10_IN_SEL_M (GPIO_FUNC10_IN_SEL_V << GPIO_FUNC10_IN_SEL_S) -#define GPIO_FUNC10_IN_SEL_V 0x0000003FU +#define GPIO_FUNC10_IN_SEL_V 0x0000007FU #define GPIO_FUNC10_IN_SEL_S 0 -/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC10_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL (BIT(7)) #define GPIO_FUNC10_IN_INV_SEL_M (GPIO_FUNC10_IN_INV_SEL_V << GPIO_FUNC10_IN_INV_SEL_S) #define GPIO_FUNC10_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC10_IN_INV_SEL_S 6 -/** GPIO_SIG10_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC10_IN_INV_SEL_S 7 +/** GPIO_SIG10_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL (BIT(8)) #define GPIO_SIG10_IN_SEL_M (GPIO_SIG10_IN_SEL_V << GPIO_SIG10_IN_SEL_S) #define GPIO_SIG10_IN_SEL_V 0x00000001U -#define GPIO_SIG10_IN_SEL_S 7 +#define GPIO_SIG10_IN_SEL_S 8 /** GPIO_FUNC11_IN_SEL_CFG_REG register - * Configuration register for input signal 11 + * GPIO input function configuration register */ -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) -/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 11.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/** GPIO_FUNC11_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC11_IN_SEL 0x0000003FU +#define GPIO_FUNC11_IN_SEL 0x0000007FU #define GPIO_FUNC11_IN_SEL_M (GPIO_FUNC11_IN_SEL_V << GPIO_FUNC11_IN_SEL_S) -#define GPIO_FUNC11_IN_SEL_V 0x0000003FU +#define GPIO_FUNC11_IN_SEL_V 0x0000007FU #define GPIO_FUNC11_IN_SEL_S 0 -/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC11_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL (BIT(7)) #define GPIO_FUNC11_IN_INV_SEL_M (GPIO_FUNC11_IN_INV_SEL_V << GPIO_FUNC11_IN_INV_SEL_S) #define GPIO_FUNC11_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC11_IN_INV_SEL_S 6 -/** GPIO_SIG11_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC11_IN_INV_SEL_S 7 +/** GPIO_SIG11_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL (BIT(8)) #define GPIO_SIG11_IN_SEL_M (GPIO_SIG11_IN_SEL_V << GPIO_SIG11_IN_SEL_S) #define GPIO_SIG11_IN_SEL_V 0x00000001U -#define GPIO_SIG11_IN_SEL_S 7 +#define GPIO_SIG11_IN_SEL_S 8 /** GPIO_FUNC12_IN_SEL_CFG_REG register - * Configuration register for input signal 12 + * GPIO input function configuration register */ -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) -/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 12.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/** GPIO_FUNC12_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC12_IN_SEL 0x0000003FU +#define GPIO_FUNC12_IN_SEL 0x0000007FU #define GPIO_FUNC12_IN_SEL_M (GPIO_FUNC12_IN_SEL_V << GPIO_FUNC12_IN_SEL_S) -#define GPIO_FUNC12_IN_SEL_V 0x0000003FU +#define GPIO_FUNC12_IN_SEL_V 0x0000007FU #define GPIO_FUNC12_IN_SEL_S 0 -/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC12_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL (BIT(7)) #define GPIO_FUNC12_IN_INV_SEL_M (GPIO_FUNC12_IN_INV_SEL_V << GPIO_FUNC12_IN_INV_SEL_S) #define GPIO_FUNC12_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC12_IN_INV_SEL_S 6 -/** GPIO_SIG12_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC12_IN_INV_SEL_S 7 +/** GPIO_SIG12_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL (BIT(8)) #define GPIO_SIG12_IN_SEL_M (GPIO_SIG12_IN_SEL_V << GPIO_SIG12_IN_SEL_S) #define GPIO_SIG12_IN_SEL_V 0x00000001U -#define GPIO_SIG12_IN_SEL_S 7 +#define GPIO_SIG12_IN_SEL_S 8 /** GPIO_FUNC13_IN_SEL_CFG_REG register - * Configuration register for input signal 13 + * GPIO input function configuration register */ -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) -/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 13.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/** GPIO_FUNC13_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC13_IN_SEL 0x0000003FU +#define GPIO_FUNC13_IN_SEL 0x0000007FU #define GPIO_FUNC13_IN_SEL_M (GPIO_FUNC13_IN_SEL_V << GPIO_FUNC13_IN_SEL_S) -#define GPIO_FUNC13_IN_SEL_V 0x0000003FU +#define GPIO_FUNC13_IN_SEL_V 0x0000007FU #define GPIO_FUNC13_IN_SEL_S 0 -/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC13_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL (BIT(7)) #define GPIO_FUNC13_IN_INV_SEL_M (GPIO_FUNC13_IN_INV_SEL_V << GPIO_FUNC13_IN_INV_SEL_S) #define GPIO_FUNC13_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC13_IN_INV_SEL_S 6 -/** GPIO_SIG13_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC13_IN_INV_SEL_S 7 +/** GPIO_SIG13_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL (BIT(8)) #define GPIO_SIG13_IN_SEL_M (GPIO_SIG13_IN_SEL_V << GPIO_SIG13_IN_SEL_S) #define GPIO_SIG13_IN_SEL_V 0x00000001U -#define GPIO_SIG13_IN_SEL_S 7 +#define GPIO_SIG13_IN_SEL_S 8 /** GPIO_FUNC14_IN_SEL_CFG_REG register - * Configuration register for input signal 14 + * GPIO input function configuration register */ -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) -/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 14.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) +/** GPIO_FUNC14_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC14_IN_SEL 0x0000003FU +#define GPIO_FUNC14_IN_SEL 0x0000007FU #define GPIO_FUNC14_IN_SEL_M (GPIO_FUNC14_IN_SEL_V << GPIO_FUNC14_IN_SEL_S) -#define GPIO_FUNC14_IN_SEL_V 0x0000003FU +#define GPIO_FUNC14_IN_SEL_V 0x0000007FU #define GPIO_FUNC14_IN_SEL_S 0 -/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC14_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL (BIT(7)) #define GPIO_FUNC14_IN_INV_SEL_M (GPIO_FUNC14_IN_INV_SEL_V << GPIO_FUNC14_IN_INV_SEL_S) #define GPIO_FUNC14_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC14_IN_INV_SEL_S 6 -/** GPIO_SIG14_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC14_IN_INV_SEL_S 7 +/** GPIO_SIG14_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL (BIT(8)) #define GPIO_SIG14_IN_SEL_M (GPIO_SIG14_IN_SEL_V << GPIO_SIG14_IN_SEL_S) #define GPIO_SIG14_IN_SEL_V 0x00000001U -#define GPIO_SIG14_IN_SEL_S 7 +#define GPIO_SIG14_IN_SEL_S 8 /** GPIO_FUNC15_IN_SEL_CFG_REG register - * Configuration register for input signal 15 + * GPIO input function configuration register */ -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) -/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 15.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/** GPIO_FUNC15_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC15_IN_SEL 0x0000003FU +#define GPIO_FUNC15_IN_SEL 0x0000007FU #define GPIO_FUNC15_IN_SEL_M (GPIO_FUNC15_IN_SEL_V << GPIO_FUNC15_IN_SEL_S) -#define GPIO_FUNC15_IN_SEL_V 0x0000003FU +#define GPIO_FUNC15_IN_SEL_V 0x0000007FU #define GPIO_FUNC15_IN_SEL_S 0 -/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC15_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL (BIT(7)) #define GPIO_FUNC15_IN_INV_SEL_M (GPIO_FUNC15_IN_INV_SEL_V << GPIO_FUNC15_IN_INV_SEL_S) #define GPIO_FUNC15_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC15_IN_INV_SEL_S 6 -/** GPIO_SIG15_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC15_IN_INV_SEL_S 7 +/** GPIO_SIG15_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL (BIT(8)) #define GPIO_SIG15_IN_SEL_M (GPIO_SIG15_IN_SEL_V << GPIO_SIG15_IN_SEL_S) #define GPIO_SIG15_IN_SEL_V 0x00000001U -#define GPIO_SIG15_IN_SEL_S 7 +#define GPIO_SIG15_IN_SEL_S 8 /** GPIO_FUNC16_IN_SEL_CFG_REG register - * Configuration register for input signal 16 + * GPIO input function configuration register */ -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) -/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 16.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/** GPIO_FUNC16_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC16_IN_SEL 0x0000003FU +#define GPIO_FUNC16_IN_SEL 0x0000007FU #define GPIO_FUNC16_IN_SEL_M (GPIO_FUNC16_IN_SEL_V << GPIO_FUNC16_IN_SEL_S) -#define GPIO_FUNC16_IN_SEL_V 0x0000003FU +#define GPIO_FUNC16_IN_SEL_V 0x0000007FU #define GPIO_FUNC16_IN_SEL_S 0 -/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC16_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL (BIT(7)) #define GPIO_FUNC16_IN_INV_SEL_M (GPIO_FUNC16_IN_INV_SEL_V << GPIO_FUNC16_IN_INV_SEL_S) #define GPIO_FUNC16_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC16_IN_INV_SEL_S 6 -/** GPIO_SIG16_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC16_IN_INV_SEL_S 7 +/** GPIO_SIG16_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL (BIT(8)) #define GPIO_SIG16_IN_SEL_M (GPIO_SIG16_IN_SEL_V << GPIO_SIG16_IN_SEL_S) #define GPIO_SIG16_IN_SEL_V 0x00000001U -#define GPIO_SIG16_IN_SEL_S 7 +#define GPIO_SIG16_IN_SEL_S 8 /** GPIO_FUNC17_IN_SEL_CFG_REG register - * Configuration register for input signal 17 + * GPIO input function configuration register */ -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) -/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 17.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/** GPIO_FUNC17_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC17_IN_SEL 0x0000003FU +#define GPIO_FUNC17_IN_SEL 0x0000007FU #define GPIO_FUNC17_IN_SEL_M (GPIO_FUNC17_IN_SEL_V << GPIO_FUNC17_IN_SEL_S) -#define GPIO_FUNC17_IN_SEL_V 0x0000003FU +#define GPIO_FUNC17_IN_SEL_V 0x0000007FU #define GPIO_FUNC17_IN_SEL_S 0 -/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC17_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL (BIT(7)) #define GPIO_FUNC17_IN_INV_SEL_M (GPIO_FUNC17_IN_INV_SEL_V << GPIO_FUNC17_IN_INV_SEL_S) #define GPIO_FUNC17_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC17_IN_INV_SEL_S 6 -/** GPIO_SIG17_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC17_IN_INV_SEL_S 7 +/** GPIO_SIG17_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL (BIT(8)) #define GPIO_SIG17_IN_SEL_M (GPIO_SIG17_IN_SEL_V << GPIO_SIG17_IN_SEL_S) #define GPIO_SIG17_IN_SEL_V 0x00000001U -#define GPIO_SIG17_IN_SEL_S 7 +#define GPIO_SIG17_IN_SEL_S 8 /** GPIO_FUNC27_IN_SEL_CFG_REG register - * Configuration register for input signal 27 + * GPIO input function configuration register */ -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) -/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 27.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/** GPIO_FUNC27_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC27_IN_SEL 0x0000003FU +#define GPIO_FUNC27_IN_SEL 0x0000007FU #define GPIO_FUNC27_IN_SEL_M (GPIO_FUNC27_IN_SEL_V << GPIO_FUNC27_IN_SEL_S) -#define GPIO_FUNC27_IN_SEL_V 0x0000003FU +#define GPIO_FUNC27_IN_SEL_V 0x0000007FU #define GPIO_FUNC27_IN_SEL_S 0 -/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC27_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL (BIT(7)) #define GPIO_FUNC27_IN_INV_SEL_M (GPIO_FUNC27_IN_INV_SEL_V << GPIO_FUNC27_IN_INV_SEL_S) #define GPIO_FUNC27_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC27_IN_INV_SEL_S 6 -/** GPIO_SIG27_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC27_IN_INV_SEL_S 7 +/** GPIO_SIG27_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL (BIT(8)) #define GPIO_SIG27_IN_SEL_M (GPIO_SIG27_IN_SEL_V << GPIO_SIG27_IN_SEL_S) #define GPIO_SIG27_IN_SEL_V 0x00000001U -#define GPIO_SIG27_IN_SEL_S 7 +#define GPIO_SIG27_IN_SEL_S 8 /** GPIO_FUNC28_IN_SEL_CFG_REG register - * Configuration register for input signal 28 + * GPIO input function configuration register */ -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) -/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 28.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/** GPIO_FUNC28_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC28_IN_SEL 0x0000003FU +#define GPIO_FUNC28_IN_SEL 0x0000007FU #define GPIO_FUNC28_IN_SEL_M (GPIO_FUNC28_IN_SEL_V << GPIO_FUNC28_IN_SEL_S) -#define GPIO_FUNC28_IN_SEL_V 0x0000003FU +#define GPIO_FUNC28_IN_SEL_V 0x0000007FU #define GPIO_FUNC28_IN_SEL_S 0 -/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC28_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL (BIT(7)) #define GPIO_FUNC28_IN_INV_SEL_M (GPIO_FUNC28_IN_INV_SEL_V << GPIO_FUNC28_IN_INV_SEL_S) #define GPIO_FUNC28_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC28_IN_INV_SEL_S 6 -/** GPIO_SIG28_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC28_IN_INV_SEL_S 7 +/** GPIO_SIG28_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL (BIT(8)) #define GPIO_SIG28_IN_SEL_M (GPIO_SIG28_IN_SEL_V << GPIO_SIG28_IN_SEL_S) #define GPIO_SIG28_IN_SEL_V 0x00000001U -#define GPIO_SIG28_IN_SEL_S 7 +#define GPIO_SIG28_IN_SEL_S 8 /** GPIO_FUNC29_IN_SEL_CFG_REG register - * Configuration register for input signal 29 + * GPIO input function configuration register */ -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) -/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 29.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/** GPIO_FUNC29_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC29_IN_SEL 0x0000003FU +#define GPIO_FUNC29_IN_SEL 0x0000007FU #define GPIO_FUNC29_IN_SEL_M (GPIO_FUNC29_IN_SEL_V << GPIO_FUNC29_IN_SEL_S) -#define GPIO_FUNC29_IN_SEL_V 0x0000003FU +#define GPIO_FUNC29_IN_SEL_V 0x0000007FU #define GPIO_FUNC29_IN_SEL_S 0 -/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC29_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL (BIT(7)) #define GPIO_FUNC29_IN_INV_SEL_M (GPIO_FUNC29_IN_INV_SEL_V << GPIO_FUNC29_IN_INV_SEL_S) #define GPIO_FUNC29_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC29_IN_INV_SEL_S 6 -/** GPIO_SIG29_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC29_IN_INV_SEL_S 7 +/** GPIO_SIG29_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL (BIT(8)) #define GPIO_SIG29_IN_SEL_M (GPIO_SIG29_IN_SEL_V << GPIO_SIG29_IN_SEL_S) #define GPIO_SIG29_IN_SEL_V 0x00000001U -#define GPIO_SIG29_IN_SEL_S 7 +#define GPIO_SIG29_IN_SEL_S 8 /** GPIO_FUNC30_IN_SEL_CFG_REG register - * Configuration register for input signal 30 + * GPIO input function configuration register */ -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) -/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 30.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) +/** GPIO_FUNC30_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC30_IN_SEL 0x0000003FU +#define GPIO_FUNC30_IN_SEL 0x0000007FU #define GPIO_FUNC30_IN_SEL_M (GPIO_FUNC30_IN_SEL_V << GPIO_FUNC30_IN_SEL_S) -#define GPIO_FUNC30_IN_SEL_V 0x0000003FU +#define GPIO_FUNC30_IN_SEL_V 0x0000007FU #define GPIO_FUNC30_IN_SEL_S 0 -/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC30_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL (BIT(7)) #define GPIO_FUNC30_IN_INV_SEL_M (GPIO_FUNC30_IN_INV_SEL_V << GPIO_FUNC30_IN_INV_SEL_S) #define GPIO_FUNC30_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC30_IN_INV_SEL_S 6 -/** GPIO_SIG30_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC30_IN_INV_SEL_S 7 +/** GPIO_SIG30_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL (BIT(8)) #define GPIO_SIG30_IN_SEL_M (GPIO_SIG30_IN_SEL_V << GPIO_SIG30_IN_SEL_S) #define GPIO_SIG30_IN_SEL_V 0x00000001U -#define GPIO_SIG30_IN_SEL_S 7 +#define GPIO_SIG30_IN_SEL_S 8 /** GPIO_FUNC31_IN_SEL_CFG_REG register - * Configuration register for input signal 31 + * GPIO input function configuration register */ -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) -/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 31.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/** GPIO_FUNC31_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC31_IN_SEL 0x0000003FU +#define GPIO_FUNC31_IN_SEL 0x0000007FU #define GPIO_FUNC31_IN_SEL_M (GPIO_FUNC31_IN_SEL_V << GPIO_FUNC31_IN_SEL_S) -#define GPIO_FUNC31_IN_SEL_V 0x0000003FU +#define GPIO_FUNC31_IN_SEL_V 0x0000007FU #define GPIO_FUNC31_IN_SEL_S 0 -/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC31_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL (BIT(7)) #define GPIO_FUNC31_IN_INV_SEL_M (GPIO_FUNC31_IN_INV_SEL_V << GPIO_FUNC31_IN_INV_SEL_S) #define GPIO_FUNC31_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC31_IN_INV_SEL_S 6 -/** GPIO_SIG31_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC31_IN_INV_SEL_S 7 +/** GPIO_SIG31_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL (BIT(8)) #define GPIO_SIG31_IN_SEL_M (GPIO_SIG31_IN_SEL_V << GPIO_SIG31_IN_SEL_S) #define GPIO_SIG31_IN_SEL_V 0x00000001U -#define GPIO_SIG31_IN_SEL_S 7 +#define GPIO_SIG31_IN_SEL_S 8 /** GPIO_FUNC32_IN_SEL_CFG_REG register - * Configuration register for input signal 32 + * GPIO input function configuration register */ -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) -/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 32.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) +/** GPIO_FUNC32_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC32_IN_SEL 0x0000003FU +#define GPIO_FUNC32_IN_SEL 0x0000007FU #define GPIO_FUNC32_IN_SEL_M (GPIO_FUNC32_IN_SEL_V << GPIO_FUNC32_IN_SEL_S) -#define GPIO_FUNC32_IN_SEL_V 0x0000003FU +#define GPIO_FUNC32_IN_SEL_V 0x0000007FU #define GPIO_FUNC32_IN_SEL_S 0 -/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC32_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL (BIT(7)) #define GPIO_FUNC32_IN_INV_SEL_M (GPIO_FUNC32_IN_INV_SEL_V << GPIO_FUNC32_IN_INV_SEL_S) #define GPIO_FUNC32_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC32_IN_INV_SEL_S 6 -/** GPIO_SIG32_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC32_IN_INV_SEL_S 7 +/** GPIO_SIG32_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL (BIT(8)) #define GPIO_SIG32_IN_SEL_M (GPIO_SIG32_IN_SEL_V << GPIO_SIG32_IN_SEL_S) #define GPIO_SIG32_IN_SEL_V 0x00000001U -#define GPIO_SIG32_IN_SEL_S 7 +#define GPIO_SIG32_IN_SEL_S 8 /** GPIO_FUNC33_IN_SEL_CFG_REG register - * Configuration register for input signal 33 + * GPIO input function configuration register */ -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) -/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 33.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) +/** GPIO_FUNC33_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC33_IN_SEL 0x0000003FU +#define GPIO_FUNC33_IN_SEL 0x0000007FU #define GPIO_FUNC33_IN_SEL_M (GPIO_FUNC33_IN_SEL_V << GPIO_FUNC33_IN_SEL_S) -#define GPIO_FUNC33_IN_SEL_V 0x0000003FU +#define GPIO_FUNC33_IN_SEL_V 0x0000007FU #define GPIO_FUNC33_IN_SEL_S 0 -/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC33_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL (BIT(7)) #define GPIO_FUNC33_IN_INV_SEL_M (GPIO_FUNC33_IN_INV_SEL_V << GPIO_FUNC33_IN_INV_SEL_S) #define GPIO_FUNC33_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC33_IN_INV_SEL_S 6 -/** GPIO_SIG33_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC33_IN_INV_SEL_S 7 +/** GPIO_SIG33_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL (BIT(8)) #define GPIO_SIG33_IN_SEL_M (GPIO_SIG33_IN_SEL_V << GPIO_SIG33_IN_SEL_S) #define GPIO_SIG33_IN_SEL_V 0x00000001U -#define GPIO_SIG33_IN_SEL_S 7 +#define GPIO_SIG33_IN_SEL_S 8 /** GPIO_FUNC34_IN_SEL_CFG_REG register - * Configuration register for input signal 34 + * GPIO input function configuration register */ -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) -/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 34.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35c) +/** GPIO_FUNC34_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC34_IN_SEL 0x0000003FU +#define GPIO_FUNC34_IN_SEL 0x0000007FU #define GPIO_FUNC34_IN_SEL_M (GPIO_FUNC34_IN_SEL_V << GPIO_FUNC34_IN_SEL_S) -#define GPIO_FUNC34_IN_SEL_V 0x0000003FU +#define GPIO_FUNC34_IN_SEL_V 0x0000007FU #define GPIO_FUNC34_IN_SEL_S 0 -/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC34_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL (BIT(7)) #define GPIO_FUNC34_IN_INV_SEL_M (GPIO_FUNC34_IN_INV_SEL_V << GPIO_FUNC34_IN_INV_SEL_S) #define GPIO_FUNC34_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC34_IN_INV_SEL_S 6 -/** GPIO_SIG34_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC34_IN_INV_SEL_S 7 +/** GPIO_SIG34_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL (BIT(8)) #define GPIO_SIG34_IN_SEL_M (GPIO_SIG34_IN_SEL_V << GPIO_SIG34_IN_SEL_S) #define GPIO_SIG34_IN_SEL_V 0x00000001U -#define GPIO_SIG34_IN_SEL_S 7 +#define GPIO_SIG34_IN_SEL_S 8 /** GPIO_FUNC35_IN_SEL_CFG_REG register - * Configuration register for input signal 35 + * GPIO input function configuration register */ -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) -/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 35.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) +/** GPIO_FUNC35_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC35_IN_SEL 0x0000003FU +#define GPIO_FUNC35_IN_SEL 0x0000007FU #define GPIO_FUNC35_IN_SEL_M (GPIO_FUNC35_IN_SEL_V << GPIO_FUNC35_IN_SEL_S) -#define GPIO_FUNC35_IN_SEL_V 0x0000003FU +#define GPIO_FUNC35_IN_SEL_V 0x0000007FU #define GPIO_FUNC35_IN_SEL_S 0 -/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC35_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL (BIT(7)) #define GPIO_FUNC35_IN_INV_SEL_M (GPIO_FUNC35_IN_INV_SEL_V << GPIO_FUNC35_IN_INV_SEL_S) #define GPIO_FUNC35_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC35_IN_INV_SEL_S 6 -/** GPIO_SIG35_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC35_IN_INV_SEL_S 7 +/** GPIO_SIG35_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL (BIT(8)) #define GPIO_SIG35_IN_SEL_M (GPIO_SIG35_IN_SEL_V << GPIO_SIG35_IN_SEL_S) #define GPIO_SIG35_IN_SEL_V 0x00000001U -#define GPIO_SIG35_IN_SEL_S 7 +#define GPIO_SIG35_IN_SEL_S 8 /** GPIO_FUNC41_IN_SEL_CFG_REG register - * Configuration register for input signal 41 + * GPIO input function configuration register */ -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) -/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 41.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) +/** GPIO_FUNC41_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC41_IN_SEL 0x0000003FU +#define GPIO_FUNC41_IN_SEL 0x0000007FU #define GPIO_FUNC41_IN_SEL_M (GPIO_FUNC41_IN_SEL_V << GPIO_FUNC41_IN_SEL_S) -#define GPIO_FUNC41_IN_SEL_V 0x0000003FU +#define GPIO_FUNC41_IN_SEL_V 0x0000007FU #define GPIO_FUNC41_IN_SEL_S 0 -/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC41_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL (BIT(7)) #define GPIO_FUNC41_IN_INV_SEL_M (GPIO_FUNC41_IN_INV_SEL_V << GPIO_FUNC41_IN_INV_SEL_S) #define GPIO_FUNC41_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC41_IN_INV_SEL_S 6 -/** GPIO_SIG41_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC41_IN_INV_SEL_S 7 +/** GPIO_SIG41_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL (BIT(8)) #define GPIO_SIG41_IN_SEL_M (GPIO_SIG41_IN_SEL_V << GPIO_SIG41_IN_SEL_S) #define GPIO_SIG41_IN_SEL_V 0x00000001U -#define GPIO_SIG41_IN_SEL_S 7 +#define GPIO_SIG41_IN_SEL_S 8 /** GPIO_FUNC42_IN_SEL_CFG_REG register - * Configuration register for input signal 42 + * GPIO input function configuration register */ -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36c) -/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 42.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) +/** GPIO_FUNC42_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC42_IN_SEL 0x0000003FU +#define GPIO_FUNC42_IN_SEL 0x0000007FU #define GPIO_FUNC42_IN_SEL_M (GPIO_FUNC42_IN_SEL_V << GPIO_FUNC42_IN_SEL_S) -#define GPIO_FUNC42_IN_SEL_V 0x0000003FU +#define GPIO_FUNC42_IN_SEL_V 0x0000007FU #define GPIO_FUNC42_IN_SEL_S 0 -/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC42_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL (BIT(7)) #define GPIO_FUNC42_IN_INV_SEL_M (GPIO_FUNC42_IN_INV_SEL_V << GPIO_FUNC42_IN_INV_SEL_S) #define GPIO_FUNC42_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC42_IN_INV_SEL_S 6 -/** GPIO_SIG42_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC42_IN_INV_SEL_S 7 +/** GPIO_SIG42_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL (BIT(8)) #define GPIO_SIG42_IN_SEL_M (GPIO_SIG42_IN_SEL_V << GPIO_SIG42_IN_SEL_S) #define GPIO_SIG42_IN_SEL_V 0x00000001U -#define GPIO_SIG42_IN_SEL_S 7 +#define GPIO_SIG42_IN_SEL_S 8 /** GPIO_FUNC43_IN_SEL_CFG_REG register - * Configuration register for input signal 43 + * GPIO input function configuration register */ -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) -/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 43.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) +/** GPIO_FUNC43_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC43_IN_SEL 0x0000003FU +#define GPIO_FUNC43_IN_SEL 0x0000007FU #define GPIO_FUNC43_IN_SEL_M (GPIO_FUNC43_IN_SEL_V << GPIO_FUNC43_IN_SEL_S) -#define GPIO_FUNC43_IN_SEL_V 0x0000003FU +#define GPIO_FUNC43_IN_SEL_V 0x0000007FU #define GPIO_FUNC43_IN_SEL_S 0 -/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC43_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL (BIT(7)) #define GPIO_FUNC43_IN_INV_SEL_M (GPIO_FUNC43_IN_INV_SEL_V << GPIO_FUNC43_IN_INV_SEL_S) #define GPIO_FUNC43_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC43_IN_INV_SEL_S 6 -/** GPIO_SIG43_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC43_IN_INV_SEL_S 7 +/** GPIO_SIG43_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL (BIT(8)) #define GPIO_SIG43_IN_SEL_M (GPIO_SIG43_IN_SEL_V << GPIO_SIG43_IN_SEL_S) #define GPIO_SIG43_IN_SEL_V 0x00000001U -#define GPIO_SIG43_IN_SEL_S 7 +#define GPIO_SIG43_IN_SEL_S 8 /** GPIO_FUNC46_IN_SEL_CFG_REG register - * Configuration register for input signal 46 + * GPIO input function configuration register */ -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37c) -/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 46.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38c) +/** GPIO_FUNC46_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC46_IN_SEL 0x0000003FU +#define GPIO_FUNC46_IN_SEL 0x0000007FU #define GPIO_FUNC46_IN_SEL_M (GPIO_FUNC46_IN_SEL_V << GPIO_FUNC46_IN_SEL_S) -#define GPIO_FUNC46_IN_SEL_V 0x0000003FU +#define GPIO_FUNC46_IN_SEL_V 0x0000007FU #define GPIO_FUNC46_IN_SEL_S 0 -/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC46_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL (BIT(7)) #define GPIO_FUNC46_IN_INV_SEL_M (GPIO_FUNC46_IN_INV_SEL_V << GPIO_FUNC46_IN_INV_SEL_S) #define GPIO_FUNC46_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC46_IN_INV_SEL_S 6 -/** GPIO_SIG46_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC46_IN_INV_SEL_S 7 +/** GPIO_SIG46_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL (BIT(8)) #define GPIO_SIG46_IN_SEL_M (GPIO_SIG46_IN_SEL_V << GPIO_SIG46_IN_SEL_S) #define GPIO_SIG46_IN_SEL_V 0x00000001U -#define GPIO_SIG46_IN_SEL_S 7 +#define GPIO_SIG46_IN_SEL_S 8 /** GPIO_FUNC47_IN_SEL_CFG_REG register - * Configuration register for input signal 47 + * GPIO input function configuration register */ -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) -/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 47.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) +/** GPIO_FUNC47_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC47_IN_SEL 0x0000003FU +#define GPIO_FUNC47_IN_SEL 0x0000007FU #define GPIO_FUNC47_IN_SEL_M (GPIO_FUNC47_IN_SEL_V << GPIO_FUNC47_IN_SEL_S) -#define GPIO_FUNC47_IN_SEL_V 0x0000003FU +#define GPIO_FUNC47_IN_SEL_V 0x0000007FU #define GPIO_FUNC47_IN_SEL_S 0 -/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC47_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL (BIT(7)) #define GPIO_FUNC47_IN_INV_SEL_M (GPIO_FUNC47_IN_INV_SEL_V << GPIO_FUNC47_IN_INV_SEL_S) #define GPIO_FUNC47_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC47_IN_INV_SEL_S 6 -/** GPIO_SIG47_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC47_IN_INV_SEL_S 7 +/** GPIO_SIG47_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL (BIT(8)) #define GPIO_SIG47_IN_SEL_M (GPIO_SIG47_IN_SEL_V << GPIO_SIG47_IN_SEL_S) #define GPIO_SIG47_IN_SEL_V 0x00000001U -#define GPIO_SIG47_IN_SEL_S 7 +#define GPIO_SIG47_IN_SEL_S 8 /** GPIO_FUNC64_IN_SEL_CFG_REG register - * Configuration register for input signal 64 + * GPIO input function configuration register */ -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c4) -/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 64.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) +/** GPIO_FUNC64_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC64_IN_SEL 0x0000003FU +#define GPIO_FUNC64_IN_SEL 0x0000007FU #define GPIO_FUNC64_IN_SEL_M (GPIO_FUNC64_IN_SEL_V << GPIO_FUNC64_IN_SEL_S) -#define GPIO_FUNC64_IN_SEL_V 0x0000003FU +#define GPIO_FUNC64_IN_SEL_V 0x0000007FU #define GPIO_FUNC64_IN_SEL_S 0 -/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC64_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL (BIT(7)) #define GPIO_FUNC64_IN_INV_SEL_M (GPIO_FUNC64_IN_INV_SEL_V << GPIO_FUNC64_IN_INV_SEL_S) #define GPIO_FUNC64_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC64_IN_INV_SEL_S 6 -/** GPIO_SIG64_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC64_IN_INV_SEL_S 7 +/** GPIO_SIG64_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL (BIT(8)) #define GPIO_SIG64_IN_SEL_M (GPIO_SIG64_IN_SEL_V << GPIO_SIG64_IN_SEL_S) #define GPIO_SIG64_IN_SEL_V 0x00000001U -#define GPIO_SIG64_IN_SEL_S 7 +#define GPIO_SIG64_IN_SEL_S 8 /** GPIO_FUNC65_IN_SEL_CFG_REG register - * Configuration register for input signal 65 + * GPIO input function configuration register */ -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3c8) -/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 65.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) +/** GPIO_FUNC65_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC65_IN_SEL 0x0000003FU +#define GPIO_FUNC65_IN_SEL 0x0000007FU #define GPIO_FUNC65_IN_SEL_M (GPIO_FUNC65_IN_SEL_V << GPIO_FUNC65_IN_SEL_S) -#define GPIO_FUNC65_IN_SEL_V 0x0000003FU +#define GPIO_FUNC65_IN_SEL_V 0x0000007FU #define GPIO_FUNC65_IN_SEL_S 0 -/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC65_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL (BIT(7)) #define GPIO_FUNC65_IN_INV_SEL_M (GPIO_FUNC65_IN_INV_SEL_V << GPIO_FUNC65_IN_INV_SEL_S) #define GPIO_FUNC65_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC65_IN_INV_SEL_S 6 -/** GPIO_SIG65_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC65_IN_INV_SEL_S 7 +/** GPIO_SIG65_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL (BIT(8)) #define GPIO_SIG65_IN_SEL_M (GPIO_SIG65_IN_SEL_V << GPIO_SIG65_IN_SEL_S) #define GPIO_SIG65_IN_SEL_V 0x00000001U -#define GPIO_SIG65_IN_SEL_S 7 +#define GPIO_SIG65_IN_SEL_S 8 /** GPIO_FUNC66_IN_SEL_CFG_REG register - * Configuration register for input signal 66 + * GPIO input function configuration register */ -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3cc) -/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 66.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3dc) +/** GPIO_FUNC66_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC66_IN_SEL 0x0000003FU +#define GPIO_FUNC66_IN_SEL 0x0000007FU #define GPIO_FUNC66_IN_SEL_M (GPIO_FUNC66_IN_SEL_V << GPIO_FUNC66_IN_SEL_S) -#define GPIO_FUNC66_IN_SEL_V 0x0000003FU +#define GPIO_FUNC66_IN_SEL_V 0x0000007FU #define GPIO_FUNC66_IN_SEL_S 0 -/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC66_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL (BIT(7)) #define GPIO_FUNC66_IN_INV_SEL_M (GPIO_FUNC66_IN_INV_SEL_V << GPIO_FUNC66_IN_INV_SEL_S) #define GPIO_FUNC66_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC66_IN_INV_SEL_S 6 -/** GPIO_SIG66_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC66_IN_INV_SEL_S 7 +/** GPIO_SIG66_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL (BIT(8)) #define GPIO_SIG66_IN_SEL_M (GPIO_SIG66_IN_SEL_V << GPIO_SIG66_IN_SEL_S) #define GPIO_SIG66_IN_SEL_V 0x00000001U -#define GPIO_SIG66_IN_SEL_S 7 +#define GPIO_SIG66_IN_SEL_S 8 /** GPIO_FUNC67_IN_SEL_CFG_REG register - * Configuration register for input signal 67 + * GPIO input function configuration register */ -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d0) -/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 67.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e0) +/** GPIO_FUNC67_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC67_IN_SEL 0x0000003FU +#define GPIO_FUNC67_IN_SEL 0x0000007FU #define GPIO_FUNC67_IN_SEL_M (GPIO_FUNC67_IN_SEL_V << GPIO_FUNC67_IN_SEL_S) -#define GPIO_FUNC67_IN_SEL_V 0x0000003FU +#define GPIO_FUNC67_IN_SEL_V 0x0000007FU #define GPIO_FUNC67_IN_SEL_S 0 -/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC67_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL (BIT(7)) #define GPIO_FUNC67_IN_INV_SEL_M (GPIO_FUNC67_IN_INV_SEL_V << GPIO_FUNC67_IN_INV_SEL_S) #define GPIO_FUNC67_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC67_IN_INV_SEL_S 6 -/** GPIO_SIG67_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC67_IN_INV_SEL_S 7 +/** GPIO_SIG67_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL (BIT(8)) #define GPIO_SIG67_IN_SEL_M (GPIO_SIG67_IN_SEL_V << GPIO_SIG67_IN_SEL_S) #define GPIO_SIG67_IN_SEL_V 0x00000001U -#define GPIO_SIG67_IN_SEL_S 7 +#define GPIO_SIG67_IN_SEL_S 8 /** GPIO_FUNC68_IN_SEL_CFG_REG register - * Configuration register for input signal 68 + * GPIO input function configuration register */ -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d4) -/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 68.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) +/** GPIO_FUNC68_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC68_IN_SEL 0x0000003FU +#define GPIO_FUNC68_IN_SEL 0x0000007FU #define GPIO_FUNC68_IN_SEL_M (GPIO_FUNC68_IN_SEL_V << GPIO_FUNC68_IN_SEL_S) -#define GPIO_FUNC68_IN_SEL_V 0x0000003FU +#define GPIO_FUNC68_IN_SEL_V 0x0000007FU #define GPIO_FUNC68_IN_SEL_S 0 -/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC68_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL (BIT(7)) #define GPIO_FUNC68_IN_INV_SEL_M (GPIO_FUNC68_IN_INV_SEL_V << GPIO_FUNC68_IN_INV_SEL_S) #define GPIO_FUNC68_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC68_IN_INV_SEL_S 6 -/** GPIO_SIG68_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC68_IN_INV_SEL_S 7 +/** GPIO_SIG68_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL (BIT(8)) #define GPIO_SIG68_IN_SEL_M (GPIO_SIG68_IN_SEL_V << GPIO_SIG68_IN_SEL_S) #define GPIO_SIG68_IN_SEL_V 0x00000001U -#define GPIO_SIG68_IN_SEL_S 7 +#define GPIO_SIG68_IN_SEL_S 8 /** GPIO_FUNC69_IN_SEL_CFG_REG register - * Configuration register for input signal 69 + * GPIO input function configuration register */ -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3d8) -/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 69.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) +/** GPIO_FUNC69_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC69_IN_SEL 0x0000003FU +#define GPIO_FUNC69_IN_SEL 0x0000007FU #define GPIO_FUNC69_IN_SEL_M (GPIO_FUNC69_IN_SEL_V << GPIO_FUNC69_IN_SEL_S) -#define GPIO_FUNC69_IN_SEL_V 0x0000003FU +#define GPIO_FUNC69_IN_SEL_V 0x0000007FU #define GPIO_FUNC69_IN_SEL_S 0 -/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC69_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL (BIT(7)) #define GPIO_FUNC69_IN_INV_SEL_M (GPIO_FUNC69_IN_INV_SEL_V << GPIO_FUNC69_IN_INV_SEL_S) #define GPIO_FUNC69_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC69_IN_INV_SEL_S 6 -/** GPIO_SIG69_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC69_IN_INV_SEL_S 7 +/** GPIO_SIG69_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL (BIT(8)) #define GPIO_SIG69_IN_SEL_M (GPIO_SIG69_IN_SEL_V << GPIO_SIG69_IN_SEL_S) #define GPIO_SIG69_IN_SEL_V 0x00000001U -#define GPIO_SIG69_IN_SEL_S 7 +#define GPIO_SIG69_IN_SEL_S 8 /** GPIO_FUNC72_IN_SEL_CFG_REG register - * Configuration register for input signal 72 + * GPIO input function configuration register */ -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e4) -/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 72.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f4) +/** GPIO_FUNC72_IN_SEL : R/W; bitpos: [6:0]; default: 64; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC72_IN_SEL 0x0000003FU +#define GPIO_FUNC72_IN_SEL 0x0000007FU #define GPIO_FUNC72_IN_SEL_M (GPIO_FUNC72_IN_SEL_V << GPIO_FUNC72_IN_SEL_S) -#define GPIO_FUNC72_IN_SEL_V 0x0000003FU +#define GPIO_FUNC72_IN_SEL_V 0x0000007FU #define GPIO_FUNC72_IN_SEL_S 0 -/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC72_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL (BIT(7)) #define GPIO_FUNC72_IN_INV_SEL_M (GPIO_FUNC72_IN_INV_SEL_V << GPIO_FUNC72_IN_INV_SEL_S) #define GPIO_FUNC72_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC72_IN_INV_SEL_S 6 -/** GPIO_SIG72_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC72_IN_INV_SEL_S 7 +/** GPIO_SIG72_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL (BIT(8)) #define GPIO_SIG72_IN_SEL_M (GPIO_SIG72_IN_SEL_V << GPIO_SIG72_IN_SEL_S) #define GPIO_SIG72_IN_SEL_V 0x00000001U -#define GPIO_SIG72_IN_SEL_S 7 +#define GPIO_SIG72_IN_SEL_S 8 /** GPIO_FUNC73_IN_SEL_CFG_REG register - * Configuration register for input signal 73 + * GPIO input function configuration register */ -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3e8) -/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 73.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3f8) +/** GPIO_FUNC73_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC73_IN_SEL 0x0000003FU +#define GPIO_FUNC73_IN_SEL 0x0000007FU #define GPIO_FUNC73_IN_SEL_M (GPIO_FUNC73_IN_SEL_V << GPIO_FUNC73_IN_SEL_S) -#define GPIO_FUNC73_IN_SEL_V 0x0000003FU +#define GPIO_FUNC73_IN_SEL_V 0x0000007FU #define GPIO_FUNC73_IN_SEL_S 0 -/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC73_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL (BIT(7)) #define GPIO_FUNC73_IN_INV_SEL_M (GPIO_FUNC73_IN_INV_SEL_V << GPIO_FUNC73_IN_INV_SEL_S) #define GPIO_FUNC73_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC73_IN_INV_SEL_S 6 -/** GPIO_SIG73_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC73_IN_INV_SEL_S 7 +/** GPIO_SIG73_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL (BIT(8)) #define GPIO_SIG73_IN_SEL_M (GPIO_SIG73_IN_SEL_V << GPIO_SIG73_IN_SEL_S) #define GPIO_SIG73_IN_SEL_V 0x00000001U -#define GPIO_SIG73_IN_SEL_S 7 +#define GPIO_SIG73_IN_SEL_S 8 /** GPIO_FUNC74_IN_SEL_CFG_REG register - * Configuration register for input signal 74 + * GPIO input function configuration register */ -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3ec) -/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [5:0]; default: 32; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 74.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3fc) +/** GPIO_FUNC74_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC74_IN_SEL 0x0000003FU +#define GPIO_FUNC74_IN_SEL 0x0000007FU #define GPIO_FUNC74_IN_SEL_M (GPIO_FUNC74_IN_SEL_V << GPIO_FUNC74_IN_SEL_S) -#define GPIO_FUNC74_IN_SEL_V 0x0000003FU +#define GPIO_FUNC74_IN_SEL_V 0x0000007FU #define GPIO_FUNC74_IN_SEL_S 0 -/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC74_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL (BIT(7)) #define GPIO_FUNC74_IN_INV_SEL_M (GPIO_FUNC74_IN_INV_SEL_V << GPIO_FUNC74_IN_INV_SEL_S) #define GPIO_FUNC74_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC74_IN_INV_SEL_S 6 -/** GPIO_SIG74_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC74_IN_INV_SEL_S 7 +/** GPIO_SIG74_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL (BIT(8)) #define GPIO_SIG74_IN_SEL_M (GPIO_SIG74_IN_SEL_V << GPIO_SIG74_IN_SEL_S) #define GPIO_SIG74_IN_SEL_V 0x00000001U -#define GPIO_SIG74_IN_SEL_S 7 +#define GPIO_SIG74_IN_SEL_S 8 /** GPIO_FUNC82_IN_SEL_CFG_REG register - * Configuration register for input signal 82 + * GPIO input function configuration register */ -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40c) -/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 82.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41c) +/** GPIO_FUNC82_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC82_IN_SEL 0x0000003FU +#define GPIO_FUNC82_IN_SEL 0x0000007FU #define GPIO_FUNC82_IN_SEL_M (GPIO_FUNC82_IN_SEL_V << GPIO_FUNC82_IN_SEL_S) -#define GPIO_FUNC82_IN_SEL_V 0x0000003FU +#define GPIO_FUNC82_IN_SEL_V 0x0000007FU #define GPIO_FUNC82_IN_SEL_S 0 -/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC82_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL (BIT(7)) #define GPIO_FUNC82_IN_INV_SEL_M (GPIO_FUNC82_IN_INV_SEL_V << GPIO_FUNC82_IN_INV_SEL_S) #define GPIO_FUNC82_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC82_IN_INV_SEL_S 6 -/** GPIO_SIG82_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC82_IN_INV_SEL_S 7 +/** GPIO_SIG82_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL (BIT(8)) #define GPIO_SIG82_IN_SEL_M (GPIO_SIG82_IN_SEL_V << GPIO_SIG82_IN_SEL_S) #define GPIO_SIG82_IN_SEL_V 0x00000001U -#define GPIO_SIG82_IN_SEL_S 7 +#define GPIO_SIG82_IN_SEL_S 8 /** GPIO_FUNC83_IN_SEL_CFG_REG register - * Configuration register for input signal 83 + * GPIO input function configuration register */ -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) -/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 83.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) +/** GPIO_FUNC83_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC83_IN_SEL 0x0000003FU +#define GPIO_FUNC83_IN_SEL 0x0000007FU #define GPIO_FUNC83_IN_SEL_M (GPIO_FUNC83_IN_SEL_V << GPIO_FUNC83_IN_SEL_S) -#define GPIO_FUNC83_IN_SEL_V 0x0000003FU +#define GPIO_FUNC83_IN_SEL_V 0x0000007FU #define GPIO_FUNC83_IN_SEL_S 0 -/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC83_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL (BIT(7)) #define GPIO_FUNC83_IN_INV_SEL_M (GPIO_FUNC83_IN_INV_SEL_V << GPIO_FUNC83_IN_INV_SEL_S) #define GPIO_FUNC83_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC83_IN_INV_SEL_S 6 -/** GPIO_SIG83_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC83_IN_INV_SEL_S 7 +/** GPIO_SIG83_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL (BIT(8)) #define GPIO_SIG83_IN_SEL_M (GPIO_SIG83_IN_SEL_V << GPIO_SIG83_IN_SEL_S) #define GPIO_SIG83_IN_SEL_V 0x00000001U -#define GPIO_SIG83_IN_SEL_S 7 +#define GPIO_SIG83_IN_SEL_S 8 /** GPIO_FUNC97_IN_SEL_CFG_REG register - * Configuration register for input signal 97 + * GPIO input function configuration register */ -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) -/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 97.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) +/** GPIO_FUNC97_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC97_IN_SEL 0x0000003FU +#define GPIO_FUNC97_IN_SEL 0x0000007FU #define GPIO_FUNC97_IN_SEL_M (GPIO_FUNC97_IN_SEL_V << GPIO_FUNC97_IN_SEL_S) -#define GPIO_FUNC97_IN_SEL_V 0x0000003FU +#define GPIO_FUNC97_IN_SEL_V 0x0000007FU #define GPIO_FUNC97_IN_SEL_S 0 -/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC97_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL (BIT(7)) #define GPIO_FUNC97_IN_INV_SEL_M (GPIO_FUNC97_IN_INV_SEL_V << GPIO_FUNC97_IN_INV_SEL_S) #define GPIO_FUNC97_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC97_IN_INV_SEL_S 6 -/** GPIO_SIG97_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC97_IN_INV_SEL_S 7 +/** GPIO_SIG97_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL (BIT(8)) #define GPIO_SIG97_IN_SEL_M (GPIO_SIG97_IN_SEL_V << GPIO_SIG97_IN_SEL_S) #define GPIO_SIG97_IN_SEL_V 0x00000001U -#define GPIO_SIG97_IN_SEL_S 7 +#define GPIO_SIG97_IN_SEL_S 8 /** GPIO_FUNC98_IN_SEL_CFG_REG register - * Configuration register for input signal 98 + * GPIO input function configuration register */ -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44c) -/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 98.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45c) +/** GPIO_FUNC98_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC98_IN_SEL 0x0000003FU +#define GPIO_FUNC98_IN_SEL 0x0000007FU #define GPIO_FUNC98_IN_SEL_M (GPIO_FUNC98_IN_SEL_V << GPIO_FUNC98_IN_SEL_S) -#define GPIO_FUNC98_IN_SEL_V 0x0000003FU +#define GPIO_FUNC98_IN_SEL_V 0x0000007FU #define GPIO_FUNC98_IN_SEL_S 0 -/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC98_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL (BIT(7)) #define GPIO_FUNC98_IN_INV_SEL_M (GPIO_FUNC98_IN_INV_SEL_V << GPIO_FUNC98_IN_INV_SEL_S) #define GPIO_FUNC98_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC98_IN_INV_SEL_S 6 -/** GPIO_SIG98_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC98_IN_INV_SEL_S 7 +/** GPIO_SIG98_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL (BIT(8)) #define GPIO_SIG98_IN_SEL_M (GPIO_SIG98_IN_SEL_V << GPIO_SIG98_IN_SEL_S) #define GPIO_SIG98_IN_SEL_V 0x00000001U -#define GPIO_SIG98_IN_SEL_S 7 +#define GPIO_SIG98_IN_SEL_S 8 /** GPIO_FUNC99_IN_SEL_CFG_REG register - * Configuration register for input signal 99 + * GPIO input function configuration register */ -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) -/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 99.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) +/** GPIO_FUNC99_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC99_IN_SEL 0x0000003FU +#define GPIO_FUNC99_IN_SEL 0x0000007FU #define GPIO_FUNC99_IN_SEL_M (GPIO_FUNC99_IN_SEL_V << GPIO_FUNC99_IN_SEL_S) -#define GPIO_FUNC99_IN_SEL_V 0x0000003FU +#define GPIO_FUNC99_IN_SEL_V 0x0000007FU #define GPIO_FUNC99_IN_SEL_S 0 -/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC99_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL (BIT(7)) #define GPIO_FUNC99_IN_INV_SEL_M (GPIO_FUNC99_IN_INV_SEL_V << GPIO_FUNC99_IN_INV_SEL_S) #define GPIO_FUNC99_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC99_IN_INV_SEL_S 6 -/** GPIO_SIG99_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC99_IN_INV_SEL_S 7 +/** GPIO_SIG99_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL (BIT(8)) #define GPIO_SIG99_IN_SEL_M (GPIO_SIG99_IN_SEL_V << GPIO_SIG99_IN_SEL_S) #define GPIO_SIG99_IN_SEL_V 0x00000001U -#define GPIO_SIG99_IN_SEL_S 7 +#define GPIO_SIG99_IN_SEL_S 8 /** GPIO_FUNC100_IN_SEL_CFG_REG register - * Configuration register for input signal 100 + * GPIO input function configuration register */ -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) -/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 100.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) +/** GPIO_FUNC100_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC100_IN_SEL 0x0000003FU +#define GPIO_FUNC100_IN_SEL 0x0000007FU #define GPIO_FUNC100_IN_SEL_M (GPIO_FUNC100_IN_SEL_V << GPIO_FUNC100_IN_SEL_S) -#define GPIO_FUNC100_IN_SEL_V 0x0000003FU +#define GPIO_FUNC100_IN_SEL_V 0x0000007FU #define GPIO_FUNC100_IN_SEL_S 0 -/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC100_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL (BIT(7)) #define GPIO_FUNC100_IN_INV_SEL_M (GPIO_FUNC100_IN_INV_SEL_V << GPIO_FUNC100_IN_INV_SEL_S) #define GPIO_FUNC100_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC100_IN_INV_SEL_S 6 -/** GPIO_SIG100_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC100_IN_INV_SEL_S 7 +/** GPIO_SIG100_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL (BIT(8)) #define GPIO_SIG100_IN_SEL_M (GPIO_SIG100_IN_SEL_V << GPIO_SIG100_IN_SEL_S) #define GPIO_SIG100_IN_SEL_V 0x00000001U -#define GPIO_SIG100_IN_SEL_S 7 +#define GPIO_SIG100_IN_SEL_S 8 /** GPIO_FUNC118_IN_SEL_CFG_REG register - * Configuration register for input signal 118 + * GPIO input function configuration register */ -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49c) -/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 118.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4ac) +/** GPIO_FUNC118_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC118_IN_SEL 0x0000003FU +#define GPIO_FUNC118_IN_SEL 0x0000007FU #define GPIO_FUNC118_IN_SEL_M (GPIO_FUNC118_IN_SEL_V << GPIO_FUNC118_IN_SEL_S) -#define GPIO_FUNC118_IN_SEL_V 0x0000003FU +#define GPIO_FUNC118_IN_SEL_V 0x0000007FU #define GPIO_FUNC118_IN_SEL_S 0 -/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC118_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL (BIT(7)) #define GPIO_FUNC118_IN_INV_SEL_M (GPIO_FUNC118_IN_INV_SEL_V << GPIO_FUNC118_IN_INV_SEL_S) #define GPIO_FUNC118_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC118_IN_INV_SEL_S 6 -/** GPIO_SIG118_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC118_IN_INV_SEL_S 7 +/** GPIO_SIG118_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL (BIT(8)) #define GPIO_SIG118_IN_SEL_M (GPIO_SIG118_IN_SEL_V << GPIO_SIG118_IN_SEL_S) #define GPIO_SIG118_IN_SEL_V 0x00000001U -#define GPIO_SIG118_IN_SEL_S 7 +#define GPIO_SIG118_IN_SEL_S 8 /** GPIO_FUNC119_IN_SEL_CFG_REG register - * Configuration register for input signal 119 + * GPIO input function configuration register */ -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a0) -/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 119.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b0) +/** GPIO_FUNC119_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC119_IN_SEL 0x0000003FU +#define GPIO_FUNC119_IN_SEL 0x0000007FU #define GPIO_FUNC119_IN_SEL_M (GPIO_FUNC119_IN_SEL_V << GPIO_FUNC119_IN_SEL_S) -#define GPIO_FUNC119_IN_SEL_V 0x0000003FU +#define GPIO_FUNC119_IN_SEL_V 0x0000007FU #define GPIO_FUNC119_IN_SEL_S 0 -/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC119_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL (BIT(7)) #define GPIO_FUNC119_IN_INV_SEL_M (GPIO_FUNC119_IN_INV_SEL_V << GPIO_FUNC119_IN_INV_SEL_S) #define GPIO_FUNC119_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC119_IN_INV_SEL_S 6 -/** GPIO_SIG119_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC119_IN_INV_SEL_S 7 +/** GPIO_SIG119_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL (BIT(8)) #define GPIO_SIG119_IN_SEL_M (GPIO_SIG119_IN_SEL_V << GPIO_SIG119_IN_SEL_S) #define GPIO_SIG119_IN_SEL_V 0x00000001U -#define GPIO_SIG119_IN_SEL_S 7 +#define GPIO_SIG119_IN_SEL_S 8 /** GPIO_FUNC120_IN_SEL_CFG_REG register - * Configuration register for input signal 120 + * GPIO input function configuration register */ -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a4) -/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 120.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b4) +/** GPIO_FUNC120_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC120_IN_SEL 0x0000003FU +#define GPIO_FUNC120_IN_SEL 0x0000007FU #define GPIO_FUNC120_IN_SEL_M (GPIO_FUNC120_IN_SEL_V << GPIO_FUNC120_IN_SEL_S) -#define GPIO_FUNC120_IN_SEL_V 0x0000003FU +#define GPIO_FUNC120_IN_SEL_V 0x0000007FU #define GPIO_FUNC120_IN_SEL_S 0 -/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC120_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL (BIT(7)) #define GPIO_FUNC120_IN_INV_SEL_M (GPIO_FUNC120_IN_INV_SEL_V << GPIO_FUNC120_IN_INV_SEL_S) #define GPIO_FUNC120_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC120_IN_INV_SEL_S 6 -/** GPIO_SIG120_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC120_IN_INV_SEL_S 7 +/** GPIO_SIG120_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL (BIT(8)) #define GPIO_SIG120_IN_SEL_M (GPIO_SIG120_IN_SEL_V << GPIO_SIG120_IN_SEL_S) #define GPIO_SIG120_IN_SEL_V 0x00000001U -#define GPIO_SIG120_IN_SEL_S 7 +#define GPIO_SIG120_IN_SEL_S 8 /** GPIO_FUNC121_IN_SEL_CFG_REG register - * Configuration register for input signal 121 + * GPIO input function configuration register */ -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4a8) -/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 121.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4b8) +/** GPIO_FUNC121_IN_SEL : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ -#define GPIO_FUNC121_IN_SEL 0x0000003FU +#define GPIO_FUNC121_IN_SEL 0x0000007FU #define GPIO_FUNC121_IN_SEL_M (GPIO_FUNC121_IN_SEL_V << GPIO_FUNC121_IN_SEL_S) -#define GPIO_FUNC121_IN_SEL_V 0x0000003FU +#define GPIO_FUNC121_IN_SEL_V 0x0000007FU #define GPIO_FUNC121_IN_SEL_S 0 -/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ +/** GPIO_FUNC121_IN_INV_SEL : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ -#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL (BIT(7)) #define GPIO_FUNC121_IN_INV_SEL_M (GPIO_FUNC121_IN_INV_SEL_V << GPIO_FUNC121_IN_INV_SEL_S) #define GPIO_FUNC121_IN_INV_SEL_V 0x00000001U -#define GPIO_FUNC121_IN_INV_SEL_S 6 -/** GPIO_SIG121_IN_SEL : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ +#define GPIO_FUNC121_IN_INV_SEL_S 7 +/** GPIO_SIG121_IN_SEL : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ -#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL (BIT(8)) #define GPIO_SIG121_IN_SEL_M (GPIO_SIG121_IN_SEL_V << GPIO_SIG121_IN_SEL_S) #define GPIO_SIG121_IN_SEL_V 0x00000001U -#define GPIO_SIG121_IN_SEL_S 7 +#define GPIO_SIG121_IN_SEL_S 8 /** GPIO_FUNC0_OUT_SEL_CFG_REG register - * Configuration register for GPIO0 output + * GPIO output function select register */ -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac4) +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) /** GPIO_FUNC0_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO0.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 0 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC0_OUT_SEL 0x000001FFU #define GPIO_FUNC0_OUT_SEL_M (GPIO_FUNC0_OUT_SEL_V << GPIO_FUNC0_OUT_SEL_S) #define GPIO_FUNC0_OUT_SEL_V 0x000001FFU #define GPIO_FUNC0_OUT_SEL_S 0 /** GPIO_FUNC0_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC0_OUT_INV_SEL_M (GPIO_FUNC0_OUT_INV_SEL_V << GPIO_FUNC0_OUT_INV_SEL_S) #define GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC0_OUT_INV_SEL_S 9 /** GPIO_FUNC0_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 0 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC0_OE_SEL (BIT(10)) #define GPIO_FUNC0_OE_SEL_M (GPIO_FUNC0_OE_SEL_V << GPIO_FUNC0_OE_SEL_S) #define GPIO_FUNC0_OE_SEL_V 0x00000001U #define GPIO_FUNC0_OE_SEL_S 10 /** GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC0_OE_INV_SEL (BIT(11)) #define GPIO_FUNC0_OE_INV_SEL_M (GPIO_FUNC0_OE_INV_SEL_V << GPIO_FUNC0_OE_INV_SEL_S) @@ -3910,51 +3348,35 @@ extern "C" { #define GPIO_FUNC0_OE_INV_SEL_S 11 /** GPIO_FUNC1_OUT_SEL_CFG_REG register - * Configuration register for GPIO1 output + * GPIO output function select register */ -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xac8) +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) /** GPIO_FUNC1_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO1.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 1 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC1_OUT_SEL 0x000001FFU #define GPIO_FUNC1_OUT_SEL_M (GPIO_FUNC1_OUT_SEL_V << GPIO_FUNC1_OUT_SEL_S) #define GPIO_FUNC1_OUT_SEL_V 0x000001FFU #define GPIO_FUNC1_OUT_SEL_S 0 /** GPIO_FUNC1_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC1_OUT_INV_SEL_M (GPIO_FUNC1_OUT_INV_SEL_V << GPIO_FUNC1_OUT_INV_SEL_S) #define GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC1_OUT_INV_SEL_S 9 /** GPIO_FUNC1_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 1 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC1_OE_SEL (BIT(10)) #define GPIO_FUNC1_OE_SEL_M (GPIO_FUNC1_OE_SEL_V << GPIO_FUNC1_OE_SEL_S) #define GPIO_FUNC1_OE_SEL_V 0x00000001U #define GPIO_FUNC1_OE_SEL_S 10 /** GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC1_OE_INV_SEL (BIT(11)) #define GPIO_FUNC1_OE_INV_SEL_M (GPIO_FUNC1_OE_INV_SEL_V << GPIO_FUNC1_OE_INV_SEL_S) @@ -3962,51 +3384,35 @@ extern "C" { #define GPIO_FUNC1_OE_INV_SEL_S 11 /** GPIO_FUNC2_OUT_SEL_CFG_REG register - * Configuration register for GPIO2 output + * GPIO output function select register */ -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xacc) +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) /** GPIO_FUNC2_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO2.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 2 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC2_OUT_SEL 0x000001FFU #define GPIO_FUNC2_OUT_SEL_M (GPIO_FUNC2_OUT_SEL_V << GPIO_FUNC2_OUT_SEL_S) #define GPIO_FUNC2_OUT_SEL_V 0x000001FFU #define GPIO_FUNC2_OUT_SEL_S 0 /** GPIO_FUNC2_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC2_OUT_INV_SEL_M (GPIO_FUNC2_OUT_INV_SEL_V << GPIO_FUNC2_OUT_INV_SEL_S) #define GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC2_OUT_INV_SEL_S 9 /** GPIO_FUNC2_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 2 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC2_OE_SEL (BIT(10)) #define GPIO_FUNC2_OE_SEL_M (GPIO_FUNC2_OE_SEL_V << GPIO_FUNC2_OE_SEL_S) #define GPIO_FUNC2_OE_SEL_V 0x00000001U #define GPIO_FUNC2_OE_SEL_S 10 /** GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC2_OE_INV_SEL (BIT(11)) #define GPIO_FUNC2_OE_INV_SEL_M (GPIO_FUNC2_OE_INV_SEL_V << GPIO_FUNC2_OE_INV_SEL_S) @@ -4014,51 +3420,35 @@ extern "C" { #define GPIO_FUNC2_OE_INV_SEL_S 11 /** GPIO_FUNC3_OUT_SEL_CFG_REG register - * Configuration register for GPIO3 output + * GPIO output function select register */ -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad0) +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) /** GPIO_FUNC3_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO3.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 3 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC3_OUT_SEL 0x000001FFU #define GPIO_FUNC3_OUT_SEL_M (GPIO_FUNC3_OUT_SEL_V << GPIO_FUNC3_OUT_SEL_S) #define GPIO_FUNC3_OUT_SEL_V 0x000001FFU #define GPIO_FUNC3_OUT_SEL_S 0 /** GPIO_FUNC3_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC3_OUT_INV_SEL_M (GPIO_FUNC3_OUT_INV_SEL_V << GPIO_FUNC3_OUT_INV_SEL_S) #define GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC3_OUT_INV_SEL_S 9 /** GPIO_FUNC3_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 3 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC3_OE_SEL (BIT(10)) #define GPIO_FUNC3_OE_SEL_M (GPIO_FUNC3_OE_SEL_V << GPIO_FUNC3_OE_SEL_S) #define GPIO_FUNC3_OE_SEL_V 0x00000001U #define GPIO_FUNC3_OE_SEL_S 10 /** GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC3_OE_INV_SEL (BIT(11)) #define GPIO_FUNC3_OE_INV_SEL_M (GPIO_FUNC3_OE_INV_SEL_V << GPIO_FUNC3_OE_INV_SEL_S) @@ -4066,51 +3456,35 @@ extern "C" { #define GPIO_FUNC3_OE_INV_SEL_S 11 /** GPIO_FUNC4_OUT_SEL_CFG_REG register - * Configuration register for GPIO4 output + * GPIO output function select register */ -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad4) +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) /** GPIO_FUNC4_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO4.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 4 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC4_OUT_SEL 0x000001FFU #define GPIO_FUNC4_OUT_SEL_M (GPIO_FUNC4_OUT_SEL_V << GPIO_FUNC4_OUT_SEL_S) #define GPIO_FUNC4_OUT_SEL_V 0x000001FFU #define GPIO_FUNC4_OUT_SEL_S 0 /** GPIO_FUNC4_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC4_OUT_INV_SEL_M (GPIO_FUNC4_OUT_INV_SEL_V << GPIO_FUNC4_OUT_INV_SEL_S) #define GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC4_OUT_INV_SEL_S 9 /** GPIO_FUNC4_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 4 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC4_OE_SEL (BIT(10)) #define GPIO_FUNC4_OE_SEL_M (GPIO_FUNC4_OE_SEL_V << GPIO_FUNC4_OE_SEL_S) #define GPIO_FUNC4_OE_SEL_V 0x00000001U #define GPIO_FUNC4_OE_SEL_S 10 /** GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC4_OE_INV_SEL (BIT(11)) #define GPIO_FUNC4_OE_INV_SEL_M (GPIO_FUNC4_OE_INV_SEL_V << GPIO_FUNC4_OE_INV_SEL_S) @@ -4118,51 +3492,35 @@ extern "C" { #define GPIO_FUNC4_OE_INV_SEL_S 11 /** GPIO_FUNC5_OUT_SEL_CFG_REG register - * Configuration register for GPIO5 output + * GPIO output function select register */ -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xad8) +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) /** GPIO_FUNC5_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO5.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 5 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC5_OUT_SEL 0x000001FFU #define GPIO_FUNC5_OUT_SEL_M (GPIO_FUNC5_OUT_SEL_V << GPIO_FUNC5_OUT_SEL_S) #define GPIO_FUNC5_OUT_SEL_V 0x000001FFU #define GPIO_FUNC5_OUT_SEL_S 0 /** GPIO_FUNC5_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC5_OUT_INV_SEL_M (GPIO_FUNC5_OUT_INV_SEL_V << GPIO_FUNC5_OUT_INV_SEL_S) #define GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC5_OUT_INV_SEL_S 9 /** GPIO_FUNC5_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 5 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC5_OE_SEL (BIT(10)) #define GPIO_FUNC5_OE_SEL_M (GPIO_FUNC5_OE_SEL_V << GPIO_FUNC5_OE_SEL_S) #define GPIO_FUNC5_OE_SEL_V 0x00000001U #define GPIO_FUNC5_OE_SEL_S 10 /** GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC5_OE_INV_SEL (BIT(11)) #define GPIO_FUNC5_OE_INV_SEL_M (GPIO_FUNC5_OE_INV_SEL_V << GPIO_FUNC5_OE_INV_SEL_S) @@ -4170,51 +3528,35 @@ extern "C" { #define GPIO_FUNC5_OE_INV_SEL_S 11 /** GPIO_FUNC6_OUT_SEL_CFG_REG register - * Configuration register for GPIO6 output + * GPIO output function select register */ -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xadc) +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) /** GPIO_FUNC6_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO6.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 6 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC6_OUT_SEL 0x000001FFU #define GPIO_FUNC6_OUT_SEL_M (GPIO_FUNC6_OUT_SEL_V << GPIO_FUNC6_OUT_SEL_S) #define GPIO_FUNC6_OUT_SEL_V 0x000001FFU #define GPIO_FUNC6_OUT_SEL_S 0 /** GPIO_FUNC6_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC6_OUT_INV_SEL_M (GPIO_FUNC6_OUT_INV_SEL_V << GPIO_FUNC6_OUT_INV_SEL_S) #define GPIO_FUNC6_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC6_OUT_INV_SEL_S 9 /** GPIO_FUNC6_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 6 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC6_OE_SEL (BIT(10)) #define GPIO_FUNC6_OE_SEL_M (GPIO_FUNC6_OE_SEL_V << GPIO_FUNC6_OE_SEL_S) #define GPIO_FUNC6_OE_SEL_V 0x00000001U #define GPIO_FUNC6_OE_SEL_S 10 /** GPIO_FUNC6_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC6_OE_INV_SEL (BIT(11)) #define GPIO_FUNC6_OE_INV_SEL_M (GPIO_FUNC6_OE_INV_SEL_V << GPIO_FUNC6_OE_INV_SEL_S) @@ -4222,51 +3564,35 @@ extern "C" { #define GPIO_FUNC6_OE_INV_SEL_S 11 /** GPIO_FUNC7_OUT_SEL_CFG_REG register - * Configuration register for GPIO7 output + * GPIO output function select register */ -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae0) +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) /** GPIO_FUNC7_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO7.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 7 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC7_OUT_SEL 0x000001FFU #define GPIO_FUNC7_OUT_SEL_M (GPIO_FUNC7_OUT_SEL_V << GPIO_FUNC7_OUT_SEL_S) #define GPIO_FUNC7_OUT_SEL_V 0x000001FFU #define GPIO_FUNC7_OUT_SEL_S 0 /** GPIO_FUNC7_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC7_OUT_INV_SEL_M (GPIO_FUNC7_OUT_INV_SEL_V << GPIO_FUNC7_OUT_INV_SEL_S) #define GPIO_FUNC7_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC7_OUT_INV_SEL_S 9 /** GPIO_FUNC7_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 7 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC7_OE_SEL (BIT(10)) #define GPIO_FUNC7_OE_SEL_M (GPIO_FUNC7_OE_SEL_V << GPIO_FUNC7_OE_SEL_S) #define GPIO_FUNC7_OE_SEL_V 0x00000001U #define GPIO_FUNC7_OE_SEL_S 10 /** GPIO_FUNC7_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC7_OE_INV_SEL (BIT(11)) #define GPIO_FUNC7_OE_INV_SEL_M (GPIO_FUNC7_OE_INV_SEL_V << GPIO_FUNC7_OE_INV_SEL_S) @@ -4274,51 +3600,35 @@ extern "C" { #define GPIO_FUNC7_OE_INV_SEL_S 11 /** GPIO_FUNC8_OUT_SEL_CFG_REG register - * Configuration register for GPIO8 output + * GPIO output function select register */ -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae4) +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) /** GPIO_FUNC8_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO8.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 8 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC8_OUT_SEL 0x000001FFU #define GPIO_FUNC8_OUT_SEL_M (GPIO_FUNC8_OUT_SEL_V << GPIO_FUNC8_OUT_SEL_S) #define GPIO_FUNC8_OUT_SEL_V 0x000001FFU #define GPIO_FUNC8_OUT_SEL_S 0 /** GPIO_FUNC8_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC8_OUT_INV_SEL_M (GPIO_FUNC8_OUT_INV_SEL_V << GPIO_FUNC8_OUT_INV_SEL_S) #define GPIO_FUNC8_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC8_OUT_INV_SEL_S 9 /** GPIO_FUNC8_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 8 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC8_OE_SEL (BIT(10)) #define GPIO_FUNC8_OE_SEL_M (GPIO_FUNC8_OE_SEL_V << GPIO_FUNC8_OE_SEL_S) #define GPIO_FUNC8_OE_SEL_V 0x00000001U #define GPIO_FUNC8_OE_SEL_S 10 /** GPIO_FUNC8_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC8_OE_INV_SEL (BIT(11)) #define GPIO_FUNC8_OE_INV_SEL_M (GPIO_FUNC8_OE_INV_SEL_V << GPIO_FUNC8_OE_INV_SEL_S) @@ -4326,51 +3636,35 @@ extern "C" { #define GPIO_FUNC8_OE_INV_SEL_S 11 /** GPIO_FUNC9_OUT_SEL_CFG_REG register - * Configuration register for GPIO9 output + * GPIO output function select register */ -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xae8) +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) /** GPIO_FUNC9_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO9.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 9 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC9_OUT_SEL 0x000001FFU #define GPIO_FUNC9_OUT_SEL_M (GPIO_FUNC9_OUT_SEL_V << GPIO_FUNC9_OUT_SEL_S) #define GPIO_FUNC9_OUT_SEL_V 0x000001FFU #define GPIO_FUNC9_OUT_SEL_S 0 /** GPIO_FUNC9_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC9_OUT_INV_SEL_M (GPIO_FUNC9_OUT_INV_SEL_V << GPIO_FUNC9_OUT_INV_SEL_S) #define GPIO_FUNC9_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC9_OUT_INV_SEL_S 9 /** GPIO_FUNC9_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 9 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC9_OE_SEL (BIT(10)) #define GPIO_FUNC9_OE_SEL_M (GPIO_FUNC9_OE_SEL_V << GPIO_FUNC9_OE_SEL_S) #define GPIO_FUNC9_OE_SEL_V 0x00000001U #define GPIO_FUNC9_OE_SEL_S 10 /** GPIO_FUNC9_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC9_OE_INV_SEL (BIT(11)) #define GPIO_FUNC9_OE_INV_SEL_M (GPIO_FUNC9_OE_INV_SEL_V << GPIO_FUNC9_OE_INV_SEL_S) @@ -4378,51 +3672,35 @@ extern "C" { #define GPIO_FUNC9_OE_INV_SEL_S 11 /** GPIO_FUNC10_OUT_SEL_CFG_REG register - * Configuration register for GPIO10 output + * GPIO output function select register */ -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaec) +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) /** GPIO_FUNC10_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO10.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 10 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC10_OUT_SEL 0x000001FFU #define GPIO_FUNC10_OUT_SEL_M (GPIO_FUNC10_OUT_SEL_V << GPIO_FUNC10_OUT_SEL_S) #define GPIO_FUNC10_OUT_SEL_V 0x000001FFU #define GPIO_FUNC10_OUT_SEL_S 0 /** GPIO_FUNC10_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC10_OUT_INV_SEL_M (GPIO_FUNC10_OUT_INV_SEL_V << GPIO_FUNC10_OUT_INV_SEL_S) #define GPIO_FUNC10_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC10_OUT_INV_SEL_S 9 /** GPIO_FUNC10_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 10 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC10_OE_SEL (BIT(10)) #define GPIO_FUNC10_OE_SEL_M (GPIO_FUNC10_OE_SEL_V << GPIO_FUNC10_OE_SEL_S) #define GPIO_FUNC10_OE_SEL_V 0x00000001U #define GPIO_FUNC10_OE_SEL_S 10 /** GPIO_FUNC10_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC10_OE_INV_SEL (BIT(11)) #define GPIO_FUNC10_OE_INV_SEL_M (GPIO_FUNC10_OE_INV_SEL_V << GPIO_FUNC10_OE_INV_SEL_S) @@ -4430,51 +3708,35 @@ extern "C" { #define GPIO_FUNC10_OE_INV_SEL_S 11 /** GPIO_FUNC11_OUT_SEL_CFG_REG register - * Configuration register for GPIO11 output + * GPIO output function select register */ -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf0) +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) /** GPIO_FUNC11_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO11.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 11 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC11_OUT_SEL 0x000001FFU #define GPIO_FUNC11_OUT_SEL_M (GPIO_FUNC11_OUT_SEL_V << GPIO_FUNC11_OUT_SEL_S) #define GPIO_FUNC11_OUT_SEL_V 0x000001FFU #define GPIO_FUNC11_OUT_SEL_S 0 /** GPIO_FUNC11_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC11_OUT_INV_SEL_M (GPIO_FUNC11_OUT_INV_SEL_V << GPIO_FUNC11_OUT_INV_SEL_S) #define GPIO_FUNC11_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC11_OUT_INV_SEL_S 9 /** GPIO_FUNC11_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 11 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC11_OE_SEL (BIT(10)) #define GPIO_FUNC11_OE_SEL_M (GPIO_FUNC11_OE_SEL_V << GPIO_FUNC11_OE_SEL_S) #define GPIO_FUNC11_OE_SEL_V 0x00000001U #define GPIO_FUNC11_OE_SEL_S 10 /** GPIO_FUNC11_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC11_OE_INV_SEL (BIT(11)) #define GPIO_FUNC11_OE_INV_SEL_M (GPIO_FUNC11_OE_INV_SEL_V << GPIO_FUNC11_OE_INV_SEL_S) @@ -4482,51 +3744,35 @@ extern "C" { #define GPIO_FUNC11_OE_INV_SEL_S 11 /** GPIO_FUNC12_OUT_SEL_CFG_REG register - * Configuration register for GPIO12 output + * GPIO output function select register */ -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf4) +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) /** GPIO_FUNC12_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO12.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 12 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC12_OUT_SEL 0x000001FFU #define GPIO_FUNC12_OUT_SEL_M (GPIO_FUNC12_OUT_SEL_V << GPIO_FUNC12_OUT_SEL_S) #define GPIO_FUNC12_OUT_SEL_V 0x000001FFU #define GPIO_FUNC12_OUT_SEL_S 0 /** GPIO_FUNC12_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC12_OUT_INV_SEL_M (GPIO_FUNC12_OUT_INV_SEL_V << GPIO_FUNC12_OUT_INV_SEL_S) #define GPIO_FUNC12_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC12_OUT_INV_SEL_S 9 /** GPIO_FUNC12_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 12 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC12_OE_SEL (BIT(10)) #define GPIO_FUNC12_OE_SEL_M (GPIO_FUNC12_OE_SEL_V << GPIO_FUNC12_OE_SEL_S) #define GPIO_FUNC12_OE_SEL_V 0x00000001U #define GPIO_FUNC12_OE_SEL_S 10 /** GPIO_FUNC12_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC12_OE_INV_SEL (BIT(11)) #define GPIO_FUNC12_OE_INV_SEL_M (GPIO_FUNC12_OE_INV_SEL_V << GPIO_FUNC12_OE_INV_SEL_S) @@ -4534,51 +3780,35 @@ extern "C" { #define GPIO_FUNC12_OE_INV_SEL_S 11 /** GPIO_FUNC13_OUT_SEL_CFG_REG register - * Configuration register for GPIO13 output + * GPIO output function select register */ -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xaf8) +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) /** GPIO_FUNC13_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO13.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 13 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC13_OUT_SEL 0x000001FFU #define GPIO_FUNC13_OUT_SEL_M (GPIO_FUNC13_OUT_SEL_V << GPIO_FUNC13_OUT_SEL_S) #define GPIO_FUNC13_OUT_SEL_V 0x000001FFU #define GPIO_FUNC13_OUT_SEL_S 0 /** GPIO_FUNC13_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC13_OUT_INV_SEL_M (GPIO_FUNC13_OUT_INV_SEL_V << GPIO_FUNC13_OUT_INV_SEL_S) #define GPIO_FUNC13_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC13_OUT_INV_SEL_S 9 /** GPIO_FUNC13_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 13 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC13_OE_SEL (BIT(10)) #define GPIO_FUNC13_OE_SEL_M (GPIO_FUNC13_OE_SEL_V << GPIO_FUNC13_OE_SEL_S) #define GPIO_FUNC13_OE_SEL_V 0x00000001U #define GPIO_FUNC13_OE_SEL_S 10 /** GPIO_FUNC13_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC13_OE_INV_SEL (BIT(11)) #define GPIO_FUNC13_OE_INV_SEL_M (GPIO_FUNC13_OE_INV_SEL_V << GPIO_FUNC13_OE_INV_SEL_S) @@ -4586,51 +3816,35 @@ extern "C" { #define GPIO_FUNC13_OE_INV_SEL_S 11 /** GPIO_FUNC14_OUT_SEL_CFG_REG register - * Configuration register for GPIO14 output + * GPIO output function select register */ -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xafc) +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) /** GPIO_FUNC14_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO14.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 14 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC14_OUT_SEL 0x000001FFU #define GPIO_FUNC14_OUT_SEL_M (GPIO_FUNC14_OUT_SEL_V << GPIO_FUNC14_OUT_SEL_S) #define GPIO_FUNC14_OUT_SEL_V 0x000001FFU #define GPIO_FUNC14_OUT_SEL_S 0 /** GPIO_FUNC14_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC14_OUT_INV_SEL_M (GPIO_FUNC14_OUT_INV_SEL_V << GPIO_FUNC14_OUT_INV_SEL_S) #define GPIO_FUNC14_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC14_OUT_INV_SEL_S 9 /** GPIO_FUNC14_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 14 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC14_OE_SEL (BIT(10)) #define GPIO_FUNC14_OE_SEL_M (GPIO_FUNC14_OE_SEL_V << GPIO_FUNC14_OE_SEL_S) #define GPIO_FUNC14_OE_SEL_V 0x00000001U #define GPIO_FUNC14_OE_SEL_S 10 /** GPIO_FUNC14_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC14_OE_INV_SEL (BIT(11)) #define GPIO_FUNC14_OE_INV_SEL_M (GPIO_FUNC14_OE_INV_SEL_V << GPIO_FUNC14_OE_INV_SEL_S) @@ -4638,51 +3852,35 @@ extern "C" { #define GPIO_FUNC14_OE_INV_SEL_S 11 /** GPIO_FUNC15_OUT_SEL_CFG_REG register - * Configuration register for GPIO15 output + * GPIO output function select register */ -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb00) +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) /** GPIO_FUNC15_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO15.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 15 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC15_OUT_SEL 0x000001FFU #define GPIO_FUNC15_OUT_SEL_M (GPIO_FUNC15_OUT_SEL_V << GPIO_FUNC15_OUT_SEL_S) #define GPIO_FUNC15_OUT_SEL_V 0x000001FFU #define GPIO_FUNC15_OUT_SEL_S 0 /** GPIO_FUNC15_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC15_OUT_INV_SEL_M (GPIO_FUNC15_OUT_INV_SEL_V << GPIO_FUNC15_OUT_INV_SEL_S) #define GPIO_FUNC15_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC15_OUT_INV_SEL_S 9 /** GPIO_FUNC15_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 15 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC15_OE_SEL (BIT(10)) #define GPIO_FUNC15_OE_SEL_M (GPIO_FUNC15_OE_SEL_V << GPIO_FUNC15_OE_SEL_S) #define GPIO_FUNC15_OE_SEL_V 0x00000001U #define GPIO_FUNC15_OE_SEL_S 10 /** GPIO_FUNC15_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC15_OE_INV_SEL (BIT(11)) #define GPIO_FUNC15_OE_INV_SEL_M (GPIO_FUNC15_OE_INV_SEL_V << GPIO_FUNC15_OE_INV_SEL_S) @@ -4690,51 +3888,35 @@ extern "C" { #define GPIO_FUNC15_OE_INV_SEL_S 11 /** GPIO_FUNC16_OUT_SEL_CFG_REG register - * Configuration register for GPIO16 output + * GPIO output function select register */ -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb04) +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) /** GPIO_FUNC16_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO16.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 16 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC16_OUT_SEL 0x000001FFU #define GPIO_FUNC16_OUT_SEL_M (GPIO_FUNC16_OUT_SEL_V << GPIO_FUNC16_OUT_SEL_S) #define GPIO_FUNC16_OUT_SEL_V 0x000001FFU #define GPIO_FUNC16_OUT_SEL_S 0 /** GPIO_FUNC16_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC16_OUT_INV_SEL_M (GPIO_FUNC16_OUT_INV_SEL_V << GPIO_FUNC16_OUT_INV_SEL_S) #define GPIO_FUNC16_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC16_OUT_INV_SEL_S 9 /** GPIO_FUNC16_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 16 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC16_OE_SEL (BIT(10)) #define GPIO_FUNC16_OE_SEL_M (GPIO_FUNC16_OE_SEL_V << GPIO_FUNC16_OE_SEL_S) #define GPIO_FUNC16_OE_SEL_V 0x00000001U #define GPIO_FUNC16_OE_SEL_S 10 /** GPIO_FUNC16_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC16_OE_INV_SEL (BIT(11)) #define GPIO_FUNC16_OE_INV_SEL_M (GPIO_FUNC16_OE_INV_SEL_V << GPIO_FUNC16_OE_INV_SEL_S) @@ -4742,51 +3924,35 @@ extern "C" { #define GPIO_FUNC16_OE_INV_SEL_S 11 /** GPIO_FUNC17_OUT_SEL_CFG_REG register - * Configuration register for GPIO17 output + * GPIO output function select register */ -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb08) +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) /** GPIO_FUNC17_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO17.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 17 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC17_OUT_SEL 0x000001FFU #define GPIO_FUNC17_OUT_SEL_M (GPIO_FUNC17_OUT_SEL_V << GPIO_FUNC17_OUT_SEL_S) #define GPIO_FUNC17_OUT_SEL_V 0x000001FFU #define GPIO_FUNC17_OUT_SEL_S 0 /** GPIO_FUNC17_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC17_OUT_INV_SEL_M (GPIO_FUNC17_OUT_INV_SEL_V << GPIO_FUNC17_OUT_INV_SEL_S) #define GPIO_FUNC17_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC17_OUT_INV_SEL_S 9 /** GPIO_FUNC17_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 17 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC17_OE_SEL (BIT(10)) #define GPIO_FUNC17_OE_SEL_M (GPIO_FUNC17_OE_SEL_V << GPIO_FUNC17_OE_SEL_S) #define GPIO_FUNC17_OE_SEL_V 0x00000001U #define GPIO_FUNC17_OE_SEL_S 10 /** GPIO_FUNC17_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC17_OE_INV_SEL (BIT(11)) #define GPIO_FUNC17_OE_INV_SEL_M (GPIO_FUNC17_OE_INV_SEL_V << GPIO_FUNC17_OE_INV_SEL_S) @@ -4794,51 +3960,35 @@ extern "C" { #define GPIO_FUNC17_OE_INV_SEL_S 11 /** GPIO_FUNC18_OUT_SEL_CFG_REG register - * Configuration register for GPIO18 output + * GPIO output function select register */ -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb0c) +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) /** GPIO_FUNC18_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO18.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 18 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC18_OUT_SEL 0x000001FFU #define GPIO_FUNC18_OUT_SEL_M (GPIO_FUNC18_OUT_SEL_V << GPIO_FUNC18_OUT_SEL_S) #define GPIO_FUNC18_OUT_SEL_V 0x000001FFU #define GPIO_FUNC18_OUT_SEL_S 0 /** GPIO_FUNC18_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC18_OUT_INV_SEL_M (GPIO_FUNC18_OUT_INV_SEL_V << GPIO_FUNC18_OUT_INV_SEL_S) #define GPIO_FUNC18_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC18_OUT_INV_SEL_S 9 /** GPIO_FUNC18_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 18 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC18_OE_SEL (BIT(10)) #define GPIO_FUNC18_OE_SEL_M (GPIO_FUNC18_OE_SEL_V << GPIO_FUNC18_OE_SEL_S) #define GPIO_FUNC18_OE_SEL_V 0x00000001U #define GPIO_FUNC18_OE_SEL_S 10 /** GPIO_FUNC18_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC18_OE_INV_SEL (BIT(11)) #define GPIO_FUNC18_OE_INV_SEL_M (GPIO_FUNC18_OE_INV_SEL_V << GPIO_FUNC18_OE_INV_SEL_S) @@ -4846,51 +3996,35 @@ extern "C" { #define GPIO_FUNC18_OE_INV_SEL_S 11 /** GPIO_FUNC19_OUT_SEL_CFG_REG register - * Configuration register for GPIO19 output + * GPIO output function select register */ -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb10) +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) /** GPIO_FUNC19_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO19.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 19 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC19_OUT_SEL 0x000001FFU #define GPIO_FUNC19_OUT_SEL_M (GPIO_FUNC19_OUT_SEL_V << GPIO_FUNC19_OUT_SEL_S) #define GPIO_FUNC19_OUT_SEL_V 0x000001FFU #define GPIO_FUNC19_OUT_SEL_S 0 /** GPIO_FUNC19_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC19_OUT_INV_SEL_M (GPIO_FUNC19_OUT_INV_SEL_V << GPIO_FUNC19_OUT_INV_SEL_S) #define GPIO_FUNC19_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC19_OUT_INV_SEL_S 9 /** GPIO_FUNC19_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 19 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC19_OE_SEL (BIT(10)) #define GPIO_FUNC19_OE_SEL_M (GPIO_FUNC19_OE_SEL_V << GPIO_FUNC19_OE_SEL_S) #define GPIO_FUNC19_OE_SEL_V 0x00000001U #define GPIO_FUNC19_OE_SEL_S 10 /** GPIO_FUNC19_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC19_OE_INV_SEL (BIT(11)) #define GPIO_FUNC19_OE_INV_SEL_M (GPIO_FUNC19_OE_INV_SEL_V << GPIO_FUNC19_OE_INV_SEL_S) @@ -4898,51 +4032,35 @@ extern "C" { #define GPIO_FUNC19_OE_INV_SEL_S 11 /** GPIO_FUNC20_OUT_SEL_CFG_REG register - * Configuration register for GPIO20 output + * GPIO output function select register */ -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb14) +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) /** GPIO_FUNC20_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO20.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 20 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC20_OUT_SEL 0x000001FFU #define GPIO_FUNC20_OUT_SEL_M (GPIO_FUNC20_OUT_SEL_V << GPIO_FUNC20_OUT_SEL_S) #define GPIO_FUNC20_OUT_SEL_V 0x000001FFU #define GPIO_FUNC20_OUT_SEL_S 0 /** GPIO_FUNC20_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC20_OUT_INV_SEL_M (GPIO_FUNC20_OUT_INV_SEL_V << GPIO_FUNC20_OUT_INV_SEL_S) #define GPIO_FUNC20_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC20_OUT_INV_SEL_S 9 /** GPIO_FUNC20_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 20 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC20_OE_SEL (BIT(10)) #define GPIO_FUNC20_OE_SEL_M (GPIO_FUNC20_OE_SEL_V << GPIO_FUNC20_OE_SEL_S) #define GPIO_FUNC20_OE_SEL_V 0x00000001U #define GPIO_FUNC20_OE_SEL_S 10 /** GPIO_FUNC20_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC20_OE_INV_SEL (BIT(11)) #define GPIO_FUNC20_OE_INV_SEL_M (GPIO_FUNC20_OE_INV_SEL_V << GPIO_FUNC20_OE_INV_SEL_S) @@ -4950,51 +4068,35 @@ extern "C" { #define GPIO_FUNC20_OE_INV_SEL_S 11 /** GPIO_FUNC21_OUT_SEL_CFG_REG register - * Configuration register for GPIO21 output + * GPIO output function select register */ -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb18) +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28) /** GPIO_FUNC21_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO21.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 21 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC21_OUT_SEL 0x000001FFU #define GPIO_FUNC21_OUT_SEL_M (GPIO_FUNC21_OUT_SEL_V << GPIO_FUNC21_OUT_SEL_S) #define GPIO_FUNC21_OUT_SEL_V 0x000001FFU #define GPIO_FUNC21_OUT_SEL_S 0 /** GPIO_FUNC21_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC21_OUT_INV_SEL_M (GPIO_FUNC21_OUT_INV_SEL_V << GPIO_FUNC21_OUT_INV_SEL_S) #define GPIO_FUNC21_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC21_OUT_INV_SEL_S 9 /** GPIO_FUNC21_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 21 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC21_OE_SEL (BIT(10)) #define GPIO_FUNC21_OE_SEL_M (GPIO_FUNC21_OE_SEL_V << GPIO_FUNC21_OE_SEL_S) #define GPIO_FUNC21_OE_SEL_V 0x00000001U #define GPIO_FUNC21_OE_SEL_S 10 /** GPIO_FUNC21_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC21_OE_INV_SEL (BIT(11)) #define GPIO_FUNC21_OE_INV_SEL_M (GPIO_FUNC21_OE_INV_SEL_V << GPIO_FUNC21_OE_INV_SEL_S) @@ -5002,51 +4104,35 @@ extern "C" { #define GPIO_FUNC21_OE_INV_SEL_S 11 /** GPIO_FUNC22_OUT_SEL_CFG_REG register - * Configuration register for GPIO22 output + * GPIO output function select register */ -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c) +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c) /** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO22.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC22_OUT_SEL 0x000001FFU #define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S) #define GPIO_FUNC22_OUT_SEL_V 0x000001FFU #define GPIO_FUNC22_OUT_SEL_S 0 /** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S) #define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC22_OUT_INV_SEL_S 9 /** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC22_OE_SEL (BIT(10)) #define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S) #define GPIO_FUNC22_OE_SEL_V 0x00000001U #define GPIO_FUNC22_OE_SEL_S 10 /** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC22_OE_INV_SEL (BIT(11)) #define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S) @@ -5054,51 +4140,35 @@ extern "C" { #define GPIO_FUNC22_OE_INV_SEL_S 11 /** GPIO_FUNC23_OUT_SEL_CFG_REG register - * Configuration register for GPIO23 output + * GPIO output function select register */ -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20) +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30) /** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO23.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC23_OUT_SEL 0x000001FFU #define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S) #define GPIO_FUNC23_OUT_SEL_V 0x000001FFU #define GPIO_FUNC23_OUT_SEL_S 0 /** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S) #define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC23_OUT_INV_SEL_S 9 /** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC23_OE_SEL (BIT(10)) #define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S) #define GPIO_FUNC23_OE_SEL_V 0x00000001U #define GPIO_FUNC23_OE_SEL_S 10 /** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC23_OE_INV_SEL (BIT(11)) #define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S) @@ -5106,65 +4176,371 @@ extern "C" { #define GPIO_FUNC23_OE_INV_SEL_S 11 /** GPIO_FUNC24_OUT_SEL_CFG_REG register - * Configuration register for GPIO24 output + * GPIO output function select register */ -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24) +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34) /** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIO24.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value - * and output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ #define GPIO_FUNC24_OUT_SEL 0x000001FFU #define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S) #define GPIO_FUNC24_OUT_SEL_V 0x000001FFU #define GPIO_FUNC24_OUT_SEL_S 0 /** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ #define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) #define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S) #define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U #define GPIO_FUNC24_OUT_INV_SEL_S 9 /** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ #define GPIO_FUNC24_OE_SEL (BIT(10)) #define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S) #define GPIO_FUNC24_OE_SEL_V 0x00000001U #define GPIO_FUNC24_OE_SEL_S 10 /** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ #define GPIO_FUNC24_OE_INV_SEL (BIT(11)) #define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S) #define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U #define GPIO_FUNC24_OE_INV_SEL_S 11 +/** GPIO_FUNC25_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb38) +/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC25_OUT_SEL 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S) +#define GPIO_FUNC25_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC25_OUT_SEL_S 0 +/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC25_OE_SEL (BIT(10)) +#define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S) +#define GPIO_FUNC25_OE_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_SEL_S 10 +/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC25_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S) +#define GPIO_FUNC25_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC25_OE_INV_SEL_S 11 + +/** GPIO_FUNC26_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb3c) +/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC26_OUT_SEL 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S) +#define GPIO_FUNC26_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC26_OUT_SEL_S 0 +/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC26_OE_SEL (BIT(10)) +#define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S) +#define GPIO_FUNC26_OE_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_SEL_S 10 +/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC26_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S) +#define GPIO_FUNC26_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC26_OE_INV_SEL_S 11 + +/** GPIO_FUNC27_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb40) +/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC27_OUT_SEL 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S) +#define GPIO_FUNC27_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC27_OUT_SEL_S 0 +/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC27_OE_SEL (BIT(10)) +#define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S) +#define GPIO_FUNC27_OE_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_SEL_S 10 +/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC27_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S) +#define GPIO_FUNC27_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC27_OE_INV_SEL_S 11 + +/** GPIO_FUNC28_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb44) +/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC28_OUT_SEL 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S) +#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC28_OUT_SEL_S 0 +/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC28_OE_SEL (BIT(10)) +#define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S) +#define GPIO_FUNC28_OE_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_SEL_S 10 +/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC28_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S) +#define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC28_OE_INV_SEL_S 11 + +/** GPIO_FUNC29_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb48) +/** GPIO_FUNC29_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC29_OUT_SEL 0x000001FFU +#define GPIO_FUNC29_OUT_SEL_M (GPIO_FUNC29_OUT_SEL_V << GPIO_FUNC29_OUT_SEL_S) +#define GPIO_FUNC29_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC29_OUT_SEL_S 0 +/** GPIO_FUNC29_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (GPIO_FUNC29_OUT_INV_SEL_V << GPIO_FUNC29_OUT_INV_SEL_S) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OUT_INV_SEL_S 9 +/** GPIO_FUNC29_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC29_OE_SEL (BIT(10)) +#define GPIO_FUNC29_OE_SEL_M (GPIO_FUNC29_OE_SEL_V << GPIO_FUNC29_OE_SEL_S) +#define GPIO_FUNC29_OE_SEL_V 0x00000001U +#define GPIO_FUNC29_OE_SEL_S 10 +/** GPIO_FUNC29_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC29_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OE_INV_SEL_M (GPIO_FUNC29_OE_INV_SEL_V << GPIO_FUNC29_OE_INV_SEL_S) +#define GPIO_FUNC29_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC29_OE_INV_SEL_S 11 + +/** GPIO_FUNC30_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb4c) +/** GPIO_FUNC30_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC30_OUT_SEL 0x000001FFU +#define GPIO_FUNC30_OUT_SEL_M (GPIO_FUNC30_OUT_SEL_V << GPIO_FUNC30_OUT_SEL_S) +#define GPIO_FUNC30_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC30_OUT_SEL_S 0 +/** GPIO_FUNC30_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (GPIO_FUNC30_OUT_INV_SEL_V << GPIO_FUNC30_OUT_INV_SEL_S) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OUT_INV_SEL_S 9 +/** GPIO_FUNC30_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC30_OE_SEL (BIT(10)) +#define GPIO_FUNC30_OE_SEL_M (GPIO_FUNC30_OE_SEL_V << GPIO_FUNC30_OE_SEL_S) +#define GPIO_FUNC30_OE_SEL_V 0x00000001U +#define GPIO_FUNC30_OE_SEL_S 10 +/** GPIO_FUNC30_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC30_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OE_INV_SEL_M (GPIO_FUNC30_OE_INV_SEL_V << GPIO_FUNC30_OE_INV_SEL_S) +#define GPIO_FUNC30_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC30_OE_INV_SEL_S 11 + +/** GPIO_FUNC31_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb50) +/** GPIO_FUNC31_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC31_OUT_SEL 0x000001FFU +#define GPIO_FUNC31_OUT_SEL_M (GPIO_FUNC31_OUT_SEL_V << GPIO_FUNC31_OUT_SEL_S) +#define GPIO_FUNC31_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC31_OUT_SEL_S 0 +/** GPIO_FUNC31_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (GPIO_FUNC31_OUT_INV_SEL_V << GPIO_FUNC31_OUT_INV_SEL_S) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OUT_INV_SEL_S 9 +/** GPIO_FUNC31_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC31_OE_SEL (BIT(10)) +#define GPIO_FUNC31_OE_SEL_M (GPIO_FUNC31_OE_SEL_V << GPIO_FUNC31_OE_SEL_S) +#define GPIO_FUNC31_OE_SEL_V 0x00000001U +#define GPIO_FUNC31_OE_SEL_S 10 +/** GPIO_FUNC31_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC31_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OE_INV_SEL_M (GPIO_FUNC31_OE_INV_SEL_V << GPIO_FUNC31_OE_INV_SEL_S) +#define GPIO_FUNC31_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC31_OE_INV_SEL_S 11 + +/** GPIO_FUNC32_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb54) +/** GPIO_FUNC32_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC32_OUT_SEL 0x000001FFU +#define GPIO_FUNC32_OUT_SEL_M (GPIO_FUNC32_OUT_SEL_V << GPIO_FUNC32_OUT_SEL_S) +#define GPIO_FUNC32_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC32_OUT_SEL_S 0 +/** GPIO_FUNC32_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (GPIO_FUNC32_OUT_INV_SEL_V << GPIO_FUNC32_OUT_INV_SEL_S) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OUT_INV_SEL_S 9 +/** GPIO_FUNC32_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC32_OE_SEL (BIT(10)) +#define GPIO_FUNC32_OE_SEL_M (GPIO_FUNC32_OE_SEL_V << GPIO_FUNC32_OE_SEL_S) +#define GPIO_FUNC32_OE_SEL_V 0x00000001U +#define GPIO_FUNC32_OE_SEL_S 10 +/** GPIO_FUNC32_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC32_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OE_INV_SEL_M (GPIO_FUNC32_OE_INV_SEL_V << GPIO_FUNC32_OE_INV_SEL_S) +#define GPIO_FUNC32_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC32_OE_INV_SEL_S 11 + +/** GPIO_FUNC33_OUT_SEL_CFG_REG register + * GPIO output function select register + */ +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb58) +/** GPIO_FUNC33_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256; + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. + */ +#define GPIO_FUNC33_OUT_SEL 0x000001FFU +#define GPIO_FUNC33_OUT_SEL_M (GPIO_FUNC33_OUT_SEL_V << GPIO_FUNC33_OUT_SEL_S) +#define GPIO_FUNC33_OUT_SEL_V 0x000001FFU +#define GPIO_FUNC33_OUT_SEL_S 0 +/** GPIO_FUNC33_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0; + * set this bit to invert output signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (GPIO_FUNC33_OUT_INV_SEL_V << GPIO_FUNC33_OUT_INV_SEL_S) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OUT_INV_SEL_S 9 +/** GPIO_FUNC33_OE_SEL : R/W; bitpos: [10]; default: 0; + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. + */ +#define GPIO_FUNC33_OE_SEL (BIT(10)) +#define GPIO_FUNC33_OE_SEL_M (GPIO_FUNC33_OE_SEL_V << GPIO_FUNC33_OE_SEL_S) +#define GPIO_FUNC33_OE_SEL_V 0x00000001U +#define GPIO_FUNC33_OE_SEL_S 10 +/** GPIO_FUNC33_OE_INV_SEL : R/W; bitpos: [11]; default: 0; + * set this bit to invert output enable signal.1:invert.0:not invert. + */ +#define GPIO_FUNC33_OE_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OE_INV_SEL_M (GPIO_FUNC33_OE_INV_SEL_V << GPIO_FUNC33_OE_INV_SEL_S) +#define GPIO_FUNC33_OE_INV_SEL_V 0x00000001U +#define GPIO_FUNC33_OE_INV_SEL_S 11 + /** GPIO_CLOCK_GATE_REG register * GPIO clock gate register */ #define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0xdf8) /** GPIO_CLK_EN : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * set this bit to enable GPIO clock gate */ #define GPIO_CLK_EN (BIT(0)) #define GPIO_CLK_EN_M (GPIO_CLK_EN_V << GPIO_CLK_EN_S) @@ -5175,8 +4551,8 @@ extern "C" { * GPIO version register */ #define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0xdfc) -/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37753392; - * Version control register. \\ +/** GPIO_DATE : R/W; bitpos: [27:0]; default: 37823120; + * version register */ #define GPIO_DATE 0x0FFFFFFFU #define GPIO_DATE_M (GPIO_DATE_V << GPIO_DATE_S) diff --git a/components/soc/esp32c61/register/soc/gpio_struct.h b/components/soc/esp32c61/register/soc/gpio_struct.h index d37ed33d56..e5f244d4de 100644 --- a/components/soc/esp32c61/register/soc/gpio_struct.h +++ b/components/soc/esp32c61/register/soc/gpio_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,20 +10,14 @@ extern "C" { #endif -/** Group: Configuration Registers */ +/** Group: configuration register */ /** Type of strap register - * Strapping pin register + * pad strapping register */ typedef union { struct { /** strapping : RO; bitpos: [15:0]; default: 0; - * Represents the values of GPIO strapping pins. - * - * - bit0 ~ bit1: invalid - * - bit2: GPIO8 - * - bit3: GPIO9 - * - bit4: GPIO7 - * - bit5 ~ bit15: invalid + * pad strapping register */ uint32_t strapping:16; uint32_t reserved_16:16; @@ -32,297 +26,389 @@ typedef union { } gpio_strap_reg_t; /** Type of out register - * GPIO output register + * GPIO output register for GPIO0-31 */ typedef union { struct { - /** out_data_orig : R/W/SC/WTC; bitpos: [28:0]; default: 0; - * Configures the output value of GPIO0 ~ 24 output in simple GPIO output mode.\\ - * 0: Low level\\ - * 1: High level\\ - * The value of bit0 ~ bit24 correspond to the output value of GPIO0 ~ GPIO24 - * respectively. Bit25 ~ bit31 are invalid.\\ + /** out_data_orig : R/W/SC/WTC; bitpos: [31:0]; default: 0; + * GPIO output register for GPIO0-31 */ - uint32_t out_data_orig:29; - uint32_t reserved_29:3; + uint32_t out_data_orig:32; }; uint32_t val; } gpio_out_reg_t; /** Type of out_w1ts register - * GPIO output set register + * GPIO output set register for GPIO0-31 */ typedef union { struct { - /** out_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_OUT_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_OUT_REG. \\ + /** out_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output set register for GPIO0-31 */ - uint32_t out_w1ts:29; - uint32_t reserved_29:3; + uint32_t out_w1ts:32; }; uint32_t val; } gpio_out_w1ts_reg_t; /** Type of out_w1tc register - * GPIO output clear register + * GPIO output clear register for GPIO0-31 */ typedef union { struct { - /** out_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output register GPIO_OUT_REG of GPIO0 ~ - * GPIO24 output.\\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_OUT_REG will be cleared.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_OUT_REG. \\ + /** out_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output clear register for GPIO0-31 */ - uint32_t out_w1tc:29; - uint32_t reserved_29:3; + uint32_t out_w1tc:32; }; uint32_t val; } gpio_out_w1tc_reg_t; -/** Type of enable register - * GPIO output enable register +/** Type of out1 register + * GPIO output register for GPIO32-33 */ typedef union { struct { - /** enable_data : R/W/WTC; bitpos: [28:0]; default: 0; - * Configures whether or not to enable the output of GPIO0 ~ GPIO24.\\ - * 0: Not enable\\ - * 1: Enable\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + /** out1_data_orig : R/W/SC/WTC; bitpos: [1:0]; default: 0; + * GPIO output register for GPIO32-33 */ - uint32_t enable_data:29; - uint32_t reserved_29:3; + uint32_t out1_data_orig:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_reg_t; + +/** Type of out1_w1ts register + * GPIO output set register for GPIO32-33 + */ +typedef union { + struct { + /** out1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO output set register for GPIO32-33 + */ + uint32_t out1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_w1ts_reg_t; + +/** Type of out1_w1tc register + * GPIO output clear register for GPIO32-33 + */ +typedef union { + struct { + /** out1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO output clear register for GPIO32-33 + */ + uint32_t out1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_out1_w1tc_reg_t; + +/** Type of enable register + * GPIO output enable register for GPIO0-31 + */ +typedef union { + struct { + /** enable_data : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO output enable register for GPIO0-31 + */ + uint32_t enable_data:32; }; uint32_t val; } gpio_enable_reg_t; /** Type of enable_w1ts register - * GPIO output enable set register + * GPIO output enable set register for GPIO0-31 */ typedef union { struct { - /** enable_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24.\\ - * 0: Not set\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be set to 1\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to set GPIO_ENABLE_REG.\\ + /** enable_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO output enable set register for GPIO0-31 */ - uint32_t enable_w1ts:29; - uint32_t reserved_29:3; + uint32_t enable_w1ts:32; }; uint32_t val; } gpio_enable_w1ts_reg_t; /** Type of enable_w1tc register - * GPIO output enable clear register + * GPIO output enable clear register for GPIO0-31 */ typedef union { struct { - /** enable_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the output enable register GPIO_ENABLE_REG of - * GPIO0 ~ GPIO24. \\ - * 0: Not clear\\ - * 1: The corresponding bit in GPIO_ENABLE_REG will be cleared\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. \\ - * Recommended operation: use this register to clear GPIO_ENABLE_REG.\\ + /** enable_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO output enable clear register for GPIO0-31 */ - uint32_t enable_w1tc:29; - uint32_t reserved_29:3; + uint32_t enable_w1tc:32; }; uint32_t val; } gpio_enable_w1tc_reg_t; -/** Type of in register - * GPIO input register +/** Type of enable1 register + * GPIO output enable register for GPIO32-33 */ typedef union { struct { - /** in_data_next : RO; bitpos: [28:0]; default: 0; - * Represents the input value of GPIO0 ~ GPIO24. Each bit represents a pin input - * value:\\ - * 0: Low level\\ - * 1: High level\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid.\\ + /** enable1_data : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO output enable register for GPIO32-33 */ - uint32_t in_data_next:29; - uint32_t reserved_29:3; + uint32_t enable1_data:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_reg_t; + +/** Type of enable1_w1ts register + * GPIO output enable set register for GPIO32-33 + */ +typedef union { + struct { + /** enable1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO output enable set register for GPIO32-33 + */ + uint32_t enable1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_w1ts_reg_t; + +/** Type of enable1_w1tc register + * GPIO output enable clear register for GPIO32-33 + */ +typedef union { + struct { + /** enable1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO output enable clear register for GPIO32-33 + */ + uint32_t enable1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_enable1_w1tc_reg_t; + +/** Type of in register + * GPIO input register for GPIO0-31 + */ +typedef union { + struct { + /** in_data_next : RO; bitpos: [31:0]; default: 0; + * GPIO input register for GPIO0-31 + */ + uint32_t in_data_next:32; }; uint32_t val; } gpio_in_reg_t; - -/** Group: Interrupt Status Registers */ -/** Type of status register - * GPIO interrupt status register +/** Type of in1 register + * GPIO input register for GPIO32-33 */ typedef union { struct { - /** status_interrupt : R/W/WTC; bitpos: [28:0]; default: 0; - * The interrupt status of GPIO0 ~ GPIO24, can be configured by the software. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - Each bit represents the status of its corresponding GPIO: - * - * - 0: Represents the GPIO does not generate the interrupt configured by - * GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software. - * - 1: Represents the GPIO generates the interrupt configured by GPIO_PIN$n_INT_TYPE, - * or this bit is configured to 1 by the software. - * + /** in1_data_next : RO; bitpos: [1:0]; default: 0; + * GPIO input register for GPIO32-33 */ - uint32_t status_interrupt:29; - uint32_t reserved_29:3; + uint32_t in1_data_next:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_in1_reg_t; + +/** Type of status register + * GPIO interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt : R/W/WTC; bitpos: [31:0]; default: 0; + * GPIO interrupt status register for GPIO0-31 + */ + uint32_t status_interrupt:32; }; uint32_t val; } gpio_status_reg_t; /** Type of status_w1ts register - * GPIO interrupt status set register + * GPIO interrupt status set register for GPIO0-31 */ typedef union { struct { - /** status_w1ts : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to set the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this - * register to set GPIO_STATUS_INTERRUPT. + /** status_w1ts : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status set register for GPIO0-31 */ - uint32_t status_w1ts:29; - uint32_t reserved_29:3; + uint32_t status_w1ts:32; }; uint32_t val; } gpio_status_w1ts_reg_t; /** Type of status_w1tc register - * GPIO interrupt status clear register + * GPIO interrupt status clear register for GPIO0-31 */ typedef union { struct { - /** status_w1tc : WT; bitpos: [28:0]; default: 0; - * Configures whether or not to clear the interrupt status register - * GPIO_STATUS_INTERRUPT of GPIO0 ~ GPIO24. - * - * - Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. - * - If the value 1 is written to a bit here, the corresponding bit in - * GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this - * register to clear GPIO_STATUS_INTERRUPT. + /** status_w1tc : WT; bitpos: [31:0]; default: 0; + * GPIO interrupt status clear register for GPIO0-31 */ - uint32_t status_w1tc:29; - uint32_t reserved_29:3; + uint32_t status_w1tc:32; }; uint32_t val; } gpio_status_w1tc_reg_t; -/** Type of procpu_int register - * CPU interrupt status register +/** Type of status1 register + * GPIO interrupt status register for GPIO32-33 */ typedef union { struct { - /** procpu_int : RO; bitpos: [28:0]; default: 0; - * Represents the CPU interrupt status of GPIO0 ~ GPIO24. Each bit represents:\\ - * 0: Represents CPU interrupt is not enabled, or the GPIO does not generate the - * interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: Represents the GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE - * after the CPU interrupt is enabled.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. This - * interrupt status is corresponding to the bit in GPIO_STATUS_REG when assert (high) - * enable signal (bit13 of GPIO_PIN$n_REG). \\ + /** status1_interrupt : R/W/WTC; bitpos: [1:0]; default: 0; + * GPIO interrupt status register for GPIO32-33 */ - uint32_t procpu_int:29; - uint32_t reserved_29:3; + uint32_t status1_interrupt:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_reg_t; + +/** Type of status1_w1ts register + * GPIO interrupt status set register for GPIO32-33 + */ +typedef union { + struct { + /** status1_w1ts : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status set register for GPIO32-33 + */ + uint32_t status1_w1ts:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_w1ts_reg_t; + +/** Type of status1_w1tc register + * GPIO interrupt status clear register for GPIO32-33 + */ +typedef union { + struct { + /** status1_w1tc : WT; bitpos: [1:0]; default: 0; + * GPIO interrupt status clear register for GPIO32-33 + */ + uint32_t status1_w1tc:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status1_w1tc_reg_t; + +/** Type of procpu_int register + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + */ +typedef union { + struct { + /** procpu_int : RO; bitpos: [31:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO0-31 + */ + uint32_t procpu_int:32; }; uint32_t val; } gpio_procpu_int_reg_t; -/** Type of status_next register - * GPIO interrupt source register +/** Type of sdio_int register + * GPIO_SDIO_INT interrupt status register for GPIO0-31 */ typedef union { struct { - /** status_interrupt_next : RO; bitpos: [28:0]; default: 0; - * Represents the interrupt source signal of GPIO0 ~ GPIO24.\\ - * Bit0 ~ bit24 are corresponding to GPIO0 ~ GPIO24. Bit25 ~ bit31 are invalid. Each - * bit represents:\\ - * 0: The GPIO does not generate the interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * 1: The GPIO generates an interrupt configured by GPIO_PIN$n_INT_TYPE.\\ - * The interrupt could be rising edge interrupt, falling edge interrupt, level - * sensitive interrupt and any edge interrupt.\\ + /** sdio_int : RO; bitpos: [31:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO0-31 */ - uint32_t status_interrupt_next:29; - uint32_t reserved_29:3; + uint32_t sdio_int:32; + }; + uint32_t val; +} gpio_sdio_int_reg_t; + +/** Type of procpu_int1 register + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ +typedef union { + struct { + /** procpu_int1 : RO; bitpos: [1:0]; default: 0; + * GPIO_PROCPU_INT interrupt status register for GPIO32-33 + */ + uint32_t procpu_int1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_procpu_int1_reg_t; + +/** Type of sdio_int1 register + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ +typedef union { + struct { + /** sdio_int1 : RO; bitpos: [1:0]; default: 0; + * GPIO_SDIO_INT interrupt status register for GPIO32-33 + */ + uint32_t sdio_int1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_sdio_int1_reg_t; + +/** Type of status_next register + * GPIO interrupt source register for GPIO0-31 + */ +typedef union { + struct { + /** status_interrupt_next : RO; bitpos: [31:0]; default: 0; + * GPIO interrupt source register for GPIO0-31 + */ + uint32_t status_interrupt_next:32; }; uint32_t val; } gpio_status_next_reg_t; +/** Type of status_next1 register + * GPIO interrupt source register for GPIO32-33 + */ +typedef union { + struct { + /** status_interrupt_next1 : RO; bitpos: [1:0]; default: 0; + * GPIO interrupt source register for GPIO32-33 + */ + uint32_t status_interrupt_next1:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} gpio_status_next1_reg_t; -/** Group: Pin Configuration Registers */ /** Type of pinn register - * GPIOn configuration register + * GPIO pin configuration register */ typedef union { struct { /** pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the second-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync2_bypass:2; /** pinn_pad_driver : R/W; bitpos: [2]; default: 0; - * Configures to select pin drive mode. \\ - * 0: Normal output\\ - * 1: Open drain output \\ + * set this bit to select pad driver. 1:open-drain. 0:normal. */ uint32_t pinn_pad_driver:1; /** pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0; - * Configures whether or not to synchronize GPIO input data on either edge of IO MUX - * operating clock for the first-level synchronization.\\ - * 0: Not synchronize\\ - * 1: Synchronize on falling edge\\ - * 2: Synchronize on rising edge\\ - * 3: Synchronize on rising edge\\ + * set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at + * posedge. */ uint32_t pinn_sync1_bypass:2; uint32_t reserved_5:2; /** pinn_int_type : R/W; bitpos: [9:7]; default: 0; - * Configures GPIO interrupt type.\\ - * 0: GPIO interrupt disabled\\ - * 1: Rising edge trigger\\ - * 2: Falling edge trigger\\ - * 3: Any edge trigger\\ - * 4: Low level trigger\\ - * 5: High level trigger\\ + * set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at + * posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid + * at high level */ uint32_t pinn_int_type:3; /** pinn_wakeup_enable : R/W; bitpos: [10]; default: 0; - * Configures whether or not to enable GPIO wake-up function.\\ - * 0: Disable\\ - * 1: Enable\\ - * This function only wakes up the CPU from Light-sleep. \\ + * set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) */ uint32_t pinn_wakeup_enable:1; uint32_t reserved_11:2; /** pinn_int_ena : R/W; bitpos: [17:13]; default: 0; - * Configures whether or not to enable CPU interrupt. - * - * - bit13: Configures whether or not to enable CPU interrupt:\\ - * 0: Disable\\ - * 1: Enable\\ - * - bit14 ~ bit17: invalid + * set bit 13 to enable gpio_procpu_int. set bit 15 to enable gpio_sdio_int. */ uint32_t pinn_int_ena:5; uint32_t reserved_18:14; @@ -330,82 +416,51 @@ typedef union { uint32_t val; } gpio_pinn_reg_t; - -/** Group: Input Configuration Registers */ -/** Type of func0_in_sel_cfg register - * Configuration register for input signal 0 +/** Type of func_in_sel_cfg register + * GPIO input function configuration register */ typedef union { struct { - /** func_in_sel : R/W; bitpos: [5:0]; default: 48; - * Configures to select a pin from the 25 GPIO pins to connect the input signal 0.\\ - * 0: Select GPIO0\\ - * 1: Select GPIO1\\ - * ......\\ - * 23: Select GPIO23\\ - * 24: Select GPIO24\\ - * Or\\ - * 0x20: A constantly high input\\ - * 0x30: A constantly low input\\ + /** func_in_sel : R/W; bitpos: [6:0]; default: 96; + * set this value: s=0-33: connect GPIO[s] to this port. s=0x40: set this port always + * high level. s=0x60: set this port always low level. */ - uint32_t func_in_sel:6; - /** func_in_inv_sel : R/W; bitpos: [6]; default: 0; - * Configures whether or not to invert the input value.\\ - * 0: Not invert\\ - * 1: Invert\\ + uint32_t func_in_sel:7; + /** func_in_inv_sel : R/W; bitpos: [7]; default: 0; + * set this bit to invert input signal. 1:invert. 0:not invert. */ uint32_t func_in_inv_sel:1; - /** sig_in_sel : R/W; bitpos: [7]; default: 0; - * Configures whether or not to route signals via GPIO matrix.\\ - * 0: Bypass GPIO matrix, i.e., connect signals directly to peripheral configured in - * IO MUX.\\ - * 1: Route signals via GPIO matrix.\\ + /** sig0_in_sel : R/W; bitpos: [8]; default: 0; + * set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. */ uint32_t sig_in_sel:1; - uint32_t reserved_8:24; + uint32_t reserved_9:23; }; uint32_t val; } gpio_func_in_sel_cfg_reg_t; -/** Group: Output Configuration Registers */ /** Type of funcn_out_sel_cfg register - * Configuration register for GPIOn output + * GPIO output function select register */ typedef union { struct { /** funcn_out_sel : R/W/SC; bitpos: [8:0]; default: 256; - * Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be - * output from GPIOn.\\ - * 0: Select signal 0\\ - * 1: Select signal 1\\ - * ......\\ - * 254: Select signal 254\\ - * 255: Select signal 255\\ - * Or\\ - * 256: Bit n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value and - * output enable. - * - * For the detailed signal list, see Table link. - * " + * The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-127: + * output of GPIO[n] equals input of peripheral[s]. s=128: output of GPIO[n] equals + * GPIO_OUT_REG[n]. */ uint32_t funcn_out_sel:9; /** funcn_out_inv_sel : R/W/SC; bitpos: [9]; default: 0; - * Configures whether or not to invert the output value.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output signal.1:invert.0:not invert. */ uint32_t funcn_out_inv_sel:1; /** funcn_oe_sel : R/W; bitpos: [10]; default: 0; - * Configures to select the source of output enable signal.\\ - * 0: Use output enable signal from peripheral.\\ - * 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. \\ + * set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output + * enable signal.0:use peripheral output enable signal. */ uint32_t funcn_oe_sel:1; /** funcn_oe_inv_sel : R/W; bitpos: [11]; default: 0; - * Configures whether or not to invert the output enable signal.\\ - * 0: Not invert\\ - * 1: Invert\\ + * set this bit to invert output enable signal.1:invert.0:not invert. */ uint32_t funcn_oe_inv_sel:1; uint32_t reserved_12:20; @@ -413,17 +468,13 @@ typedef union { uint32_t val; } gpio_funcn_out_sel_cfg_reg_t; - -/** Group: Clock Gate Register */ /** Type of clock_gate register * GPIO clock gate register */ typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 1; - * Configures whether or not to enable clock gate.\\ - * 0: Not enable\\ - * 1: Enable, the clock is free running. \\ + * set this bit to enable GPIO clock gate */ uint32_t clk_en:1; uint32_t reserved_1:31; @@ -431,15 +482,13 @@ typedef union { uint32_t val; } gpio_clock_gate_reg_t; - -/** Group: Version Register */ /** Type of date register * GPIO version register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753392; - * Version control register. \\ + /** date : R/W; bitpos: [27:0]; default: 37823120; + * version register */ uint32_t date:28; uint32_t reserved_28:4; @@ -453,27 +502,41 @@ typedef struct { volatile gpio_out_reg_t out; volatile gpio_out_w1ts_reg_t out_w1ts; volatile gpio_out_w1tc_reg_t out_w1tc; - uint32_t reserved_010[9]; + volatile gpio_out1_reg_t out1; + volatile gpio_out1_w1ts_reg_t out1_w1ts; + volatile gpio_out1_w1tc_reg_t out1_w1tc; + uint32_t reserved_01c[6]; volatile gpio_enable_reg_t enable; volatile gpio_enable_w1ts_reg_t enable_w1ts; volatile gpio_enable_w1tc_reg_t enable_w1tc; - uint32_t reserved_040[9]; + volatile gpio_enable1_reg_t enable1; + volatile gpio_enable1_w1ts_reg_t enable1_w1ts; + volatile gpio_enable1_w1tc_reg_t enable1_w1tc; + uint32_t reserved_04c[6]; volatile gpio_in_reg_t in; - uint32_t reserved_068[3]; + volatile gpio_in1_reg_t in1; + uint32_t reserved_06c[2]; volatile gpio_status_reg_t status; volatile gpio_status_w1ts_reg_t status_w1ts; volatile gpio_status_w1tc_reg_t status_w1tc; - uint32_t reserved_080[9]; + volatile gpio_status1_reg_t status1; + volatile gpio_status1_w1ts_reg_t status1_w1ts; + volatile gpio_status1_w1tc_reg_t status1_w1tc; + uint32_t reserved_08c[6]; volatile gpio_procpu_int_reg_t procpu_int; - uint32_t reserved_0a8[3]; + volatile gpio_sdio_int_reg_t sdio_int; + volatile gpio_procpu_int1_reg_t procpu_int1; + volatile gpio_sdio_int1_reg_t sdio_int1; + uint32_t reserved_0b4[4]; volatile gpio_status_next_reg_t status_next; - uint32_t reserved_0b8[3]; - volatile gpio_pinn_reg_t pinn[25]; // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available. - uint32_t reserved_128[103]; - volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255; - uint32_t reserved_4ac[256]; - volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25]; - uint32_t reserved_b28[180]; + volatile gpio_status_next1_reg_t status_next1; + uint32_t reserved_0cc[2]; + volatile gpio_pinn_reg_t pinn[34]; // 0~29 available, 30~34 not fan out, N/A + uint32_t reserved_15c[94]; + volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; // 0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255 + uint32_t reserved_542[256]; + volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[34]; // 0~29 available, 30~34 not fan out, N/A + uint32_t reserved_b5c[167]; volatile gpio_clock_gate_reg_t clock_gate; volatile gpio_date_reg_t date; } gpio_dev_t; diff --git a/components/soc/esp32c61/register/soc/hp_system_reg.h b/components/soc/esp32c61/register/soc/hp_system_reg.h index 168e95015c..83459c8135 100644 --- a/components/soc/esp32c61/register/soc/hp_system_reg.h +++ b/components/soc/esp32c61/register/soc/hp_system_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -16,9 +16,9 @@ extern "C" { */ #define HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_HP_SYSTEM_BASE + 0x0) /** HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) #define HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) @@ -32,10 +32,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001U #define HP_SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 /** HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) @@ -43,9 +42,9 @@ extern "C" { #define HP_SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 /** HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) #define HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) @@ -56,13 +55,6 @@ extern "C" { * HP memory usage configuration register */ #define HP_SYSTEM_SRAM_USAGE_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x4) -/** HP_SYSTEM_CACHE_USAGE : HRO; bitpos: [0]; default: 0; - * reserved - */ -#define HP_SYSTEM_CACHE_USAGE (BIT(0)) -#define HP_SYSTEM_CACHE_USAGE_M (HP_SYSTEM_CACHE_USAGE_V << HP_SYSTEM_CACHE_USAGE_S) -#define HP_SYSTEM_CACHE_USAGE_V 0x00000001U -#define HP_SYSTEM_CACHE_USAGE_S 0 /** HP_SYSTEM_SRAM_USAGE : R/W; bitpos: [12:8]; default: 0; * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. */ @@ -84,11 +76,11 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x8) /** HP_SYSTEM_SEC_DPA_LEVEL : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ #define HP_SYSTEM_SEC_DPA_LEVEL 0x00000003U #define HP_SYSTEM_SEC_DPA_LEVEL_M (HP_SYSTEM_SEC_DPA_LEVEL_V << HP_SYSTEM_SEC_DPA_LEVEL_S) @@ -96,9 +88,9 @@ extern "C" { #define HP_SYSTEM_SEC_DPA_LEVEL_S 0 /** HP_SYSTEM_SEC_DPA_CFG_SEL : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ #define HP_SYSTEM_SEC_DPA_CFG_SEL (BIT(2)) #define HP_SYSTEM_SEC_DPA_CFG_SEL_M (HP_SYSTEM_SEC_DPA_CFG_SEL_V << HP_SYSTEM_SEC_DPA_CFG_SEL_S) @@ -126,9 +118,9 @@ extern "C" { #define HP_SYSTEM_CPU_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_CPU_PERI_TIMEOUT_PROTECT_EN_S) @@ -173,9 +165,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_V 0x0000FFFFU #define HP_SYSTEM_HP_PERI_TIMEOUT_THRES_S 0 /** HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR (BIT(16)) #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S) @@ -183,9 +175,9 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_INT_CLEAR_S 16 /** HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN (BIT(17)) #define HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_HP_PERI_TIMEOUT_PROTECT_EN_S) @@ -217,66 +209,14 @@ extern "C" { #define HP_SYSTEM_HP_PERI_TIMEOUT_UID_V 0x0000007FU #define HP_SYSTEM_HP_PERI_TIMEOUT_UID_S 0 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG register - * MODEM_PERI_TIMEOUT configuration register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_CONF_REG (DR_REG_HP_SYSTEM_BASE + 0x24) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES : R/W; bitpos: [15:0]; default: 65535; - * Set the timeout threshold for bus access, corresponding to the number of clock - * cycles of the clock domain. - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES 0x0000FFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_V 0x0000FFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_THRES_S 0 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR : WT; bitpos: [16]; default: 0; - * Set this bit as 1 to clear timeout interrupt - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR (BIT(16)) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_V 0x00000001U -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_INT_CLEAR_S 16 -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN : R/W; bitpos: [17]; default: 1; - * Set this bit as 1 to enable timeout protection for accessing modem registers - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN (BIT(17)) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_V 0x00000001U -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_PROTECT_EN_S 17 - -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG register - * MODEM_PERI_TIMEOUT_ADDR register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_REG (DR_REG_HP_SYSTEM_BASE + 0x28) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR : RO; bitpos: [31:0]; default: 0; - * Record the address information of abnormal access - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR 0xFFFFFFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_V 0xFFFFFFFFU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_ADDR_S 0 - -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG register - * MODEM_PERI_TIMEOUT_UID register - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_REG (DR_REG_HP_SYSTEM_BASE + 0x2c) -/** HP_SYSTEM_MODEM_PERI_TIMEOUT_UID : RO; bitpos: [6:0]; default: 0; - * Record master id[4:0] & master permission[6:5] when trigger timeout. This register - * will be cleared after the interrupt is cleared. - */ -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID 0x0000007FU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_M (HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V << HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S) -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_V 0x0000007FU -#define HP_SYSTEM_MODEM_PERI_TIMEOUT_UID_S 0 - /** HP_SYSTEM_ROM_TABLE_LOCK_REG register * ROM-Table lock register */ #define HP_SYSTEM_ROM_TABLE_LOCK_REG (DR_REG_HP_SYSTEM_BASE + 0x30) /** HP_SYSTEM_ROM_TABLE_LOCK : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ #define HP_SYSTEM_ROM_TABLE_LOCK (BIT(0)) #define HP_SYSTEM_ROM_TABLE_LOCK_M (HP_SYSTEM_ROM_TABLE_LOCK_V << HP_SYSTEM_ROM_TABLE_LOCK_S) @@ -357,78 +297,66 @@ extern "C" { #define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_V 0xFFFFFFFFU #define HP_SYSTEM_SDPRF_MEM_AUX_CTRL_S 0 -/** HP_SYSTEM_RND_ECO_REG register - * redcy eco register. - */ -#define HP_SYSTEM_RND_ECO_REG (DR_REG_HP_SYSTEM_BASE + 0x4c) -/** HP_SYSTEM_REDCY_ENA : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_ENA (BIT(0)) -#define HP_SYSTEM_REDCY_ENA_M (HP_SYSTEM_REDCY_ENA_V << HP_SYSTEM_REDCY_ENA_S) -#define HP_SYSTEM_REDCY_ENA_V 0x00000001U -#define HP_SYSTEM_REDCY_ENA_S 0 -/** HP_SYSTEM_REDCY_RESULT : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_RESULT (BIT(1)) -#define HP_SYSTEM_REDCY_RESULT_M (HP_SYSTEM_REDCY_RESULT_V << HP_SYSTEM_REDCY_RESULT_S) -#define HP_SYSTEM_REDCY_RESULT_V 0x00000001U -#define HP_SYSTEM_REDCY_RESULT_S 1 - -/** HP_SYSTEM_RND_ECO_LOW_REG register - * redcy eco low register. - */ -#define HP_SYSTEM_RND_ECO_LOW_REG (DR_REG_HP_SYSTEM_BASE + 0x50) -/** HP_SYSTEM_REDCY_LOW : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_LOW 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_LOW_M (HP_SYSTEM_REDCY_LOW_V << HP_SYSTEM_REDCY_LOW_S) -#define HP_SYSTEM_REDCY_LOW_V 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_LOW_S 0 - -/** HP_SYSTEM_RND_ECO_HIGH_REG register - * redcy eco high register. - */ -#define HP_SYSTEM_RND_ECO_HIGH_REG (DR_REG_HP_SYSTEM_BASE + 0x54) -/** HP_SYSTEM_REDCY_HIGH : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ -#define HP_SYSTEM_REDCY_HIGH 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_HIGH_M (HP_SYSTEM_REDCY_HIGH_V << HP_SYSTEM_REDCY_HIGH_S) -#define HP_SYSTEM_REDCY_HIGH_V 0xFFFFFFFFU -#define HP_SYSTEM_REDCY_HIGH_S 0 - -/** HP_SYSTEM_DEBUG_REG register - * HP-SYSTEM debug register - */ -#define HP_SYSTEM_DEBUG_REG (DR_REG_HP_SYSTEM_BASE + 0x58) -/** HP_SYSTEM_FPGA_DEBUG : R/W; bitpos: [0]; default: 1; - * Reserved - */ -#define HP_SYSTEM_FPGA_DEBUG (BIT(0)) -#define HP_SYSTEM_FPGA_DEBUG_M (HP_SYSTEM_FPGA_DEBUG_V << HP_SYSTEM_FPGA_DEBUG_S) -#define HP_SYSTEM_FPGA_DEBUG_V 0x00000001U -#define HP_SYSTEM_FPGA_DEBUG_S 0 - /** HP_SYSTEM_CLOCK_GATE_REG register * HP-SYSTEM clock gating configure register + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define HP_SYSTEM_CLOCK_GATE_REG (DR_REG_HP_SYSTEM_BASE + 0x5c) /** HP_SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 0; * Set this bit as 1 to force on clock gating. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define HP_SYSTEM_CLK_EN (BIT(0)) #define HP_SYSTEM_CLK_EN_M (HP_SYSTEM_CLK_EN_V << HP_SYSTEM_CLK_EN_S) #define HP_SYSTEM_CLK_EN_V 0x00000001U #define HP_SYSTEM_CLK_EN_S 0 +/** HP_SYSTEM_AXI_MST_PRI_REG register + * AXI mst priority configuration register + */ +#define HP_SYSTEM_AXI_MST_PRI_REG (DR_REG_HP_SYSTEM_BASE + 0x60) +/** HP_SYSTEM_DMA_PRIORITY : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_DMA_PRIORITY (BIT(0)) +#define HP_SYSTEM_DMA_PRIORITY_M (HP_SYSTEM_DMA_PRIORITY_V << HP_SYSTEM_DMA_PRIORITY_S) +#define HP_SYSTEM_DMA_PRIORITY_V 0x00000001U +#define HP_SYSTEM_DMA_PRIORITY_S 0 +/** HP_SYSTEM_CACHE_PRIORITY : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ +#define HP_SYSTEM_CACHE_PRIORITY (BIT(1)) +#define HP_SYSTEM_CACHE_PRIORITY_M (HP_SYSTEM_CACHE_PRIORITY_V << HP_SYSTEM_CACHE_PRIORITY_S) +#define HP_SYSTEM_CACHE_PRIORITY_V 0x00000001U +#define HP_SYSTEM_CACHE_PRIORITY_S 1 + +/** HP_SYSTEM_SDIO_CTRL_REG register + * SDIO Control configuration register + */ +#define HP_SYSTEM_SDIO_CTRL_REG (DR_REG_HP_SYSTEM_BASE + 0x64) +/** HP_SYSTEM_DIS_SDIO_PROB : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ +#define HP_SYSTEM_DIS_SDIO_PROB (BIT(0)) +#define HP_SYSTEM_DIS_SDIO_PROB_M (HP_SYSTEM_DIS_SDIO_PROB_V << HP_SYSTEM_DIS_SDIO_PROB_S) +#define HP_SYSTEM_DIS_SDIO_PROB_V 0x00000001U +#define HP_SYSTEM_DIS_SDIO_PROB_S 0 +/** HP_SYSTEM_SDIO_WIN_ACCESS_EN : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN (BIT(1)) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_M (HP_SYSTEM_SDIO_WIN_ACCESS_EN_V << HP_SYSTEM_SDIO_WIN_ACCESS_EN_S) +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_V 0x00000001U +#define HP_SYSTEM_SDIO_WIN_ACCESS_EN_S 1 + /** HP_SYSTEM_DATE_REG register * Date control and version control register */ #define HP_SYSTEM_DATE_REG (DR_REG_HP_SYSTEM_BASE + 0x3fc) -/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 36769824; +/** HP_SYSTEM_DATE : R/W; bitpos: [27:0]; default: 37823088; * Version control register. */ #define HP_SYSTEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/hp_system_struct.h b/components/soc/esp32c61/register/soc/hp_system_struct.h index 6c786758a9..23c94a00cb 100644 --- a/components/soc/esp32c61/register/soc/hp_system_struct.h +++ b/components/soc/esp32c61/register/soc/hp_system_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,438 +11,344 @@ extern "C" { #endif /** Group: Configuration Register */ -/** Type of external_device_encrypt_decrypt_control register +/** Type of system_external_device_encrypt_decrypt_control register * External device encryption/decryption configuration register */ typedef union { struct { - /** enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode.\\ - * 0: Disable\\ - * 1: Enable\\ + /** system_enable_spi_manual_encrypt : R/W; bitpos: [0]; default: 0; + * Configures whether or not to enable MSPI XTS manual encryption in SPI boot mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_spi_manual_encrypt:1; - /** enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; + uint32_t system_enable_spi_manual_encrypt:1; + /** system_enable_download_db_encrypt : R/W; bitpos: [1]; default: 0; * reserved */ - uint32_t enable_download_db_encrypt:1; - /** enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; - * Configures whether or not to enable MSPI XTS auto decryption in download boot - * mode.\\ - * 0: Disable\\ - * 1: Enable\\ + uint32_t system_enable_download_db_encrypt:1; + /** system_enable_download_g0cb_decrypt : R/W; bitpos: [2]; default: 0; + * Configures whether or not to enable MSPI XTS auto decryption in download boot mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_download_g0cb_decrypt:1; - /** enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; + uint32_t system_enable_download_g0cb_decrypt:1; + /** system_enable_download_manual_encrypt : R/W; bitpos: [3]; default: 0; * Configures whether or not to enable MSPI XTS manual encryption in download boot - * mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * mode. + * 0: Disable + * 1: Enable */ - uint32_t enable_download_manual_encrypt:1; + uint32_t system_enable_download_manual_encrypt:1; uint32_t reserved_4:28; }; uint32_t val; } hp_system_external_device_encrypt_decrypt_control_reg_t; -/** Type of sram_usage_conf register +/** Type of system_sram_usage_conf register * HP memory usage configuration register */ typedef union { struct { - /** cache_usage : HRO; bitpos: [0]; default: 0; - * reserved - */ - uint32_t cache_usage:1; - uint32_t reserved_1:7; - /** sram_usage : R/W; bitpos: [12:8]; default: 0; + uint32_t reserved_0:8; + /** system_sram_usage : R/W; bitpos: [12:8]; default: 0; * 0: cpu use hp-memory. 1:mac-dump accessing hp-memory. */ - uint32_t sram_usage:5; + uint32_t system_sram_usage:5; uint32_t reserved_13:3; - /** mac_dump_alloc : R/W; bitpos: [16]; default: 0; + /** system_mac_dump_alloc : R/W; bitpos: [16]; default: 0; * Set this bit as 1 to add an offset (64KB) when mac-dump accessing hp-memory. */ - uint32_t mac_dump_alloc:1; + uint32_t system_mac_dump_alloc:1; uint32_t reserved_17:15; }; uint32_t val; } hp_system_sram_usage_conf_reg_t; -/** Type of sec_dpa_conf register +/** Type of system_sec_dpa_conf register * HP anti-DPA security configuration register */ typedef union { struct { - /** sec_dpa_level : R/W; bitpos: [1:0]; default: 0; + /** system_sec_dpa_level : R/W; bitpos: [1:0]; default: 0; * Configures whether or not to enable anti-DPA attack. Valid only when - * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. \\ - * 0: Disable\\ + * HP_SYSTEM_SEC_DPA_CFG_SEL is 0. + * 0: Disable * 1-3: Enable. The larger the number, the higher the security level, which represents * the ability to resist DPA attacks, with increased computational overhead of the - * hardware crypto-accelerators at the same time. \\ + * hardware crypto-accelerators at the same time. */ - uint32_t sec_dpa_level:2; - /** sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; + uint32_t system_sec_dpa_level:2; + /** system_sec_dpa_cfg_sel : R/W; bitpos: [2]; default: 0; * Configures whether to select HP_SYSTEM_SEC_DPA_LEVEL or EFUSE_SEC_DPA_LEVEL (from - * eFuse) to control DPA level. \\ - * 0: Select EFUSE_SEC_DPA_LEVEL\\ - * 1: Select HP_SYSTEM_SEC_DPA_LEVEL\\ + * eFuse) to control DPA level. + * 0: Select EFUSE_SEC_DPA_LEVEL + * 1: Select HP_SYSTEM_SEC_DPA_LEVEL */ - uint32_t sec_dpa_cfg_sel:1; + uint32_t system_sec_dpa_cfg_sel:1; uint32_t reserved_3:29; }; uint32_t val; } hp_system_sec_dpa_conf_reg_t; -/** Type of rom_table_lock register +/** Type of system_rom_table_lock register * ROM-Table lock register */ typedef union { struct { - /** rom_table_lock : R/W; bitpos: [0]; default: 0; - * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. \\ - * 0: Unlock \\ - * 1: Lock \\ + /** system_rom_table_lock : R/W; bitpos: [0]; default: 0; + * Configures whether or not to lock the value contained in HP_SYSTEM_ROM_TABLE. + * 0: Unlock + * 1: Lock */ - uint32_t rom_table_lock:1; + uint32_t system_rom_table_lock:1; uint32_t reserved_1:31; }; uint32_t val; } hp_system_rom_table_lock_reg_t; -/** Type of rom_table register +/** Type of system_rom_table register * ROM-Table register */ typedef union { struct { - /** rom_table : R/W; bitpos: [31:0]; default: 0; + /** system_rom_table : R/W; bitpos: [31:0]; default: 0; * Software ROM-Table register, whose content can be modified only when * HP_SYSTEM_ROM_TABLE_LOCK is 0. */ - uint32_t rom_table:32; + uint32_t system_rom_table:32; }; uint32_t val; } hp_system_rom_table_reg_t; -/** Type of core_debug_runstall_conf register +/** Type of system_core_debug_runstall_conf register * Core Debug RunStall configurion register */ typedef union { struct { uint32_t reserved_0:1; - /** core_runstalled : RO; bitpos: [1]; default: 0; + /** system_core_runstalled : RO; bitpos: [1]; default: 0; * Software can read this field to get the runstall status of hp-core. 1: stalled, 0: * not stalled. */ - uint32_t core_runstalled:1; + uint32_t system_core_runstalled:1; uint32_t reserved_2:30; }; uint32_t val; } hp_system_core_debug_runstall_conf_reg_t; -/** Type of sprom_ctrl register +/** Type of system_sprom_ctrl register * reserved */ typedef union { struct { - /** sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; + /** system_sprom_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 112; * reserved */ - uint32_t sprom_mem_aux_ctrl:32; + uint32_t system_sprom_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprom_ctrl_reg_t; -/** Type of spram_ctrl register +/** Type of system_spram_ctrl register * reserved */ typedef union { struct { - /** spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + /** system_spram_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * reserved */ - uint32_t spram_mem_aux_ctrl:32; + uint32_t system_spram_mem_aux_ctrl:32; }; uint32_t val; } hp_system_spram_ctrl_reg_t; -/** Type of sprf_ctrl register +/** Type of system_sprf_ctrl register * reserved */ typedef union { struct { - /** sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; + /** system_sprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 8304; * reserved */ - uint32_t sprf_mem_aux_ctrl:32; + uint32_t system_sprf_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sprf_ctrl_reg_t; -/** Type of sdprf_ctrl register +/** Type of system_sdprf_ctrl register * reserved */ typedef union { struct { - /** sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; + /** system_sdprf_mem_aux_ctrl : R/W; bitpos: [31:0]; default: 0; * reserved */ - uint32_t sdprf_mem_aux_ctrl:32; + uint32_t system_sdprf_mem_aux_ctrl:32; }; uint32_t val; } hp_system_sdprf_ctrl_reg_t; -/** Type of clock_gate register - * HP-SYSTEM clock gating configure register +/** Type of system_axi_mst_pri register + * AXI mst priority configuration register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. + /** system_dma_priority : R/W; bitpos: [0]; default: 0; + * AHB-DMA arbitration priority for command channels between masters connected to + * ext_mem_DW_axi */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t system_dma_priority:1; + /** system_cache_priority : R/W; bitpos: [1]; default: 0; + * CACHE arbitration priority for command channels between masters connected to + * ext_mem_DW_axi + */ + uint32_t system_cache_priority:1; + uint32_t reserved_2:30; }; uint32_t val; -} hp_system_clock_gate_reg_t; +} hp_system_axi_mst_pri_reg_t; + +/** Type of system_sdio_ctrl register + * SDIO Control configuration register + */ +typedef union { + struct { + /** system_dis_sdio_prob : R/W; bitpos: [0]; default: 1; + * Set this bit as 1 to disable SDIO_PROB function. disable by default. + */ + uint32_t system_dis_sdio_prob:1; + /** system_sdio_win_access_en : R/W; bitpos: [1]; default: 1; + * Enable sdio slave to access other peripherals on the chip + */ + uint32_t system_sdio_win_access_en:1; + uint32_t reserved_2:30; + }; + uint32_t val; +} hp_system_sdio_ctrl_reg_t; /** Group: Timeout Register */ -/** Type of cpu_peri_timeout_conf register +/** Type of system_cpu_peri_timeout_conf register * CPU_PERI_TIMEOUT configuration register */ typedef union { struct { - /** cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** system_cpu_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing CPU peripheral * register in the number of clock cycles of the clock domain. */ - uint32_t cpu_peri_timeout_thres:16; - /** cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + uint32_t system_cpu_peri_timeout_thres:16; + /** system_cpu_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; * Write 1 to clear timeout interrupt. */ - uint32_t cpu_peri_timeout_int_clear:1; - /** cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t system_cpu_peri_timeout_int_clear:1; + /** system_cpu_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing CPU peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ - uint32_t cpu_peri_timeout_protect_en:1; + uint32_t system_cpu_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_cpu_peri_timeout_conf_reg_t; -/** Type of cpu_peri_timeout_addr register +/** Type of system_cpu_peri_timeout_addr register * CPU_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** system_cpu_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t cpu_peri_timeout_addr:32; + uint32_t system_cpu_peri_timeout_addr:32; }; uint32_t val; } hp_system_cpu_peri_timeout_addr_reg_t; -/** Type of cpu_peri_timeout_uid register +/** Type of system_cpu_peri_timeout_uid register * CPU_PERI_TIMEOUT_UID register */ typedef union { struct { - /** cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** system_cpu_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t cpu_peri_timeout_uid:7; + uint32_t system_cpu_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; } hp_system_cpu_peri_timeout_uid_reg_t; -/** Type of hp_peri_timeout_conf register +/** Type of system_hp_peri_timeout_conf register * HP_PERI_TIMEOUT configuration register */ typedef union { struct { - /** hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; + /** system_hp_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; * Configures the timeout threshold for bus access for accessing HP peripheral * register, corresponding to the number of clock cycles of the clock domain. */ - uint32_t hp_peri_timeout_thres:16; - /** hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear timeout interrupt.\\ - * 0: No effect\\ - * 1: Clear timeout interrupt\\ + uint32_t system_hp_peri_timeout_thres:16; + /** system_hp_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear timeout interrupt. + * 0: No effect + * 1: Clear timeout interrupt */ - uint32_t hp_peri_timeout_int_clear:1; - /** hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; + uint32_t system_hp_peri_timeout_int_clear:1; + /** system_hp_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; * Configures whether or not to enable timeout protection for accessing HP peripheral - * registers.\\ - * 0: Disable\\ - * 1: Enable\\ + * registers. + * 0: Disable + * 1: Enable */ - uint32_t hp_peri_timeout_protect_en:1; + uint32_t system_hp_peri_timeout_protect_en:1; uint32_t reserved_18:14; }; uint32_t val; } hp_system_hp_peri_timeout_conf_reg_t; -/** Type of hp_peri_timeout_addr register +/** Type of system_hp_peri_timeout_addr register * HP_PERI_TIMEOUT_ADDR register */ typedef union { struct { - /** hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; + /** system_hp_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; * Represents the address information of abnormal access. */ - uint32_t hp_peri_timeout_addr:32; + uint32_t system_hp_peri_timeout_addr:32; }; uint32_t val; } hp_system_hp_peri_timeout_addr_reg_t; -/** Type of hp_peri_timeout_uid register +/** Type of system_hp_peri_timeout_uid register * HP_PERI_TIMEOUT_UID register */ typedef union { struct { - /** hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; + /** system_hp_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; * Represents the master id[4:0] and master permission[6:5] when trigger timeout. This * register will be cleared after the interrupt is cleared. */ - uint32_t hp_peri_timeout_uid:7; + uint32_t system_hp_peri_timeout_uid:7; uint32_t reserved_7:25; }; uint32_t val; } hp_system_hp_peri_timeout_uid_reg_t; -/** Type of modem_peri_timeout_conf register - * MODEM_PERI_TIMEOUT configuration register - */ -typedef union { - struct { - /** modem_peri_timeout_thres : R/W; bitpos: [15:0]; default: 65535; - * Set the timeout threshold for bus access, corresponding to the number of clock - * cycles of the clock domain. - */ - uint32_t modem_peri_timeout_thres:16; - /** modem_peri_timeout_int_clear : WT; bitpos: [16]; default: 0; - * Set this bit as 1 to clear timeout interrupt - */ - uint32_t modem_peri_timeout_int_clear:1; - /** modem_peri_timeout_protect_en : R/W; bitpos: [17]; default: 1; - * Set this bit as 1 to enable timeout protection for accessing modem registers - */ - uint32_t modem_peri_timeout_protect_en:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} hp_system_modem_peri_timeout_conf_reg_t; - -/** Type of modem_peri_timeout_addr register - * MODEM_PERI_TIMEOUT_ADDR register - */ -typedef union { - struct { - /** modem_peri_timeout_addr : RO; bitpos: [31:0]; default: 0; - * Record the address information of abnormal access - */ - uint32_t modem_peri_timeout_addr:32; - }; - uint32_t val; -} hp_system_modem_peri_timeout_addr_reg_t; - -/** Type of modem_peri_timeout_uid register - * MODEM_PERI_TIMEOUT_UID register - */ -typedef union { - struct { - /** modem_peri_timeout_uid : RO; bitpos: [6:0]; default: 0; - * Record master id[4:0] & master permission[6:5] when trigger timeout. This register - * will be cleared after the interrupt is cleared. - */ - uint32_t modem_peri_timeout_uid:7; - uint32_t reserved_7:25; - }; - uint32_t val; -} hp_system_modem_peri_timeout_uid_reg_t; - - -/** Group: Redcy ECO Registers */ -/** Type of rnd_eco register - * redcy eco register. - */ -typedef union { - struct { - /** redcy_ena : W/R; bitpos: [0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_ena:1; - /** redcy_result : RO; bitpos: [1]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_result:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} hp_system_rnd_eco_reg_t; - -/** Type of rnd_eco_low register - * redcy eco low register. - */ -typedef union { - struct { - /** redcy_low : W/R; bitpos: [31:0]; default: 0; - * Only reserved for ECO. - */ - uint32_t redcy_low:32; - }; - uint32_t val; -} hp_system_rnd_eco_low_reg_t; - -/** Type of rnd_eco_high register - * redcy eco high register. - */ -typedef union { - struct { - /** redcy_high : W/R; bitpos: [31:0]; default: 4294967295; - * Only reserved for ECO. - */ - uint32_t redcy_high:32; - }; - uint32_t val; -} hp_system_rnd_eco_high_reg_t; - - -/** Group: Debug Register */ -/** Type of debug register - * HP-SYSTEM debug register - */ -typedef union { - struct { - /** fpga_debug : R/W; bitpos: [0]; default: 1; - * Reserved - */ - uint32_t fpga_debug:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} hp_system_debug_reg_t; - /** Group: Version Register */ -/** Type of date register +/** Type of system_date register * Date control and version control register */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36769824; + /** system_date : R/W; bitpos: [27:0]; default: 37823088; * Version control register. */ - uint32_t date:28; + uint32_t system_date:28; uint32_t reserved_28:4; }; uint32_t val; @@ -450,32 +356,28 @@ typedef union { typedef struct { - volatile hp_system_external_device_encrypt_decrypt_control_reg_t external_device_encrypt_decrypt_control; - volatile hp_system_sram_usage_conf_reg_t sram_usage_conf; - volatile hp_system_sec_dpa_conf_reg_t sec_dpa_conf; - volatile hp_system_cpu_peri_timeout_conf_reg_t cpu_peri_timeout_conf; - volatile hp_system_cpu_peri_timeout_addr_reg_t cpu_peri_timeout_addr; - volatile hp_system_cpu_peri_timeout_uid_reg_t cpu_peri_timeout_uid; - volatile hp_system_hp_peri_timeout_conf_reg_t hp_peri_timeout_conf; - volatile hp_system_hp_peri_timeout_addr_reg_t hp_peri_timeout_addr; - volatile hp_system_hp_peri_timeout_uid_reg_t hp_peri_timeout_uid; - volatile hp_system_modem_peri_timeout_conf_reg_t modem_peri_timeout_conf; - volatile hp_system_modem_peri_timeout_addr_reg_t modem_peri_timeout_addr; - volatile hp_system_modem_peri_timeout_uid_reg_t modem_peri_timeout_uid; - volatile hp_system_rom_table_lock_reg_t rom_table_lock; - volatile hp_system_rom_table_reg_t rom_table; - volatile hp_system_core_debug_runstall_conf_reg_t core_debug_runstall_conf; - volatile hp_system_sprom_ctrl_reg_t sprom_ctrl; - volatile hp_system_spram_ctrl_reg_t spram_ctrl; - volatile hp_system_sprf_ctrl_reg_t sprf_ctrl; - volatile hp_system_sdprf_ctrl_reg_t sdprf_ctrl; - volatile hp_system_rnd_eco_reg_t rnd_eco; - volatile hp_system_rnd_eco_low_reg_t rnd_eco_low; - volatile hp_system_rnd_eco_high_reg_t rnd_eco_high; - volatile hp_system_debug_reg_t debug; - volatile hp_system_clock_gate_reg_t clock_gate; - uint32_t reserved_060[231]; - volatile hp_system_date_reg_t date; + volatile hp_system_external_device_encrypt_decrypt_control_reg_t system_external_device_encrypt_decrypt_control; + volatile hp_system_sram_usage_conf_reg_t system_sram_usage_conf; + volatile hp_system_sec_dpa_conf_reg_t system_sec_dpa_conf; + volatile hp_system_cpu_peri_timeout_conf_reg_t system_cpu_peri_timeout_conf; + volatile hp_system_cpu_peri_timeout_addr_reg_t system_cpu_peri_timeout_addr; + volatile hp_system_cpu_peri_timeout_uid_reg_t system_cpu_peri_timeout_uid; + volatile hp_system_hp_peri_timeout_conf_reg_t system_hp_peri_timeout_conf; + volatile hp_system_hp_peri_timeout_addr_reg_t system_hp_peri_timeout_addr; + volatile hp_system_hp_peri_timeout_uid_reg_t system_hp_peri_timeout_uid; + uint32_t reserved_024[3]; + volatile hp_system_rom_table_lock_reg_t system_rom_table_lock; + volatile hp_system_rom_table_reg_t system_rom_table; + volatile hp_system_core_debug_runstall_conf_reg_t system_core_debug_runstall_conf; + volatile hp_system_sprom_ctrl_reg_t system_sprom_ctrl; + volatile hp_system_spram_ctrl_reg_t system_spram_ctrl; + volatile hp_system_sprf_ctrl_reg_t system_sprf_ctrl; + volatile hp_system_sdprf_ctrl_reg_t system_sdprf_ctrl; + uint32_t reserved_04c[5]; + volatile hp_system_axi_mst_pri_reg_t system_axi_mst_pri; + volatile hp_system_sdio_ctrl_reg_t system_sdio_ctrl; + uint32_t reserved_068[229]; + volatile hp_system_date_reg_t system_date; } hp_system_dev_t; extern hp_system_dev_t HP_SYSTEM; diff --git a/components/soc/esp32c61/register/soc/i2c_reg.h b/components/soc/esp32c61/register/soc/i2c_reg.h index 07e1c4309d..cd4228ee9b 100644 --- a/components/soc/esp32c61/register/soc/i2c_reg.h +++ b/components/soc/esp32c61/register/soc/i2c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -17,8 +17,8 @@ extern "C" { */ #define I2C_SCL_LOW_PERIOD_REG (DR_REG_I2C_BASE + 0x0) /** I2C_SCL_LOW_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock in master mode. \\ - * Measurement unit: i2c_sclk \\ + * Configures the low level width of the SCL Clock in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_LOW_PERIOD 0x000001FFU #define I2C_SCL_LOW_PERIOD_M (I2C_SCL_LOW_PERIOD_V << I2C_SCL_LOW_PERIOD_S) @@ -30,27 +30,27 @@ extern "C" { */ #define I2C_CTR_REG (DR_REG_I2C_BASE + 0x4) /** I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SDA_FORCE_OUT (BIT(0)) #define I2C_SDA_FORCE_OUT_M (I2C_SDA_FORCE_OUT_V << I2C_SDA_FORCE_OUT_S) #define I2C_SDA_FORCE_OUT_V 0x00000001U #define I2C_SDA_FORCE_OUT_S 0 /** I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ #define I2C_SCL_FORCE_OUT (BIT(1)) #define I2C_SCL_FORCE_OUT_M (I2C_SCL_FORCE_OUT_V << I2C_SCL_FORCE_OUT_S) #define I2C_SCL_FORCE_OUT_V 0x00000001U #define I2C_SCL_FORCE_OUT_S 1 /** I2C_SAMPLE_SCL_LEVEL : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA.\\ - * 0: Sample SDA data on the SCL high level \\ - * 1: Sample SDA data on the SCL low level \\ + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ #define I2C_SAMPLE_SCL_LEVEL (BIT(2)) #define I2C_SAMPLE_SCL_LEVEL_M (I2C_SAMPLE_SCL_LEVEL_V << I2C_SAMPLE_SCL_LEVEL_S) @@ -58,24 +58,24 @@ extern "C" { #define I2C_SAMPLE_SCL_LEVEL_S 2 /** I2C_RX_FULL_ACK_LEVEL : R/W; bitpos: [3]; default: 1; * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold.\\ + * reached the threshold. */ #define I2C_RX_FULL_ACK_LEVEL (BIT(3)) #define I2C_RX_FULL_ACK_LEVEL_M (I2C_RX_FULL_ACK_LEVEL_V << I2C_RX_FULL_ACK_LEVEL_S) #define I2C_RX_FULL_ACK_LEVEL_V 0x00000001U #define I2C_RX_FULL_ACK_LEVEL_S 3 /** I2C_MS_MODE : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave.\\ - * 0: Slave \\ - * 1: Master \\ + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ #define I2C_MS_MODE (BIT(4)) #define I2C_MS_MODE_M (I2C_MS_MODE_V << I2C_MS_MODE_S) #define I2C_MS_MODE_V 0x00000001U #define I2C_MS_MODE_S 4 /** I2C_TRANS_START : WT; bitpos: [5]; default: 0; - * Configures whether the slave starts sending the data in txfifo.\\ - * 0: No effect \\ + * Configures whether the slave starts sending the data in txfifo. + * 0: No effect * 1: Start */ #define I2C_TRANS_START (BIT(5)) @@ -83,44 +83,44 @@ extern "C" { #define I2C_TRANS_START_V 0x00000001U #define I2C_TRANS_START_S 5 /** I2C_TX_LSB_FIRST : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent.\\ - * 0: send data from the most significant bit \\ - * 1: send data from the least significant bit \\ + * Configures to control the sending order for data needing to be sent. + * 0: send data from the most significant bit + * 1: send data from the least significant bit */ #define I2C_TX_LSB_FIRST (BIT(6)) #define I2C_TX_LSB_FIRST_M (I2C_TX_LSB_FIRST_V << I2C_TX_LSB_FIRST_S) #define I2C_TX_LSB_FIRST_V 0x00000001U #define I2C_TX_LSB_FIRST_S 6 /** I2C_RX_LSB_FIRST : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data.\\ - * 0: receive data from the most significant bit \\ - * 1: receive data from the least significant bit \\ + * Configures to control the storage order for received data. + * 0: receive data from the most significant bit + * 1: receive data from the least significant bit */ #define I2C_RX_LSB_FIRST (BIT(7)) #define I2C_RX_LSB_FIRST_M (I2C_RX_LSB_FIRST_V << I2C_RX_LSB_FIRST_S) #define I2C_RX_LSB_FIRST_V 0x00000001U #define I2C_RX_LSB_FIRST_S 7 /** I2C_CLK_EN : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers.\\ - * 0: Support clock only when registers are read or written to by software \\ - * 1: Force clock on for registers \\ + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ #define I2C_CLK_EN (BIT(8)) #define I2C_CLK_EN_M (I2C_CLK_EN_V << I2C_CLK_EN_S) #define I2C_CLK_EN_V 0x00000001U #define I2C_CLK_EN_S 8 /** I2C_ARBITRATION_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ #define I2C_ARBITRATION_EN (BIT(9)) #define I2C_ARBITRATION_EN_M (I2C_ARBITRATION_EN_V << I2C_ARBITRATION_EN_S) #define I2C_ARBITRATION_EN_V 0x00000001U #define I2C_ARBITRATION_EN_S 9 /** I2C_FSM_RST : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM.\\ - * 0: No effect \\ + * Configures to reset the SCL_FSM. + * 0: No effect * 1: Reset */ #define I2C_FSM_RST (BIT(10)) @@ -128,8 +128,8 @@ extern "C" { #define I2C_FSM_RST_V 0x00000001U #define I2C_FSM_RST_S 10 /** I2C_CONF_UPGATE : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization.\\ - * 0: No effect \\ + * Configures this bit for synchronization. + * 0: No effect * 1: Synchronize */ #define I2C_CONF_UPGATE (BIT(11)) @@ -137,17 +137,17 @@ extern "C" { #define I2C_CONF_UPGATE_V 0x00000001U #define I2C_CONF_UPGATE_S 11 /** I2C_SLV_TX_AUTO_START_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically\\ - * 0: Disable\\ - * 1: Enable \\ + * Configures to enable slave to send data automatically + * 0: Disable + * 1: Enable */ #define I2C_SLV_TX_AUTO_START_EN (BIT(12)) #define I2C_SLV_TX_AUTO_START_EN_M (I2C_SLV_TX_AUTO_START_EN_V << I2C_SLV_TX_AUTO_START_EN_S) #define I2C_SLV_TX_AUTO_START_EN_V 0x00000001U #define I2C_SLV_TX_AUTO_START_EN_S 12 /** I2C_ADDR_10BIT_RW_CHECK_EN : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ - * 0: Not check\\ + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check * 1: Check */ #define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) @@ -155,9 +155,9 @@ extern "C" { #define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x00000001U #define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 /** I2C_ADDR_BROADCASTING_EN : R/W; bitpos: [14]; default: 0; - * Configures to support the 7 bit general call function.\\ - * 0: Not support \\ - * 1: Support \\ + * Configures to support the 7 bit general call function. + * 0: Not support + * 1: Support */ #define I2C_ADDR_BROADCASTING_EN (BIT(14)) #define I2C_ADDR_BROADCASTING_EN_M (I2C_ADDR_BROADCASTING_EN_V << I2C_ADDR_BROADCASTING_EN_S) @@ -169,8 +169,8 @@ extern "C" { */ #define I2C_SR_REG (DR_REG_I2C_BASE + 0x8) /** I2C_RESP_REC : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode.\\ - * 0: ACK\\ + * Represents the received ACK value in master mode or slave mode. + * 0: ACK * 1: NACK. */ #define I2C_RESP_REC (BIT(0)) @@ -178,8 +178,8 @@ extern "C" { #define I2C_RESP_REC_V 0x00000001U #define I2C_RESP_REC_S 0 /** I2C_SLAVE_RW : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode.\\ - * 1: Master reads from slave\\ + * Represents the transfer direction in slave mode. + * 1: Master reads from slave * 0: Master writes to slave. */ #define I2C_SLAVE_RW (BIT(1)) @@ -187,18 +187,18 @@ extern "C" { #define I2C_SLAVE_RW_V 0x00000001U #define I2C_SLAVE_RW_S 1 /** I2C_ARB_LOST : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line.\\ - * 0: No arbitration lost\\ - * 1: Arbitration lost\\ + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ #define I2C_ARB_LOST (BIT(3)) #define I2C_ARB_LOST_M (I2C_ARB_LOST_V << I2C_ARB_LOST_S) #define I2C_ARB_LOST_V 0x00000001U #define I2C_ARB_LOST_S 3 /** I2C_BUS_BUSY : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state.\\ - * 1: The I2C bus is busy transferring data\\ - * 0: The I2C bus is in idle state.\\ + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data + * 0: The I2C bus is in idle state. */ #define I2C_BUS_BUSY (BIT(4)) #define I2C_BUS_BUSY_M (I2C_BUS_BUSY_V << I2C_BUS_BUSY_S) @@ -206,10 +206,10 @@ extern "C" { #define I2C_BUS_BUSY_S 4 /** I2C_SLAVE_ADDRESSED : RO; bitpos: [5]; default: 0; * Represents whether the address sent by the master is equal to the address of the - * slave.\\ - * Valid only when the module is configured as an I2C Slave.\\ - * 0: Not equal\\ - * 1: Equal\\ + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ #define I2C_SLAVE_ADDRESSED (BIT(5)) #define I2C_SLAVE_ADDRESSED_M (I2C_SLAVE_ADDRESSED_V << I2C_SLAVE_ADDRESSED_S) @@ -223,9 +223,9 @@ extern "C" { #define I2C_RXFIFO_CNT_V 0x0000003FU #define I2C_RXFIFO_CNT_S 8 /** I2C_STRETCH_CAUSE : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode.\\ - * 0: Stretching SCL low when the master starts to read data.\\ - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. */ #define I2C_STRETCH_CAUSE 0x00000003U @@ -240,13 +240,13 @@ extern "C" { #define I2C_TXFIFO_CNT_V 0x0000003FU #define I2C_TXFIFO_CNT_S 18 /** I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine.\\ - * 0: Idle\\ - * 1: Address shift\\ - * 2: ACK address\\ - * 3: Rx data\\ - * 4: Tx data\\ - * 5: Send ACK\\ + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK * 6: Wait ACK */ #define I2C_SCL_MAIN_STATE_LAST 0x00000007U @@ -254,13 +254,13 @@ extern "C" { #define I2C_SCL_MAIN_STATE_LAST_V 0x00000007U #define I2C_SCL_MAIN_STATE_LAST_S 24 /** I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL.\\ - * 0: Idle\\ - * 1: Start\\ - * 2: Negative edge\\ - * 3: Low\\ - * 4: Positive edge\\ - * 5: High\\ + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High * 6: Stop */ #define I2C_SCL_STATE_LAST 0x00000007U @@ -274,17 +274,17 @@ extern "C" { #define I2C_TO_REG (DR_REG_I2C_BASE + 0xc) /** I2C_TIME_OUT_VALUE : R/W; bitpos: [4:0]; default: 16; * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2\^{}(reg_time_out_value).\\ - * Measurement unit: i2c_sclk \\ + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: i2c_sclk */ #define I2C_TIME_OUT_VALUE 0x0000001FU #define I2C_TIME_OUT_VALUE_M (I2C_TIME_OUT_VALUE_V << I2C_TIME_OUT_VALUE_S) #define I2C_TIME_OUT_VALUE_V 0x0000001FU #define I2C_TIME_OUT_VALUE_S 0 /** I2C_TIME_OUT_EN : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable time out control. + * 0: No effect + * 1: Enable */ #define I2C_TIME_OUT_EN (BIT(5)) #define I2C_TIME_OUT_EN_M (I2C_TIME_OUT_EN_V << I2C_TIME_OUT_EN_S) @@ -296,16 +296,16 @@ extern "C" { */ #define I2C_SLAVE_ADDR_REG (DR_REG_I2C_BASE + 0x10) /** I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave.\\ + * Configure the slave address of I2C Slave. */ #define I2C_SLAVE_ADDR 0x00007FFFU #define I2C_SLAVE_ADDR_M (I2C_SLAVE_ADDR_V << I2C_SLAVE_ADDR_S) #define I2C_SLAVE_ADDR_V 0x00007FFFU #define I2C_SLAVE_ADDR_S 0 /** I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * 1: Enable */ #define I2C_ADDR_10BIT_EN (BIT(31)) #define I2C_ADDR_10BIT_EN_M (I2C_ADDR_10BIT_EN_V << I2C_ADDR_10BIT_EN_S) @@ -387,17 +387,17 @@ extern "C" { /** I2C_FIFO_ADDR_CFG_EN : R/W; bitpos: [11]; default: 0; * Configures the slave to enable dual address mode. When this mode is enabled, the * byte received after the I2C address byte represents the offset address in the I2C - * Slave RAM. \\ - * 0: Disable\\ - * 1: Enable \\ + * Slave RAM. + * 0: Disable + * 1: Enable */ #define I2C_FIFO_ADDR_CFG_EN (BIT(11)) #define I2C_FIFO_ADDR_CFG_EN_M (I2C_FIFO_ADDR_CFG_EN_V << I2C_FIFO_ADDR_CFG_EN_S) #define I2C_FIFO_ADDR_CFG_EN_V 0x00000001U #define I2C_FIFO_ADDR_CFG_EN_S 11 /** I2C_RX_FIFO_RST : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO.\\ - * 0: No effect \\ + * Configures to reset RXFIFO. + * 0: No effect * 1: Reset */ #define I2C_RX_FIFO_RST (BIT(12)) @@ -405,8 +405,8 @@ extern "C" { #define I2C_RX_FIFO_RST_V 0x00000001U #define I2C_RX_FIFO_RST_S 12 /** I2C_TX_FIFO_RST : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO.\\ - * 0: No effect \\ + * Configures to reset TXFIFO. + * 0: No effect * 1: Reset */ #define I2C_TX_FIFO_RST (BIT(13)) @@ -415,9 +415,9 @@ extern "C" { #define I2C_TX_FIFO_RST_S 13 /** I2C_FIFO_PRT_EN : R/W; bitpos: [14]; default: 1; * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ - * 0: No effect \\ - * 1: Enable \\ + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * 1: Enable */ #define I2C_FIFO_PRT_EN (BIT(14)) #define I2C_FIFO_PRT_EN_M (I2C_FIFO_PRT_EN_V << I2C_FIFO_PRT_EN_S) @@ -993,8 +993,8 @@ extern "C" { */ #define I2C_SDA_HOLD_REG (DR_REG_I2C_BASE + 0x30) /** I2C_SDA_HOLD_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk */ #define I2C_SDA_HOLD_TIME 0x000001FFU #define I2C_SDA_HOLD_TIME_M (I2C_SDA_HOLD_TIME_V << I2C_SDA_HOLD_TIME_S) @@ -1006,8 +1006,8 @@ extern "C" { */ #define I2C_SDA_SAMPLE_REG (DR_REG_I2C_BASE + 0x34) /** I2C_SDA_SAMPLE_TIME : R/W; bitpos: [8:0]; default: 0; - * Configures the time for sampling SDA.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time for sampling SDA. + * Measurement unit: i2c_sclk */ #define I2C_SDA_SAMPLE_TIME 0x000001FFU #define I2C_SDA_SAMPLE_TIME_M (I2C_SDA_SAMPLE_TIME_V << I2C_SDA_SAMPLE_TIME_S) @@ -1019,16 +1019,16 @@ extern "C" { */ #define I2C_SCL_HIGH_PERIOD_REG (DR_REG_I2C_BASE + 0x38) /** I2C_SCL_HIGH_PERIOD : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_HIGH_PERIOD 0x000001FFU #define I2C_SCL_HIGH_PERIOD_M (I2C_SCL_HIGH_PERIOD_V << I2C_SCL_HIGH_PERIOD_S) #define I2C_SCL_HIGH_PERIOD_V 0x000001FFU #define I2C_SCL_HIGH_PERIOD_S 0 /** I2C_SCL_WAIT_HIGH_PERIOD : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk */ #define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007FU #define I2C_SCL_WAIT_HIGH_PERIOD_M (I2C_SCL_WAIT_HIGH_PERIOD_V << I2C_SCL_WAIT_HIGH_PERIOD_S) @@ -1041,8 +1041,8 @@ extern "C" { #define I2C_SCL_START_HOLD_REG (DR_REG_I2C_BASE + 0x40) /** I2C_SCL_START_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition.\\ - * Measurement unit: i2c_sclk \\ + * a START condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_START_HOLD_TIME 0x000001FFU #define I2C_SCL_START_HOLD_TIME_M (I2C_SCL_START_HOLD_TIME_V << I2C_SCL_START_HOLD_TIME_S) @@ -1056,8 +1056,8 @@ extern "C" { #define I2C_SCL_RSTART_SETUP_REG (DR_REG_I2C_BASE + 0x44) /** I2C_SCL_RSTART_SETUP_TIME : R/W; bitpos: [8:0]; default: 8; * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition.\\ - * Measurement unit: i2c_sclk \\ + * for a RESTART condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_RSTART_SETUP_TIME 0x000001FFU #define I2C_SCL_RSTART_SETUP_TIME_M (I2C_SCL_RSTART_SETUP_TIME_V << I2C_SCL_RSTART_SETUP_TIME_S) @@ -1070,8 +1070,8 @@ extern "C" { */ #define I2C_SCL_STOP_HOLD_REG (DR_REG_I2C_BASE + 0x48) /** I2C_SCL_STOP_HOLD_TIME : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition.\\ - * Measurement unit: i2c_sclk \\ + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk */ #define I2C_SCL_STOP_HOLD_TIME 0x000001FFU #define I2C_SCL_STOP_HOLD_TIME_M (I2C_SCL_STOP_HOLD_TIME_V << I2C_SCL_STOP_HOLD_TIME_S) @@ -1100,7 +1100,7 @@ extern "C" { * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ #define I2C_SCL_FILTER_THRES 0x0000000FU #define I2C_SCL_FILTER_THRES_M (I2C_SCL_FILTER_THRES_V << I2C_SCL_FILTER_THRES_S) @@ -1110,97 +1110,57 @@ extern "C" { * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ #define I2C_SDA_FILTER_THRES 0x0000000FU #define I2C_SDA_FILTER_THRES_M (I2C_SDA_FILTER_THRES_V << I2C_SDA_FILTER_THRES_S) #define I2C_SDA_FILTER_THRES_V 0x0000000FU #define I2C_SDA_FILTER_THRES_S 4 /** I2C_SCL_FILTER_EN : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ #define I2C_SCL_FILTER_EN (BIT(8)) #define I2C_SCL_FILTER_EN_M (I2C_SCL_FILTER_EN_V << I2C_SCL_FILTER_EN_S) #define I2C_SCL_FILTER_EN_V 0x00000001U #define I2C_SCL_FILTER_EN_S 8 /** I2C_SDA_FILTER_EN : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ #define I2C_SDA_FILTER_EN (BIT(9)) #define I2C_SDA_FILTER_EN_M (I2C_SDA_FILTER_EN_V << I2C_SDA_FILTER_EN_S) #define I2C_SDA_FILTER_EN_V 0x00000001U #define I2C_SDA_FILTER_EN_S 9 -/** I2C_CLK_CONF_REG register - * I2C CLK configuration register - */ -#define I2C_CLK_CONF_REG (DR_REG_I2C_BASE + 0x54) -/** I2C_SCLK_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_NUM 0x000000FFU -#define I2C_SCLK_DIV_NUM_M (I2C_SCLK_DIV_NUM_V << I2C_SCLK_DIV_NUM_S) -#define I2C_SCLK_DIV_NUM_V 0x000000FFU -#define I2C_SCLK_DIV_NUM_S 0 -/** I2C_SCLK_DIV_A : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_A 0x0000003FU -#define I2C_SCLK_DIV_A_M (I2C_SCLK_DIV_A_V << I2C_SCLK_DIV_A_S) -#define I2C_SCLK_DIV_A_V 0x0000003FU -#define I2C_SCLK_DIV_A_S 8 -/** I2C_SCLK_DIV_B : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ -#define I2C_SCLK_DIV_B 0x0000003FU -#define I2C_SCLK_DIV_B_M (I2C_SCLK_DIV_B_V << I2C_SCLK_DIV_B_S) -#define I2C_SCLK_DIV_B_V 0x0000003FU -#define I2C_SCLK_DIV_B_S 14 -/** I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (I2C_SCLK_SEL_V << I2C_SCLK_SEL_S) -#define I2C_SCLK_SEL_V 0x00000001U -#define I2C_SCLK_SEL_S 20 -/** I2C_SCLK_ACTIVE : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (I2C_SCLK_ACTIVE_V << I2C_SCLK_ACTIVE_S) -#define I2C_SCLK_ACTIVE_V 0x00000001U -#define I2C_SCLK_ACTIVE_S 21 - /** I2C_COMD0_REG register * I2C command register 0 */ #define I2C_COMD0_REG (DR_REG_I2C_BASE + 0x58) /** I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. \\ - * It consists of three parts:\\ - * op_code is the command\\ - * 1: WRITE\\ - * 2: STOP\\ - * 3: READ\\ - * 4: END\\ - * 6: RSTART\\ - * Byte_num represents the number of bytes that need to be sent or received.\\ + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 1: WRITE + * 2: STOP + * 3: READ + * 4: END + * 6: RSTART + * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure link for more information. - * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + * structure for more information. + * \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" */ #define I2C_COMMAND0 0x00003FFFU #define I2C_COMMAND0_M (I2C_COMMAND0_V << I2C_COMMAND0_S) #define I2C_COMMAND0_V 0x00003FFFU #define I2C_COMMAND0_S 0 /** I2C_COMMAND0_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND0_DONE (BIT(31)) #define I2C_COMMAND0_DONE_M (I2C_COMMAND0_DONE_V << I2C_COMMAND0_DONE_S) @@ -1212,7 +1172,7 @@ extern "C" { */ #define I2C_COMD1_REG (DR_REG_I2C_BASE + 0x5c) /** I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 0; - * Configures command 1.\\ + * Configures command 1. * See details in I2C_CMD0_REG[13:0]. */ #define I2C_COMMAND1 0x00003FFFU @@ -1220,9 +1180,9 @@ extern "C" { #define I2C_COMMAND1_V 0x00003FFFU #define I2C_COMMAND1_S 0 /** I2C_COMMAND1_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 1 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 1 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND1_DONE (BIT(31)) #define I2C_COMMAND1_DONE_M (I2C_COMMAND1_DONE_V << I2C_COMMAND1_DONE_S) @@ -1241,9 +1201,9 @@ extern "C" { #define I2C_COMMAND2_V 0x00003FFFU #define I2C_COMMAND2_S 0 /** I2C_COMMAND2_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 2 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 2 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND2_DONE (BIT(31)) #define I2C_COMMAND2_DONE_M (I2C_COMMAND2_DONE_V << I2C_COMMAND2_DONE_S) @@ -1262,9 +1222,9 @@ extern "C" { #define I2C_COMMAND3_V 0x00003FFFU #define I2C_COMMAND3_S 0 /** I2C_COMMAND3_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 3 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 3 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND3_DONE (BIT(31)) #define I2C_COMMAND3_DONE_M (I2C_COMMAND3_DONE_V << I2C_COMMAND3_DONE_S) @@ -1283,9 +1243,9 @@ extern "C" { #define I2C_COMMAND4_V 0x00003FFFU #define I2C_COMMAND4_S 0 /** I2C_COMMAND4_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 4 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 4 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND4_DONE (BIT(31)) #define I2C_COMMAND4_DONE_M (I2C_COMMAND4_DONE_V << I2C_COMMAND4_DONE_S) @@ -1304,9 +1264,9 @@ extern "C" { #define I2C_COMMAND5_V 0x00003FFFU #define I2C_COMMAND5_S 0 /** I2C_COMMAND5_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 5 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 5 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND5_DONE (BIT(31)) #define I2C_COMMAND5_DONE_M (I2C_COMMAND5_DONE_V << I2C_COMMAND5_DONE_S) @@ -1325,9 +1285,9 @@ extern "C" { #define I2C_COMMAND6_V 0x00003FFFU #define I2C_COMMAND6_S 0 /** I2C_COMMAND6_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 6 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 6 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND6_DONE (BIT(31)) #define I2C_COMMAND6_DONE_M (I2C_COMMAND6_DONE_V << I2C_COMMAND6_DONE_S) @@ -1346,9 +1306,9 @@ extern "C" { #define I2C_COMMAND7_V 0x00003FFFU #define I2C_COMMAND7_S 0 /** I2C_COMMAND7_DONE : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 7 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + * Represents whether command 7 is done in I2C Master mode. + * 0: Not done + * 1: Done */ #define I2C_COMMAND7_DONE (BIT(31)) #define I2C_COMMAND7_DONE_M (I2C_COMMAND7_DONE_V << I2C_COMMAND7_DONE_S) @@ -1361,8 +1321,8 @@ extern "C" { #define I2C_SCL_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x78) /** I2C_SCL_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23.\\ - * Measurement unit: i2c_sclk \\ + * more than 23. + * Measurement unit: i2c_sclk */ #define I2C_SCL_ST_TO_I2C 0x0000001FU #define I2C_SCL_ST_TO_I2C_M (I2C_SCL_ST_TO_I2C_V << I2C_SCL_ST_TO_I2C_S) @@ -1375,8 +1335,8 @@ extern "C" { #define I2C_SCL_MAIN_ST_TIME_OUT_REG (DR_REG_I2C_BASE + 0x7c) /** I2C_SCL_MAIN_ST_TO_I2C : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be - * no more than 23.\\ - * Measurement unit: i2c_sclk \\ + * no more than 23. + * Measurement unit: i2c_sclk */ #define I2C_SCL_MAIN_ST_TO_I2C 0x0000001FU #define I2C_SCL_MAIN_ST_TO_I2C_M (I2C_SCL_MAIN_ST_TO_I2C_V << I2C_SCL_MAIN_ST_TO_I2C_S) @@ -1396,18 +1356,18 @@ extern "C" { #define I2C_SCL_RST_SLV_EN_V 0x00000001U #define I2C_SCL_RST_SLV_EN_S 0 /** I2C_SCL_RST_SLV_NUM : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. \\ - * Valid when I2C_SCL_RST_SLV_EN is 1.\\ - * Measurement unit: i2c_sclk \\ + * Configure the pulses of SCL generated in I2C master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: i2c_sclk */ #define I2C_SCL_RST_SLV_NUM 0x0000001FU #define I2C_SCL_RST_SLV_NUM_M (I2C_SCL_RST_SLV_NUM_V << I2C_SCL_RST_SLV_NUM_S) #define I2C_SCL_RST_SLV_NUM_V 0x0000001FU #define I2C_SCL_RST_SLV_NUM_S 1 /** I2C_SCL_PD_EN : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SCL_FORCE_OUT is 1. */ #define I2C_SCL_PD_EN (BIT(6)) @@ -1415,9 +1375,9 @@ extern "C" { #define I2C_SCL_PD_EN_V 0x00000001U #define I2C_SCL_PD_EN_S 6 /** I2C_SDA_PD_EN : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SDA_FORCE_OUT is 1. */ #define I2C_SDA_PD_EN (BIT(7)) @@ -1431,8 +1391,8 @@ extern "C" { #define I2C_SCL_STRETCH_CONF_REG (DR_REG_I2C_BASE + 0x84) /** I2C_STRETCH_PROTECT_NUM : R/W; bitpos: [9:0]; default: 0; * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time.\\ - * Measurement unit: i2c_sclk \\ + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk */ #define I2C_STRETCH_PROTECT_NUM 0x000003FFU #define I2C_STRETCH_PROTECT_NUM_M (I2C_STRETCH_PROTECT_NUM_V << I2C_STRETCH_PROTECT_NUM_S) @@ -1441,36 +1401,36 @@ extern "C" { /** I2C_SLAVE_SCL_STRETCH_EN : R/W; bitpos: [10]; default: 0; * Configures to enable slave SCL stretch function. The SCL output line will be * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The - * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ - * 0: Disable \\ - * 1: Enable \\ + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) #define I2C_SLAVE_SCL_STRETCH_EN_M (I2C_SLAVE_SCL_STRETCH_EN_V << I2C_SLAVE_SCL_STRETCH_EN_S) #define I2C_SLAVE_SCL_STRETCH_EN_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_EN_S 10 /** I2C_SLAVE_SCL_STRETCH_CLR : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function.\\ - * 0: No effect \\ - * 1: Clear\\ + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ #define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) #define I2C_SLAVE_SCL_STRETCH_CLR_M (I2C_SLAVE_SCL_STRETCH_CLR_V << I2C_SLAVE_SCL_STRETCH_CLR_S) #define I2C_SLAVE_SCL_STRETCH_CLR_V 0x00000001U #define I2C_SLAVE_SCL_STRETCH_CLR_S 11 /** I2C_SLAVE_BYTE_ACK_CTL_EN : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ #define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) #define I2C_SLAVE_BYTE_ACK_CTL_EN_M (I2C_SLAVE_BYTE_ACK_CTL_EN_V << I2C_SLAVE_BYTE_ACK_CTL_EN_S) #define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x00000001U #define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 /** I2C_SLAVE_BYTE_ACK_LVL : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables.\\ - * 0: Low level\\ - * 1: High level \\ + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ #define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) #define I2C_SLAVE_BYTE_ACK_LVL_M (I2C_SLAVE_BYTE_ACK_LVL_V << I2C_SLAVE_BYTE_ACK_LVL_S) @@ -1481,7 +1441,7 @@ extern "C" { * Version register */ #define I2C_DATE_REG (DR_REG_I2C_BASE + 0xf8) -/** I2C_DATE : R/W; bitpos: [31:0]; default: 37752896; +/** I2C_DATE : R/W; bitpos: [31:0]; default: 37765248; * Version control register. */ #define I2C_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32c61/register/soc/i2c_struct.h b/components/soc/esp32c61/register/soc/i2c_struct.h index 4cb22ab31c..73534f36d9 100644 --- a/components/soc/esp32c61/register/soc/i2c_struct.h +++ b/components/soc/esp32c61/register/soc/i2c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,8 +18,8 @@ extern "C" { typedef union { struct { /** scl_low_period : R/W; bitpos: [8:0]; default: 0; - * Configures the low level width of the SCL Clock in master mode. \\ - * Measurement unit: i2c_sclk \\ + * Configures the low level width of the SCL Clock in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_low_period:9; uint32_t reserved_9:23; @@ -33,8 +33,8 @@ typedef union { typedef union { struct { /** sda_hold_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time to hold the data after the falling edge of SCL.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time to hold the data after the falling edge of SCL. + * Measurement unit: i2c_sclk */ uint32_t sda_hold_time:9; uint32_t reserved_9:23; @@ -48,8 +48,8 @@ typedef union { typedef union { struct { /** sda_sample_time : R/W; bitpos: [8:0]; default: 0; - * Configures the time for sampling SDA.\\ - * Measurement unit: i2c_sclk \\ + * Configures the time for sampling SDA. + * Measurement unit: i2c_sclk */ uint32_t sda_sample_time:9; uint32_t reserved_9:23; @@ -63,13 +63,13 @@ typedef union { typedef union { struct { /** scl_high_period : R/W; bitpos: [8:0]; default: 0; - * Configures for how long SCL remains high in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures for how long SCL remains high in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_high_period:9; /** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0; - * Configures the SCL_FSM's waiting period for SCL high level in master mode.\\ - * Measurement unit: i2c_sclk \\ + * Configures the SCL_FSM's waiting period for SCL high level in master mode. + * Measurement unit: i2c_sclk */ uint32_t scl_wait_high_period:7; uint32_t reserved_16:16; @@ -84,8 +84,8 @@ typedef union { struct { /** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8; * Configures the time between the falling edge of SDA and the falling edge of SCL for - * a START condition.\\ - * Measurement unit: i2c_sclk \\ + * a START condition. + * Measurement unit: i2c_sclk */ uint32_t scl_start_hold_time:9; uint32_t reserved_9:23; @@ -101,8 +101,8 @@ typedef union { struct { /** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8; * Configures the time between the positive edge of SCL and the negative edge of SDA - * for a RESTART condition.\\ - * Measurement unit: i2c_sclk \\ + * for a RESTART condition. + * Measurement unit: i2c_sclk */ uint32_t scl_rstart_setup_time:9; uint32_t reserved_9:23; @@ -117,8 +117,8 @@ typedef union { typedef union { struct { /** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8; - * Configures the delay after the STOP condition.\\ - * Measurement unit: i2c_sclk \\ + * Configures the delay after the STOP condition. + * Measurement unit: i2c_sclk */ uint32_t scl_stop_hold_time:9; uint32_t reserved_9:23; @@ -149,8 +149,8 @@ typedef union { struct { /** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_FSM state unchanged period. It should be no - * more than 23.\\ - * Measurement unit: i2c_sclk \\ + * more than 23. + * Measurement unit: i2c_sclk */ uint32_t scl_st_to_i2c:5; uint32_t reserved_5:27; @@ -165,8 +165,8 @@ typedef union { struct { /** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16; * Configures the threshold value of SCL_MAIN_FSM state unchanged period. It should be - * no more than 23.\\ - * Measurement unit: i2c_sclk \\ + * no more than 23. + * Measurement unit: i2c_sclk */ uint32_t scl_main_st_to_i2c:5; uint32_t reserved_5:27; @@ -182,92 +182,92 @@ typedef union { typedef union { struct { /** sda_force_out : R/W; bitpos: [0]; default: 0; - * Configures the SDA output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SDA output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t sda_force_out:1; /** scl_force_out : R/W; bitpos: [1]; default: 0; - * Configures the SCL output mode.\\ - * 0: Open drain output \\ - * 1: Direct output \\ + * Configures the SCL output mode. + * 0: Open drain output + * 1: Direct output */ uint32_t scl_force_out:1; /** sample_scl_level : R/W; bitpos: [2]; default: 0; - * Configures the sample mode for SDA.\\ - * 0: Sample SDA data on the SCL high level \\ - * 1: Sample SDA data on the SCL low level \\ + * Configures the sample mode for SDA. + * 0: Sample SDA data on the SCL high level + * 1: Sample SDA data on the SCL low level */ uint32_t sample_scl_level:1; /** rx_full_ack_level : R/W; bitpos: [3]; default: 1; * Configures the ACK value that needs to be sent by master when the rx_fifo_cnt has - * reached the threshold.\\ + * reached the threshold. */ uint32_t rx_full_ack_level:1; /** ms_mode : R/W; bitpos: [4]; default: 0; - * Configures the module as an I2C Master or Slave.\\ - * 0: Slave \\ - * 1: Master \\ + * Configures the module as an I2C Master or Slave. + * 0: Slave + * 1: Master */ uint32_t ms_mode:1; /** trans_start : WT; bitpos: [5]; default: 0; - * Configures whether the slave starts sending the data in txfifo.\\ - * 0: No effect \\ + * Configures whether the slave starts sending the data in txfifo. + * 0: No effect * 1: Start */ uint32_t trans_start:1; /** tx_lsb_first : R/W; bitpos: [6]; default: 0; - * Configures to control the sending order for data needing to be sent.\\ - * 0: send data from the most significant bit \\ - * 1: send data from the least significant bit \\ + * Configures to control the sending order for data needing to be sent. + * 0: send data from the most significant bit + * 1: send data from the least significant bit */ uint32_t tx_lsb_first:1; /** rx_lsb_first : R/W; bitpos: [7]; default: 0; - * Configures to control the storage order for received data.\\ - * 0: receive data from the most significant bit \\ - * 1: receive data from the least significant bit \\ + * Configures to control the storage order for received data. + * 0: receive data from the most significant bit + * 1: receive data from the least significant bit */ uint32_t rx_lsb_first:1; /** clk_en : R/W; bitpos: [8]; default: 0; - * Configures whether to gate clock signal for registers.\\ - * 0: Support clock only when registers are read or written to by software \\ - * 1: Force clock on for registers \\ + * Configures whether to gate clock signal for registers. + * 0: Support clock only when registers are read or written to by software + * 1: Force clock on for registers */ uint32_t clk_en:1; /** arbitration_en : R/W; bitpos: [9]; default: 1; - * Configures to enable I2C bus arbitration detection.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable I2C bus arbitration detection. + * 0: No effect + * 1: Enable */ uint32_t arbitration_en:1; /** fsm_rst : WT; bitpos: [10]; default: 0; - * Configures to reset the SCL_FSM.\\ - * 0: No effect \\ + * Configures to reset the SCL_FSM. + * 0: No effect * 1: Reset */ uint32_t fsm_rst:1; /** conf_upgate : WT; bitpos: [11]; default: 0; - * Configures this bit for synchronization.\\ - * 0: No effect \\ + * Configures this bit for synchronization. + * 0: No effect * 1: Synchronize */ uint32_t conf_upgate:1; /** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0; - * Configures to enable slave to send data automatically\\ - * 0: Disable\\ - * 1: Enable \\ + * Configures to enable slave to send data automatically + * 0: Disable + * 1: Enable */ uint32_t slv_tx_auto_start_en:1; /** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0; - * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol.\\ - * 0: Not check\\ + * Configures to check if the r/w bit of 10bit addressing consists with I2C protocol. + * 0: Not check * 1: Check */ uint32_t addr_10bit_rw_check_en:1; /** addr_broadcasting_en : R/W; bitpos: [14]; default: 0; - * Configures to support the 7 bit general call function.\\ - * 0: Not support \\ - * 1: Support \\ + * Configures to support the 7 bit general call function. + * 0: Not support + * 1: Support */ uint32_t addr_broadcasting_en:1; uint32_t reserved_15:17; @@ -282,14 +282,14 @@ typedef union { struct { /** time_out_value : R/W; bitpos: [4:0]; default: 16; * Configures the timeout threshold period for SCL stucking at high or low level. The - * actual period is 2\^{}(reg_time_out_value).\\ - * Measurement unit: i2c_sclk \\ + * actual period is 2\^{}(reg_time_out_value). + * Measurement unit: i2c_sclk */ uint32_t time_out_value:5; /** time_out_en : R/W; bitpos: [5]; default: 0; - * Configures to enable time out control.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable time out control. + * 0: No effect + * 1: Enable */ uint32_t time_out_en:1; uint32_t reserved_6:26; @@ -303,14 +303,14 @@ typedef union { typedef union { struct { /** slave_addr : R/W; bitpos: [14:0]; default: 0; - * Configure the slave address of I2C Slave.\\ + * Configure the slave address of I2C Slave. */ uint32_t slave_addr:15; uint32_t reserved_15:16; /** addr_10bit_en : R/W; bitpos: [31]; default: 0; - * Configures to enable the slave 10-bit addressing mode in master mode.\\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the slave 10-bit addressing mode in master mode. + * 0: No effect + * 1: Enable */ uint32_t addr_10bit_en:1; }; @@ -343,28 +343,28 @@ typedef union { /** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0; * Configures the slave to enable dual address mode. When this mode is enabled, the * byte received after the I2C address byte represents the offset address in the I2C - * Slave RAM. \\ - * 0: Disable\\ - * 1: Enable \\ + * Slave RAM. + * 0: Disable + * 1: Enable */ uint32_t fifo_addr_cfg_en:1; /** rx_fifo_rst : R/W; bitpos: [12]; default: 0; - * Configures to reset RXFIFO.\\ - * 0: No effect \\ + * Configures to reset RXFIFO. + * 0: No effect * 1: Reset */ uint32_t rx_fifo_rst:1; /** tx_fifo_rst : R/W; bitpos: [13]; default: 0; - * Configures to reset TXFIFO.\\ - * 0: No effect \\ + * Configures to reset TXFIFO. + * 0: No effect * 1: Reset */ uint32_t tx_fifo_rst:1; /** fifo_prt_en : R/W; bitpos: [14]; default: 1; * Configures to enable FIFO pointer in non-fifo access mode. This bit controls the - * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts.\\ - * 0: No effect \\ - * 1: Enable \\ + * valid bits and the TX/RX FIFO overflow, underflow, full and empty interrupts. + * 0: No effect + * 1: Enable */ uint32_t fifo_prt_en:1; uint32_t reserved_15:17; @@ -381,26 +381,26 @@ typedef union { * Configures the threshold pulse width to be filtered on SCL. When a pulse on the SCL * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ uint32_t scl_filter_thres:4; /** sda_filter_thres : R/W; bitpos: [7:4]; default: 0; * Configures the threshold pulse width to be filtered on SDA. When a pulse on the SDA * input has smaller width than this register value, the I2C controller will ignore * that pulse. - * Measurement unit: i2c_sclk \\ + * Measurement unit: i2c_sclk */ uint32_t sda_filter_thres:4; /** scl_filter_en : R/W; bitpos: [8]; default: 1; - * Configures to enable the filter function for SCL. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SCL. + * 0: No effect + * 1: Enable */ uint32_t scl_filter_en:1; /** sda_filter_en : R/W; bitpos: [9]; default: 1; - * Configures to enable the filter function for SDA. \\ - * 0: No effect \\ - * 1: Enable \\ + * Configures to enable the filter function for SDA. + * 0: No effect + * 1: Enable */ uint32_t sda_filter_en:1; uint32_t reserved_10:22; @@ -408,36 +408,6 @@ typedef union { uint32_t val; } i2c_filter_cfg_reg_t; -/** Type of clk_conf register - * I2C CLK configuration register - */ -typedef union { - struct { - /** sclk_div_num : R/W; bitpos: [7:0]; default: 0; - * the integral part of the fractional divisor for i2c module - */ - uint32_t sclk_div_num:8; - /** sclk_div_a : R/W; bitpos: [13:8]; default: 0; - * the numerator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_a:6; - /** sclk_div_b : R/W; bitpos: [19:14]; default: 0; - * the denominator of the fractional part of the fractional divisor for i2c module - */ - uint32_t sclk_div_b:6; - /** sclk_sel : R/W; bitpos: [20]; default: 0; - * The clock selection for i2c module:0-XTAL,1-CLK_8MHz. - */ - uint32_t sclk_sel:1; - /** sclk_active : R/W; bitpos: [21]; default: 1; - * The clock switch for i2c module - */ - uint32_t sclk_active:1; - uint32_t reserved_22:10; - }; - uint32_t val; -} i2c_clk_conf_reg_t; - /** Type of scl_sp_conf register * Power configuration register */ @@ -449,22 +419,22 @@ typedef union { */ uint32_t scl_rst_slv_en:1; /** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0; - * Configure the pulses of SCL generated in I2C master mode. \\ - * Valid when I2C_SCL_RST_SLV_EN is 1.\\ - * Measurement unit: i2c_sclk \\ + * Configure the pulses of SCL generated in I2C master mode. + * Valid when I2C_SCL_RST_SLV_EN is 1. + * Measurement unit: i2c_sclk */ uint32_t scl_rst_slv_num:5; /** scl_pd_en : R/W; bitpos: [6]; default: 0; - * Configures to power down the I2C output SCL line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SCL line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SCL_FORCE_OUT is 1. */ uint32_t scl_pd_en:1; /** sda_pd_en : R/W; bitpos: [7]; default: 0; - * Configures to power down the I2C output SDA line. \\ - * 0: Not power down.\\ - * 1: Not work and power down.\\ + * Configures to power down the I2C output SDA line. + * 0: Not power down. + * 1: Not work and power down. * Valid only when I2C_SDA_FORCE_OUT is 1. */ uint32_t sda_pd_en:1; @@ -480,34 +450,34 @@ typedef union { struct { /** stretch_protect_num : R/W; bitpos: [9:0]; default: 0; * Configures the time period to release the SCL line from stretching to avoid timing - * violation. Usually it should be larger than the SDA setup time.\\ - * Measurement unit: i2c_sclk \\ + * violation. Usually it should be larger than the SDA setup time. + * Measurement unit: i2c_sclk */ uint32_t stretch_protect_num:10; /** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0; * Configures to enable slave SCL stretch function. The SCL output line will be * stretched low when I2C_SLAVE_SCL_STRETCH_EN is 1 and stretch event happens. The - * stretch cause can be seen in I2C_STRETCH_CAUSE.\\ - * 0: Disable \\ - * 1: Enable \\ + * stretch cause can be seen in I2C_STRETCH_CAUSE. + * 0: Disable + * 1: Enable */ uint32_t slave_scl_stretch_en:1; /** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0; - * Configures to clear the I2C slave SCL stretch function.\\ - * 0: No effect \\ - * 1: Clear\\ + * Configures to clear the I2C slave SCL stretch function. + * 0: No effect + * 1: Clear */ uint32_t slave_scl_stretch_clr:1; /** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0; - * Configures to enable the function for slave to control ACK level.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures to enable the function for slave to control ACK level. + * 0: Disable + * 1: Enable */ uint32_t slave_byte_ack_ctl_en:1; /** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0; - * Set the ACK level when slave controlling ACK level function enables.\\ - * 0: Low level\\ - * 1: High level \\ + * Set the ACK level when slave controlling ACK level function enables. + * 0: Low level + * 1: High level */ uint32_t slave_byte_ack_lvl:1; uint32_t reserved_14:18; @@ -523,36 +493,36 @@ typedef union { typedef union { struct { /** resp_rec : RO; bitpos: [0]; default: 0; - * Represents the received ACK value in master mode or slave mode.\\ - * 0: ACK\\ + * Represents the received ACK value in master mode or slave mode. + * 0: ACK * 1: NACK. */ uint32_t resp_rec:1; /** slave_rw : RO; bitpos: [1]; default: 0; - * Represents the transfer direction in slave mode.\\ - * 1: Master reads from slave\\ + * Represents the transfer direction in slave mode. + * 1: Master reads from slave * 0: Master writes to slave. */ uint32_t slave_rw:1; uint32_t reserved_2:1; /** arb_lost : RO; bitpos: [3]; default: 0; - * Represents whether the I2C controller loses control of SCL line.\\ - * 0: No arbitration lost\\ - * 1: Arbitration lost\\ + * Represents whether the I2C controller loses control of SCL line. + * 0: No arbitration lost + * 1: Arbitration lost */ uint32_t arb_lost:1; /** bus_busy : RO; bitpos: [4]; default: 0; - * Represents the I2C bus state.\\ - * 1: The I2C bus is busy transferring data\\ - * 0: The I2C bus is in idle state.\\ + * Represents the I2C bus state. + * 1: The I2C bus is busy transferring data + * 0: The I2C bus is in idle state. */ uint32_t bus_busy:1; /** slave_addressed : RO; bitpos: [5]; default: 0; * Represents whether the address sent by the master is equal to the address of the - * slave.\\ - * Valid only when the module is configured as an I2C Slave.\\ - * 0: Not equal\\ - * 1: Equal\\ + * slave. + * Valid only when the module is configured as an I2C Slave. + * 0: Not equal + * 1: Equal */ uint32_t slave_addressed:1; uint32_t reserved_6:2; @@ -561,9 +531,9 @@ typedef union { */ uint32_t rxfifo_cnt:6; /** stretch_cause : RO; bitpos: [15:14]; default: 3; - * Represents the cause of SCL clocking stretching in slave mode.\\ - * 0: Stretching SCL low when the master starts to read data.\\ - * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode.\\ + * Represents the cause of SCL clocking stretching in slave mode. + * 0: Stretching SCL low when the master starts to read data. + * 1: Stretching SCL low when I2C TX FIFO is empty in slave mode. * 2: Stretching SCL low when I2C RX FIFO is full in slave mode. */ uint32_t stretch_cause:2; @@ -573,25 +543,25 @@ typedef union { */ uint32_t txfifo_cnt:6; /** scl_main_state_last : RO; bitpos: [26:24]; default: 0; - * Represents the states of the I2C module state machine.\\ - * 0: Idle\\ - * 1: Address shift\\ - * 2: ACK address\\ - * 3: Rx data\\ - * 4: Tx data\\ - * 5: Send ACK\\ + * Represents the states of the I2C module state machine. + * 0: Idle + * 1: Address shift + * 2: ACK address + * 3: Rx data + * 4: Tx data + * 5: Send ACK * 6: Wait ACK */ uint32_t scl_main_state_last:3; uint32_t reserved_27:1; /** scl_state_last : RO; bitpos: [30:28]; default: 0; - * Represents the states of the state machine used to produce SCL.\\ - * 0: Idle\\ - * 1: Start\\ - * 2: Negative edge\\ - * 3: Low\\ - * 4: Positive edge\\ - * 5: High\\ + * Represents the states of the state machine used to produce SCL. + * 0: Idle + * 1: Start + * 2: Negative edge + * 3: Low + * 4: Positive edge + * 5: High * 6: Stop */ uint32_t scl_state_last:3; @@ -1000,38 +970,39 @@ typedef union { typedef union { struct { /** command : R/W; bitpos: [13:0]; default: 0; - * Configures command 0. \\ - * It consists of three parts:\\ - * op_code is the command\\ - * 1: WRITE\\ - * 2: STOP\\ - * 3: READ\\ - * 4: END\\ - * 6: RSTART\\ - * Byte_num represents the number of bytes that need to be sent or received.\\ + * Configures command 0. + * It consists of three parts: + * op_code is the command + * 1: WRITE + * 2: STOP + * 3: READ + * 4: END + * 6: RSTART + * Byte_num represents the number of bytes that need to be sent or received. * ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd - * structure link for more information. - * \\\tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" + * structure for more information. + * \tododone{for CJ, please add a hyperlink for I2C CMD structure.CJ: done.}" */ uint32_t command:14; uint32_t reserved_14:17; - /** command0_done : R/W/SS; bitpos: [31]; default: 0; - * Represents whether command 0 is done in I2C Master mode.\\ - * 0: Not done \\ - * 1: Done \\ + /** command_done : R/W/SS; bitpos: [31]; default: 0; + * Represents whether command 0 is done in I2C Master mode. + * 0: Not done + * 1: Done */ uint32_t command_done:1; }; uint32_t val; } i2c_comd_reg_t; + /** Group: Version register */ /** Type of date register * Version register */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 37752896; + /** date : R/W; bitpos: [31:0]; default: 37765248; * Version control register. */ uint32_t date:32; @@ -1040,6 +1011,34 @@ typedef union { } i2c_date_reg_t; +/** Group: Address register */ +/** Type of txfifo_start_addr register + * I2C TXFIFO base address register + */ +typedef union { + struct { + /** txfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C txfifo first address. + */ + uint32_t txfifo_start_addr:32; + }; + uint32_t val; +} i2c_txfifo_start_addr_reg_t; + +/** Type of rxfifo_start_addr register + * I2C RXFIFO base address register + */ +typedef union { + struct { + /** rxfifo_start_addr : HRO; bitpos: [31:0]; default: 0; + * Represents the I2C rxfifo first address. + */ + uint32_t rxfifo_start_addr:32; + }; + uint32_t val; +} i2c_rxfifo_start_addr_reg_t; + + typedef struct { volatile i2c_scl_low_period_reg_t scl_low_period; volatile i2c_ctr_reg_t ctr; @@ -1062,7 +1061,7 @@ typedef struct { volatile i2c_scl_stop_hold_reg_t scl_stop_hold; volatile i2c_scl_stop_setup_reg_t scl_stop_setup; volatile i2c_filter_cfg_reg_t filter_cfg; - volatile i2c_clk_conf_reg_t clk_conf; + uint32_t reserved_054; volatile i2c_comd_reg_t command[8]; volatile i2c_scl_st_time_out_reg_t scl_st_time_out; volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out; diff --git a/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h index f76f3e6593..ad4026911d 100644 --- a/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h +++ b/components/soc/esp32c61/register/soc/interrupt_matrix_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,7 +14,7 @@ extern "C" { /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG register * WIFI_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x0) /** INTERRUPT_CORE0_WIFI_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -22,11 +22,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_M (INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V << INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG register * WIFI_MAC_NMI mapping register */ -#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x4) /** INTERRUPT_CORE0_WIFI_MAC_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -34,11 +41,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_M (INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V << INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S) #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_MAC_NMI_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_MAC_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG register * WIFI_PWR_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8) /** INTERRUPT_CORE0_WIFI_PWR_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -46,11 +60,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_M (INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V << INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_PWR_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_PWR_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG register * WIFI_BB_INTR mapping register */ -#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc) +#define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc) /** INTERRUPT_CORE0_WIFI_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -58,11 +79,18 @@ extern "C" { #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_M (INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V << INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S) #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_WIFI_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_WIFI_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG register * BT_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10) +#define INTERRUPT_CORE0_BT_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x10) /** INTERRUPT_CORE0_BT_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -70,11 +98,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_M (INTERRUPT_CORE0_BT_MAC_INTR_MAP_V << INTERRUPT_CORE0_BT_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_INTR_MAP_REG register * BT_BB_INTR mapping register */ -#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14) +#define INTERRUPT_CORE0_BT_BB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x14) /** INTERRUPT_CORE0_BT_BB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -82,11 +117,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_INTR_MAP_M (INTERRUPT_CORE0_BT_BB_INTR_MAP_V << INTERRUPT_CORE0_BT_BB_INTR_MAP_S) #define INTERRUPT_CORE0_BT_BB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BT_BB_NMI_MAP_REG register * BT_BB_NMI mapping register */ -#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTMTX_BASE + 0x18) /** INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -94,11 +136,18 @@ extern "C" { #define INTERRUPT_CORE0_BT_BB_NMI_MAP_M (INTERRUPT_CORE0_BT_BB_NMI_MAP_V << INTERRUPT_CORE0_BT_BB_NMI_MAP_S) #define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 +/** INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_M (INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V << INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BT_BB_NMI_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG register * LP_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x1c) +#define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x1c) /** INTERRUPT_CORE0_LP_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -106,11 +155,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_COEX_INTR_MAP_REG register * COEX_INTR mapping register */ -#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x20) +#define INTERRUPT_CORE0_COEX_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x20) /** INTERRUPT_CORE0_COEX_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -118,11 +174,18 @@ extern "C" { #define INTERRUPT_CORE0_COEX_INTR_MAP_M (INTERRUPT_CORE0_COEX_INTR_MAP_V << INTERRUPT_CORE0_COEX_INTR_MAP_S) #define INTERRUPT_CORE0_COEX_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_COEX_INTR_MAP_S 0 +/** INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_COEX_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG register * BLE_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x24) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x24) /** INTERRUPT_CORE0_BLE_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -130,11 +193,18 @@ extern "C" { #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_M (INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V << INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG register * BLE_SEC_INTR mapping register */ -#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x28) +#define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x28) /** INTERRUPT_CORE0_BLE_SEC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -142,11 +212,18 @@ extern "C" { #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_M (INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V << INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S) #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_BLE_SEC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_BLE_SEC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG register * I2C_MST_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x2c) +#define INTERRUPT_CORE0_I2C_MST_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x2c) /** INTERRUPT_CORE0_I2C_MST_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -154,11 +231,18 @@ extern "C" { #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_M (INTERRUPT_CORE0_I2C_MST_INTR_MAP_V << INTERRUPT_CORE0_I2C_MST_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_MST_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_MST_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG register * ZB_MAC_INTR mapping register */ -#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x30) +#define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x30) /** INTERRUPT_CORE0_ZB_MAC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -166,11 +250,18 @@ extern "C" { #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_M (INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V << INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S) #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ZB_MAC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ZB_MAC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PMU_INTR_MAP_REG register * PMU_INTR mapping register */ -#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x34) +#define INTERRUPT_CORE0_PMU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x34) /** INTERRUPT_CORE0_PMU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -178,11 +269,18 @@ extern "C" { #define INTERRUPT_CORE0_PMU_INTR_MAP_M (INTERRUPT_CORE0_PMU_INTR_MAP_V << INTERRUPT_CORE0_PMU_INTR_MAP_S) #define INTERRUPT_CORE0_PMU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PMU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PMU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_EFUSE_INTR_MAP_REG register * EFUSE_INTR mapping register */ -#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x38) +#define INTERRUPT_CORE0_EFUSE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x38) /** INTERRUPT_CORE0_EFUSE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -190,11 +288,18 @@ extern "C" { #define INTERRUPT_CORE0_EFUSE_INTR_MAP_M (INTERRUPT_CORE0_EFUSE_INTR_MAP_V << INTERRUPT_CORE0_EFUSE_INTR_MAP_S) #define INTERRUPT_CORE0_EFUSE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_EFUSE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_EFUSE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG register * LP_RTC_TIMER_INTR mapping register */ -#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x3c) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x3c) /** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -202,11 +307,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S) #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_RTC_TIMER_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG register * LP_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x40) +#define INTERRUPT_CORE0_LP_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x40) /** INTERRUPT_CORE0_LP_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -214,11 +326,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_M (INTERRUPT_CORE0_LP_WDT_INTR_MAP_V << INTERRUPT_CORE0_LP_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG register * LP_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x44) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x44) /** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -226,11 +345,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG register * LP_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x48) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x48) /** INTERRUPT_CORE0_LP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -238,11 +364,18 @@ extern "C" { #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG register * CPU_INTR_FROM_CPU_0 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x4c) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTMTX_BASE + 0x4c) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -250,11 +383,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG register * CPU_INTR_FROM_CPU_1 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x50) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTMTX_BASE + 0x50) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -262,11 +402,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG register * CPU_INTR_FROM_CPU_2 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x54) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTMTX_BASE + 0x54) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -274,11 +421,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG register * CPU_INTR_FROM_CPU_3 mapping register */ -#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x58) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTMTX_BASE + 0x58) /** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -286,11 +440,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S) #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 +/** INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register * ASSIST_DEBUG_INTR mapping register */ -#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x5c) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x5c) /** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -298,11 +459,18 @@ extern "C" { #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S) #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register * TRACE_INTR mapping register */ -#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x60) +#define INTERRUPT_CORE0_TRACE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x60) /** INTERRUPT_CORE0_TRACE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -310,11 +478,18 @@ extern "C" { #define INTERRUPT_CORE0_TRACE_INTR_MAP_M (INTERRUPT_CORE0_TRACE_INTR_MAP_V << INTERRUPT_CORE0_TRACE_INTR_MAP_S) #define INTERRUPT_CORE0_TRACE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TRACE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TRACE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CACHE_INTR_MAP_REG register * CACHE_INTR mapping register */ -#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x64) +#define INTERRUPT_CORE0_CACHE_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x64) /** INTERRUPT_CORE0_CACHE_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -322,11 +497,18 @@ extern "C" { #define INTERRUPT_CORE0_CACHE_INTR_MAP_M (INTERRUPT_CORE0_CACHE_INTR_MAP_V << INTERRUPT_CORE0_CACHE_INTR_MAP_S) #define INTERRUPT_CORE0_CACHE_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CACHE_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CACHE_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG register * CPU_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x68) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x68) /** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -334,11 +516,18 @@ extern "C" { #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG register * GPIO_INTERRUPT_PRO mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTMTX_BASE + 0x6c) /** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -346,11 +535,18 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register * GPIO_INTERRUPT_EXT mapping register */ -#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x70) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTMTX_BASE + 0x70) /** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -358,11 +554,18 @@ extern "C" { #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S) #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0 +/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_PAU_INTR_MAP_REG register * PAU_INTR mapping register */ -#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x74) +#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x74) /** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -370,11 +573,18 @@ extern "C" { #define INTERRUPT_CORE0_PAU_INTR_MAP_M (INTERRUPT_CORE0_PAU_INTR_MAP_V << INTERRUPT_CORE0_PAU_INTR_MAP_S) #define INTERRUPT_CORE0_PAU_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_PAU_INTR_MAP_S 0 +/** INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_PAU_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register * HP_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x78) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x78) /** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -382,11 +592,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register * MODEM_PERI_TIMEOUT_INTR mapping register */ -#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7c) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x7c) /** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -394,11 +611,18 @@ extern "C" { #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S) #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register * HP_APM_M0_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x80) /** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -406,11 +630,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register * HP_APM_M1_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x84) /** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -418,11 +649,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register * HP_APM_M2_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x88) /** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -430,11 +668,18 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register * HP_APM_M3_INTR mapping register */ -#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x8c) /** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -442,11 +687,56 @@ extern "C" { #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S) #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0 +/** INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_HP_APM_M3_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG register + * CPU_APM_M0_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x90) +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG register + * CPU_APM_M1_INTR mapping register + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x94) +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_CPU_APM_M1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_MSPI_INTR_MAP_REG register * MSPI_INTR mapping register */ -#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90) +#define INTERRUPT_CORE0_MSPI_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x98) /** INTERRUPT_CORE0_MSPI_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -454,11 +744,18 @@ extern "C" { #define INTERRUPT_CORE0_MSPI_INTR_MAP_M (INTERRUPT_CORE0_MSPI_INTR_MAP_V << INTERRUPT_CORE0_MSPI_INTR_MAP_S) #define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0 +/** INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_MSPI_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register * I2S1_INTR mapping register */ -#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94) +#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x9c) /** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -466,11 +763,18 @@ extern "C" { #define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S) #define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2S1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART0_INTR_MAP_REG register * UART0_INTR mapping register */ -#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98) +#define INTERRUPT_CORE0_UART0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa0) /** INTERRUPT_CORE0_UART0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -478,11 +782,18 @@ extern "C" { #define INTERRUPT_CORE0_UART0_INTR_MAP_M (INTERRUPT_CORE0_UART0_INTR_MAP_V << INTERRUPT_CORE0_UART0_INTR_MAP_S) #define INTERRUPT_CORE0_UART0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART1_INTR_MAP_REG register * UART1_INTR mapping register */ -#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c) +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa4) /** INTERRUPT_CORE0_UART1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -490,11 +801,18 @@ extern "C" { #define INTERRUPT_CORE0_UART1_INTR_MAP_M (INTERRUPT_CORE0_UART1_INTR_MAP_V << INTERRUPT_CORE0_UART1_INTR_MAP_S) #define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_UART2_INTR_MAP_REG register * UART2_INTR mapping register */ -#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0) +#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xa8) /** INTERRUPT_CORE0_UART2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -502,11 +820,18 @@ extern "C" { #define INTERRUPT_CORE0_UART2_INTR_MAP_M (INTERRUPT_CORE0_UART2_INTR_MAP_V << INTERRUPT_CORE0_UART2_INTR_MAP_S) #define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_UART2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_LEDC_INTR_MAP_REG register * LEDC_INTR mapping register */ -#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa4) +#define INTERRUPT_CORE0_LEDC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xac) /** INTERRUPT_CORE0_LEDC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -514,11 +839,18 @@ extern "C" { #define INTERRUPT_CORE0_LEDC_INTR_MAP_M (INTERRUPT_CORE0_LEDC_INTR_MAP_V << INTERRUPT_CORE0_LEDC_INTR_MAP_S) #define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_LEDC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_USB_INTR_MAP_REG register * USB_INTR mapping register */ -#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa8) +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb0) /** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -526,11 +858,18 @@ extern "C" { #define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S) #define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_USB_INTR_MAP_S 0 +/** INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_USB_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register * I2C_EXT0_INTR mapping register */ -#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb4) /** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -538,11 +877,18 @@ extern "C" { #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V << INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S) #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_I2C_EXT0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register * TG0_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb0) +#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xb8) /** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -550,11 +896,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_M (INTERRUPT_CORE0_TG0_T0_INTR_MAP_V << INTERRUPT_CORE0_TG0_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register * TG0_T1_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb4) +#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xbc) /** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -562,11 +915,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_T1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register * TG0_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xb8) +#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc0) /** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -574,11 +934,18 @@ extern "C" { #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG0_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register * TG1_T0_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xbc) +#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc4) /** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -586,11 +953,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_M (INTERRUPT_CORE0_TG1_T0_INTR_MAP_V << INTERRUPT_CORE0_TG1_T0_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register * TG1_T1_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0) +#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xc8) /** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -598,11 +972,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_T1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register * TG1_WDT_INTR mapping register */ -#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4) +#define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xcc) /** INTERRUPT_CORE0_TG1_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -610,11 +991,18 @@ extern "C" { #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_M (INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V << INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S) #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_TG1_WDT_INTR_MAP_S 0 +/** INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_TG1_WDT_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG register * SYSTIMER_TARGET0_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd0) /** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -622,11 +1010,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG register * SYSTIMER_TARGET1_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd4) /** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -634,11 +1029,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG register * SYSTIMER_TARGET2_INTR mapping register */ -#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xd8) /** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -646,11 +1048,18 @@ extern "C" { #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S) #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG register * APB_ADC_INTR mapping register */ -#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4) +#define INTERRUPT_CORE0_APB_ADC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xdc) /** INTERRUPT_CORE0_APB_ADC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -658,11 +1067,56 @@ extern "C" { #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_M (INTERRUPT_CORE0_APB_ADC_INTR_MAP_V << INTERRUPT_CORE0_APB_ADC_INTR_MAP_S) #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_APB_ADC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_APB_ADC_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register + * SLC0_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe0) +/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC0_INTR_PASS_IN_SEC_S 8 + +/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register + * SLC1_INTR mapping register + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe4) +/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SLC1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register * DMA_IN_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xe8) /** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -670,11 +1124,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register * DMA_IN_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xec) /** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -682,11 +1143,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register * DMA_OUT_CH0_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf0) /** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -694,11 +1162,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register * DMA_OUT_CH1_INTR mapping register */ -#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf4) /** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -706,11 +1181,18 @@ extern "C" { #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S) #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_S 0 +/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register * GPSPI2_INTR mapping register */ -#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe8) +#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xf8) /** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -718,11 +1200,18 @@ extern "C" { #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_M (INTERRUPT_CORE0_GPSPI2_INTR_MAP_V << INTERRUPT_CORE0_GPSPI2_INTR_MAP_S) #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_GPSPI2_INTR_MAP_S 0 +/** INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_GPSPI2_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_SHA_INTR_MAP_REG register * SHA_INTR mapping register */ -#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xec) +#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0xfc) /** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -730,11 +1219,18 @@ extern "C" { #define INTERRUPT_CORE0_SHA_INTR_MAP_M (INTERRUPT_CORE0_SHA_INTR_MAP_V << INTERRUPT_CORE0_SHA_INTR_MAP_S) #define INTERRUPT_CORE0_SHA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_SHA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_SHA_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECC_INTR_MAP_REG register * ECC_INTR mapping register */ -#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf0) +#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x100) /** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -742,11 +1238,18 @@ extern "C" { #define INTERRUPT_CORE0_ECC_INTR_MAP_M (INTERRUPT_CORE0_ECC_INTR_MAP_V << INTERRUPT_CORE0_ECC_INTR_MAP_S) #define INTERRUPT_CORE0_ECC_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECC_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECC_INTR_PASS_IN_SEC_S 8 /** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register * ECDSA_INTR mapping register */ -#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf4) +#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTMTX_BASE + 0x104) /** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ @@ -754,14 +1257,21 @@ extern "C" { #define INTERRUPT_CORE0_ECDSA_INTR_MAP_M (INTERRUPT_CORE0_ECDSA_INTR_MAP_V << INTERRUPT_CORE0_ECDSA_INTR_MAP_S) #define INTERRUPT_CORE0_ECDSA_INTR_MAP_V 0x0000003FU #define INTERRUPT_CORE0_ECDSA_INTR_MAP_S 0 +/** INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC (BIT(8)) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_M (INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V << INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S) +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_V 0x00000001U +#define INTERRUPT_CORE0_ECDSA_INTR_PASS_IN_SEC_S 8 -/** INTERRUPT_CORE0_INT_STATUS_0_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register * Status register for interrupt sources 0 ~ 31 */ -#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xf8) +#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTMTX_BASE + 0x108) /** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -770,13 +1280,13 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_0_S 0 -/** INTERRUPT_CORE0_INT_STATUS_1_REG register +/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register * Status register for interrupt sources 32 ~ 63 */ -#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xfc) +#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTMTX_BASE + 0x10c) /** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source * 0:The corresponding interrupt source triggered an interrupt * 1:No interrupt triggered */ @@ -785,10 +1295,94 @@ extern "C" { #define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU #define INTERRUPT_CORE0_INT_STATUS_1_S 0 +/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register + * Status register for interrupt sources 64 ~ 65 + */ +#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTMTX_BASE + 0x110) +/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ +#define INTERRUPT_CORE0_INT_STATUS_2 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_2_M (INTERRUPT_CORE0_INT_STATUS_2_V << INTERRUPT_CORE0_INT_STATUS_2_S) +#define INTERRUPT_CORE0_INT_STATUS_2_V 0x00000003U +#define INTERRUPT_CORE0_INT_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_0_REG (DR_REG_INTMTX_BASE + 0x114) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_0_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_1_REG (DR_REG_INTMTX_BASE + 0x118) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_1_S 0 + +/** INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG register + * PASS_IN_SEC status register for interrupt sources 64 ~ 65 + */ +#define INTERRUPT_CORE0_SRC_PASS_IN_SEC_STATUS_2_REG (DR_REG_INTMTX_BASE + 0x11c) +/** INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_M (INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V << INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S) +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_V 0x00000003U +#define INTERRUPT_CORE0_INT_SRC_PASS_IN_SEC_STATUS_2_S 0 + +/** INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG register + * reserved + */ +#define INTERRUPT_CORE0_SIG_IDX_ASSERT_IN_SEC_REG (DR_REG_INTMTX_BASE + 0x120) +/** INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC : R/W; bitpos: [5:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_M (INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V << INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S) +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_V 0x0000003FU +#define INTERRUPT_CORE0_INT_SIG_IDX_ASSERT_IN_SEC_S 0 + +/** INTERRUPT_CORE0_SECURE_STATUS_REG register + * reserved + */ +#define INTERRUPT_CORE0_SECURE_STATUS_REG (DR_REG_INTMTX_BASE + 0x124) +/** INTERRUPT_CORE0_INT_SECURE_STATUS : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define INTERRUPT_CORE0_INT_SECURE_STATUS 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_M (INTERRUPT_CORE0_INT_SECURE_STATUS_V << INTERRUPT_CORE0_INT_SECURE_STATUS_S) +#define INTERRUPT_CORE0_INT_SECURE_STATUS_V 0xFFFFFFFFU +#define INTERRUPT_CORE0_INT_SECURE_STATUS_S 0 + /** INTERRUPT_CORE0_CLOCK_GATE_REG register * Interrupt clock gating configure register */ -#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTMTX_BASE + 0x128) /** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ @@ -800,8 +1394,8 @@ extern "C" { /** INTERRUPT_CORE0_INTERRUPT_DATE_REG register * Version control register */ -#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc) -/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36774400; +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTMTX_BASE + 0x7fc) +/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 38801441; * Version control register */ #define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h index 2b7d52e189..1920ed6d89 100644 --- a/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h +++ b/components/soc/esp32c61/register/soc/interrupt_matrix_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,1005 +11,1496 @@ extern "C" { #endif /** Group: Configuration Registers */ -/** Type of wifi_mac_intr_map register +/** Type of core0_wifi_mac_intr_map register * WIFI_MAC_INTR mapping register */ typedef union { struct { - /** wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_mac_intr_map_reg_t; +} interrupt_core0_wifi_mac_intr_map_reg_t; -/** Type of wifi_mac_nmi_map register +/** Type of core0_wifi_mac_nmi_map register * WIFI_MAC_NMI mapping register */ typedef union { struct { - /** wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_mac_nmi_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_mac_nmi_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_mac_nmi_map:6; + uint32_t reserved_6:2; + /** core0_wifi_mac_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_mac_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_mac_nmi_map_reg_t; +} interrupt_core0_wifi_mac_nmi_map_reg_t; -/** Type of wifi_pwr_intr_map register +/** Type of core0_wifi_pwr_intr_map register * WIFI_PWR_INTR mapping register */ typedef union { struct { - /** wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_pwr_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_pwr_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_pwr_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_pwr_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_pwr_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_pwr_intr_map_reg_t; +} interrupt_core0_wifi_pwr_intr_map_reg_t; -/** Type of wifi_bb_intr_map register +/** Type of core0_wifi_bb_intr_map register * WIFI_BB_INTR mapping register */ typedef union { struct { - /** wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_wifi_bb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t wifi_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_wifi_bb_intr_map:6; + uint32_t reserved_6:2; + /** core0_wifi_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_wifi_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_wifi_bb_intr_map_reg_t; +} interrupt_core0_wifi_bb_intr_map_reg_t; -/** Type of bt_mac_intr_map register +/** Type of core0_bt_mac_intr_map register * BT_MAC_INTR mapping register */ typedef union { struct { - /** bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_bt_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_mac_intr_map_reg_t; +} interrupt_core0_bt_mac_intr_map_reg_t; -/** Type of bt_bb_intr_map register +/** Type of core0_bt_bb_intr_map register * BT_BB_INTR mapping register */ typedef union { struct { - /** bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_bb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_bb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_bb_intr_map:6; + uint32_t reserved_6:2; + /** core0_bt_bb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_bb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_bb_intr_map_reg_t; +} interrupt_core0_bt_bb_intr_map_reg_t; -/** Type of bt_bb_nmi_map register +/** Type of core0_bt_bb_nmi_map register * BT_BB_NMI mapping register */ typedef union { struct { - /** bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; + /** core0_bt_bb_nmi_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t bt_bb_nmi_map:6; - uint32_t reserved_6:26; + uint32_t core0_bt_bb_nmi_map:6; + uint32_t reserved_6:2; + /** core0_bt_bb_nmi_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_bt_bb_nmi_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_bt_bb_nmi_map_reg_t; +} interrupt_core0_bt_bb_nmi_map_reg_t; -/** Type of lp_timer_intr_map register +/** Type of core0_lp_timer_intr_map register * LP_TIMER_INTR mapping register */ typedef union { struct { - /** lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_timer_intr_map_reg_t; +} interrupt_core0_lp_timer_intr_map_reg_t; -/** Type of coex_intr_map register +/** Type of core0_coex_intr_map register * COEX_INTR mapping register */ typedef union { struct { - /** coex_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_coex_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t coex_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_coex_intr_map:6; + uint32_t reserved_6:2; + /** core0_coex_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_coex_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_coex_intr_map_reg_t; +} interrupt_core0_coex_intr_map_reg_t; -/** Type of ble_timer_intr_map register +/** Type of core0_ble_timer_intr_map register * BLE_TIMER_INTR mapping register */ typedef union { struct { - /** ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ble_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ble_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ble_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_ble_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ble_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ble_timer_intr_map_reg_t; +} interrupt_core0_ble_timer_intr_map_reg_t; -/** Type of ble_sec_intr_map register +/** Type of core0_ble_sec_intr_map register * BLE_SEC_INTR mapping register */ typedef union { struct { - /** ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ble_sec_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ble_sec_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ble_sec_intr_map:6; + uint32_t reserved_6:2; + /** core0_ble_sec_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ble_sec_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ble_sec_intr_map_reg_t; +} interrupt_core0_ble_sec_intr_map_reg_t; -/** Type of i2c_mst_intr_map register +/** Type of core0_i2c_mst_intr_map register * I2C_MST_INTR mapping register */ typedef union { struct { - /** i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2c_mst_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2c_mst_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2c_mst_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2c_mst_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2c_mst_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2c_mst_intr_map_reg_t; +} interrupt_core0_i2c_mst_intr_map_reg_t; -/** Type of zb_mac_intr_map register +/** Type of core0_zb_mac_intr_map register * ZB_MAC_INTR mapping register */ typedef union { struct { - /** zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_zb_mac_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t zb_mac_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_zb_mac_intr_map:6; + uint32_t reserved_6:2; + /** core0_zb_mac_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_zb_mac_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_zb_mac_intr_map_reg_t; +} interrupt_core0_zb_mac_intr_map_reg_t; -/** Type of pmu_intr_map register +/** Type of core0_pmu_intr_map register * PMU_INTR mapping register */ typedef union { struct { - /** pmu_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_pmu_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t pmu_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_pmu_intr_map:6; + uint32_t reserved_6:2; + /** core0_pmu_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_pmu_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_pmu_intr_map_reg_t; +} interrupt_core0_pmu_intr_map_reg_t; -/** Type of efuse_intr_map register +/** Type of core0_efuse_intr_map register * EFUSE_INTR mapping register */ typedef union { struct { - /** efuse_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_efuse_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t efuse_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_efuse_intr_map:6; + uint32_t reserved_6:2; + /** core0_efuse_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_efuse_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_efuse_intr_map_reg_t; +} interrupt_core0_efuse_intr_map_reg_t; -/** Type of lp_rtc_timer_intr_map register +/** Type of core0_lp_rtc_timer_intr_map register * LP_RTC_TIMER_INTR mapping register */ typedef union { struct { - /** lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_rtc_timer_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_rtc_timer_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_rtc_timer_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_rtc_timer_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_rtc_timer_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_rtc_timer_intr_map_reg_t; +} interrupt_core0_lp_rtc_timer_intr_map_reg_t; -/** Type of lp_wdt_intr_map register +/** Type of core0_lp_wdt_intr_map register * LP_WDT_INTR mapping register */ typedef union { struct { - /** lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_wdt_intr_map_reg_t; +} interrupt_core0_lp_wdt_intr_map_reg_t; -/** Type of lp_peri_timeout_intr_map register +/** Type of core0_lp_peri_timeout_intr_map register * LP_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_peri_timeout_intr_map_reg_t; +} interrupt_core0_lp_peri_timeout_intr_map_reg_t; -/** Type of lp_apm_m0_intr_map register +/** Type of core0_lp_apm_m0_intr_map register * LP_APM_M0_INTR mapping register */ typedef union { struct { - /** lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_lp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t lp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_lp_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_lp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_lp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_lp_apm_m0_intr_map_reg_t; +} interrupt_core0_lp_apm_m0_intr_map_reg_t; -/** Type of cpu_intr_from_cpu_0_map register +/** Type of core0_cpu_intr_from_cpu_0_map register * CPU_INTR_FROM_CPU_0 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_0_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_0_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_0_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_0_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_0_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_0_map_reg_t; -/** Type of cpu_intr_from_cpu_1_map register +/** Type of core0_cpu_intr_from_cpu_1_map register * CPU_INTR_FROM_CPU_1 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_1_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_1_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_1_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_1_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_1_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_1_map_reg_t; -/** Type of cpu_intr_from_cpu_2_map register +/** Type of core0_cpu_intr_from_cpu_2_map register * CPU_INTR_FROM_CPU_2 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_2_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_2_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_2_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_2_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_2_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_2_map_reg_t; -/** Type of cpu_intr_from_cpu_3_map register +/** Type of core0_cpu_intr_from_cpu_3_map register * CPU_INTR_FROM_CPU_3 mapping register */ typedef union { struct { - /** cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_intr_from_cpu_3_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_intr_from_cpu_3_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_intr_from_cpu_3_map:6; + uint32_t reserved_6:2; + /** core0_cpu_intr_from_cpu_3_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_intr_from_cpu_3_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t; +} interrupt_core0_cpu_intr_from_cpu_3_map_reg_t; -/** Type of assist_debug_intr_map register +/** Type of core0_assist_debug_intr_map register * ASSIST_DEBUG_INTR mapping register */ typedef union { struct { - /** assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_assist_debug_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t assist_debug_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_assist_debug_intr_map:6; + uint32_t reserved_6:2; + /** core0_assist_debug_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_assist_debug_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_assist_debug_intr_map_reg_t; +} interrupt_core0_assist_debug_intr_map_reg_t; -/** Type of trace_intr_map register +/** Type of core0_trace_intr_map register * TRACE_INTR mapping register */ typedef union { struct { - /** trace_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_trace_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t trace_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_trace_intr_map:6; + uint32_t reserved_6:2; + /** core0_trace_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_trace_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_trace_intr_map_reg_t; +} interrupt_core0_trace_intr_map_reg_t; -/** Type of cache_intr_map register +/** Type of core0_cache_intr_map register * CACHE_INTR mapping register */ typedef union { struct { - /** cache_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cache_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cache_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_cache_intr_map:6; + uint32_t reserved_6:2; + /** core0_cache_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cache_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cache_intr_map_reg_t; +} interrupt_core0_cache_intr_map_reg_t; -/** Type of cpu_peri_timeout_intr_map register +/** Type of core0_cpu_peri_timeout_intr_map register * CPU_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_cpu_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t cpu_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_cpu_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_cpu_peri_timeout_intr_map_reg_t; +} interrupt_core0_cpu_peri_timeout_intr_map_reg_t; -/** Type of gpio_interrupt_pro_map register +/** Type of core0_gpio_interrupt_pro_map register * GPIO_INTERRUPT_PRO mapping register */ typedef union { struct { - /** gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpio_interrupt_pro_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpio_interrupt_pro_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpio_interrupt_pro_map:6; + uint32_t reserved_6:2; + /** core0_gpio_interrupt_pro_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpio_interrupt_pro_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpio_interrupt_pro_map_reg_t; +} interrupt_core0_gpio_interrupt_pro_map_reg_t; -/** Type of gpio_interrupt_ext_map register +/** Type of core0_gpio_interrupt_ext_map register * GPIO_INTERRUPT_EXT mapping register */ typedef union { struct { - /** gpio_interrupt_ext_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpio_interrupt_ext_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpio_interrupt_ext_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpio_interrupt_ext_map:6; + uint32_t reserved_6:2; + /** core0_gpio_interrupt_ext_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpio_interrupt_ext_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpio_interrupt_ext_map_reg_t; +} interrupt_core0_gpio_interrupt_ext_map_reg_t; -/** Type of pau_intr_map register +/** Type of core0_pau_intr_map register * PAU_INTR mapping register */ typedef union { struct { - /** pau_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_pau_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t pau_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_pau_intr_map:6; + uint32_t reserved_6:2; + /** core0_pau_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_pau_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_pau_intr_map_reg_t; +} interrupt_core0_pau_intr_map_reg_t; -/** Type of hp_peri_timeout_intr_map register +/** Type of core0_hp_peri_timeout_intr_map register * HP_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_peri_timeout_intr_map_reg_t; +} interrupt_core0_hp_peri_timeout_intr_map_reg_t; -/** Type of modem_peri_timeout_intr_map register +/** Type of core0_modem_peri_timeout_intr_map register * MODEM_PERI_TIMEOUT_INTR mapping register */ typedef union { struct { - /** modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_modem_peri_timeout_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t modem_peri_timeout_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_modem_peri_timeout_intr_map:6; + uint32_t reserved_6:2; + /** core0_modem_peri_timeout_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_modem_peri_timeout_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_modem_peri_timeout_intr_map_reg_t; +} interrupt_core0_modem_peri_timeout_intr_map_reg_t; -/** Type of hp_apm_m0_intr_map register +/** Type of core0_hp_apm_m0_intr_map register * HP_APM_M0_INTR mapping register */ typedef union { struct { - /** hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m0_intr_map_reg_t; +} interrupt_core0_hp_apm_m0_intr_map_reg_t; -/** Type of hp_apm_m1_intr_map register +/** Type of core0_hp_apm_m1_intr_map register * HP_APM_M1_INTR mapping register */ typedef union { struct { - /** hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m1_intr_map_reg_t; +} interrupt_core0_hp_apm_m1_intr_map_reg_t; -/** Type of hp_apm_m2_intr_map register +/** Type of core0_hp_apm_m2_intr_map register * HP_APM_M2_INTR mapping register */ typedef union { struct { - /** hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m2_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m2_intr_map_reg_t; +} interrupt_core0_hp_apm_m2_intr_map_reg_t; -/** Type of hp_apm_m3_intr_map register +/** Type of core0_hp_apm_m3_intr_map register * HP_APM_M3_INTR mapping register */ typedef union { struct { - /** hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_hp_apm_m3_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t hp_apm_m3_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_hp_apm_m3_intr_map:6; + uint32_t reserved_6:2; + /** core0_hp_apm_m3_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_hp_apm_m3_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_hp_apm_m3_intr_map_reg_t; +} interrupt_core0_hp_apm_m3_intr_map_reg_t; -/** Type of mspi_intr_map register +/** Type of core0_cpu_apm_m0_intr_map register + * CPU_APM_M0_INTR mapping register + */ +typedef union { + struct { + /** core0_cpu_apm_m0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_cpu_apm_m0_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_apm_m0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_apm_m0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m0_intr_map_reg_t; + +/** Type of core0_cpu_apm_m1_intr_map register + * CPU_APM_M1_INTR mapping register + */ +typedef union { + struct { + /** core0_cpu_apm_m1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_cpu_apm_m1_intr_map:6; + uint32_t reserved_6:2; + /** core0_cpu_apm_m1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_cpu_apm_m1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_cpu_apm_m1_intr_map_reg_t; + +/** Type of core0_mspi_intr_map register * MSPI_INTR mapping register */ typedef union { struct { - /** mspi_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_mspi_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t mspi_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_mspi_intr_map:6; + uint32_t reserved_6:2; + /** core0_mspi_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_mspi_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_mspi_intr_map_reg_t; +} interrupt_core0_mspi_intr_map_reg_t; -/** Type of i2s1_intr_map register +/** Type of core0_i2s1_intr_map register * I2S1_INTR mapping register */ typedef union { struct { - /** i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2s1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2s1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2s1_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2s1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2s1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2s1_intr_map_reg_t; +} interrupt_core0_i2s1_intr_map_reg_t; -/** Type of uart0_intr_map register +/** Type of core0_uart0_intr_map register * UART0_INTR mapping register */ typedef union { struct { - /** uart0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart0_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart0_intr_map_reg_t; +} interrupt_core0_uart0_intr_map_reg_t; -/** Type of uart1_intr_map register +/** Type of core0_uart1_intr_map register * UART1_INTR mapping register */ typedef union { struct { - /** uart1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart1_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart1_intr_map_reg_t; +} interrupt_core0_uart1_intr_map_reg_t; -/** Type of uart2_intr_map register +/** Type of core0_uart2_intr_map register * UART2_INTR mapping register */ typedef union { struct { - /** uart2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_uart2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t uart2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_uart2_intr_map:6; + uint32_t reserved_6:2; + /** core0_uart2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_uart2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_uart2_intr_map_reg_t; +} interrupt_core0_uart2_intr_map_reg_t; -/** Type of ledc_intr_map register +/** Type of core0_ledc_intr_map register * LEDC_INTR mapping register */ typedef union { struct { - /** ledc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ledc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ledc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ledc_intr_map:6; + uint32_t reserved_6:2; + /** core0_ledc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ledc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ledc_intr_map_reg_t; +} interrupt_core0_ledc_intr_map_reg_t; -/** Type of usb_intr_map register +/** Type of core0_usb_intr_map register * USB_INTR mapping register */ typedef union { struct { - /** usb_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_usb_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t usb_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_usb_intr_map:6; + uint32_t reserved_6:2; + /** core0_usb_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_usb_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_usb_intr_map_reg_t; +} interrupt_core0_usb_intr_map_reg_t; -/** Type of i2c_ext0_intr_map register +/** Type of core0_i2c_ext0_intr_map register * I2C_EXT0_INTR mapping register */ typedef union { struct { - /** i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_i2c_ext0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t i2c_ext0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_i2c_ext0_intr_map:6; + uint32_t reserved_6:2; + /** core0_i2c_ext0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_i2c_ext0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_i2c_ext0_intr_map_reg_t; +} interrupt_core0_i2c_ext0_intr_map_reg_t; -/** Type of tg0_t0_intr_map register +/** Type of core0_tg0_t0_intr_map register * TG0_T0_INTR mapping register */ typedef union { struct { - /** tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_t0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_t0_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_t0_intr_map_reg_t; +} interrupt_core0_tg0_t0_intr_map_reg_t; -/** Type of tg0_t1_intr_map register +/** Type of core0_tg0_t1_intr_map register * TG0_T1_INTR mapping register */ typedef union { struct { - /** tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_t1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_t1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_t1_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_t1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_t1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_t1_intr_map_reg_t; +} interrupt_core0_tg0_t1_intr_map_reg_t; -/** Type of tg0_wdt_intr_map register +/** Type of core0_tg0_wdt_intr_map register * TG0_WDT_INTR mapping register */ typedef union { struct { - /** tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg0_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg0_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg0_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg0_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg0_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg0_wdt_intr_map_reg_t; +} interrupt_core0_tg0_wdt_intr_map_reg_t; -/** Type of tg1_t0_intr_map register +/** Type of core0_tg1_t0_intr_map register * TG1_T0_INTR mapping register */ typedef union { struct { - /** tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_t0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_t0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_t0_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_t0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_t0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_t0_intr_map_reg_t; +} interrupt_core0_tg1_t0_intr_map_reg_t; -/** Type of tg1_t1_intr_map register +/** Type of core0_tg1_t1_intr_map register * TG1_T1_INTR mapping register */ typedef union { struct { - /** tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_t1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_t1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_t1_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_t1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_t1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_t1_intr_map_reg_t; +} interrupt_core0_tg1_t1_intr_map_reg_t; -/** Type of tg1_wdt_intr_map register +/** Type of core0_tg1_wdt_intr_map register * TG1_WDT_INTR mapping register */ typedef union { struct { - /** tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_tg1_wdt_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t tg1_wdt_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_tg1_wdt_intr_map:6; + uint32_t reserved_6:2; + /** core0_tg1_wdt_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_tg1_wdt_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_tg1_wdt_intr_map_reg_t; +} interrupt_core0_tg1_wdt_intr_map_reg_t; -/** Type of systimer_target0_intr_map register +/** Type of core0_systimer_target0_intr_map register * SYSTIMER_TARGET0_INTR mapping register */ typedef union { struct { - /** systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target0_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target0_intr_map_reg_t; +} interrupt_core0_systimer_target0_intr_map_reg_t; -/** Type of systimer_target1_intr_map register +/** Type of core0_systimer_target1_intr_map register * SYSTIMER_TARGET1_INTR mapping register */ typedef union { struct { - /** systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target1_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target1_intr_map_reg_t; +} interrupt_core0_systimer_target1_intr_map_reg_t; -/** Type of systimer_target2_intr_map register +/** Type of core0_systimer_target2_intr_map register * SYSTIMER_TARGET2_INTR mapping register */ typedef union { struct { - /** systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_systimer_target2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t systimer_target2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_systimer_target2_intr_map:6; + uint32_t reserved_6:2; + /** core0_systimer_target2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_systimer_target2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_systimer_target2_intr_map_reg_t; +} interrupt_core0_systimer_target2_intr_map_reg_t; -/** Type of apb_adc_intr_map register +/** Type of core0_apb_adc_intr_map register * APB_ADC_INTR mapping register */ typedef union { struct { - /** apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_apb_adc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t apb_adc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_apb_adc_intr_map:6; + uint32_t reserved_6:2; + /** core0_apb_adc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_apb_adc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_apb_adc_intr_map_reg_t; +} interrupt_core0_apb_adc_intr_map_reg_t; -/** Type of dma_in_ch0_intr_map register +/** Type of core0_slc0_intr_map register + * SLC0_INTR mapping register + */ +typedef union { + struct { + /** core0_slc0_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_slc0_intr_map:6; + uint32_t reserved_6:2; + /** core0_slc0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_slc0_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc0_intr_map_reg_t; + +/** Type of core0_slc1_intr_map register + * SLC1_INTR mapping register + */ +typedef union { + struct { + /** core0_slc1_intr_map : R/W; bitpos: [5:0]; default: 0; + * Configures the interrupt source into one CPU interrupt. + */ + uint32_t core0_slc1_intr_map:6; + uint32_t reserved_6:2; + /** core0_slc1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_slc1_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_slc1_intr_map_reg_t; + +/** Type of core0_dma_in_ch0_intr_map register * DMA_IN_CH0_INTR mapping register */ typedef union { struct { - /** dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_in_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_in_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_in_ch0_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_in_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_in_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_in_ch0_intr_map_reg_t; +} interrupt_core0_dma_in_ch0_intr_map_reg_t; -/** Type of dma_in_ch1_intr_map register +/** Type of core0_dma_in_ch1_intr_map register * DMA_IN_CH1_INTR mapping register */ typedef union { struct { - /** dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_in_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_in_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_in_ch1_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_in_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_in_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_in_ch1_intr_map_reg_t; +} interrupt_core0_dma_in_ch1_intr_map_reg_t; -/** Type of dma_out_ch0_intr_map register +/** Type of core0_dma_out_ch0_intr_map register * DMA_OUT_CH0_INTR mapping register */ typedef union { struct { - /** dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_out_ch0_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_out_ch0_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_out_ch0_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_out_ch0_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_out_ch0_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_out_ch0_intr_map_reg_t; +} interrupt_core0_dma_out_ch0_intr_map_reg_t; -/** Type of dma_out_ch1_intr_map register +/** Type of core0_dma_out_ch1_intr_map register * DMA_OUT_CH1_INTR mapping register */ typedef union { struct { - /** dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_dma_out_ch1_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t dma_out_ch1_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_dma_out_ch1_intr_map:6; + uint32_t reserved_6:2; + /** core0_dma_out_ch1_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_dma_out_ch1_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_dma_out_ch1_intr_map_reg_t; +} interrupt_core0_dma_out_ch1_intr_map_reg_t; -/** Type of gpspi2_intr_map register +/** Type of core0_gpspi2_intr_map register * GPSPI2_INTR mapping register */ typedef union { struct { - /** gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_gpspi2_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t gpspi2_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_gpspi2_intr_map:6; + uint32_t reserved_6:2; + /** core0_gpspi2_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_gpspi2_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_gpspi2_intr_map_reg_t; +} interrupt_core0_gpspi2_intr_map_reg_t; -/** Type of sha_intr_map register +/** Type of core0_sha_intr_map register * SHA_INTR mapping register */ typedef union { struct { - /** sha_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_sha_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t sha_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_sha_intr_map:6; + uint32_t reserved_6:2; + /** core0_sha_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_sha_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_sha_intr_map_reg_t; +} interrupt_core0_sha_intr_map_reg_t; -/** Type of ecc_intr_map register +/** Type of core0_ecc_intr_map register * ECC_INTR mapping register */ typedef union { struct { - /** ecc_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ecc_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ecc_intr_map:6; - uint32_t reserved_6:26; + uint32_t core0_ecc_intr_map:6; + uint32_t reserved_6:2; + /** core0_ecc_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ecc_intr_pass_in_sec:1; + uint32_t reserved_9:23; }; uint32_t val; -} interrupt_matrix_ecc_intr_map_reg_t; +} interrupt_core0_ecc_intr_map_reg_t; -/** Type of ecdsa_intr_map register +/** Type of core0_ecdsa_intr_map register * ECDSA_INTR mapping register */ typedef union { struct { - /** ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; + /** core0_ecdsa_intr_map : R/W; bitpos: [5:0]; default: 0; * Configures the interrupt source into one CPU interrupt. */ - uint32_t ecdsa_intr_map:6; + uint32_t core0_ecdsa_intr_map:6; + uint32_t reserved_6:2; + /** core0_ecdsa_intr_pass_in_sec : R/W; bitpos: [8]; default: 0; + * Configures the PASS_IN_SEC flag of the interrupt source. + */ + uint32_t core0_ecdsa_intr_pass_in_sec:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} interrupt_core0_ecdsa_intr_map_reg_t; + +/** Type of core0_sig_idx_assert_in_sec register + * reserved + */ +typedef union { + struct { + /** core0_int_sig_idx_assert_in_sec : R/W; bitpos: [5:0]; default: 0; + * reserved + */ + uint32_t core0_int_sig_idx_assert_in_sec:6; uint32_t reserved_6:26; }; uint32_t val; -} interrupt_matrix_ecdsa_intr_map_reg_t; +} interrupt_core0_sig_idx_assert_in_sec_reg_t; -/** Type of int_status_0 register - * Status register for interrupt sources 0 ~ 31 - */ -typedef union { - struct { - /** int_status_0 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_0:32; - }; - uint32_t val; -} interrupt_matrix_int_status_0_reg_t; - -/** Type of int_status_1 register - * Status register for interrupt sources 32 ~ 63 - */ -typedef union { - struct { - /** int_status_1 : RO; bitpos: [31:0]; default: 0; - * Represents the status of the interrupt sources numbered from .Each bit corresponds - * to one interrupt source - * 0:The corresponding interrupt source triggered an interrupt - * 1:No interrupt triggered - */ - uint32_t int_status_1:32; - }; - uint32_t val; -} interrupt_matrix_int_status_1_reg_t; - -/** Type of clock_gate register +/** Type of core0_clock_gate register * Interrupt clock gating configure register */ typedef union { struct { - /** reg_clk_en : R/W; bitpos: [0]; default: 0; + /** core0_reg_clk_en : R/W; bitpos: [0]; default: 0; * Interrupt clock gating configure register */ - uint32_t reg_clk_en:1; + uint32_t core0_reg_clk_en:1; uint32_t reserved_1:31; }; uint32_t val; -} interrupt_matrix_clock_gate_reg_t; +} interrupt_core0_clock_gate_reg_t; + + +/** Group: Status Registers */ +/** Type of core0_int_status_reg_0 register + * Status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** core0_int_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 0 ~ 31. + * Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_0:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_0_reg_t; + +/** Type of core0_int_status_reg_1 register + * Status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** core0_int_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 32 ~ + * 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_1:32; + }; + uint32_t val; +} interrupt_core0_int_status_reg_1_reg_t; + +/** Type of core0_int_status_reg_2 register + * Status register for interrupt sources 64 ~ 65 + */ +typedef union { + struct { + /** core0_int_status_2 : RO; bitpos: [1:0]; default: 0; + * Represents the status of the interrupt sources within interrupt-index-range 64 ~ + * 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source triggered an interrupt + * 1:No interrupt triggered + */ + uint32_t core0_int_status_2:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_int_status_reg_2_reg_t; + +/** Type of core0_src_pass_in_sec_status_0 register + * PASS_IN_SEC status register for interrupt sources 0 ~ 31 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_0 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 0 ~ 31. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_0:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_0_reg_t; + +/** Type of core0_src_pass_in_sec_status_1 register + * PASS_IN_SEC status register for interrupt sources 32 ~ 63 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_1 : RO; bitpos: [31:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources within + * interrupt-index-range 32 ~ 63. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_1:32; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_1_reg_t; + +/** Type of core0_src_pass_in_sec_status_2 register + * PASS_IN_SEC status register for interrupt sources 64 ~ 65 + */ +typedef union { + struct { + /** core0_int_src_pass_in_sec_status_2 : RO; bitpos: [1:0]; default: 0; + * Represents the PASS_IN_SEC status of the interrupt sources with + * interrupt-index-range 64 ~ 65. Each bit corresponds to one interrupt source + * 0:The corresponding interrupt source is not PASS_IN_SEC. + * 1:The corresponding interrupt source is PASS_IN_SEC. + */ + uint32_t core0_int_src_pass_in_sec_status_2:2; + uint32_t reserved_2:30; + }; + uint32_t val; +} interrupt_core0_src_pass_in_sec_status_2_reg_t; + +/** Type of core0_secure_status register + * reserved + */ +typedef union { + struct { + /** core0_int_secure_status : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t core0_int_secure_status:32; + }; + uint32_t val; +} interrupt_core0_secure_status_reg_t; /** Group: Version Register */ -/** Type of interrupt_date register +/** Type of core0_interrupt_date register * Version control register */ typedef union { struct { - /** interrupt_date : R/W; bitpos: [27:0]; default: 36774400; + /** core0_interrupt_date : R/W; bitpos: [27:0]; default: 38801441; * Version control register */ - uint32_t interrupt_date:28; + uint32_t core0_interrupt_date:28; uint32_t reserved_28:4; }; uint32_t val; -} interrupt_matrix_interrupt_date_reg_t; +} interrupt_core0_interrupt_date_reg_t; typedef struct { - volatile interrupt_matrix_wifi_mac_intr_map_reg_t wifi_mac_intr_map; - volatile interrupt_matrix_wifi_mac_nmi_map_reg_t wifi_mac_nmi_map; - volatile interrupt_matrix_wifi_pwr_intr_map_reg_t wifi_pwr_intr_map; - volatile interrupt_matrix_wifi_bb_intr_map_reg_t wifi_bb_intr_map; - volatile interrupt_matrix_bt_mac_intr_map_reg_t bt_mac_intr_map; - volatile interrupt_matrix_bt_bb_intr_map_reg_t bt_bb_intr_map; - volatile interrupt_matrix_bt_bb_nmi_map_reg_t bt_bb_nmi_map; - volatile interrupt_matrix_lp_timer_intr_map_reg_t lp_timer_intr_map; - volatile interrupt_matrix_coex_intr_map_reg_t coex_intr_map; - volatile interrupt_matrix_ble_timer_intr_map_reg_t ble_timer_intr_map; - volatile interrupt_matrix_ble_sec_intr_map_reg_t ble_sec_intr_map; - volatile interrupt_matrix_i2c_mst_intr_map_reg_t i2c_mst_intr_map; - volatile interrupt_matrix_zb_mac_intr_map_reg_t zb_mac_intr_map; - volatile interrupt_matrix_pmu_intr_map_reg_t pmu_intr_map; - volatile interrupt_matrix_efuse_intr_map_reg_t efuse_intr_map; - volatile interrupt_matrix_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map; - volatile interrupt_matrix_lp_wdt_intr_map_reg_t lp_wdt_intr_map; - volatile interrupt_matrix_lp_peri_timeout_intr_map_reg_t lp_peri_timeout_intr_map; - volatile interrupt_matrix_lp_apm_m0_intr_map_reg_t lp_apm_m0_intr_map; - volatile interrupt_matrix_cpu_intr_from_cpu_0_map_reg_t cpu_intr_from_cpu_0_map; - volatile interrupt_matrix_cpu_intr_from_cpu_1_map_reg_t cpu_intr_from_cpu_1_map; - volatile interrupt_matrix_cpu_intr_from_cpu_2_map_reg_t cpu_intr_from_cpu_2_map; - volatile interrupt_matrix_cpu_intr_from_cpu_3_map_reg_t cpu_intr_from_cpu_3_map; - volatile interrupt_matrix_assist_debug_intr_map_reg_t assist_debug_intr_map; - volatile interrupt_matrix_trace_intr_map_reg_t trace_intr_map; - volatile interrupt_matrix_cache_intr_map_reg_t cache_intr_map; - volatile interrupt_matrix_cpu_peri_timeout_intr_map_reg_t cpu_peri_timeout_intr_map; - volatile interrupt_matrix_gpio_interrupt_pro_map_reg_t gpio_interrupt_pro_map; - volatile interrupt_matrix_gpio_interrupt_ext_map_reg_t gpio_interrupt_ext_map; - volatile interrupt_matrix_pau_intr_map_reg_t pau_intr_map; - volatile interrupt_matrix_hp_peri_timeout_intr_map_reg_t hp_peri_timeout_intr_map; - volatile interrupt_matrix_modem_peri_timeout_intr_map_reg_t modem_peri_timeout_intr_map; - volatile interrupt_matrix_hp_apm_m0_intr_map_reg_t hp_apm_m0_intr_map; - volatile interrupt_matrix_hp_apm_m1_intr_map_reg_t hp_apm_m1_intr_map; - volatile interrupt_matrix_hp_apm_m2_intr_map_reg_t hp_apm_m2_intr_map; - volatile interrupt_matrix_hp_apm_m3_intr_map_reg_t hp_apm_m3_intr_map; - volatile interrupt_matrix_mspi_intr_map_reg_t mspi_intr_map; - volatile interrupt_matrix_i2s1_intr_map_reg_t i2s1_intr_map; - volatile interrupt_matrix_uart0_intr_map_reg_t uart0_intr_map; - volatile interrupt_matrix_uart1_intr_map_reg_t uart1_intr_map; - volatile interrupt_matrix_uart2_intr_map_reg_t uart2_intr_map; - volatile interrupt_matrix_ledc_intr_map_reg_t ledc_intr_map; - volatile interrupt_matrix_usb_intr_map_reg_t usb_intr_map; - volatile interrupt_matrix_i2c_ext0_intr_map_reg_t i2c_ext0_intr_map; - volatile interrupt_matrix_tg0_t0_intr_map_reg_t tg0_t0_intr_map; - volatile interrupt_matrix_tg0_t1_intr_map_reg_t tg0_t1_intr_map; - volatile interrupt_matrix_tg0_wdt_intr_map_reg_t tg0_wdt_intr_map; - volatile interrupt_matrix_tg1_t0_intr_map_reg_t tg1_t0_intr_map; - volatile interrupt_matrix_tg1_t1_intr_map_reg_t tg1_t1_intr_map; - volatile interrupt_matrix_tg1_wdt_intr_map_reg_t tg1_wdt_intr_map; - volatile interrupt_matrix_systimer_target0_intr_map_reg_t systimer_target0_intr_map; - volatile interrupt_matrix_systimer_target1_intr_map_reg_t systimer_target1_intr_map; - volatile interrupt_matrix_systimer_target2_intr_map_reg_t systimer_target2_intr_map; - volatile interrupt_matrix_apb_adc_intr_map_reg_t apb_adc_intr_map; - volatile interrupt_matrix_dma_in_ch0_intr_map_reg_t dma_in_ch0_intr_map; - volatile interrupt_matrix_dma_in_ch1_intr_map_reg_t dma_in_ch1_intr_map; - volatile interrupt_matrix_dma_out_ch0_intr_map_reg_t dma_out_ch0_intr_map; - volatile interrupt_matrix_dma_out_ch1_intr_map_reg_t dma_out_ch1_intr_map; - volatile interrupt_matrix_gpspi2_intr_map_reg_t gpspi2_intr_map; - volatile interrupt_matrix_sha_intr_map_reg_t sha_intr_map; - volatile interrupt_matrix_ecc_intr_map_reg_t ecc_intr_map; - volatile interrupt_matrix_ecdsa_intr_map_reg_t ecdsa_intr_map; - volatile interrupt_matrix_int_status_0_reg_t int_status_0; - volatile interrupt_matrix_int_status_1_reg_t int_status_1; - volatile interrupt_matrix_clock_gate_reg_t clock_gate; - uint32_t reserved_104[446]; - volatile interrupt_matrix_interrupt_date_reg_t interrupt_date; + volatile interrupt_core0_wifi_mac_intr_map_reg_t core0_wifi_mac_intr_map; + volatile interrupt_core0_wifi_mac_nmi_map_reg_t core0_wifi_mac_nmi_map; + volatile interrupt_core0_wifi_pwr_intr_map_reg_t core0_wifi_pwr_intr_map; + volatile interrupt_core0_wifi_bb_intr_map_reg_t core0_wifi_bb_intr_map; + volatile interrupt_core0_bt_mac_intr_map_reg_t core0_bt_mac_intr_map; + volatile interrupt_core0_bt_bb_intr_map_reg_t core0_bt_bb_intr_map; + volatile interrupt_core0_bt_bb_nmi_map_reg_t core0_bt_bb_nmi_map; + volatile interrupt_core0_lp_timer_intr_map_reg_t core0_lp_timer_intr_map; + volatile interrupt_core0_coex_intr_map_reg_t core0_coex_intr_map; + volatile interrupt_core0_ble_timer_intr_map_reg_t core0_ble_timer_intr_map; + volatile interrupt_core0_ble_sec_intr_map_reg_t core0_ble_sec_intr_map; + volatile interrupt_core0_i2c_mst_intr_map_reg_t core0_i2c_mst_intr_map; + volatile interrupt_core0_zb_mac_intr_map_reg_t core0_zb_mac_intr_map; + volatile interrupt_core0_pmu_intr_map_reg_t core0_pmu_intr_map; + volatile interrupt_core0_efuse_intr_map_reg_t core0_efuse_intr_map; + volatile interrupt_core0_lp_rtc_timer_intr_map_reg_t core0_lp_rtc_timer_intr_map; + volatile interrupt_core0_lp_wdt_intr_map_reg_t core0_lp_wdt_intr_map; + volatile interrupt_core0_lp_peri_timeout_intr_map_reg_t core0_lp_peri_timeout_intr_map; + volatile interrupt_core0_lp_apm_m0_intr_map_reg_t core0_lp_apm_m0_intr_map; + volatile interrupt_core0_cpu_intr_from_cpu_0_map_reg_t core0_cpu_intr_from_cpu_0_map; + volatile interrupt_core0_cpu_intr_from_cpu_1_map_reg_t core0_cpu_intr_from_cpu_1_map; + volatile interrupt_core0_cpu_intr_from_cpu_2_map_reg_t core0_cpu_intr_from_cpu_2_map; + volatile interrupt_core0_cpu_intr_from_cpu_3_map_reg_t core0_cpu_intr_from_cpu_3_map; + volatile interrupt_core0_assist_debug_intr_map_reg_t core0_assist_debug_intr_map; + volatile interrupt_core0_trace_intr_map_reg_t core0_trace_intr_map; + volatile interrupt_core0_cache_intr_map_reg_t core0_cache_intr_map; + volatile interrupt_core0_cpu_peri_timeout_intr_map_reg_t core0_cpu_peri_timeout_intr_map; + volatile interrupt_core0_gpio_interrupt_pro_map_reg_t core0_gpio_interrupt_pro_map; + volatile interrupt_core0_gpio_interrupt_ext_map_reg_t core0_gpio_interrupt_ext_map; + volatile interrupt_core0_pau_intr_map_reg_t core0_pau_intr_map; + volatile interrupt_core0_hp_peri_timeout_intr_map_reg_t core0_hp_peri_timeout_intr_map; + volatile interrupt_core0_modem_peri_timeout_intr_map_reg_t core0_modem_peri_timeout_intr_map; + volatile interrupt_core0_hp_apm_m0_intr_map_reg_t core0_hp_apm_m0_intr_map; + volatile interrupt_core0_hp_apm_m1_intr_map_reg_t core0_hp_apm_m1_intr_map; + volatile interrupt_core0_hp_apm_m2_intr_map_reg_t core0_hp_apm_m2_intr_map; + volatile interrupt_core0_hp_apm_m3_intr_map_reg_t core0_hp_apm_m3_intr_map; + volatile interrupt_core0_cpu_apm_m0_intr_map_reg_t core0_cpu_apm_m0_intr_map; + volatile interrupt_core0_cpu_apm_m1_intr_map_reg_t core0_cpu_apm_m1_intr_map; + volatile interrupt_core0_mspi_intr_map_reg_t core0_mspi_intr_map; + volatile interrupt_core0_i2s1_intr_map_reg_t core0_i2s1_intr_map; + volatile interrupt_core0_uart0_intr_map_reg_t core0_uart0_intr_map; + volatile interrupt_core0_uart1_intr_map_reg_t core0_uart1_intr_map; + volatile interrupt_core0_uart2_intr_map_reg_t core0_uart2_intr_map; + volatile interrupt_core0_ledc_intr_map_reg_t core0_ledc_intr_map; + volatile interrupt_core0_usb_intr_map_reg_t core0_usb_intr_map; + volatile interrupt_core0_i2c_ext0_intr_map_reg_t core0_i2c_ext0_intr_map; + volatile interrupt_core0_tg0_t0_intr_map_reg_t core0_tg0_t0_intr_map; + volatile interrupt_core0_tg0_t1_intr_map_reg_t core0_tg0_t1_intr_map; + volatile interrupt_core0_tg0_wdt_intr_map_reg_t core0_tg0_wdt_intr_map; + volatile interrupt_core0_tg1_t0_intr_map_reg_t core0_tg1_t0_intr_map; + volatile interrupt_core0_tg1_t1_intr_map_reg_t core0_tg1_t1_intr_map; + volatile interrupt_core0_tg1_wdt_intr_map_reg_t core0_tg1_wdt_intr_map; + volatile interrupt_core0_systimer_target0_intr_map_reg_t core0_systimer_target0_intr_map; + volatile interrupt_core0_systimer_target1_intr_map_reg_t core0_systimer_target1_intr_map; + volatile interrupt_core0_systimer_target2_intr_map_reg_t core0_systimer_target2_intr_map; + volatile interrupt_core0_apb_adc_intr_map_reg_t core0_apb_adc_intr_map; + volatile interrupt_core0_slc0_intr_map_reg_t core0_slc0_intr_map; + volatile interrupt_core0_slc1_intr_map_reg_t core0_slc1_intr_map; + volatile interrupt_core0_dma_in_ch0_intr_map_reg_t core0_dma_in_ch0_intr_map; + volatile interrupt_core0_dma_in_ch1_intr_map_reg_t core0_dma_in_ch1_intr_map; + volatile interrupt_core0_dma_out_ch0_intr_map_reg_t core0_dma_out_ch0_intr_map; + volatile interrupt_core0_dma_out_ch1_intr_map_reg_t core0_dma_out_ch1_intr_map; + volatile interrupt_core0_gpspi2_intr_map_reg_t core0_gpspi2_intr_map; + volatile interrupt_core0_sha_intr_map_reg_t core0_sha_intr_map; + volatile interrupt_core0_ecc_intr_map_reg_t core0_ecc_intr_map; + volatile interrupt_core0_ecdsa_intr_map_reg_t core0_ecdsa_intr_map; + volatile interrupt_core0_int_status_reg_0_reg_t core0_int_status_reg_0; + volatile interrupt_core0_int_status_reg_1_reg_t core0_int_status_reg_1; + volatile interrupt_core0_int_status_reg_2_reg_t core0_int_status_reg_2; + volatile interrupt_core0_src_pass_in_sec_status_0_reg_t core0_src_pass_in_sec_status_0; + volatile interrupt_core0_src_pass_in_sec_status_1_reg_t core0_src_pass_in_sec_status_1; + volatile interrupt_core0_src_pass_in_sec_status_2_reg_t core0_src_pass_in_sec_status_2; + volatile interrupt_core0_sig_idx_assert_in_sec_reg_t core0_sig_idx_assert_in_sec; + volatile interrupt_core0_secure_status_reg_t core0_secure_status; + volatile interrupt_core0_clock_gate_reg_t core0_clock_gate; + uint32_t reserved_12c[436]; + volatile interrupt_core0_interrupt_date_reg_t core0_interrupt_date; } interrupt_matrix_dev_t; extern interrupt_matrix_dev_t INTMTX; diff --git a/components/soc/esp32c61/register/soc/io_mux_reg.h b/components/soc/esp32c61/register/soc/io_mux_reg.h index 78c9face38..9d88d39db7 100644 --- a/components/soc/esp32c61/register/soc/io_mux_reg.h +++ b/components/soc/esp32c61/register/soc/io_mux_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -73,59 +73,38 @@ extern "C" { #define FILTER_EN_V 1 #define FILTER_EN_S 15 -#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE) -#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE) -#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU) -#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD) -#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL) -#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL) +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS1_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_VDD_SPI_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U +#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U +#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_GPIO24_U +#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SDIO_CMD_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SDIO_CLK_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SDIO_DATA0_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SDIO_DATA1_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_GPIO29_U -#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) -#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); -#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) -#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) -#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) -#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) -#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN) -#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN) - -#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P -#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N -#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2 -#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_MTMS -#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_MTDI -#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_MTCK -#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_MTDO -#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_GPIO7 -#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_GPIO8 -#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_GPIO9 -#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_U0RXD -#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_U0TXD -#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_GPIO12 -#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13 -#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_SPICS1 -#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_SPICS0 -#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_SPIQ -#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_SPIWP -#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_VDD_SPI -#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD -#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK -#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID -#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22 -#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23 -#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24 - -#define PIN_FUNC_GPIO 1 - -#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) -#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) +#define PIN_FUNC_GPIO 1 #define USB_INT_PHY0_DM_GPIO_NUM 12 #define USB_INT_PHY0_DP_GPIO_NUM 13 @@ -133,119 +112,143 @@ extern "C" { #define EXT_OSC_SLOW_GPIO_NUM 0 #define MAX_RTC_GPIO_NUM 6 -#define MAX_PAD_GPIO_NUM 24 -#define MAX_GPIO_NUM 28 -#define HIGH_IO_HOLD_BIT_SHIFT 32 +#define MAX_PAD_GPIO_NUM 29 +#define MAX_GPIO_NUM 33 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE // definitions above are inherited from previous version of code, should double check // definitions below are generated from pin_txt.csv -#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x0) -#define FUNC_XTAL_32K_P_GPIO0 1 -#define FUNC_XTAL_32K_P_GPIO0_0 0 +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x0) +#define FUNC_XTAL_32K_P_GPIO0 1 +#define FUNC_XTAL_32K_P_GPIO0_0 0 -#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x4) -#define FUNC_XTAL_32K_N_GPIO1 1 -#define FUNC_XTAL_32K_N_GPIO1_0 0 +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x4) +#define FUNC_XTAL_32K_N_GPIO1_0 0 +#define FUNC_XTAL_32K_N_GPIO1 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8) -#define FUNC_GPIO2_FSPIQ 2 -#define FUNC_GPIO2_GPIO2 1 -#define FUNC_GPIO2_GPIO2_0 0 +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0x8) +#define FUNC_GPIO2_GPIO2_0 0 +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_FSPIQ 2 -#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0xC) -#define FUNC_MTMS_FSPIHD 2 -#define FUNC_MTMS_GPIO3 1 -#define FUNC_MTMS_MTMS 0 +// Strapping: Boot Mode select 0/SDIO input strapping +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0xc) +#define FUNC_MTMS_MTMS 0 +#define FUNC_MTMS_GPIO3 1 +#define FUNC_MTMS_FSPIHD 2 -#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x10) -#define FUNC_MTDI_FSPIWP 2 -#define FUNC_MTDI_GPIO4 1 -#define FUNC_MTDI_MTDI 0 +// Strapping: Boot Mode select 1/SDIO output strapping +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x10) +#define FUNC_MTDI_MTDI 0 +#define FUNC_MTDI_GPIO4 1 +#define FUNC_MTDI_FSPIWP 2 -#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x14) -#define FUNC_MTCK_GPIO5 1 -#define FUNC_MTCK_MTCK 0 +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x14) +#define FUNC_MTCK_MTCK 0 +#define FUNC_MTCK_GPIO5 1 -#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x18) -#define FUNC_MTDO_FSPICLK 2 -#define FUNC_MTDO_GPIO6 1 -#define FUNC_MTDO_MTDO 0 +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x18) +#define FUNC_MTDO_MTDO 0 +#define FUNC_MTDO_GPIO6 1 +#define FUNC_MTDO_FSPICLK 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO7 (REG_IO_MUX_BASE + 0x1C) -#define FUNC_GPIO7_FSPID 2 -#define FUNC_GPIO7_GPIO7 1 -#define FUNC_GPIO7_GPIO7_0 0 +// Strapping: JTAG select +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE + 0x1c) +#define FUNC_GPIO7_GPIO7_0 0 +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_FSPID 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO8 (REG_IO_MUX_BASE + 0x20) -#define FUNC_GPIO8_FSPICS0 2 -#define FUNC_GPIO8_GPIO8 1 -#define FUNC_GPIO8_GPIO8_0 0 +// Strapping: Boot Mode select 2 +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x20) +#define FUNC_GPIO8_GPIO8_0 0 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_FSPICS0 2 -#define PERIPHS_IO_MUX_U_PAD_GPIO9 (REG_IO_MUX_BASE + 0x24) -#define FUNC_GPIO9_GPIO9 1 -#define FUNC_GPIO9_GPIO9_0 0 +// Strapping: Boot Mode select 3 +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x24) +#define FUNC_GPIO9_GPIO9_0 0 +#define FUNC_GPIO9_GPIO9 1 -#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x28) -#define FUNC_U0RXD_GPIO10 1 -#define FUNC_U0RXD_U0RXD 0 +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x28) +#define FUNC_U0RXD_U0RXD 0 +#define FUNC_U0RXD_GPIO10 1 -#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x2C) -#define FUNC_U0TXD_GPIO11 1 -#define FUNC_U0TXD_U0TXD 0 +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x2c) +#define FUNC_U0TXD_U0TXD 0 +#define FUNC_U0TXD_GPIO11 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO12 (REG_IO_MUX_BASE + 0x30) -#define FUNC_GPIO12_GPIO12 1 -#define FUNC_GPIO12_GPIO12_0 0 +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x30) +#define FUNC_GPIO12_GPIO12_0 0 +#define FUNC_GPIO12_GPIO12 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34) -#define FUNC_GPIO13_GPIO13 1 -#define FUNC_GPIO13_GPIO13_0 0 +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x34) +#define FUNC_GPIO13_GPIO13_0 0 +#define FUNC_GPIO13_GPIO13 1 -#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x38) -#define FUNC_SPICS1_GPIO14 1 -#define FUNC_SPICS1_SPICS1 0 +#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE + 0x38) +#define FUNC_SPICS1_SPICS1 0 +#define FUNC_SPICS1_GPIO14 1 -#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x3C) -#define FUNC_SPICS0_GPIO15 1 -#define FUNC_SPICS0_SPICS0 0 +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x3c) +#define FUNC_SPICS0_SPICS0 0 +#define FUNC_SPICS0_GPIO15 1 -#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x40) -#define FUNC_SPIQ_GPIO16 1 -#define FUNC_SPIQ_SPIQ 0 +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x40) +#define FUNC_SPIQ_SPIQ 0 +#define FUNC_SPIQ_GPIO16 1 -#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x44) -#define FUNC_SPIWP_GPIO17 1 -#define FUNC_SPIWP_SPIWP 0 +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x44) +#define FUNC_SPIWP_SPIWP 0 +#define FUNC_SPIWP_GPIO17 1 -#define PERIPHS_IO_MUX_U_PAD_VDD_SPI (REG_IO_MUX_BASE + 0x48) -#define FUNC_VDD_SPI_GPIO18 1 -#define FUNC_VDD_SPI_GPIO18_0 0 +#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x48) +#define FUNC_VDD_SPI_GPIO18_0 0 +#define FUNC_VDD_SPI_GPIO18 1 -#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x4C) -#define FUNC_SPIHD_GPIO19 1 -#define FUNC_SPIHD_SPIHD 0 +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x4c) +#define FUNC_SPIHD_SPIHD 0 +#define FUNC_SPIHD_GPIO19 1 -#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x50) -#define FUNC_SPICLK_GPIO20 1 -#define FUNC_SPICLK_SPICLK 0 +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x50) +#define FUNC_SPICLK_SPICLK 0 +#define FUNC_SPICLK_GPIO20 1 -#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x54) -#define FUNC_SPID_GPIO21 1 -#define FUNC_SPID_SPID 0 +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x54) +#define FUNC_SPID_SPID 0 +#define FUNC_SPID_GPIO21 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58) -#define FUNC_GPIO22_GPIO22 1 -#define FUNC_GPIO22_GPIO22_0 0 +#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x58) +#define FUNC_SDIO_DATA2_SDIO_DATA2 0 +#define FUNC_SDIO_DATA2_GPIO22 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C) -#define FUNC_GPIO23_GPIO23 1 -#define FUNC_GPIO23_GPIO23_0 0 +#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x5c) +#define FUNC_SDIO_DATA3_SDIO_DATA3 0 +#define FUNC_SDIO_DATA3_GPIO23 1 -#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60) -#define FUNC_GPIO24_GPIO24 1 -#define FUNC_GPIO24_GPIO24_0 0 +#define PERIPHS_IO_MUX_GPIO24_U (REG_IO_MUX_BASE + 0x60) +#define FUNC_GPIO24_GPIO24_0 0 +#define FUNC_GPIO24_GPIO24 1 + +#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x64) +#define FUNC_SDIO_CMD_SDIO_CMD 0 +#define FUNC_SDIO_CMD_GPIO25 1 + +#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x68) +#define FUNC_SDIO_CLK_SDIO_CLK 0 +#define FUNC_SDIO_CLK_GPIO26 1 + +#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x6c) +#define FUNC_SDIO_DATA0_SDIO_DATA0 0 +#define FUNC_SDIO_DATA0_GPIO27 1 + +#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x70) +#define FUNC_SDIO_DATA1_SDIO_DATA1 0 +#define FUNC_SDIO_DATA1_GPIO28 1 + +#define PERIPHS_IO_MUX_GPIO29_U (REG_IO_MUX_BASE + 0x74) +#define FUNC_GPIO29_GPIO29_0 0 +#define FUNC_GPIO29_GPIO29 1 /** IO_MUX_DATE_REG register * Version control register diff --git a/components/soc/esp32c61/register/soc/io_mux_struct.h b/components/soc/esp32c61/register/soc/io_mux_struct.h index b4091d4d98..e04f4ba0e0 100644 --- a/components/soc/esp32c61/register/soc/io_mux_struct.h +++ b/components/soc/esp32c61/register/soc/io_mux_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,100 +10,73 @@ extern "C" { #endif -/** Group: Configuration Registers */ +/** Group: Configure Registers */ /** Type of gpion register - * IO MUX configuration register for GPIOn + * IO_MUX Configure Register */ typedef union { struct { /** gpion_mcu_oe : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable the output of GPIOn in sleep mode. - * 0: Disable\\ - * 1: Enable\\ + * Output enable of the pad in sleep mode. 1: output enabled. 0: output disabled. */ uint32_t gpion_mcu_oe:1; /** gpion_slp_sel : R/W; bitpos: [1]; default: 0; - * Configures whether or not to enter sleep mode for GPIOn.\\ - * 0: Not enter\\ - * 1: Enter\\ + * Sleep mode selection of this pad. Set to 1 to put the pad in pad mode. */ uint32_t gpion_slp_sel:1; /** gpion_mcu_wpd : R/W; bitpos: [2]; default: 0; - * Configure whether or not to enable pull-down resistor of GPIOn in sleep mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled. 0: + * internal pull-down disabled. */ uint32_t gpion_mcu_wpd:1; /** gpion_mcu_wpu : R/W; bitpos: [3]; default: 0; - * Configures whether or not to enable pull-up resistor of GPIOn during sleep mode. \\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled. 0: + * internal pull-up disabled. */ uint32_t gpion_mcu_wpu:1; /** gpion_mcu_ie : R/W; bitpos: [4]; default: 0; - * Configures whether or not to enable the input of GPIOn during sleep mode.\\ - * 0: Disable\\ - * 1: Enable\\ + * Input enable of the pad during sleep mode. 1: input enabled. 0: input disabled. */ uint32_t gpion_mcu_ie:1; /** gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0; - * Configures the drive strength of GPIOn during sleep mode. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad during sleep mode. */ uint32_t gpion_mcu_drv:2; /** gpion_fun_wpd : R/W; bitpos: [7]; default: 0; - * Configures whether or not to enable pull-down resistor of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-down enable of the pad. 1: internal pull-down enabled. 0: internal pull-down + * disabled. */ uint32_t gpion_fun_wpd:1; /** gpion_fun_wpu : R/W; bitpos: [8]; default: 0; - * Configures whether or not enable pull-up resistor of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Pull-up enable of the pad. 1: internal pull-up enabled. 0: internal pull-up + * disabled. */ uint32_t gpion_fun_wpu:1; /** gpion_fun_ie : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable input of GPIOn.\\ - * 0: Disable\\ - * 1: Enable\\ + * Input enable of the pad. 1: input enabled. 0: input disabled. */ uint32_t gpion_fun_ie:1; /** gpion_fun_drv : R/W; bitpos: [11:10]; default: 2; - * Configures the drive strength of GPIOn. \\ - * 0: ~5 mA\\ - * 1: ~10 mA\\ - * 2: ~20 mA\\ - * 3: ~40 mA\\ + * Select the drive strength of the pad. */ uint32_t gpion_fun_drv:2; /** gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1; - * Configures to select IO MUX function for this signal. \\ - * 0: Select Function 0\\ - * 1: Select Function 1\\ - * ......\\ + * Select IO MUX function for this signal. 0: Select Function 1. 1: Select Function 2. + * etc. */ uint32_t gpion_mcu_sel:3; /** gpion_filter_en : R/W; bitpos: [15]; default: 0; - * Configures whether or not to enable filter for pin input signals.\\ - * 0: Disable\\ - * 1: Enable\\ + * Enable filter for pin input signals. 1: Filter enabled. 0: Filter disabled. */ uint32_t gpion_filter_en:1; /** gpion_hys_en : R/W; bitpos: [16]; default: 0; - * Configures whether or not to enable the hysteresis function of the pin when - * IO_MUX_GPIOn_HYS_SEL is set to 1.\\ - * 0: Disable\\ - * 1: Enable\\ + * Software enables hysteresis function for the pad. 1: Hysteresis enabled. 0: + * Hysteresis disabled. */ uint32_t gpion_hys_en:1; /** gpion_hys_sel : R/W; bitpos: [17]; default: 0; - * Configures to choose the signal for enabling the hysteresis function for GPIOn. \\ - * 0: Choose the output enable signal of eFuse, there is no efuse bit for it, should never set to 0\\ - * 1: Choose the output enable signal of IO_MUX_GPIOn_HYS_EN, always set to 1\\ + * Select enabling signals of the pad from software and efuse hardware. 1: Select + * enabling signal from slftware. 0: Select enabling signal from efuse hardware. */ uint32_t gpion_hys_sel:1; uint32_t reserved_18:14; @@ -111,14 +84,12 @@ typedef union { uint32_t val; } io_mux_gpion_reg_t; - -/** Group: Version Register */ /** Type of date register - * Version control register + * IO_MUX Version Control Register */ typedef union { struct { - /** reg_date : R/W; bitpos: [27:0]; default: 36774288; + /** reg_date : R/W; bitpos: [27:0]; default: 37823072; * Version control register */ uint32_t reg_date:28; @@ -129,8 +100,8 @@ typedef union { typedef struct { - volatile io_mux_gpion_reg_t gpion[25]; - uint32_t reserved_064[102]; + volatile io_mux_gpion_reg_t gpion[30]; + uint32_t reserved_078[97]; volatile io_mux_date_reg_t date; } io_mux_dev_t; diff --git a/components/soc/esp32c61/register/soc/lp_aon_reg.h b/components/soc/esp32c61/register/soc/lp_aon_reg.h index 7ed2a522c4..5979338227 100644 --- a/components/soc/esp32c61/register/soc/lp_aon_reg.h +++ b/components/soc/esp32c61/register/soc/lp_aon_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -290,31 +290,17 @@ extern "C" { #define LP_AON_USB_RESET_DISABLE_V 0x00000001U #define LP_AON_USB_RESET_DISABLE_S 31 -/** LP_AON_LPBUS_REG register +/** LP_AON_SDIO_ACTIVE_REG register * need_des */ -#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) -/** LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. +#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) +/** LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; + * need_des */ -#define LP_AON_FAST_MEM_WPULSE 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) -#define LP_AON_FAST_MEM_WPULSE_V 0x00000007U -#define LP_AON_FAST_MEM_WPULSE_S 16 -/** LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ -#define LP_AON_FAST_MEM_WA 0x00000007U -#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) -#define LP_AON_FAST_MEM_WA_V 0x00000007U -#define LP_AON_FAST_MEM_WA_S 19 -/** LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ -#define LP_AON_FAST_MEM_RA 0x00000003U -#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) -#define LP_AON_FAST_MEM_RA_V 0x00000003U -#define LP_AON_FAST_MEM_RA_S 22 +#define LP_AON_SDIO_ACT_DNUM 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) +#define LP_AON_SDIO_ACT_DNUM_V 0x000003FFU +#define LP_AON_SDIO_ACT_DNUM_S 22 /** LP_AON_LPCORE_REG register * need_des @@ -439,7 +425,7 @@ extern "C" { * need_des */ #define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) -/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 36766272; +/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823232; * need_des */ #define LP_AON_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/lp_aon_struct.h b/components/soc/esp32c61/register/soc/lp_aon_struct.h index 96660def85..77a93971bc 100644 --- a/components/soc/esp32c61/register/soc/lp_aon_struct.h +++ b/components/soc/esp32c61/register/soc/lp_aon_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -287,28 +287,19 @@ typedef union { uint32_t val; } lp_aon_usb_reg_t; -/** Type of lpbus register +/** Type of sdio_active register * need_des */ typedef union { struct { - uint32_t reserved_0:16; - /** fast_mem_wpulse : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. + uint32_t reserved_0:22; + /** sdio_act_dnum : R/W; bitpos: [31:22]; default: 10; + * need_des */ - uint32_t fast_mem_wpulse:3; - /** fast_mem_wa : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ - uint32_t fast_mem_wa:3; - /** fast_mem_ra : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ - uint32_t fast_mem_ra:2; - uint32_t reserved_24:8; + uint32_t sdio_act_dnum:10; }; uint32_t val; -} lp_aon_lpbus_reg_t; +} lp_aon_sdio_active_reg_t; /** Type of lpcore register * need_des @@ -405,7 +396,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [30:0]; default: 36766272; + /** date : R/W; bitpos: [30:0]; default: 37823232; * need_des */ uint32_t date:31; @@ -465,8 +456,8 @@ typedef struct { volatile lp_aon_io_mux_reg_t io_mux; volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl; volatile lp_aon_usb_reg_t usb; - volatile lp_aon_lpbus_reg_t lpbus; - uint32_t reserved_04c; + uint32_t reserved_048; + volatile lp_aon_sdio_active_reg_t sdio_active; volatile lp_aon_lpcore_reg_t lpcore; volatile lp_aon_sar_cct_reg_t sar_cct; volatile lp_aon_modem_bus_reg_t modem_bus; diff --git a/components/soc/esp32c61/register/soc/pcr_reg.h b/components/soc/esp32c61/register/soc/pcr_reg.h index feedd3ae52..c6d3a60ba9 100644 --- a/components/soc/esp32c61/register/soc/pcr_reg.h +++ b/components/soc/esp32c61/register/soc/pcr_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,7 @@ extern "C" { #define PCR_UART0_CLK_EN_V 0x00000001U #define PCR_UART0_CLK_EN_S 0 /** PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ #define PCR_UART0_RST_EN (BIT(1)) #define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) @@ -63,10 +63,10 @@ extern "C" { #define PCR_UART0_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART0_SCLK_DIV_NUM_S 12 /** PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART0_SCLK_SEL 0x00000003U #define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) @@ -111,7 +111,7 @@ extern "C" { #define PCR_UART1_CLK_EN_V 0x00000001U #define PCR_UART1_CLK_EN_S 0 /** PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ #define PCR_UART1_RST_EN (BIT(1)) #define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) @@ -151,10 +151,10 @@ extern "C" { #define PCR_UART1_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART1_SCLK_DIV_NUM_S 12 /** PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART1_SCLK_SEL 0x00000003U #define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) @@ -199,7 +199,7 @@ extern "C" { #define PCR_UART2_CLK_EN_V 0x00000001U #define PCR_UART2_CLK_EN_S 0 /** PCR_UART2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart2 module + * Set 1 to reset uart2 module */ #define PCR_UART2_RST_EN (BIT(1)) #define PCR_UART2_RST_EN_M (PCR_UART2_RST_EN_V << PCR_UART2_RST_EN_S) @@ -239,10 +239,10 @@ extern "C" { #define PCR_UART2_SCLK_DIV_NUM_V 0x000000FFU #define PCR_UART2_SCLK_DIV_NUM_S 12 /** PCR_UART2_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART2.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART2. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_UART2_SCLK_SEL 0x00000003U #define PCR_UART2_SCLK_SEL_M (PCR_UART2_SCLK_SEL_V << PCR_UART2_SCLK_SEL_S) @@ -287,7 +287,7 @@ extern "C" { #define PCR_MSPI_CLK_EN_V 0x00000001U #define PCR_MSPI_CLK_EN_S 0 /** PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ #define PCR_MSPI_RST_EN (BIT(1)) #define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) @@ -322,10 +322,10 @@ extern "C" { #define PCR_MSPI_FAST_DIV_NUM_V 0x000000FFU #define PCR_MSPI_FAST_DIV_NUM_S 0 /** PCR_MSPI_FUNC_CLK_SEL : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_MSPI_FUNC_CLK_SEL 0x00000003U #define PCR_MSPI_FUNC_CLK_SEL_M (PCR_MSPI_FUNC_CLK_SEL_V << PCR_MSPI_FUNC_CLK_SEL_S) @@ -339,7 +339,7 @@ extern "C" { #define PCR_MSPI_FUNC_CLK_EN_V 0x00000001U #define PCR_MSPI_FUNC_CLK_EN_S 10 /** PCR_MSPI_AXI_RST_EN : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ #define PCR_MSPI_AXI_RST_EN (BIT(11)) #define PCR_MSPI_AXI_RST_EN_M (PCR_MSPI_AXI_RST_EN_V << PCR_MSPI_AXI_RST_EN_S) @@ -358,7 +358,7 @@ extern "C" { #define PCR_I2C_CLK_EN_V 0x00000001U #define PCR_I2C_CLK_EN_S 0 /** PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ #define PCR_I2C_RST_EN (BIT(1)) #define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) @@ -391,9 +391,9 @@ extern "C" { #define PCR_I2C_SCLK_DIV_NUM_V 0x000000FFU #define PCR_I2C_SCLK_DIV_NUM_S 12 /** PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_I2C_SCLK_SEL (BIT(20)) #define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) @@ -419,7 +419,7 @@ extern "C" { #define PCR_LEDC_CLK_EN_V 0x00000001U #define PCR_LEDC_CLK_EN_S 0 /** PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ #define PCR_LEDC_RST_EN (BIT(1)) #define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) @@ -438,10 +438,10 @@ extern "C" { */ #define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) /** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_LEDC_SCLK_SEL 0x00000003U #define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) @@ -486,7 +486,7 @@ extern "C" { #define PCR_TG0_CLK_EN_V 0x00000001U #define PCR_TG0_CLK_EN_S 0 /** PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ #define PCR_TG0_RST_EN (BIT(1)) #define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) @@ -519,10 +519,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) /** PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_TIMER_CLK_SEL 0x00000003U #define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) @@ -541,10 +541,10 @@ extern "C" { */ #define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x48) /** PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG0_WDT_CLK_SEL 0x00000003U #define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) @@ -570,7 +570,7 @@ extern "C" { #define PCR_TG1_CLK_EN_V 0x00000001U #define PCR_TG1_CLK_EN_S 0 /** PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ #define PCR_TG1_RST_EN (BIT(1)) #define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) @@ -603,10 +603,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) /** PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_TIMER_CLK_SEL 0x00000003U #define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) @@ -625,10 +625,10 @@ extern "C" { */ #define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x54) /** PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_TG1_WDT_CLK_SEL 0x00000003U #define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) @@ -654,7 +654,7 @@ extern "C" { #define PCR_SYSTIMER_CLK_EN_V 0x00000001U #define PCR_SYSTIMER_CLK_EN_S 0 /** PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ #define PCR_SYSTIMER_RST_EN (BIT(1)) #define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) @@ -673,9 +673,9 @@ extern "C" { */ #define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x5c) /** PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) #define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) @@ -701,7 +701,7 @@ extern "C" { #define PCR_I2S_CLK_EN_V 0x00000001U #define PCR_I2S_CLK_EN_S 0 /** PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ #define PCR_I2S_RST_EN (BIT(1)) #define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) @@ -737,11 +737,11 @@ extern "C" { #define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_TX_CLKM_DIV_NUM_S 12 /** PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_TX_CLKM_SEL 0x00000003U #define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) @@ -804,11 +804,11 @@ extern "C" { #define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000FFU #define PCR_I2S_RX_CLKM_DIV_NUM_S 12 /** PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ #define PCR_I2S_RX_CLKM_SEL 0x00000003U #define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) @@ -822,9 +822,9 @@ extern "C" { #define PCR_I2S_RX_CLKM_EN_V 0x00000001U #define PCR_I2S_RX_CLKM_EN_S 22 /** PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ #define PCR_I2S_MCLK_SEL (BIT(23)) #define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) @@ -880,7 +880,7 @@ extern "C" { #define PCR_SARADC_CLK_EN_V 0x00000001U #define PCR_SARADC_CLK_EN_S 0 /** PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ #define PCR_SARADC_RST_EN (BIT(1)) #define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) @@ -894,7 +894,7 @@ extern "C" { #define PCR_SARADC_REG_CLK_EN_V 0x00000001U #define PCR_SARADC_REG_CLK_EN_S 2 /** PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ #define PCR_SARADC_REG_RST_EN (BIT(3)) #define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) @@ -927,10 +927,10 @@ extern "C" { #define PCR_SARADC_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SARADC_CLKM_DIV_NUM_S 12 /** PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_SARADC_CLKM_SEL 0x00000003U #define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) @@ -949,9 +949,9 @@ extern "C" { */ #define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x7c) /** PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ #define PCR_TSENS_CLK_SEL (BIT(20)) #define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) @@ -965,7 +965,7 @@ extern "C" { #define PCR_TSENS_CLK_EN_V 0x00000001U #define PCR_TSENS_CLK_EN_S 22 /** PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ #define PCR_TSENS_RST_EN (BIT(23)) #define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) @@ -984,7 +984,7 @@ extern "C" { #define PCR_USB_DEVICE_CLK_EN_V 0x00000001U #define PCR_USB_DEVICE_CLK_EN_S 0 /** PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ #define PCR_USB_DEVICE_RST_EN (BIT(1)) #define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) @@ -1010,7 +1010,7 @@ extern "C" { #define PCR_INTMTX_CLK_EN_V 0x00000001U #define PCR_INTMTX_CLK_EN_S 0 /** PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ #define PCR_INTMTX_RST_EN (BIT(1)) #define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) @@ -1076,9 +1076,9 @@ extern "C" { #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000FU #define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 /** PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ #define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) #define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) @@ -1104,7 +1104,7 @@ extern "C" { #define PCR_GDMA_CLK_EN_V 0x00000001U #define PCR_GDMA_CLK_EN_S 0 /** PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ #define PCR_GDMA_RST_EN (BIT(1)) #define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) @@ -1123,7 +1123,7 @@ extern "C" { #define PCR_SPI2_CLK_EN_V 0x00000001U #define PCR_SPI2_CLK_EN_S 0 /** PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ #define PCR_SPI2_RST_EN (BIT(1)) #define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) @@ -1149,10 +1149,10 @@ extern "C" { #define PCR_SPI2_CLKM_DIV_NUM_V 0x000000FFU #define PCR_SPI2_CLKM_DIV_NUM_S 12 /** PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK */ #define PCR_SPI2_CLKM_SEL 0x00000003U #define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) @@ -1178,7 +1178,7 @@ extern "C" { #define PCR_AES_CLK_EN_V 0x00000001U #define PCR_AES_CLK_EN_S 0 /** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ #define PCR_AES_RST_EN (BIT(1)) #define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) @@ -1204,7 +1204,7 @@ extern "C" { #define PCR_SHA_CLK_EN_V 0x00000001U #define PCR_SHA_CLK_EN_S 0 /** PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ #define PCR_SHA_RST_EN (BIT(1)) #define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) @@ -1230,7 +1230,7 @@ extern "C" { #define PCR_RSA_CLK_EN_V 0x00000001U #define PCR_RSA_CLK_EN_S 0 /** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ #define PCR_RSA_RST_EN (BIT(1)) #define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) @@ -1282,7 +1282,7 @@ extern "C" { #define PCR_ECC_CLK_EN_V 0x00000001U #define PCR_ECC_CLK_EN_S 0 /** PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ #define PCR_ECC_RST_EN (BIT(1)) #define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) @@ -1334,7 +1334,7 @@ extern "C" { #define PCR_DS_CLK_EN_V 0x00000001U #define PCR_DS_CLK_EN_S 0 /** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ #define PCR_DS_RST_EN (BIT(1)) #define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) @@ -1360,7 +1360,7 @@ extern "C" { #define PCR_HMAC_CLK_EN_V 0x00000001U #define PCR_HMAC_CLK_EN_S 0 /** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ #define PCR_HMAC_RST_EN (BIT(1)) #define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) @@ -1386,7 +1386,7 @@ extern "C" { #define PCR_ECDSA_CLK_EN_V 0x00000001U #define PCR_ECDSA_CLK_EN_S 0 /** PCR_ECDSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ #define PCR_ECDSA_RST_EN (BIT(1)) #define PCR_ECDSA_RST_EN_M (PCR_ECDSA_RST_EN_V << PCR_ECDSA_RST_EN_S) @@ -1412,7 +1412,7 @@ extern "C" { #define PCR_IOMUX_CLK_EN_V 0x00000001U #define PCR_IOMUX_CLK_EN_S 0 /** PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ #define PCR_IOMUX_RST_EN (BIT(1)) #define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) @@ -1424,10 +1424,10 @@ extern "C" { */ #define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xc4) /** PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ #define PCR_IOMUX_FUNC_CLK_SEL 0x00000003U #define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) @@ -1453,7 +1453,7 @@ extern "C" { #define PCR_TCM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_TCM_MEM_MONITOR_CLK_EN_S 0 /** PCR_TCM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ #define PCR_TCM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_TCM_MEM_MONITOR_RST_EN_M (PCR_TCM_MEM_MONITOR_RST_EN_V << PCR_TCM_MEM_MONITOR_RST_EN_S) @@ -1479,7 +1479,7 @@ extern "C" { #define PCR_PSRAM_MEM_MONITOR_CLK_EN_V 0x00000001U #define PCR_PSRAM_MEM_MONITOR_CLK_EN_S 0 /** PCR_PSRAM_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ #define PCR_PSRAM_MEM_MONITOR_RST_EN (BIT(1)) #define PCR_PSRAM_MEM_MONITOR_RST_EN_M (PCR_PSRAM_MEM_MONITOR_RST_EN_V << PCR_PSRAM_MEM_MONITOR_RST_EN_S) @@ -1505,7 +1505,7 @@ extern "C" { #define PCR_TRACE_CLK_EN_V 0x00000001U #define PCR_TRACE_CLK_EN_S 0 /** PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ #define PCR_TRACE_RST_EN (BIT(1)) #define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) @@ -1524,7 +1524,7 @@ extern "C" { #define PCR_ASSIST_CLK_EN_V 0x00000001U #define PCR_ASSIST_CLK_EN_S 0 /** PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ #define PCR_ASSIST_RST_EN (BIT(1)) #define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) @@ -1543,7 +1543,7 @@ extern "C" { #define PCR_CACHE_CLK_EN_V 0x00000001U #define PCR_CACHE_CLK_EN_S 0 /** PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ #define PCR_CACHE_RST_EN (BIT(1)) #define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) @@ -1601,14 +1601,14 @@ extern "C" { */ #define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0xe4) /** PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ #define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) #define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) #define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001U #define PCR_CPU_TIMEOUT_RST_EN_S 1 /** PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ #define PCR_HP_TIMEOUT_RST_EN (BIT(2)) #define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) @@ -1619,11 +1619,26 @@ extern "C" { * SYSCLK configuration register */ #define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0xe8) +/** PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ +#define PCR_LS_DIV_NUM 0x000000FFU +#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) +#define PCR_LS_DIV_NUM_V 0x000000FFU +#define PCR_LS_DIV_NUM_S 0 +/** PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ +#define PCR_HS_DIV_NUM 0x000000FFU +#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) +#define PCR_HS_DIV_NUM_V 0x000000FFU +#define PCR_HS_DIV_NUM_S 8 /** PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ #define PCR_SOC_CLK_SEL 0x00000003U #define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) @@ -1649,20 +1664,6 @@ extern "C" { * CPU_WAITI configuration register */ #define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0xec) -/** PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_CPUPERIOD_SEL 0x00000003U -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003U -#define PCR_CPUPERIOD_SEL_S 0 -/** PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001U -#define PCR_PLL_FREQ_SEL_S 2 /** PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1684,7 +1685,7 @@ extern "C" { */ #define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf0) /** PCR_CPU_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1698,7 +1699,7 @@ extern "C" { */ #define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0xf4) /** PCR_AHB_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -1726,7 +1727,7 @@ extern "C" { #define PCR_APB_DECREASE_DIV_NUM_V 0x000000FFU #define PCR_APB_DECREASE_DIV_NUM_S 0 /** PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ #define PCR_APB_DIV_NUM 0x000000FFU @@ -1758,7 +1759,7 @@ extern "C" { */ #define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x100) /** PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_160M_CLK_EN (BIT(1)) @@ -1766,7 +1767,7 @@ extern "C" { #define PCR_PLL_160M_CLK_EN_V 0x00000001U #define PCR_PLL_160M_CLK_EN_S 1 /** PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_120M_CLK_EN (BIT(2)) @@ -1774,7 +1775,7 @@ extern "C" { #define PCR_PLL_120M_CLK_EN_V 0x00000001U #define PCR_PLL_120M_CLK_EN_S 2 /** PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_80M_CLK_EN (BIT(3)) @@ -1782,7 +1783,7 @@ extern "C" { #define PCR_PLL_80M_CLK_EN_V 0x00000001U #define PCR_PLL_80M_CLK_EN_S 3 /** PCR_PLL_60M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_60M_CLK_EN (BIT(4)) @@ -1790,7 +1791,7 @@ extern "C" { #define PCR_PLL_60M_CLK_EN_V 0x00000001U #define PCR_PLL_60M_CLK_EN_S 4 /** PCR_PLL_48M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_48M_CLK_EN (BIT(5)) @@ -1798,7 +1799,7 @@ extern "C" { #define PCR_PLL_48M_CLK_EN_V 0x00000001U #define PCR_PLL_48M_CLK_EN_S 5 /** PCR_PLL_40M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_40M_CLK_EN (BIT(6)) @@ -1806,21 +1807,13 @@ extern "C" { #define PCR_PLL_40M_CLK_EN_V 0x00000001U #define PCR_PLL_40M_CLK_EN_S 6 /** PCR_PLL_20M_CLK_EN : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ #define PCR_PLL_20M_CLK_EN (BIT(7)) #define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) #define PCR_PLL_20M_CLK_EN_V 0x00000001U #define PCR_PLL_20M_CLK_EN_S 7 -/** PCR_PLL_12M_CLK_EN : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, - * 1: open(default). Only available when high-speed clock-source SPLL is active. - */ -#define PCR_PLL_12M_CLK_EN (BIT(8)) -#define PCR_PLL_12M_CLK_EN_M (PCR_PLL_12M_CLK_EN_V << PCR_PLL_12M_CLK_EN_S) -#define PCR_PLL_12M_CLK_EN_V 0x00000001U -#define PCR_PLL_12M_CLK_EN_S 8 /** PCR_CTRL_CLK_OUT_EN_REG register * CLK_OUT_EN configuration register @@ -1902,12 +1895,12 @@ extern "C" { */ #define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x10c) /** PCR_32K_SEL : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ #define PCR_32K_SEL 0x00000007U #define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) @@ -1982,52 +1975,33 @@ extern "C" { #define PCR_SEC_CONF_REG (DR_REG_PCR_BASE + 0x118) /** PCR_SEC_CLK_SEL : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ #define PCR_SEC_CLK_SEL 0x00000003U #define PCR_SEC_CLK_SEL_M (PCR_SEC_CLK_SEL_V << PCR_SEC_CLK_SEL_S) #define PCR_SEC_CLK_SEL_V 0x00000003U #define PCR_SEC_CLK_SEL_S 0 /** PCR_SEC_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ #define PCR_SEC_RST_EN (BIT(2)) #define PCR_SEC_RST_EN_M (PCR_SEC_RST_EN_V << PCR_SEC_RST_EN_S) #define PCR_SEC_RST_EN_V 0x00000001U #define PCR_SEC_RST_EN_S 2 -/** PCR_ADC_DAC_INV_PHASE_CONF_REG register - * xxxx - */ -#define PCR_ADC_DAC_INV_PHASE_CONF_REG (DR_REG_PCR_BASE + 0x11c) -/** PCR_CLK_RX_ADC_INV_PHASE_ENA : R/W; bitpos: [0]; default: 0; - * xxxx - */ -#define PCR_CLK_RX_ADC_INV_PHASE_ENA (BIT(0)) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_M (PCR_CLK_RX_ADC_INV_PHASE_ENA_V << PCR_CLK_RX_ADC_INV_PHASE_ENA_S) -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_RX_ADC_INV_PHASE_ENA_S 0 -/** PCR_CLK_TX_DAC_INV_PHASE_ENA : R/W; bitpos: [1]; default: 0; - * xxxx - */ -#define PCR_CLK_TX_DAC_INV_PHASE_ENA (BIT(1)) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_M (PCR_CLK_TX_DAC_INV_PHASE_ENA_V << PCR_CLK_TX_DAC_INV_PHASE_ENA_S) -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_V 0x00000001U -#define PCR_CLK_TX_DAC_INV_PHASE_ENA_S 1 - /** PCR_BUS_CLK_UPDATE_REG register * Configuration register for applying updated high-performance system clock sources */ #define PCR_BUS_CLK_UPDATE_REG (DR_REG_PCR_BASE + 0x120) /** PCR_BUS_CLOCK_UPDATE : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ #define PCR_BUS_CLOCK_UPDATE (BIT(0)) #define PCR_BUS_CLOCK_UPDATE_M (PCR_BUS_CLOCK_UPDATE_V << PCR_BUS_CLOCK_UPDATE_S) @@ -2039,54 +2013,33 @@ extern "C" { */ #define PCR_SAR_CLK_DIV_REG (DR_REG_PCR_BASE + 0x124) /** PCR_SAR2_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ #define PCR_SAR2_CLK_DIV_NUM 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_M (PCR_SAR2_CLK_DIV_NUM_V << PCR_SAR2_CLK_DIV_NUM_S) #define PCR_SAR2_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR2_CLK_DIV_NUM_S 0 /** PCR_SAR1_CLK_DIV_NUM : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ #define PCR_SAR1_CLK_DIV_NUM 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_M (PCR_SAR1_CLK_DIV_NUM_V << PCR_SAR1_CLK_DIV_NUM_S) #define PCR_SAR1_CLK_DIV_NUM_V 0x000000FFU #define PCR_SAR1_CLK_DIV_NUM_S 8 -/** PCR_PWDET_SAR_CLK_CONF_REG register - * xxxx - */ -#define PCR_PWDET_SAR_CLK_CONF_REG (DR_REG_PCR_BASE + 0x128) -/** PCR_PWDET_SAR_CLK_DIV_NUM : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_DIV_NUM 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_M (PCR_PWDET_SAR_CLK_DIV_NUM_V << PCR_PWDET_SAR_CLK_DIV_NUM_S) -#define PCR_PWDET_SAR_CLK_DIV_NUM_V 0x000000FFU -#define PCR_PWDET_SAR_CLK_DIV_NUM_S 0 -/** PCR_PWDET_SAR_CLK_EN : R/W; bitpos: [8]; default: 1; - * xxxx - */ -#define PCR_PWDET_SAR_CLK_EN (BIT(8)) -#define PCR_PWDET_SAR_CLK_EN_M (PCR_PWDET_SAR_CLK_EN_V << PCR_PWDET_SAR_CLK_EN_S) -#define PCR_PWDET_SAR_CLK_EN_V 0x00000001U -#define PCR_PWDET_SAR_CLK_EN_S 8 - /** PCR_TIMERGROUP_WDT_CONF_REG register * TIMERGROUP_WDT configuration register */ #define PCR_TIMERGROUP_WDT_CONF_REG (DR_REG_PCR_BASE + 0x12c) /** PCR_TG0_WDT_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ #define PCR_TG0_WDT_RST_EN (BIT(0)) #define PCR_TG0_WDT_RST_EN_M (PCR_TG0_WDT_RST_EN_V << PCR_TG0_WDT_RST_EN_S) #define PCR_TG0_WDT_RST_EN_V 0x00000001U #define PCR_TG0_WDT_RST_EN_S 0 /** PCR_TG1_WDT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ #define PCR_TG1_WDT_RST_EN (BIT(1)) #define PCR_TG1_WDT_RST_EN_M (PCR_TG1_WDT_RST_EN_V << PCR_TG1_WDT_RST_EN_S) @@ -2098,14 +2051,14 @@ extern "C" { */ #define PCR_TIMERGROUP_XTAL_CONF_REG (DR_REG_PCR_BASE + 0x130) /** PCR_TG0_XTAL_RST_EN : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ #define PCR_TG0_XTAL_RST_EN (BIT(0)) #define PCR_TG0_XTAL_RST_EN_M (PCR_TG0_XTAL_RST_EN_V << PCR_TG0_XTAL_RST_EN_S) #define PCR_TG0_XTAL_RST_EN_V 0x00000001U #define PCR_TG0_XTAL_RST_EN_S 0 /** PCR_TG1_XTAL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ #define PCR_TG1_XTAL_RST_EN (BIT(1)) #define PCR_TG1_XTAL_RST_EN_M (PCR_TG1_XTAL_RST_EN_V << PCR_TG1_XTAL_RST_EN_S) @@ -2156,7 +2109,7 @@ extern "C" { #define PCR_REGDMA_CLK_EN_V 0x00000001U #define PCR_REGDMA_CLK_EN_S 0 /** PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ #define PCR_REGDMA_RST_EN (BIT(1)) #define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) @@ -2175,7 +2128,7 @@ extern "C" { #define PCR_ETM_CLK_EN_V 0x00000001U #define PCR_ETM_CLK_EN_S 0 /** PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ #define PCR_ETM_RST_EN (BIT(1)) #define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) @@ -2189,35 +2142,49 @@ extern "C" { #define PCR_ETM_READY_V 0x00000001U #define PCR_ETM_READY_S 2 -/** PCR_FPGA_DEBUG_REG register - * fpga debug register +/** PCR_SDIO_SLAVE_CONF_REG register + * SDIO_SLAVE configuration register */ -#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) -/** PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. +#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0x158) +/** PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock */ -#define PCR_FPGA_DEBUG 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) -#define PCR_FPGA_DEBUG_V 0xFFFFFFFFU -#define PCR_FPGA_DEBUG_S 0 +#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) +#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) +#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_CLK_EN_S 0 +/** PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ +#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) +#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) +#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001U +#define PCR_SDIO_SLAVE_RST_EN_S 1 -/** PCR_CLOCK_GATE_REG register - * PCR clock gating configure register +/** PCR_SDIO_SLAVE_PD_CTRL_REG register + * LEDC power control register */ -#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) -/** PCR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. +#define PCR_SDIO_SLAVE_PD_CTRL_REG (DR_REG_PCR_BASE + 0x15c) +/** PCR_SDIO_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down SDIO memory. */ -#define PCR_CLK_EN (BIT(0)) -#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) -#define PCR_CLK_EN_V 0x00000001U -#define PCR_CLK_EN_S 0 +#define PCR_SDIO_MEM_FORCE_PU (BIT(1)) +#define PCR_SDIO_MEM_FORCE_PU_M (PCR_SDIO_MEM_FORCE_PU_V << PCR_SDIO_MEM_FORCE_PU_S) +#define PCR_SDIO_MEM_FORCE_PU_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PU_S 1 +/** PCR_SDIO_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up SDIO memory. + */ +#define PCR_SDIO_MEM_FORCE_PD (BIT(2)) +#define PCR_SDIO_MEM_FORCE_PD_M (PCR_SDIO_MEM_FORCE_PD_V << PCR_SDIO_MEM_FORCE_PD_S) +#define PCR_SDIO_MEM_FORCE_PD_V 0x00000001U +#define PCR_SDIO_MEM_FORCE_PD_S 2 /** PCR_DATE_REG register * Date register. */ #define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) -/** PCR_DATE : R/W; bitpos: [27:0]; default: 37753376; +/** PCR_DATE : R/W; bitpos: [27:0]; default: 37823120; * PCR version information. */ #define PCR_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/pcr_struct.h b/components/soc/esp32c61/register/soc/pcr_struct.h index 0591f845ef..9e36f9e790 100644 --- a/components/soc/esp32c61/register/soc/pcr_struct.h +++ b/components/soc/esp32c61/register/soc/pcr_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -21,7 +21,7 @@ typedef union { */ uint32_t uart0_clk_en:1; /** uart0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module + * Set 1 to reset uart0 module */ uint32_t uart0_rst_en:1; /** uart0_ready : RO; bitpos: [2]; default: 1; @@ -51,10 +51,10 @@ typedef union { */ uint32_t uart0_sclk_div_num:8; /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart0_sclk_sel:2; /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; @@ -95,7 +95,7 @@ typedef union { */ uint32_t uart1_clk_en:1; /** uart1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module + * Set 1 to reset uart1 module */ uint32_t uart1_rst_en:1; /** uart1_ready : RO; bitpos: [2]; default: 1; @@ -125,10 +125,10 @@ typedef union { */ uint32_t uart1_sclk_div_num:8; /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart1_sclk_sel:2; /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; @@ -169,7 +169,7 @@ typedef union { */ uint32_t uart2_clk_en:1; /** uart2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart2 module + * Set 1 to reset uart2 module */ uint32_t uart2_rst_en:1; /** uart2_ready : RO; bitpos: [2]; default: 1; @@ -199,10 +199,10 @@ typedef union { */ uint32_t uart2_sclk_div_num:8; /** uart2_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of UART2.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of UART2. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t uart2_sclk_sel:2; /** uart2_sclk_en : R/W; bitpos: [22]; default: 1; @@ -243,7 +243,7 @@ typedef union { */ uint32_t mspi_clk_en:1; /** mspi_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module + * Set 1 to reset mspi module */ uint32_t mspi_rst_en:1; /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; @@ -271,10 +271,10 @@ typedef union { */ uint32_t mspi_fast_div_num:8; /** mspi_func_clk_sel : R/W; bitpos: [9:8]; default: 0; - * Configures the clock source for MSPI.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * Configures the clock source for MSPI. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t mspi_func_clk_sel:2; /** mspi_func_clk_en : R/W; bitpos: [10]; default: 1; @@ -282,7 +282,7 @@ typedef union { */ uint32_t mspi_func_clk_en:1; /** mspi_axi_rst_en : R/W; bitpos: [11]; default: 0; - * Set 0 to reset axi_clock domain of mspi module + * Set 1 to reset axi_clock domain of mspi module */ uint32_t mspi_axi_rst_en:1; uint32_t reserved_12:20; @@ -300,7 +300,7 @@ typedef union { */ uint32_t i2c_clk_en:1; /** i2c_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module + * Set 1 to reset i2c module */ uint32_t i2c_rst_en:1; uint32_t reserved_2:30; @@ -326,9 +326,9 @@ typedef union { */ uint32_t i2c_sclk_div_num:8; /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of I2C.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of I2C. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t i2c_sclk_sel:1; uint32_t reserved_21:1; @@ -351,7 +351,7 @@ typedef union { */ uint32_t ledc_clk_en:1; /** ledc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module + * Set 1 to reset ledc module */ uint32_t ledc_rst_en:1; /** ledc_ready : RO; bitpos: [2]; default: 1; @@ -370,10 +370,10 @@ typedef union { struct { uint32_t reserved_0:20; /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of LEDC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of LEDC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t ledc_sclk_sel:2; /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; @@ -414,7 +414,7 @@ typedef union { */ uint32_t tg0_clk_en:1; /** tg0_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module + * Set 1 to reset timer_group0 module */ uint32_t tg0_rst_en:1; /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; @@ -441,10 +441,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_timer_clk_sel:2; /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -463,10 +463,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 0.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 0. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg0_wdt_clk_sel:2; /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -488,7 +488,7 @@ typedef union { */ uint32_t tg1_clk_en:1; /** tg1_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module + * Set 1 to reset timer_group1 module */ uint32_t tg1_rst_en:1; /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; @@ -515,10 +515,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of general-purpose timers in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of general-purpose timers in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_timer_clk_sel:2; /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; @@ -537,10 +537,10 @@ typedef union { struct { uint32_t reserved_0:20; /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of WDT in Timer Group 1.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of WDT in Timer Group 1. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t tg1_wdt_clk_sel:2; /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; @@ -562,7 +562,7 @@ typedef union { */ uint32_t systimer_clk_en:1; /** systimer_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module + * Set 1 to reset systimer module */ uint32_t systimer_rst_en:1; /** systimer_ready : RO; bitpos: [2]; default: 1; @@ -581,9 +581,9 @@ typedef union { struct { uint32_t reserved_0:20; /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of System Timer.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of System Timer. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t systimer_func_clk_sel:1; uint32_t reserved_21:1; @@ -606,7 +606,7 @@ typedef union { */ uint32_t i2s_clk_en:1; /** i2s_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module + * Set 1 to reset i2s module */ uint32_t i2s_rst_en:1; /** i2s_rx_ready : RO; bitpos: [2]; default: 1; @@ -636,11 +636,11 @@ typedef union { */ uint32_t i2s_tx_clkm_div_num:8; /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S TX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S TX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_tx_clkm_sel:2; /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; @@ -693,11 +693,11 @@ typedef union { */ uint32_t i2s_rx_clkm_div_num:8; /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of I2S RX.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F120M_CLK\\ - * 2: PLL_F160M_CLK\\ - * 3: I2S_MCLK_in\\ + * Configures the clock source of I2S RX. + * 0 (default): XTAL_CLK + * 1: PLL_F120M_CLK + * 2: PLL_F160M_CLK + * 3: I2S_MCLK_in */ uint32_t i2s_rx_clkm_sel:2; /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; @@ -705,9 +705,9 @@ typedef union { */ uint32_t i2s_rx_clkm_en:1; /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; - * Configures to select master clock.\\ - * 0 (default): I2S_TX_CLK\\ - * 1: I2S_RX_CLK\\ + * Configures to select master clock. + * 0 (default): I2S_TX_CLK + * 1: I2S_RX_CLK */ uint32_t i2s_mclk_sel:1; uint32_t reserved_24:8; @@ -755,7 +755,7 @@ typedef union { */ uint32_t saradc_clk_en:1; /** saradc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module + * Set 1 to reset function_register of saradc module */ uint32_t saradc_rst_en:1; /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; @@ -763,7 +763,7 @@ typedef union { */ uint32_t saradc_reg_clk_en:1; /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module + * Set 1 to reset apb_register of saradc module */ uint32_t saradc_reg_rst_en:1; uint32_t reserved_4:28; @@ -789,10 +789,10 @@ typedef union { */ uint32_t saradc_clkm_div_num:8; /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SAR ADC.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of SAR ADC. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t saradc_clkm_sel:2; /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; @@ -811,9 +811,9 @@ typedef union { struct { uint32_t reserved_0:20; /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of the temperature sensor.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ + * Configures the clock source of the temperature sensor. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK */ uint32_t tsens_clk_sel:1; uint32_t reserved_21:1; @@ -822,7 +822,7 @@ typedef union { */ uint32_t tsens_clk_en:1; /** tsens_rst_en : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module + * Set 1 to reset tsens module */ uint32_t tsens_rst_en:1; uint32_t reserved_24:8; @@ -840,7 +840,7 @@ typedef union { */ uint32_t usb_device_clk_en:1; /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module + * Set 1 to reset usb_device module */ uint32_t usb_device_rst_en:1; /** usb_device_ready : RO; bitpos: [2]; default: 1; @@ -862,7 +862,7 @@ typedef union { */ uint32_t intmtx_clk_en:1; /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module + * Set 1 to reset intmtx module */ uint32_t intmtx_rst_en:1; /** intmtx_ready : RO; bitpos: [2]; default: 1; @@ -916,9 +916,9 @@ typedef union { uint32_t pvt_monitor_func_clk_div_num:4; uint32_t reserved_4:16; /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; - * Configures the clock source of PVT MONITOR.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ + * Configures the clock source of PVT MONITOR. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK */ uint32_t pvt_monitor_func_clk_sel:1; uint32_t reserved_21:1; @@ -941,7 +941,7 @@ typedef union { */ uint32_t gdma_clk_en:1; /** gdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module + * Set 1 to reset gdma module */ uint32_t gdma_rst_en:1; uint32_t reserved_2:30; @@ -959,7 +959,7 @@ typedef union { */ uint32_t spi2_clk_en:1; /** spi2_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module + * Set 1 to reset spi2 module */ uint32_t spi2_rst_en:1; /** spi2_ready : RO; bitpos: [2]; default: 1; @@ -982,10 +982,10 @@ typedef union { */ uint32_t spi2_clkm_div_num:8; /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of SPI2.\\ - * 0 (default): XTAL_CLK\\ - * 1: PLL_F160M_CLK\\ - * 2: RC_FAST_CLK\\ + * Configures the clock source of SPI2. + * 0 (default): XTAL_CLK + * 1: PLL_F160M_CLK + * 2: RC_FAST_CLK */ uint32_t spi2_clkm_sel:2; /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; @@ -1007,7 +1007,7 @@ typedef union { */ uint32_t aes_clk_en:1; /** aes_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module + * Set 1 to reset aes module */ uint32_t aes_rst_en:1; /** aes_ready : RO; bitpos: [2]; default: 1; @@ -1029,7 +1029,7 @@ typedef union { */ uint32_t sha_clk_en:1; /** sha_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module + * Set 1 to reset sha module */ uint32_t sha_rst_en:1; /** sha_ready : RO; bitpos: [2]; default: 1; @@ -1051,7 +1051,7 @@ typedef union { */ uint32_t rsa_clk_en:1; /** rsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module + * Set 1 to reset rsa module */ uint32_t rsa_rst_en:1; /** rsa_ready : RO; bitpos: [2]; default: 1; @@ -1095,7 +1095,7 @@ typedef union { */ uint32_t ecc_clk_en:1; /** ecc_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module + * Set 1 to reset ecc module */ uint32_t ecc_rst_en:1; /** ecc_ready : RO; bitpos: [2]; default: 1; @@ -1139,7 +1139,7 @@ typedef union { */ uint32_t ds_clk_en:1; /** ds_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module + * Set 1 to reset ds module */ uint32_t ds_rst_en:1; /** ds_ready : RO; bitpos: [2]; default: 1; @@ -1161,7 +1161,7 @@ typedef union { */ uint32_t hmac_clk_en:1; /** hmac_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module + * Set 1 to reset hmac module */ uint32_t hmac_rst_en:1; /** hmac_ready : RO; bitpos: [2]; default: 1; @@ -1183,7 +1183,7 @@ typedef union { */ uint32_t ecdsa_clk_en:1; /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecdsa module + * Set 1 to reset ecdsa module */ uint32_t ecdsa_rst_en:1; /** ecdsa_ready : RO; bitpos: [2]; default: 1; @@ -1205,7 +1205,7 @@ typedef union { */ uint32_t iomux_clk_en:1; /** iomux_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module + * Set 1 to reset iomux module */ uint32_t iomux_rst_en:1; uint32_t reserved_2:30; @@ -1220,10 +1220,10 @@ typedef union { struct { uint32_t reserved_0:20; /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; - * Configures the clock source of IO MUX.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F80M_CLK\\ + * Configures the clock source of IO MUX. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F80M_CLK */ uint32_t iomux_func_clk_sel:2; /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; @@ -1245,7 +1245,7 @@ typedef union { */ uint32_t tcm_mem_monitor_clk_en:1; /** tcm_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset tcm_mem_monitor module + * Set 1 to reset tcm_mem_monitor module */ uint32_t tcm_mem_monitor_rst_en:1; /** tcm_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -1267,7 +1267,7 @@ typedef union { */ uint32_t psram_mem_monitor_clk_en:1; /** psram_mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset psram_mem_monitor module + * Set 1 to reset psram_mem_monitor module */ uint32_t psram_mem_monitor_rst_en:1; /** psram_mem_monitor_ready : RO; bitpos: [2]; default: 1; @@ -1289,7 +1289,7 @@ typedef union { */ uint32_t trace_clk_en:1; /** trace_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module + * Set 1 to reset trace module */ uint32_t trace_rst_en:1; uint32_t reserved_2:30; @@ -1307,7 +1307,7 @@ typedef union { */ uint32_t assist_clk_en:1; /** assist_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module + * Set 1 to reset assist module */ uint32_t assist_rst_en:1; uint32_t reserved_2:30; @@ -1325,7 +1325,7 @@ typedef union { */ uint32_t cache_clk_en:1; /** cache_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module + * Set 1 to reset cache module */ uint32_t cache_rst_en:1; uint32_t reserved_2:30; @@ -1382,11 +1382,11 @@ typedef union { struct { uint32_t reserved_0:1; /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module + * Set 1 to reset cpu_peri timeout module */ uint32_t cpu_timeout_rst_en:1; /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module + * Set 1 to reset hp_peri timeout module and hp_modem timeout module */ uint32_t hp_timeout_rst_en:1; uint32_t reserved_3:29; @@ -1399,12 +1399,20 @@ typedef union { */ typedef union { struct { - uint32_t reserved_0:16; + /** ls_div_num : HRO; bitpos: [7:0]; default: 0; + * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed + * clock-source such as XTAL/FOSC. + */ + uint32_t ls_div_num:8; + /** hs_div_num : HRO; bitpos: [15:8]; default: 2; + * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. + */ + uint32_t hs_div_num:8; /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; - * Configures to select the clock source of HP_ROOT_CLK.\\ - * 0 (default): XTAL_CLK\\ - * 1: RC_FAST_CLK\\ - * 2: PLL_F160M_CLK\\ + * Configures to select the clock source of HP_ROOT_CLK. + * 0 (default): XTAL_CLK + * 1: RC_FAST_CLK + * 2: PLL_F160M_CLK */ uint32_t soc_clk_sel:2; uint32_t reserved_18:6; @@ -1426,14 +1434,7 @@ typedef union { */ typedef union { struct { - /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t cpuperiod_sel:2; - /** pll_freq_sel : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM - */ - uint32_t pll_freq_sel:1; + uint32_t reserved_0:3; /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; * Set 1 to force cpu_waiti_clk enable. */ @@ -1454,7 +1455,7 @@ typedef union { typedef union { struct { /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_cpu derived by clk_hproot. The clk_cpu is + * Set this field to generate clk_cpu driven by clk_hproot. The clk_cpu is * div1(default)/div2/div4 of clk_hproot. This field is only available for low-speed * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. */ @@ -1470,7 +1471,7 @@ typedef union { typedef union { struct { /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; - * Set this field to generate clk_ahb derived by clk_hproot. The clk_ahb is + * Set this field to generate clk_ahb driven by clk_hproot. The clk_ahb is * div1(default)/div2/div4/div8 of clk_hproot. This field is only available for * low-speed clock-source such as XTAL/FOSC, and should be used together with * PCR_CPU_DIV_NUM. @@ -1497,7 +1498,7 @@ typedef union { */ uint32_t apb_decrease_div_num:8; /** apb_div_num : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb derived by clk_ahb. The clk_apb is + * Set as one within (0,1,3) to generate clk_apb driven by clk_ahb. The clk_apb is * div1(default)/div2/div4 of clk_ahb. */ uint32_t apb_div_num:8; @@ -1513,46 +1514,41 @@ typedef union { struct { uint32_t reserved_0:1; /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) derived from SPLL. 0: close, + * This field is used to open 160 MHz clock (div3 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_160m_clk_en:1; /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) derived from SPLL. 0: close, + * This field is used to open 120 MHz clock (div4 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_120m_clk_en:1; /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) derived from SPLL. 0: close, + * This field is used to open 80 MHz clock (div6 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_80m_clk_en:1; /** pll_60m_clk_en : R/W; bitpos: [4]; default: 1; - * This field is used to open 60 MHz clock (div8 of SPLL) derived from SPLL. 0: close, + * This field is used to open 60 MHz clock (div8 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_60m_clk_en:1; /** pll_48m_clk_en : R/W; bitpos: [5]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) derived from SPLL. 0: close, + * This field is used to open 48 MHz clock (div10 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_48m_clk_en:1; /** pll_40m_clk_en : R/W; bitpos: [6]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) derived from SPLL. 0: close, + * This field is used to open 40 MHz clock (div12 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_40m_clk_en:1; /** pll_20m_clk_en : R/W; bitpos: [7]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) derived from SPLL. 0: close, + * This field is used to open 20 MHz clock (div24 of SPLL) driven from SPLL. 0: close, * 1: open(default). Only available when high-speed clock-source SPLL is active. */ uint32_t pll_20m_clk_en:1; - /** pll_12m_clk_en : HRO; bitpos: [8]; default: 1; - * This field is used to open 12 MHz clock (div40 of SPLL) derived from SPLL. 0: close, - * 1: open(default). Only available when high-speed clock-source SPLL is active. - */ - uint32_t pll_12m_clk_en:1; - uint32_t reserved_9:23; + uint32_t reserved_8:24; }; uint32_t val; } pcr_pll_div_clk_en_reg_t; @@ -1612,13 +1608,13 @@ typedef union { */ typedef union { struct { - /** 32k_sel : R/W; bitpos: [2:0]; default: 0; - * Configures the 32KHz clock for TIMER_GROUP.\\ - * 0 (default): RC32K_CLK\\ - * 1: XTAL32K_CLK\\ - * 2: OSC_SLOW_CLK\\ - * 3: RC_SLOW_CLK\\ - * 4: RC_FAST_CLK\\ + /** clk_32k_sel : R/W; bitpos: [2:0]; default: 0; + * Configures the 32KHz clock for TIMER_GROUP. + * 0 (default): RC32K_CLK + * 1: XTAL32K_CLK + * 2: OSC_SLOW_CLK + * 3: RC_SLOW_CLK + * 4: RC_FAST_CLK */ uint32_t clk_32k_sel:3; uint32_t reserved_3:5; @@ -1687,14 +1683,14 @@ typedef union { struct { /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; * Configures the clock source for the External Memory Encryption and Decryption - * module.\\ - * 0(default): XTAL_CLK\\ - * 1 RC_FAST_CLK\\ - * 2: PLL_F480M_CLK\\ + * module. + * 0(default): XTAL_CLK + * 1 RC_FAST_CLK + * 2: PLL_F480M_CLK */ uint32_t sec_clk_sel:2; /** sec_rst_en : R/W; bitpos: [2]; default: 0; - * Set 0 to reset sec module + * Set 1 to reset sec module */ uint32_t sec_rst_en:1; uint32_t reserved_3:29; @@ -1702,24 +1698,6 @@ typedef union { uint32_t val; } pcr_sec_conf_reg_t; -/** Type of adc_dac_inv_phase_conf register - * xxxx - */ -typedef union { - struct { - /** clk_rx_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; - * xxxx - */ - uint32_t clk_rx_adc_inv_phase_ena:1; - /** clk_tx_dac_inv_phase_ena : R/W; bitpos: [1]; default: 0; - * xxxx - */ - uint32_t clk_tx_dac_inv_phase_ena:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pcr_adc_dac_inv_phase_conf_reg_t; - /** Type of bus_clk_update register * Configuration register for applying updated high-performance system clock sources */ @@ -1727,10 +1705,10 @@ typedef union { struct { /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; * Configures whether or not to update configurations for CPU_CLK division, AHB_CLK - * division and HP_ROOT_CLK clock source selection.\\ - * 0: Not update configurations\\ - * 1: Update configurations\\ - * This bit is automatically cleared when configurations have been updated.\\ + * division and HP_ROOT_CLK clock source selection. + * 0: Not update configurations + * 1: Update configurations + * This bit is automatically cleared when configurations have been updated. */ uint32_t bus_clock_update:1; uint32_t reserved_1:31; @@ -1744,13 +1722,11 @@ typedef union { typedef union { struct { /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; - * Configures the divisor for SAR ADC 2 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 2 clock to generate ADC analog control signals. */ uint32_t sar2_clk_div_num:8; /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; - * Configures the divisor for SAR ADC 1 clock to generate ADC analog control - * signals.\\ + * Configures the divisor for SAR ADC 1 clock to generate ADC analog control signals. */ uint32_t sar1_clk_div_num:8; uint32_t reserved_16:16; @@ -1758,35 +1734,17 @@ typedef union { uint32_t val; } pcr_sar_clk_div_reg_t; -/** Type of pwdet_sar_clk_conf register - * xxxx - */ -typedef union { - struct { - /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; - * xxxx - */ - uint32_t pwdet_sar_clk_div_num:8; - /** pwdet_sar_clk_en : R/W; bitpos: [8]; default: 1; - * xxxx - */ - uint32_t pwdet_sar_clk_en:1; - uint32_t reserved_9:23; - }; - uint32_t val; -} pcr_pwdet_sar_clk_conf_reg_t; - /** Type of timergroup_wdt_conf register * TIMERGROUP_WDT configuration register */ typedef union { struct { /** tg0_wdt_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 wdt module + * Set 1 to reset timer_group0 wdt module */ uint32_t tg0_wdt_rst_en:1; /** tg1_wdt_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 wdt module + * Set 1 to reset timer_group1 wdt module */ uint32_t tg1_wdt_rst_en:1; uint32_t reserved_2:30; @@ -1800,11 +1758,11 @@ typedef union { typedef union { struct { /** tg0_xtal_rst_en : R/W; bitpos: [0]; default: 0; - * Set 0 to reset timer_group0 xtal clock domain + * Set 1 to reset timer_group0 xtal clock domain */ uint32_t tg0_xtal_rst_en:1; /** tg1_xtal_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 xtal clock domain + * Set 1 to reset timer_group1 xtal clock domain */ uint32_t tg1_xtal_rst_en:1; /** tg0_xtal_clk_en : R/W; bitpos: [2]; default: 1; @@ -1816,30 +1774,6 @@ typedef union { uint32_t val; } pcr_timergroup_xtal_conf_reg_t; -/** Type of reset_event_bypass register - * reset event bypass backdoor configuration register - */ -typedef union { - struct { - /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; - * This field is used to control reset event relationship for - * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset - * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg - * will not only be reset by power-reset, but also some reset event. - */ - uint32_t reset_event_bypass_apm:1; - /** reset_event_bypass : R/W; bitpos: [1]; default: 1; - * This field is used to control reset event relationship for system-bus. 1: system - * bus (including arbiter/router) will only be reset by power-reset. some reset event - * will be bypass. 0: system bus (including arbiter/router) will not only be reset by - * power-reset, but also some reset event. - */ - uint32_t reset_event_bypass:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} pcr_reset_event_bypass_reg_t; - /** Type of regdma_conf register * REGDMA configuration register */ @@ -1850,7 +1784,7 @@ typedef union { */ uint32_t regdma_clk_en:1; /** regdma_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module + * Set 1 to reset regdma module */ uint32_t regdma_rst_en:1; uint32_t reserved_2:30; @@ -1868,7 +1802,7 @@ typedef union { */ uint32_t etm_clk_en:1; /** etm_rst_en : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module + * Set 1 to reset etm module */ uint32_t etm_rst_en:1; /** etm_ready : RO; bitpos: [2]; default: 1; @@ -1880,19 +1814,42 @@ typedef union { uint32_t val; } pcr_etm_conf_reg_t; -/** Type of clock_gate register - * PCR clock gating configure register +/** Type of sdio_slave_conf register + * SDIO_SLAVE configuration register */ typedef union { struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. + /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; + * Set 1 to enable sdio_slave clock */ - uint32_t clk_en:1; - uint32_t reserved_1:31; + uint32_t sdio_slave_clk_en:1; + /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; + * Set 1 to reset sdio_slave module + */ + uint32_t sdio_slave_rst_en:1; + uint32_t reserved_2:30; }; uint32_t val; -} pcr_clock_gate_reg_t; +} pcr_sdio_slave_conf_reg_t; + +/** Type of sdio_slave_pd_ctrl register + * LEDC power control register + */ +typedef union { + struct { + uint32_t reserved_0:1; + /** sdio_mem_force_pu : R/W; bitpos: [1]; default: 1; + * Set this bit to force power down SDIO memory. + */ + uint32_t sdio_mem_force_pu:1; + /** sdio_mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to force power up SDIO memory. + */ + uint32_t sdio_mem_force_pd:1; + uint32_t reserved_3:29; + }; + uint32_t val; +} pcr_sdio_slave_pd_ctrl_reg_t; /** Group: Frequency Statistics Register */ @@ -1915,28 +1872,13 @@ typedef union { } pcr_sysclk_freq_query_0_reg_t; -/** Group: FPGA Debug Register */ -/** Type of fpga_debug register - * fpga debug register - */ -typedef union { - struct { - /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. - */ - uint32_t fpga_debug:32; - }; - uint32_t val; -} pcr_fpga_debug_reg_t; - - /** Group: Version Register */ /** Type of date register * Date register. */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 37753376; + /** date : R/W; bitpos: [27:0]; default: 37823120; * PCR version information. */ uint32_t date:28; @@ -2018,18 +1960,19 @@ typedef struct { volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; volatile pcr_sec_conf_reg_t sec_conf; - volatile pcr_adc_dac_inv_phase_conf_reg_t adc_dac_inv_phase_conf; + uint32_t reserved_11c; volatile pcr_bus_clk_update_reg_t bus_clk_update; volatile pcr_sar_clk_div_reg_t sar_clk_div; - volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; + uint32_t reserved_128; volatile pcr_timergroup_wdt_conf_reg_t timergroup_wdt_conf; volatile pcr_timergroup_xtal_conf_reg_t timergroup_xtal_conf; - volatile pcr_reset_event_bypass_reg_t reset_event_bypass; + uint32_t reserved_134; volatile pcr_regdma_conf_reg_t regdma_conf; volatile pcr_etm_conf_reg_t etm_conf; - uint32_t reserved_140[941]; - volatile pcr_fpga_debug_reg_t fpga_debug; - volatile pcr_clock_gate_reg_t clock_gate; + uint32_t reserved_140[6]; + volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; + volatile pcr_sdio_slave_pd_ctrl_reg_t sdio_slave_pd_ctrl; + uint32_t reserved_160[935]; volatile pcr_date_reg_t date; } pcr_dev_t; diff --git a/components/soc/esp32c61/register/soc/pmu_reg.h b/components/soc/esp32c61/register/soc/pmu_reg.h index ad4b994f78..cf9244c633 100644 --- a/components/soc/esp32c61/register/soc/pmu_reg.h +++ b/components/soc/esp32c61/register/soc/pmu_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -1336,18 +1336,6 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_DRV_B_S 28 -/** PMU_HP_SLEEP_LP_DCDC_RESERVE_REG register - * need_des - */ -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_REG (DR_REG_PMU_BASE + 0xa4) -/** PMU_HP_SLEEP_LP_DCDC_RESERVE : WT; bitpos: [31:0]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_LP_DCDC_RESERVE 0xFFFFFFFFU -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_M (PMU_HP_SLEEP_LP_DCDC_RESERVE_V << PMU_HP_SLEEP_LP_DCDC_RESERVE_S) -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_V 0xFFFFFFFFU -#define PMU_HP_SLEEP_LP_DCDC_RESERVE_S 0 - /** PMU_HP_SLEEP_LP_DIG_POWER_REG register * need_des */ @@ -1400,18 +1388,6 @@ extern "C" { #define PMU_HP_SLEEP_PD_OSC_CLK_V 0x00000001U #define PMU_HP_SLEEP_PD_OSC_CLK_S 31 -/** PMU_LP_SLEEP_LP_BIAS_RESERVE_REG register - * need_des - */ -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_REG (DR_REG_PMU_BASE + 0xb0) -/** PMU_LP_SLEEP_LP_BIAS_RESERVE : WT; bitpos: [31:0]; default: 0; - * need_des - */ -#define PMU_LP_SLEEP_LP_BIAS_RESERVE 0xFFFFFFFFU -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_M (PMU_LP_SLEEP_LP_BIAS_RESERVE_V << PMU_LP_SLEEP_LP_BIAS_RESERVE_S) -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_V 0xFFFFFFFFU -#define PMU_LP_SLEEP_LP_BIAS_RESERVE_S 0 - /** PMU_LP_SLEEP_LP_REGULATOR0_REG register * need_des */ diff --git a/components/soc/esp32c61/register/soc/pmu_struct.h b/components/soc/esp32c61/register/soc/pmu_struct.h index e59470be4e..71d954027a 100644 --- a/components/soc/esp32c61/register/soc/pmu_struct.h +++ b/components/soc/esp32c61/register/soc/pmu_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -156,6 +156,23 @@ typedef union { uint32_t slp_logic_dbias: 4; uint32_t dbias : 5; }; + struct { + uint32_t reserved2 : 3; + uint32_t slp_connect_en_active: 1; + uint32_t reserved3 : 11; + uint32_t dbias_init_active : 1; + uint32_t reserved4 : 16; + }; + struct { + uint32_t reserved5 : 15; + uint32_t slp_connect_en_modem : 1; + uint32_t reserved6 : 16; + }; + struct { + uint32_t reserved7 : 15; + uint32_t slp_connect_en_sleep : 1; + uint32_t reserved8 : 16; + }; uint32_t val; } pmu_hp_regulator0_reg_t; diff --git a/components/soc/esp32c61/register/soc/reg_base.h b/components/soc/esp32c61/register/soc/reg_base.h index d0af212f56..ec98bbf341 100644 --- a/components/soc/esp32c61/register/soc/reg_base.h +++ b/components/soc/esp32c61/register/soc/reg_base.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -20,9 +20,12 @@ #define DR_REG_SARADC_BASE 0x6000E000 #define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 #define DR_REG_INTMTX_BASE 0x60010000 +#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTMTX_BASE #define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_PVT_MONITOR_BASE 0x60019000 -#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000 +#define DR_REG_HINF_BASE 0x60016000 +#define DR_REG_SLC_BASE 0x60017000 +#define DR_REG_HOST_BASE 0x60018000 +#define DR_REG_PVT_BASE 0x60019000 #define DR_REG_AHB_DMA_BASE 0x60080000 #define DR_REG_SPI2_BASE 0x60081000 #define DR_REG_SHA_BASE 0x60089000 @@ -31,18 +34,13 @@ #define DR_REG_IO_MUX_BASE 0x60090000 #define DR_REG_GPIO_BASE 0x60091000 #define DR_REG_GPIO_EXT_BASE 0x60091E00 -#define DR_REG_TCM_MEM_MONITOR_BASE 0x60092000 +#define DR_REG_MEM_MONITOR_BASE 0x60092000 #define DR_REG_PAU_BASE 0x60093000 #define DR_REG_HP_SYSTEM_BASE 0x60095000 #define DR_REG_PCR_BASE 0x60096000 #define DR_REG_TEE_BASE 0x60098000 #define DR_REG_HP_APM_BASE 0x60099000 -#define DR_REG_MISC_BASE 0x6009F000 -#define DR_REG_MODEM0_BASE 0x600A0000 -#define DR_REG_MODEM1_BASE 0x600AC000 -#define DR_REG_MODEM_PWR0_BASE 0x600AD000 -#define DR_REG_MODEM_PWR1_BASE 0x600AF000 -#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 +#define DR_REG_CPU_APM_REG_BASE 0x6009A000 #define DR_REG_PMU_BASE 0x600B0000 #define DR_REG_LP_CLKRST_BASE 0x600B0400 #define DR_REG_LP_TIMER_BASE 0x600B0C00 @@ -55,10 +53,13 @@ #define DR_REG_LP_IO_MUX_BASE 0x600B4000 #define DR_REG_LP_GPIO_BASE 0x600B4400 #define DR_REG_EFUSE0_BASE 0x600B4800 -#define DR_REG_EFUSE1_BASE 0x600B4C00 +#define DR_REG_OTP_DEBUG_BASE 0x600B4C00 #define DR_REG_TRACE_BASE 0x600C0000 #define DR_REG_BUS_MONITOR_BASE 0x600C2000 #define DR_REG_INTPRI_BASE 0x600C5000 #define DR_REG_CACHE_BASE 0x600C8000 + +// below are not generated but pick from old file #define DR_REG_CLINT_M_BASE 0x20000000 #define PWDET_CONF_REG 0x600A0808 +#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 diff --git a/components/soc/esp32c61/register/soc/sdio_hinf_reg.h b/components/soc/esp32c61/register/soc/sdio_hinf_reg.h new file mode 100644 index 0000000000..8c71517bcc --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_hinf_reg.h @@ -0,0 +1,576 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** HINF_CFG_DATA0_REG register + * Configure sdio cis content + */ +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/** HINF_DEVICE_ID_FN1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ +#define HINF_DEVICE_ID_FN1 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_M (HINF_DEVICE_ID_FN1_V << HINF_DEVICE_ID_FN1_S) +#define HINF_DEVICE_ID_FN1_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN1_S 0 +/** HINF_USER_ID_FN1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ +#define HINF_USER_ID_FN1 0x0000FFFFU +#define HINF_USER_ID_FN1_M (HINF_USER_ID_FN1_V << HINF_USER_ID_FN1_S) +#define HINF_USER_ID_FN1_V 0x0000FFFFU +#define HINF_USER_ID_FN1_S 16 + +/** HINF_CFG_DATA1_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/** HINF_SDIO_ENABLE : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (HINF_SDIO_ENABLE_V << HINF_SDIO_ENABLE_S) +#define HINF_SDIO_ENABLE_V 0x00000001U +#define HINF_SDIO_ENABLE_S 0 +/** HINF_SDIO_IOREADY1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (HINF_SDIO_IOREADY1_V << HINF_SDIO_IOREADY1_S) +#define HINF_SDIO_IOREADY1_V 0x00000001U +#define HINF_SDIO_IOREADY1_S 1 +/** HINF_HIGHSPEED_ENABLE : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (HINF_HIGHSPEED_ENABLE_V << HINF_HIGHSPEED_ENABLE_S) +#define HINF_HIGHSPEED_ENABLE_V 0x00000001U +#define HINF_HIGHSPEED_ENABLE_S 2 +/** HINF_HIGHSPEED_MODE : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (HINF_HIGHSPEED_MODE_V << HINF_HIGHSPEED_MODE_S) +#define HINF_HIGHSPEED_MODE_V 0x00000001U +#define HINF_HIGHSPEED_MODE_S 3 +/** HINF_SDIO_CD_ENABLE : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (HINF_SDIO_CD_ENABLE_V << HINF_SDIO_CD_ENABLE_S) +#define HINF_SDIO_CD_ENABLE_V 0x00000001U +#define HINF_SDIO_CD_ENABLE_S 4 +/** HINF_SDIO_IOREADY2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (HINF_SDIO_IOREADY2_V << HINF_SDIO_IOREADY2_S) +#define HINF_SDIO_IOREADY2_V 0x00000001U +#define HINF_SDIO_IOREADY2_S 5 +/** HINF_SDIO_INT_MASK : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (HINF_SDIO_INT_MASK_V << HINF_SDIO_INT_MASK_S) +#define HINF_SDIO_INT_MASK_V 0x00000001U +#define HINF_SDIO_INT_MASK_S 6 +/** HINF_IOENABLE2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (HINF_IOENABLE2_V << HINF_IOENABLE2_S) +#define HINF_IOENABLE2_V 0x00000001U +#define HINF_IOENABLE2_S 7 +/** HINF_CD_DISABLE : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (HINF_CD_DISABLE_V << HINF_CD_DISABLE_S) +#define HINF_CD_DISABLE_V 0x00000001U +#define HINF_CD_DISABLE_S 8 +/** HINF_FUNC1_EPS : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (HINF_FUNC1_EPS_V << HINF_FUNC1_EPS_S) +#define HINF_FUNC1_EPS_V 0x00000001U +#define HINF_FUNC1_EPS_S 9 +/** HINF_EMP : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (HINF_EMP_V << HINF_EMP_S) +#define HINF_EMP_V 0x00000001U +#define HINF_EMP_S 10 +/** HINF_IOENABLE1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (HINF_IOENABLE1_V << HINF_IOENABLE1_S) +#define HINF_IOENABLE1_V 0x00000001U +#define HINF_IOENABLE1_S 11 +/** HINF_SDIO_VER : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ +#define HINF_SDIO_VER 0x00000FFFU +#define HINF_SDIO_VER_M (HINF_SDIO_VER_V << HINF_SDIO_VER_S) +#define HINF_SDIO_VER_V 0x00000FFFU +#define HINF_SDIO_VER_S 12 +/** HINF_FUNC2_EPS : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ +#define HINF_FUNC2_EPS (BIT(24)) +#define HINF_FUNC2_EPS_M (HINF_FUNC2_EPS_V << HINF_FUNC2_EPS_S) +#define HINF_FUNC2_EPS_V 0x00000001U +#define HINF_FUNC2_EPS_S 24 +/** HINF_SDIO20_CONF : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ +#define HINF_SDIO20_CONF 0x0000007FU +#define HINF_SDIO20_CONF_M (HINF_SDIO20_CONF_V << HINF_SDIO20_CONF_S) +#define HINF_SDIO20_CONF_V 0x0000007FU +#define HINF_SDIO20_CONF_S 25 + +/** HINF_CFG_TIMING_REG register + * Timing configuration registers + */ +#define HINF_CFG_TIMING_REG (DR_REG_HINF_BASE + 0x8) +/** HINF_NCRC : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ +#define HINF_NCRC 0x00000007U +#define HINF_NCRC_M (HINF_NCRC_V << HINF_NCRC_S) +#define HINF_NCRC_V 0x00000007U +#define HINF_NCRC_S 0 +/** HINF_PST_END_CMD_LOW_VALUE : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ +#define HINF_PST_END_CMD_LOW_VALUE 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_M (HINF_PST_END_CMD_LOW_VALUE_V << HINF_PST_END_CMD_LOW_VALUE_S) +#define HINF_PST_END_CMD_LOW_VALUE_V 0x0000007FU +#define HINF_PST_END_CMD_LOW_VALUE_S 3 +/** HINF_PST_END_DATA_LOW_VALUE : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ +#define HINF_PST_END_DATA_LOW_VALUE 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_M (HINF_PST_END_DATA_LOW_VALUE_V << HINF_PST_END_DATA_LOW_VALUE_S) +#define HINF_PST_END_DATA_LOW_VALUE_V 0x0000003FU +#define HINF_PST_END_DATA_LOW_VALUE_S 10 +/** HINF_SDCLK_STOP_THRES : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ +#define HINF_SDCLK_STOP_THRES 0x000007FFU +#define HINF_SDCLK_STOP_THRES_M (HINF_SDCLK_STOP_THRES_V << HINF_SDCLK_STOP_THRES_S) +#define HINF_SDCLK_STOP_THRES_V 0x000007FFU +#define HINF_SDCLK_STOP_THRES_S 16 +/** HINF_SAMPLE_CLK_DIVIDER : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ +#define HINF_SAMPLE_CLK_DIVIDER 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_M (HINF_SAMPLE_CLK_DIVIDER_V << HINF_SAMPLE_CLK_DIVIDER_S) +#define HINF_SAMPLE_CLK_DIVIDER_V 0x0000000FU +#define HINF_SAMPLE_CLK_DIVIDER_S 28 + +/** HINF_CFG_UPDATE_REG register + * update sdio configurations + */ +#define HINF_CFG_UPDATE_REG (DR_REG_HINF_BASE + 0xc) +/** HINF_CONF_UPDATE : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ +#define HINF_CONF_UPDATE (BIT(0)) +#define HINF_CONF_UPDATE_M (HINF_CONF_UPDATE_V << HINF_CONF_UPDATE_S) +#define HINF_CONF_UPDATE_V 0x00000001U +#define HINF_CONF_UPDATE_S 0 + +/** HINF_CFG_DATA7_REG register + * SDIO configuration register + */ +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1c) +/** HINF_PIN_STATE : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ +#define HINF_PIN_STATE 0x000000FFU +#define HINF_PIN_STATE_M (HINF_PIN_STATE_V << HINF_PIN_STATE_S) +#define HINF_PIN_STATE_V 0x000000FFU +#define HINF_PIN_STATE_S 0 +/** HINF_CHIP_STATE : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ +#define HINF_CHIP_STATE 0x000000FFU +#define HINF_CHIP_STATE_M (HINF_CHIP_STATE_V << HINF_CHIP_STATE_S) +#define HINF_CHIP_STATE_V 0x000000FFU +#define HINF_CHIP_STATE_S 8 +/** HINF_SDIO_RST : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (HINF_SDIO_RST_V << HINF_SDIO_RST_S) +#define HINF_SDIO_RST_V 0x00000001U +#define HINF_SDIO_RST_S 16 +/** HINF_SDIO_IOREADY0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (HINF_SDIO_IOREADY0_V << HINF_SDIO_IOREADY0_S) +#define HINF_SDIO_IOREADY0_V 0x00000001U +#define HINF_SDIO_IOREADY0_S 17 +/** HINF_SDIO_MEM_PD : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ +#define HINF_SDIO_MEM_PD (BIT(18)) +#define HINF_SDIO_MEM_PD_M (HINF_SDIO_MEM_PD_V << HINF_SDIO_MEM_PD_S) +#define HINF_SDIO_MEM_PD_V 0x00000001U +#define HINF_SDIO_MEM_PD_S 18 +/** HINF_ESDIO_DATA1_INT_EN : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ +#define HINF_ESDIO_DATA1_INT_EN (BIT(19)) +#define HINF_ESDIO_DATA1_INT_EN_M (HINF_ESDIO_DATA1_INT_EN_V << HINF_ESDIO_DATA1_INT_EN_S) +#define HINF_ESDIO_DATA1_INT_EN_V 0x00000001U +#define HINF_ESDIO_DATA1_INT_EN_S 19 +/** HINF_SDIO_SWITCH_VOLT_SW : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ +#define HINF_SDIO_SWITCH_VOLT_SW (BIT(20)) +#define HINF_SDIO_SWITCH_VOLT_SW_M (HINF_SDIO_SWITCH_VOLT_SW_V << HINF_SDIO_SWITCH_VOLT_SW_S) +#define HINF_SDIO_SWITCH_VOLT_SW_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_SW_S 20 +/** HINF_DDR50_BLK_LEN_FIX_EN : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ +#define HINF_DDR50_BLK_LEN_FIX_EN (BIT(21)) +#define HINF_DDR50_BLK_LEN_FIX_EN_M (HINF_DDR50_BLK_LEN_FIX_EN_V << HINF_DDR50_BLK_LEN_FIX_EN_S) +#define HINF_DDR50_BLK_LEN_FIX_EN_V 0x00000001U +#define HINF_DDR50_BLK_LEN_FIX_EN_S 21 +/** HINF_CLK_EN : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ +#define HINF_CLK_EN (BIT(22)) +#define HINF_CLK_EN_M (HINF_CLK_EN_V << HINF_CLK_EN_S) +#define HINF_CLK_EN_V 0x00000001U +#define HINF_CLK_EN_S 22 +/** HINF_SDDR50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ +#define HINF_SDDR50 (BIT(23)) +#define HINF_SDDR50_M (HINF_SDDR50_V << HINF_SDDR50_S) +#define HINF_SDDR50_V 0x00000001U +#define HINF_SDDR50_S 23 +/** HINF_SSDR104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ +#define HINF_SSDR104 (BIT(24)) +#define HINF_SSDR104_M (HINF_SSDR104_V << HINF_SSDR104_S) +#define HINF_SSDR104_V 0x00000001U +#define HINF_SSDR104_S 24 +/** HINF_SSDR50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ +#define HINF_SSDR50 (BIT(25)) +#define HINF_SSDR50_M (HINF_SSDR50_V << HINF_SSDR50_S) +#define HINF_SSDR50_V 0x00000001U +#define HINF_SSDR50_S 25 +/** HINF_SDTD : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ +#define HINF_SDTD (BIT(26)) +#define HINF_SDTD_M (HINF_SDTD_V << HINF_SDTD_S) +#define HINF_SDTD_V 0x00000001U +#define HINF_SDTD_S 26 +/** HINF_SDTA : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ +#define HINF_SDTA (BIT(27)) +#define HINF_SDTA_M (HINF_SDTA_V << HINF_SDTA_S) +#define HINF_SDTA_V 0x00000001U +#define HINF_SDTA_S 27 +/** HINF_SDTC : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ +#define HINF_SDTC (BIT(28)) +#define HINF_SDTC_M (HINF_SDTC_V << HINF_SDTC_S) +#define HINF_SDTC_V 0x00000001U +#define HINF_SDTC_S 28 +/** HINF_SAI : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ +#define HINF_SAI (BIT(29)) +#define HINF_SAI_M (HINF_SAI_V << HINF_SAI_S) +#define HINF_SAI_V 0x00000001U +#define HINF_SAI_S 29 +/** HINF_SDIO_WAKEUP_CLR : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ +#define HINF_SDIO_WAKEUP_CLR (BIT(30)) +#define HINF_SDIO_WAKEUP_CLR_M (HINF_SDIO_WAKEUP_CLR_V << HINF_SDIO_WAKEUP_CLR_S) +#define HINF_SDIO_WAKEUP_CLR_V 0x00000001U +#define HINF_SDIO_WAKEUP_CLR_S 30 + +/** HINF_CIS_CONF_W0_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W0_REG (DR_REG_HINF_BASE + 0x20) +/** HINF_CIS_CONF_W0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ +#define HINF_CIS_CONF_W0 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_M (HINF_CIS_CONF_W0_V << HINF_CIS_CONF_W0_S) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W0_S 0 + +/** HINF_CIS_CONF_W1_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W1_REG (DR_REG_HINF_BASE + 0x24) +/** HINF_CIS_CONF_W1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ +#define HINF_CIS_CONF_W1 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_M (HINF_CIS_CONF_W1_V << HINF_CIS_CONF_W1_S) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W1_S 0 + +/** HINF_CIS_CONF_W2_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W2_REG (DR_REG_HINF_BASE + 0x28) +/** HINF_CIS_CONF_W2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ +#define HINF_CIS_CONF_W2 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_M (HINF_CIS_CONF_W2_V << HINF_CIS_CONF_W2_S) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W2_S 0 + +/** HINF_CIS_CONF_W3_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W3_REG (DR_REG_HINF_BASE + 0x2c) +/** HINF_CIS_CONF_W3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ +#define HINF_CIS_CONF_W3 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_M (HINF_CIS_CONF_W3_V << HINF_CIS_CONF_W3_S) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W3_S 0 + +/** HINF_CIS_CONF_W4_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W4_REG (DR_REG_HINF_BASE + 0x30) +/** HINF_CIS_CONF_W4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ +#define HINF_CIS_CONF_W4 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_M (HINF_CIS_CONF_W4_V << HINF_CIS_CONF_W4_S) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W4_S 0 + +/** HINF_CIS_CONF_W5_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W5_REG (DR_REG_HINF_BASE + 0x34) +/** HINF_CIS_CONF_W5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ +#define HINF_CIS_CONF_W5 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_M (HINF_CIS_CONF_W5_V << HINF_CIS_CONF_W5_S) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W5_S 0 + +/** HINF_CIS_CONF_W6_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W6_REG (DR_REG_HINF_BASE + 0x38) +/** HINF_CIS_CONF_W6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ +#define HINF_CIS_CONF_W6 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_M (HINF_CIS_CONF_W6_V << HINF_CIS_CONF_W6_S) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W6_S 0 + +/** HINF_CIS_CONF_W7_REG register + * SDIO cis configuration register + */ +#define HINF_CIS_CONF_W7_REG (DR_REG_HINF_BASE + 0x3c) +/** HINF_CIS_CONF_W7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ +#define HINF_CIS_CONF_W7 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_M (HINF_CIS_CONF_W7_V << HINF_CIS_CONF_W7_S) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFFU +#define HINF_CIS_CONF_W7_S 0 + +/** HINF_CFG_DATA16_REG register + * SDIO cis configuration register + */ +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/** HINF_DEVICE_ID_FN2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ +#define HINF_DEVICE_ID_FN2 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_M (HINF_DEVICE_ID_FN2_V << HINF_DEVICE_ID_FN2_S) +#define HINF_DEVICE_ID_FN2_V 0x0000FFFFU +#define HINF_DEVICE_ID_FN2_S 0 +/** HINF_USER_ID_FN2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ +#define HINF_USER_ID_FN2 0x0000FFFFU +#define HINF_USER_ID_FN2_M (HINF_USER_ID_FN2_V << HINF_USER_ID_FN2_S) +#define HINF_USER_ID_FN2_V 0x0000FFFFU +#define HINF_USER_ID_FN2_S 16 + +/** HINF_CFG_UHS1_INT_MODE_REG register + * configure int to start and end ahead of time in uhs1 mode + */ +#define HINF_CFG_UHS1_INT_MODE_REG (DR_REG_HINF_BASE + 0x44) +/** HINF_INTOE_END_AHEAD_MODE : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_END_AHEAD_MODE 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_M (HINF_INTOE_END_AHEAD_MODE_V << HINF_INTOE_END_AHEAD_MODE_S) +#define HINF_INTOE_END_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_END_AHEAD_MODE_S 0 +/** HINF_INT_END_AHEAD_MODE : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_END_AHEAD_MODE 0x00000003U +#define HINF_INT_END_AHEAD_MODE_M (HINF_INT_END_AHEAD_MODE_V << HINF_INT_END_AHEAD_MODE_S) +#define HINF_INT_END_AHEAD_MODE_V 0x00000003U +#define HINF_INT_END_AHEAD_MODE_S 2 +/** HINF_INTOE_ST_AHEAD_MODE : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INTOE_ST_AHEAD_MODE 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_M (HINF_INTOE_ST_AHEAD_MODE_V << HINF_INTOE_ST_AHEAD_MODE_S) +#define HINF_INTOE_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INTOE_ST_AHEAD_MODE_S 4 +/** HINF_INT_ST_AHEAD_MODE : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ +#define HINF_INT_ST_AHEAD_MODE 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_M (HINF_INT_ST_AHEAD_MODE_V << HINF_INT_ST_AHEAD_MODE_S) +#define HINF_INT_ST_AHEAD_MODE_V 0x00000003U +#define HINF_INT_ST_AHEAD_MODE_S 6 + +/** HINF_CONF_STATUS_REG register + * func0 config0 status + */ +#define HINF_CONF_STATUS_REG (DR_REG_HINF_BASE + 0x54) +/** HINF_FUNC0_CONFIG0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ +#define HINF_FUNC0_CONFIG0 0x000000FFU +#define HINF_FUNC0_CONFIG0_M (HINF_FUNC0_CONFIG0_V << HINF_FUNC0_CONFIG0_S) +#define HINF_FUNC0_CONFIG0_V 0x000000FFU +#define HINF_FUNC0_CONFIG0_S 0 +/** HINF_SDR25_ST : RO; bitpos: [8]; default: 0; + * sdr25 status + */ +#define HINF_SDR25_ST (BIT(8)) +#define HINF_SDR25_ST_M (HINF_SDR25_ST_V << HINF_SDR25_ST_S) +#define HINF_SDR25_ST_V 0x00000001U +#define HINF_SDR25_ST_S 8 +/** HINF_SDR50_ST : RO; bitpos: [9]; default: 0; + * sdr50 status + */ +#define HINF_SDR50_ST (BIT(9)) +#define HINF_SDR50_ST_M (HINF_SDR50_ST_V << HINF_SDR50_ST_S) +#define HINF_SDR50_ST_V 0x00000001U +#define HINF_SDR50_ST_S 9 +/** HINF_SDR104_ST : RO; bitpos: [10]; default: 0; + * sdr104 status + */ +#define HINF_SDR104_ST (BIT(10)) +#define HINF_SDR104_ST_M (HINF_SDR104_ST_V << HINF_SDR104_ST_S) +#define HINF_SDR104_ST_V 0x00000001U +#define HINF_SDR104_ST_S 10 +/** HINF_DDR50_ST : RO; bitpos: [11]; default: 0; + * ddr50 status + */ +#define HINF_DDR50_ST (BIT(11)) +#define HINF_DDR50_ST_M (HINF_DDR50_ST_V << HINF_DDR50_ST_S) +#define HINF_DDR50_ST_V 0x00000001U +#define HINF_DDR50_ST_S 11 +/** HINF_TUNE_ST : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ +#define HINF_TUNE_ST 0x00000007U +#define HINF_TUNE_ST_M (HINF_TUNE_ST_V << HINF_TUNE_ST_S) +#define HINF_TUNE_ST_V 0x00000007U +#define HINF_TUNE_ST_S 12 +/** HINF_SDIO_SWITCH_VOLT_ST : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ +#define HINF_SDIO_SWITCH_VOLT_ST (BIT(15)) +#define HINF_SDIO_SWITCH_VOLT_ST_M (HINF_SDIO_SWITCH_VOLT_ST_V << HINF_SDIO_SWITCH_VOLT_ST_S) +#define HINF_SDIO_SWITCH_VOLT_ST_V 0x00000001U +#define HINF_SDIO_SWITCH_VOLT_ST_S 15 +/** HINF_SDIO_SWITCH_END : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ +#define HINF_SDIO_SWITCH_END (BIT(16)) +#define HINF_SDIO_SWITCH_END_M (HINF_SDIO_SWITCH_END_V << HINF_SDIO_SWITCH_END_S) +#define HINF_SDIO_SWITCH_END_V 0x00000001U +#define HINF_SDIO_SWITCH_END_S 16 + +/** HINF_SDIO_SLAVE_LDO_CONF_REG register + * sdio slave ldo control register + */ +#define HINF_SDIO_SLAVE_LDO_CONF_REG (DR_REG_HINF_BASE + 0xb0) +/** HINF_LDO_READY_CTL_IN_EN : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ +#define HINF_LDO_READY_CTL_IN_EN (BIT(0)) +#define HINF_LDO_READY_CTL_IN_EN_M (HINF_LDO_READY_CTL_IN_EN_V << HINF_LDO_READY_CTL_IN_EN_S) +#define HINF_LDO_READY_CTL_IN_EN_V 0x00000001U +#define HINF_LDO_READY_CTL_IN_EN_S 0 +/** HINF_LDO_READY_THRES : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ +#define HINF_LDO_READY_THRES 0x0000001FU +#define HINF_LDO_READY_THRES_M (HINF_LDO_READY_THRES_V << HINF_LDO_READY_THRES_S) +#define HINF_LDO_READY_THRES_V 0x0000001FU +#define HINF_LDO_READY_THRES_S 1 +/** HINF_LDO_READY_IGNORE_EN : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ +#define HINF_LDO_READY_IGNORE_EN (BIT(6)) +#define HINF_LDO_READY_IGNORE_EN_M (HINF_LDO_READY_IGNORE_EN_V << HINF_LDO_READY_IGNORE_EN_S) +#define HINF_LDO_READY_IGNORE_EN_V 0x00000001U +#define HINF_LDO_READY_IGNORE_EN_S 6 + +/** HINF_SDIO_DATE_REG register + * ******* Description *********** + */ +#define HINF_SDIO_DATE_REG (DR_REG_HINF_BASE + 0xfc) +/** HINF_SDIO_DATE : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ +#define HINF_SDIO_DATE 0xFFFFFFFFU +#define HINF_SDIO_DATE_M (HINF_SDIO_DATE_V << HINF_SDIO_DATE_S) +#define HINF_SDIO_DATE_V 0xFFFFFFFFU +#define HINF_SDIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_hinf_struct.h b/components/soc/esp32c61/register/soc/sdio_hinf_struct.h new file mode 100644 index 0000000000..8b03a91781 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_hinf_struct.h @@ -0,0 +1,492 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of cfg_data0 register + * Configure sdio cis content + */ +typedef union { + struct { + /** device_id_fn1 : R/W; bitpos: [15:0]; default: 26214; + * configure device id of function1 in cis + */ + uint32_t device_id_fn1:16; + /** user_id_fn1 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function1 in cis + */ + uint32_t user_id_fn1:16; + }; + uint32_t val; +} hinf_cfg_data0_reg_t; + +/** Type of cfg_data1 register + * SDIO configuration register + */ +typedef union { + struct { + /** sdio_enable : R/W; bitpos: [0]; default: 1; + * Sdio clock enable + */ + uint32_t sdio_enable:1; + /** sdio_ioready1 : R/W; bitpos: [1]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready1:1; + /** highspeed_enable : R/W; bitpos: [2]; default: 0; + * Highspeed enable in cccr + */ + uint32_t highspeed_enable:1; + /** highspeed_mode : RO; bitpos: [3]; default: 0; + * highspeed mode status in cccr + */ + uint32_t highspeed_mode:1; + /** sdio_cd_enable : R/W; bitpos: [4]; default: 1; + * sdio card detect enable + */ + uint32_t sdio_cd_enable:1; + /** sdio_ioready2 : R/W; bitpos: [5]; default: 0; + * sdio function1 io ready signal in cis + */ + uint32_t sdio_ioready2:1; + /** sdio_int_mask : R/W; bitpos: [6]; default: 0; + * mask sdio interrupt in cccr, high active + */ + uint32_t sdio_int_mask:1; + /** ioenable2 : RO; bitpos: [7]; default: 0; + * ioe2 status in cccr + */ + uint32_t ioenable2:1; + /** cd_disable : RO; bitpos: [8]; default: 0; + * card disable status in cccr + */ + uint32_t cd_disable:1; + /** func1_eps : RO; bitpos: [9]; default: 0; + * function1 eps status in fbr + */ + uint32_t func1_eps:1; + /** emp : RO; bitpos: [10]; default: 0; + * empc status in cccr + */ + uint32_t emp:1; + /** ioenable1 : RO; bitpos: [11]; default: 0; + * ioe1 status in cccr + */ + uint32_t ioenable1:1; + /** sdio_ver : R/W; bitpos: [23:12]; default: 562; + * sdio version in cccr + */ + uint32_t sdio_ver:12; + /** func2_eps : RO; bitpos: [24]; default: 0; + * function2 eps status in fbr + */ + uint32_t func2_eps:1; + /** sdio20_conf : R/W; bitpos: [31:25]; default: 0; + * [29],sdio negedge sample enablel.[30],sdio posedge sample enable.[31],sdio cmd/dat + * in delayed cycles control,0:no delay, 1:delay 1 cycle. + * [25]: sdio1.1 dat/cmd sending out edge control,1:negedge,0:posedge when highseed + * mode. + * [26]: sdio2.0 dat/cmd sending out edge control,1:negedge when [12]=0,0:negedge when + * [12]=0,posedge when highspeed mode enable. + * [27]: sdio interrupt sending out delay control,1:delay one cycle, 0: no delay. + * [28]: sdio data pad pull up enable + */ + uint32_t sdio20_conf:7; + }; + uint32_t val; +} hinf_cfg_data1_reg_t; + +/** Type of cfg_timing register + * Timing configuration registers + */ +typedef union { + struct { + /** ncrc : R/W; bitpos: [2:0]; default: 2; + * configure Ncrc parameter in sdr50/104 mode, no more than 6. + */ + uint32_t ncrc:3; + /** pst_end_cmd_low_value : R/W; bitpos: [9:3]; default: 2; + * configure cycles to lower cmd after voltage is changed to 1.8V. + */ + uint32_t pst_end_cmd_low_value:7; + /** pst_end_data_low_value : R/W; bitpos: [15:10]; default: 2; + * configure cycles to lower data after voltage is changed to 1.8V. + */ + uint32_t pst_end_data_low_value:6; + /** sdclk_stop_thres : R/W; bitpos: [26:16]; default: 1400; + * Configure the number of cycles of module clk to judge sdclk has stopped + */ + uint32_t sdclk_stop_thres:11; + uint32_t reserved_27:1; + /** sample_clk_divider : R/W; bitpos: [31:28]; default: 1; + * module clk divider to sample sdclk + */ + uint32_t sample_clk_divider:4; + }; + uint32_t val; +} hinf_cfg_timing_reg_t; + +/** Type of cfg_update register + * update sdio configurations + */ +typedef union { + struct { + /** conf_update : WT; bitpos: [0]; default: 0; + * update the timing configurations + */ + uint32_t conf_update:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} hinf_cfg_update_reg_t; + +/** Type of cfg_data7 register + * SDIO configuration register + */ +typedef union { + struct { + /** pin_state : R/W; bitpos: [7:0]; default: 0; + * configure cis addr 318 and 574 + */ + uint32_t pin_state:8; + /** chip_state : R/W; bitpos: [15:8]; default: 0; + * configure cis addr 312, 315, 568 and 571 + */ + uint32_t chip_state:8; + /** sdio_rst : R/W; bitpos: [16]; default: 0; + * soft reset control for sdio module + */ + uint32_t sdio_rst:1; + /** sdio_ioready0 : R/W; bitpos: [17]; default: 1; + * sdio io ready, high enable + */ + uint32_t sdio_ioready0:1; + /** sdio_mem_pd : R/W; bitpos: [18]; default: 0; + * sdio memory power down, high active + */ + uint32_t sdio_mem_pd:1; + /** esdio_data1_int_en : R/W; bitpos: [19]; default: 0; + * enable sdio interrupt on data1 line + */ + uint32_t esdio_data1_int_en:1; + /** sdio_switch_volt_sw : R/W; bitpos: [20]; default: 0; + * control switch voltage change to 1.8V by software. 0:3.3V,1:1.8V + */ + uint32_t sdio_switch_volt_sw:1; + /** ddr50_blk_len_fix_en : R/W; bitpos: [21]; default: 0; + * enable block length to be fixed to 512 bytes in ddr50 mode + */ + uint32_t ddr50_blk_len_fix_en:1; + /** clk_en : R/W; bitpos: [22]; default: 0; + * sdio apb clock for configuration force on control:0-gating,1-force on. + */ + uint32_t clk_en:1; + /** sddr50 : R/W; bitpos: [23]; default: 1; + * configure if support sdr50 mode in cccr + */ + uint32_t sddr50:1; + /** ssdr104 : R/W; bitpos: [24]; default: 1; + * configure if support sdr104 mode in cccr + */ + uint32_t ssdr104:1; + /** ssdr50 : R/W; bitpos: [25]; default: 1; + * configure if support ddr50 mode in cccr + */ + uint32_t ssdr50:1; + /** sdtd : R/W; bitpos: [26]; default: 0; + * configure if support driver type D in cccr + */ + uint32_t sdtd:1; + /** sdta : R/W; bitpos: [27]; default: 0; + * configure if support driver type A in cccr + */ + uint32_t sdta:1; + /** sdtc : R/W; bitpos: [28]; default: 0; + * configure if support driver type C in cccr + */ + uint32_t sdtc:1; + /** sai : R/W; bitpos: [29]; default: 1; + * configure if support asynchronous interrupt in cccr + */ + uint32_t sai:1; + /** sdio_wakeup_clr : R/W; bitpos: [30]; default: 0; + * clear sdio_wake_up signal after the chip wakes up + */ + uint32_t sdio_wakeup_clr:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} hinf_cfg_data7_reg_t; + +/** Type of cis_conf_w0 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w0 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 39~36 + */ + uint32_t cis_conf_w0:32; + }; + uint32_t val; +} hinf_cis_conf_w0_reg_t; + +/** Type of cis_conf_w1 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w1 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 43~40 + */ + uint32_t cis_conf_w1:32; + }; + uint32_t val; +} hinf_cis_conf_w1_reg_t; + +/** Type of cis_conf_w2 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w2 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 47~44 + */ + uint32_t cis_conf_w2:32; + }; + uint32_t val; +} hinf_cis_conf_w2_reg_t; + +/** Type of cis_conf_w3 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w3 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 51~48 + */ + uint32_t cis_conf_w3:32; + }; + uint32_t val; +} hinf_cis_conf_w3_reg_t; + +/** Type of cis_conf_w4 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w4 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 55~52 + */ + uint32_t cis_conf_w4:32; + }; + uint32_t val; +} hinf_cis_conf_w4_reg_t; + +/** Type of cis_conf_w5 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w5 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 59~56 + */ + uint32_t cis_conf_w5:32; + }; + uint32_t val; +} hinf_cis_conf_w5_reg_t; + +/** Type of cis_conf_w6 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w6 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 63~60 + */ + uint32_t cis_conf_w6:32; + }; + uint32_t val; +} hinf_cis_conf_w6_reg_t; + +/** Type of cis_conf_w7 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** cis_conf_w7 : R/W; bitpos: [31:0]; default: 4294967295; + * Configure cis addr 67~64 + */ + uint32_t cis_conf_w7:32; + }; + uint32_t val; +} hinf_cis_conf_w7_reg_t; + +/** Type of cfg_data16 register + * SDIO cis configuration register + */ +typedef union { + struct { + /** device_id_fn2 : R/W; bitpos: [15:0]; default: 30583; + * configure device id of function2 in cis + */ + uint32_t device_id_fn2:16; + /** user_id_fn2 : R/W; bitpos: [31:16]; default: 146; + * configure user id of function2 in cis + */ + uint32_t user_id_fn2:16; + }; + uint32_t val; +} hinf_cfg_data16_reg_t; + +/** Type of cfg_uhs1_int_mode register + * configure int to start and end ahead of time in uhs1 mode + */ +typedef union { + struct { + /** intoe_end_ahead_mode : R/W; bitpos: [1:0]; default: 0; + * intoe on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_end_ahead_mode:2; + /** int_end_ahead_mode : R/W; bitpos: [3:2]; default: 0; + * int on dat1 end ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_end_ahead_mode:2; + /** intoe_st_ahead_mode : R/W; bitpos: [5:4]; default: 0; + * intoe on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t intoe_st_ahead_mode:2; + /** int_st_ahead_mode : R/W; bitpos: [7:6]; default: 0; + * int on dat1 start ahead of time: 0/3-no, 1-ahead 1sdclk, 2-ahead 2sdclk + */ + uint32_t int_st_ahead_mode:2; + uint32_t reserved_8:24; + }; + uint32_t val; +} hinf_cfg_uhs1_int_mode_reg_t; + +/** Type of sdio_slave_ldo_conf register + * sdio slave ldo control register + */ +typedef union { + struct { + /** ldo_ready_ctl_in_en : R/W; bitpos: [0]; default: 0; + * control ldo ready signal by sdio slave itself + */ + uint32_t ldo_ready_ctl_in_en:1; + /** ldo_ready_thres : R/W; bitpos: [5:1]; default: 10; + * configure ldo ready counting threshold value, the actual counting target is + * 2^(ldo_ready_thres)-1 + */ + uint32_t ldo_ready_thres:5; + /** ldo_ready_ignore_en : R/W; bitpos: [6]; default: 0; + * ignore ldo ready signal + */ + uint32_t ldo_ready_ignore_en:1; + uint32_t reserved_7:25; + }; + uint32_t val; +} hinf_sdio_slave_ldo_conf_reg_t; + + +/** Group: Status registers */ +/** Type of conf_status register + * func0 config0 status + */ +typedef union { + struct { + /** func0_config0 : RO; bitpos: [7:0]; default: 0; + * func0 config0 (addr: 0x20f0 ) status + */ + uint32_t func0_config0:8; + /** sdr25_st : RO; bitpos: [8]; default: 0; + * sdr25 status + */ + uint32_t sdr25_st:1; + /** sdr50_st : RO; bitpos: [9]; default: 0; + * sdr50 status + */ + uint32_t sdr50_st:1; + /** sdr104_st : RO; bitpos: [10]; default: 0; + * sdr104 status + */ + uint32_t sdr104_st:1; + /** ddr50_st : RO; bitpos: [11]; default: 0; + * ddr50 status + */ + uint32_t ddr50_st:1; + /** tune_st : RO; bitpos: [14:12]; default: 0; + * tune_st fsm status + */ + uint32_t tune_st:3; + /** sdio_switch_volt_st : RO; bitpos: [15]; default: 0; + * sdio switch voltage status:0-3.3V, 1-1.8V. + */ + uint32_t sdio_switch_volt_st:1; + /** sdio_switch_end : RO; bitpos: [16]; default: 0; + * sdio switch voltage ldo ready + */ + uint32_t sdio_switch_end:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} hinf_conf_status_reg_t; + + +/** Group: Version register */ +/** Type of sdio_date register + * ******* Description *********** + */ +typedef union { + struct { + /** sdio_date : R/W; bitpos: [31:0]; default: 37822544; + * sdio version date. + */ + uint32_t sdio_date:32; + }; + uint32_t val; +} hinf_sdio_date_reg_t; + + +typedef struct { + volatile hinf_cfg_data0_reg_t cfg_data0; + volatile hinf_cfg_data1_reg_t cfg_data1; + volatile hinf_cfg_timing_reg_t cfg_timing; + volatile hinf_cfg_update_reg_t cfg_update; + uint32_t reserved_010[3]; + volatile hinf_cfg_data7_reg_t cfg_data7; + volatile hinf_cis_conf_w0_reg_t cis_conf_w0; + volatile hinf_cis_conf_w1_reg_t cis_conf_w1; + volatile hinf_cis_conf_w2_reg_t cis_conf_w2; + volatile hinf_cis_conf_w3_reg_t cis_conf_w3; + volatile hinf_cis_conf_w4_reg_t cis_conf_w4; + volatile hinf_cis_conf_w5_reg_t cis_conf_w5; + volatile hinf_cis_conf_w6_reg_t cis_conf_w6; + volatile hinf_cis_conf_w7_reg_t cis_conf_w7; + volatile hinf_cfg_data16_reg_t cfg_data16; + volatile hinf_cfg_uhs1_int_mode_reg_t cfg_uhs1_int_mode; + uint32_t reserved_048[3]; + volatile hinf_conf_status_reg_t conf_status; + uint32_t reserved_058[22]; + volatile hinf_sdio_slave_ldo_conf_reg_t sdio_slave_ldo_conf; + uint32_t reserved_0b4[18]; + volatile hinf_sdio_date_reg_t sdio_date; +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifndef __cplusplus +_Static_assert(sizeof(hinf_dev_t) == 0x100, "Invalid size of hinf_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h b/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h new file mode 100644 index 0000000000..71fb89c394 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_host_reg.h @@ -0,0 +1,3883 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_HOST_FUNC2_0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_0_REG (DR_REG_HOST_BASE + 0x10) +/** SDIO_SLCHOST_SLC_FUNC2_INT : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC2_INT (BIT(24)) +#define SDIO_SLCHOST_SLC_FUNC2_INT_M (SDIO_SLCHOST_SLC_FUNC2_INT_V << SDIO_SLCHOST_SLC_FUNC2_INT_S) +#define SDIO_SLCHOST_SLC_FUNC2_INT_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC2_INT_S 24 + +/** SDIO_SLC_HOST_FUNC2_1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_1_REG (DR_REG_HOST_BASE + 0x14) +/** SDIO_SLCHOST_SLC_FUNC2_INT_EN : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN (BIT(0)) +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_M (SDIO_SLCHOST_SLC_FUNC2_INT_EN_V << SDIO_SLCHOST_SLC_FUNC2_INT_EN_S) +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC2_INT_EN_S 0 + +/** SDIO_SLC_HOST_FUNC2_2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_FUNC2_2_REG (DR_REG_HOST_BASE + 0x20) +/** SDIO_SLCHOST_SLC_FUNC1_MDSTAT : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_M (SDIO_SLCHOST_SLC_FUNC1_MDSTAT_V << SDIO_SLCHOST_SLC_FUNC1_MDSTAT_S) +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_V 0x00000001U +#define SDIO_SLCHOST_SLC_FUNC1_MDSTAT_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS0_REG (DR_REG_HOST_BASE + 0x34) +/** SDIO_SLCHOST_GPIO_SDIO_INT0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT0 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT0_M (SDIO_SLCHOST_GPIO_SDIO_INT0_V << SDIO_SLCHOST_GPIO_SDIO_INT0_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT0_S 0 + +/** SDIO_SLC_HOST_GPIO_STATUS1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_STATUS1_REG (DR_REG_HOST_BASE + 0x38) +/** SDIO_SLCHOST_GPIO_SDIO_INT1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT1 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT1_M (SDIO_SLCHOST_GPIO_SDIO_INT1_V << SDIO_SLCHOST_GPIO_SDIO_INT1_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_INT1_S 0 + +/** SDIO_SLC_HOST_GPIO_IN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN0_REG (DR_REG_HOST_BASE + 0x3c) +/** SDIO_SLCHOST_GPIO_SDIO_IN0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_IN0 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN0_M (SDIO_SLCHOST_GPIO_SDIO_IN0_V << SDIO_SLCHOST_GPIO_SDIO_IN0_S) +#define SDIO_SLCHOST_GPIO_SDIO_IN0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN0_S 0 + +/** SDIO_SLC_HOST_GPIO_IN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_GPIO_IN1_REG (DR_REG_HOST_BASE + 0x40) +/** SDIO_SLCHOST_GPIO_SDIO_IN1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_IN1 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN1_M (SDIO_SLCHOST_GPIO_SDIO_IN1_V << SDIO_SLCHOST_GPIO_SDIO_IN1_S) +#define SDIO_SLCHOST_GPIO_SDIO_IN1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_GPIO_SDIO_IN1_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_HOST_BASE + 0x44) +/** SDIO_SLCHOST_SLC0_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLCHOST_SLC0_TOKEN0_M (SDIO_SLCHOST_SLC0_TOKEN0_V << SDIO_SLCHOST_SLC0_TOKEN0_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0_TOKEN0_S 0 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID (BIT(12)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_S 12 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_TOKEN1_S 16 +/** SDIO_SLCHOST_SLC0_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_EOF 0x0000000FU +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_M (SDIO_SLCHOST_SLC0_RX_PF_EOF_V << SDIO_SLCHOST_SLC0_RX_PF_EOF_S) +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLCHOST_SLC0_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0_HOST_PF_REG (DR_REG_HOST_BASE + 0x48) +/** SDIO_SLCHOST_SLC0_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_PF_DATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0_PF_DATA_M (SDIO_SLCHOST_SLC0_PF_DATA_V << SDIO_SLCHOST_SLC0_PF_DATA_S) +#define SDIO_SLCHOST_SLC0_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC1_HOST_PF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1_HOST_PF_REG (DR_REG_HOST_BASE + 0x4c) +/** SDIO_SLCHOST_SLC1_PF_DATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_PF_DATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC1_PF_DATA_M (SDIO_SLCHOST_SLC1_PF_DATA_V << SDIO_SLCHOST_SLC1_PF_DATA_S) +#define SDIO_SLCHOST_SLC1_PF_DATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC1_PF_DATA_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_RAW_REG (DR_REG_HOST_BASE + 0x50) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_RAW_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_RAW_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_RAW : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_M (SDIO_SLCHOST_GPIO_SDIO_INT_RAW_V << SDIO_SLCHOST_GPIO_SDIO_INT_RAW_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_RAW_REG (DR_REG_HOST_BASE + 0x54) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_RAW_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_RAW_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_RAW_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_RAW_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_RAW_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_RAW_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_RAW_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_RAW_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_RAW_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_RAW_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_RAW_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_RAW_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_RAW_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_RAW_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_RAW_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_RAW_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_RAW_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ST_REG (DR_REG_HOST_BASE + 0x58) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ST_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ST_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ST_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ST_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_M (SDIO_SLCHOST_GPIO_SDIO_INT_ST_V << SDIO_SLCHOST_GPIO_SDIO_INT_ST_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ST_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ST_REG (DR_REG_HOST_BASE + 0x5c) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ST_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ST_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ST_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ST_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ST_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ST_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ST_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ST_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ST_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ST_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ST_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ST_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ST_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ST_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ST_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ST_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ST : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ST_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ST : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ST_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ST_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ST_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ST_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ST_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ST_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ST_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ST_S 25 + +/** SDIO_SLC_HOST_PKT_LEN_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN_REG (DR_REG_HOST_BASE + 0x60) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN_CHECK_S 20 + +/** SDIO_SLC_HOST_STATE_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W0_REG (DR_REG_HOST_BASE + 0x64) +/** SDIO_SLCHOST_SLCHOST_STATE0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE0 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE0_M (SDIO_SLCHOST_SLCHOST_STATE0_V << SDIO_SLCHOST_SLCHOST_STATE0_S) +#define SDIO_SLCHOST_SLCHOST_STATE0_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE0_S 0 +/** SDIO_SLCHOST_SLCHOST_STATE1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE1 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE1_M (SDIO_SLCHOST_SLCHOST_STATE1_V << SDIO_SLCHOST_SLCHOST_STATE1_S) +#define SDIO_SLCHOST_SLCHOST_STATE1_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE1_S 8 +/** SDIO_SLCHOST_SLCHOST_STATE2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE2 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE2_M (SDIO_SLCHOST_SLCHOST_STATE2_V << SDIO_SLCHOST_SLCHOST_STATE2_S) +#define SDIO_SLCHOST_SLCHOST_STATE2_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE2_S 16 +/** SDIO_SLCHOST_SLCHOST_STATE3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE3 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE3_M (SDIO_SLCHOST_SLCHOST_STATE3_V << SDIO_SLCHOST_SLCHOST_STATE3_S) +#define SDIO_SLCHOST_SLCHOST_STATE3_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE3_S 24 + +/** SDIO_SLC_HOST_STATE_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_STATE_W1_REG (DR_REG_HOST_BASE + 0x68) +/** SDIO_SLCHOST_SLCHOST_STATE4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE4 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE4_M (SDIO_SLCHOST_SLCHOST_STATE4_V << SDIO_SLCHOST_SLCHOST_STATE4_S) +#define SDIO_SLCHOST_SLCHOST_STATE4_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE4_S 0 +/** SDIO_SLCHOST_SLCHOST_STATE5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE5 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE5_M (SDIO_SLCHOST_SLCHOST_STATE5_V << SDIO_SLCHOST_SLCHOST_STATE5_S) +#define SDIO_SLCHOST_SLCHOST_STATE5_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE5_S 8 +/** SDIO_SLCHOST_SLCHOST_STATE6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE6 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE6_M (SDIO_SLCHOST_SLCHOST_STATE6_V << SDIO_SLCHOST_SLCHOST_STATE6_S) +#define SDIO_SLCHOST_SLCHOST_STATE6_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE6_S 16 +/** SDIO_SLCHOST_SLCHOST_STATE7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_STATE7 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE7_M (SDIO_SLCHOST_SLCHOST_STATE7_V << SDIO_SLCHOST_SLCHOST_STATE7_S) +#define SDIO_SLCHOST_SLCHOST_STATE7_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_STATE7_S 24 + +/** SDIO_SLC_HOST_CONF_W0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W0_REG (DR_REG_HOST_BASE + 0x6c) +/** SDIO_SLCHOST_SLCHOST_CONF0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF0 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF0_M (SDIO_SLCHOST_SLCHOST_CONF0_V << SDIO_SLCHOST_SLCHOST_CONF0_S) +#define SDIO_SLCHOST_SLCHOST_CONF0_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF0_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF1 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF1_M (SDIO_SLCHOST_SLCHOST_CONF1_V << SDIO_SLCHOST_SLCHOST_CONF1_S) +#define SDIO_SLCHOST_SLCHOST_CONF1_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF1_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF2 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF2_M (SDIO_SLCHOST_SLCHOST_CONF2_V << SDIO_SLCHOST_SLCHOST_CONF2_S) +#define SDIO_SLCHOST_SLCHOST_CONF2_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF2_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF3 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF3_M (SDIO_SLCHOST_SLCHOST_CONF3_V << SDIO_SLCHOST_SLCHOST_CONF3_S) +#define SDIO_SLCHOST_SLCHOST_CONF3_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF3_S 24 + +/** SDIO_SLC_HOST_CONF_W1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W1_REG (DR_REG_HOST_BASE + 0x70) +/** SDIO_SLCHOST_SLCHOST_CONF4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF4 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF4_M (SDIO_SLCHOST_SLCHOST_CONF4_V << SDIO_SLCHOST_SLCHOST_CONF4_S) +#define SDIO_SLCHOST_SLCHOST_CONF4_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF4_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF5 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF5_M (SDIO_SLCHOST_SLCHOST_CONF5_V << SDIO_SLCHOST_SLCHOST_CONF5_S) +#define SDIO_SLCHOST_SLCHOST_CONF5_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF5_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF6 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF6_M (SDIO_SLCHOST_SLCHOST_CONF6_V << SDIO_SLCHOST_SLCHOST_CONF6_S) +#define SDIO_SLCHOST_SLCHOST_CONF6_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF6_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF7 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF7_M (SDIO_SLCHOST_SLCHOST_CONF7_V << SDIO_SLCHOST_SLCHOST_CONF7_S) +#define SDIO_SLCHOST_SLCHOST_CONF7_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF7_S 24 + +/** SDIO_SLC_HOST_CONF_W2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W2_REG (DR_REG_HOST_BASE + 0x74) +/** SDIO_SLCHOST_SLCHOST_CONF8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF8 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF8_M (SDIO_SLCHOST_SLCHOST_CONF8_V << SDIO_SLCHOST_SLCHOST_CONF8_S) +#define SDIO_SLCHOST_SLCHOST_CONF8_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF8_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF9 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF9_M (SDIO_SLCHOST_SLCHOST_CONF9_V << SDIO_SLCHOST_SLCHOST_CONF9_S) +#define SDIO_SLCHOST_SLCHOST_CONF9_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF9_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF10 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF10_M (SDIO_SLCHOST_SLCHOST_CONF10_V << SDIO_SLCHOST_SLCHOST_CONF10_S) +#define SDIO_SLCHOST_SLCHOST_CONF10_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF10_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF11 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF11_M (SDIO_SLCHOST_SLCHOST_CONF11_V << SDIO_SLCHOST_SLCHOST_CONF11_S) +#define SDIO_SLCHOST_SLCHOST_CONF11_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF11_S 24 + +/** SDIO_SLC_HOST_CONF_W3_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W3_REG (DR_REG_HOST_BASE + 0x78) +/** SDIO_SLCHOST_SLCHOST_CONF12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF12 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF12_M (SDIO_SLCHOST_SLCHOST_CONF12_V << SDIO_SLCHOST_SLCHOST_CONF12_S) +#define SDIO_SLCHOST_SLCHOST_CONF12_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF12_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF13 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF13_M (SDIO_SLCHOST_SLCHOST_CONF13_V << SDIO_SLCHOST_SLCHOST_CONF13_S) +#define SDIO_SLCHOST_SLCHOST_CONF13_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF13_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF14 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF14_M (SDIO_SLCHOST_SLCHOST_CONF14_V << SDIO_SLCHOST_SLCHOST_CONF14_S) +#define SDIO_SLCHOST_SLCHOST_CONF14_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF14_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF15 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF15_M (SDIO_SLCHOST_SLCHOST_CONF15_V << SDIO_SLCHOST_SLCHOST_CONF15_S) +#define SDIO_SLCHOST_SLCHOST_CONF15_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF15_S 24 + +/** SDIO_SLC_HOST_CONF_W4_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W4_REG (DR_REG_HOST_BASE + 0x7c) +/** SDIO_SLCHOST_SLCHOST_CONF16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF16 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF16_M (SDIO_SLCHOST_SLCHOST_CONF16_V << SDIO_SLCHOST_SLCHOST_CONF16_S) +#define SDIO_SLCHOST_SLCHOST_CONF16_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF16_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF17 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF17_M (SDIO_SLCHOST_SLCHOST_CONF17_V << SDIO_SLCHOST_SLCHOST_CONF17_S) +#define SDIO_SLCHOST_SLCHOST_CONF17_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF17_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF18 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF18_M (SDIO_SLCHOST_SLCHOST_CONF18_V << SDIO_SLCHOST_SLCHOST_CONF18_S) +#define SDIO_SLCHOST_SLCHOST_CONF18_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF18_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF19 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF19_M (SDIO_SLCHOST_SLCHOST_CONF19_V << SDIO_SLCHOST_SLCHOST_CONF19_S) +#define SDIO_SLCHOST_SLCHOST_CONF19_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF19_S 24 + +/** SDIO_SLC_HOST_CONF_W5_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W5_REG (DR_REG_HOST_BASE + 0x80) +/** SDIO_SLCHOST_SLCHOST_CONF20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF20 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF20_M (SDIO_SLCHOST_SLCHOST_CONF20_V << SDIO_SLCHOST_SLCHOST_CONF20_S) +#define SDIO_SLCHOST_SLCHOST_CONF20_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF20_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF21 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF21_M (SDIO_SLCHOST_SLCHOST_CONF21_V << SDIO_SLCHOST_SLCHOST_CONF21_S) +#define SDIO_SLCHOST_SLCHOST_CONF21_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF21_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF22 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF22_M (SDIO_SLCHOST_SLCHOST_CONF22_V << SDIO_SLCHOST_SLCHOST_CONF22_S) +#define SDIO_SLCHOST_SLCHOST_CONF22_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF22_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF23 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF23_M (SDIO_SLCHOST_SLCHOST_CONF23_V << SDIO_SLCHOST_SLCHOST_CONF23_S) +#define SDIO_SLCHOST_SLCHOST_CONF23_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF23_S 24 + +/** SDIO_SLC_HOST_WIN_CMD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_WIN_CMD_REG (DR_REG_HOST_BASE + 0x84) +/** SDIO_SLCHOST_SLCHOST_WIN_CMD : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_WIN_CMD 0x0000FFFFU +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_M (SDIO_SLCHOST_SLCHOST_WIN_CMD_V << SDIO_SLCHOST_SLCHOST_WIN_CMD_S) +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_V 0x0000FFFFU +#define SDIO_SLCHOST_SLCHOST_WIN_CMD_S 0 + +/** SDIO_SLC_HOST_CONF_W6_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W6_REG (DR_REG_HOST_BASE + 0x88) +/** SDIO_SLCHOST_SLCHOST_CONF24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF24 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF24_M (SDIO_SLCHOST_SLCHOST_CONF24_V << SDIO_SLCHOST_SLCHOST_CONF24_S) +#define SDIO_SLCHOST_SLCHOST_CONF24_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF24_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF25 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF25_M (SDIO_SLCHOST_SLCHOST_CONF25_V << SDIO_SLCHOST_SLCHOST_CONF25_S) +#define SDIO_SLCHOST_SLCHOST_CONF25_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF25_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF26 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF26_M (SDIO_SLCHOST_SLCHOST_CONF26_V << SDIO_SLCHOST_SLCHOST_CONF26_S) +#define SDIO_SLCHOST_SLCHOST_CONF26_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF26_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF27 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF27_M (SDIO_SLCHOST_SLCHOST_CONF27_V << SDIO_SLCHOST_SLCHOST_CONF27_S) +#define SDIO_SLCHOST_SLCHOST_CONF27_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF27_S 24 + +/** SDIO_SLC_HOST_CONF_W7_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W7_REG (DR_REG_HOST_BASE + 0x8c) +/** SDIO_SLCHOST_SLCHOST_CONF28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF28 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF28_M (SDIO_SLCHOST_SLCHOST_CONF28_V << SDIO_SLCHOST_SLCHOST_CONF28_S) +#define SDIO_SLCHOST_SLCHOST_CONF28_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF28_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF29 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF29_M (SDIO_SLCHOST_SLCHOST_CONF29_V << SDIO_SLCHOST_SLCHOST_CONF29_S) +#define SDIO_SLCHOST_SLCHOST_CONF29_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF29_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF30 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF30_M (SDIO_SLCHOST_SLCHOST_CONF30_V << SDIO_SLCHOST_SLCHOST_CONF30_S) +#define SDIO_SLCHOST_SLCHOST_CONF30_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF30_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF31 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF31_M (SDIO_SLCHOST_SLCHOST_CONF31_V << SDIO_SLCHOST_SLCHOST_CONF31_S) +#define SDIO_SLCHOST_SLCHOST_CONF31_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF31_S 24 + +/** SDIO_SLC_HOST_PKT_LEN0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN0_REG (DR_REG_HOST_BASE + 0x90) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN0_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN1_REG (DR_REG_HOST_BASE + 0x94) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN1_CHECK_S 20 + +/** SDIO_SLC_HOST_PKT_LEN2_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_PKT_LEN2_REG (DR_REG_HOST_BASE + 0x98) +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_V 0x000FFFFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_S 0 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_M (SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V << SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC0_LEN2_CHECK_S 20 + +/** SDIO_SLC_HOST_CONF_W8_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W8_REG (DR_REG_HOST_BASE + 0x9c) +/** SDIO_SLCHOST_SLCHOST_CONF32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF32 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF32_M (SDIO_SLCHOST_SLCHOST_CONF32_V << SDIO_SLCHOST_SLCHOST_CONF32_S) +#define SDIO_SLCHOST_SLCHOST_CONF32_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF32_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF33 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF33_M (SDIO_SLCHOST_SLCHOST_CONF33_V << SDIO_SLCHOST_SLCHOST_CONF33_S) +#define SDIO_SLCHOST_SLCHOST_CONF33_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF33_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF34 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF34_M (SDIO_SLCHOST_SLCHOST_CONF34_V << SDIO_SLCHOST_SLCHOST_CONF34_S) +#define SDIO_SLCHOST_SLCHOST_CONF34_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF34_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF35 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF35_M (SDIO_SLCHOST_SLCHOST_CONF35_V << SDIO_SLCHOST_SLCHOST_CONF35_S) +#define SDIO_SLCHOST_SLCHOST_CONF35_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF35_S 24 + +/** SDIO_SLC_HOST_CONF_W9_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W9_REG (DR_REG_HOST_BASE + 0xa0) +/** SDIO_SLCHOST_SLCHOST_CONF36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF36 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF36_M (SDIO_SLCHOST_SLCHOST_CONF36_V << SDIO_SLCHOST_SLCHOST_CONF36_S) +#define SDIO_SLCHOST_SLCHOST_CONF36_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF36_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF37 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF37_M (SDIO_SLCHOST_SLCHOST_CONF37_V << SDIO_SLCHOST_SLCHOST_CONF37_S) +#define SDIO_SLCHOST_SLCHOST_CONF37_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF37_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF38 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF38_M (SDIO_SLCHOST_SLCHOST_CONF38_V << SDIO_SLCHOST_SLCHOST_CONF38_S) +#define SDIO_SLCHOST_SLCHOST_CONF38_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF38_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF39 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF39_M (SDIO_SLCHOST_SLCHOST_CONF39_V << SDIO_SLCHOST_SLCHOST_CONF39_S) +#define SDIO_SLCHOST_SLCHOST_CONF39_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF39_S 24 + +/** SDIO_SLC_HOST_CONF_W10_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W10_REG (DR_REG_HOST_BASE + 0xa4) +/** SDIO_SLCHOST_SLCHOST_CONF40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF40 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF40_M (SDIO_SLCHOST_SLCHOST_CONF40_V << SDIO_SLCHOST_SLCHOST_CONF40_S) +#define SDIO_SLCHOST_SLCHOST_CONF40_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF40_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF41 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF41_M (SDIO_SLCHOST_SLCHOST_CONF41_V << SDIO_SLCHOST_SLCHOST_CONF41_S) +#define SDIO_SLCHOST_SLCHOST_CONF41_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF41_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF42 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF42_M (SDIO_SLCHOST_SLCHOST_CONF42_V << SDIO_SLCHOST_SLCHOST_CONF42_S) +#define SDIO_SLCHOST_SLCHOST_CONF42_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF42_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF43 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF43_M (SDIO_SLCHOST_SLCHOST_CONF43_V << SDIO_SLCHOST_SLCHOST_CONF43_S) +#define SDIO_SLCHOST_SLCHOST_CONF43_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF43_S 24 + +/** SDIO_SLC_HOST_CONF_W11_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W11_REG (DR_REG_HOST_BASE + 0xa8) +/** SDIO_SLCHOST_SLCHOST_CONF44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF44 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF44_M (SDIO_SLCHOST_SLCHOST_CONF44_V << SDIO_SLCHOST_SLCHOST_CONF44_S) +#define SDIO_SLCHOST_SLCHOST_CONF44_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF44_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF45 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF45_M (SDIO_SLCHOST_SLCHOST_CONF45_V << SDIO_SLCHOST_SLCHOST_CONF45_S) +#define SDIO_SLCHOST_SLCHOST_CONF45_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF45_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF46 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF46_M (SDIO_SLCHOST_SLCHOST_CONF46_V << SDIO_SLCHOST_SLCHOST_CONF46_S) +#define SDIO_SLCHOST_SLCHOST_CONF46_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF46_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF47 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF47_M (SDIO_SLCHOST_SLCHOST_CONF47_V << SDIO_SLCHOST_SLCHOST_CONF47_S) +#define SDIO_SLCHOST_SLCHOST_CONF47_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF47_S 24 + +/** SDIO_SLC_HOST_CONF_W12_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W12_REG (DR_REG_HOST_BASE + 0xac) +/** SDIO_SLCHOST_SLCHOST_CONF48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF48 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF48_M (SDIO_SLCHOST_SLCHOST_CONF48_V << SDIO_SLCHOST_SLCHOST_CONF48_S) +#define SDIO_SLCHOST_SLCHOST_CONF48_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF48_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF49 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF49_M (SDIO_SLCHOST_SLCHOST_CONF49_V << SDIO_SLCHOST_SLCHOST_CONF49_S) +#define SDIO_SLCHOST_SLCHOST_CONF49_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF49_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF50 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF50_M (SDIO_SLCHOST_SLCHOST_CONF50_V << SDIO_SLCHOST_SLCHOST_CONF50_S) +#define SDIO_SLCHOST_SLCHOST_CONF50_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF50_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF51 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF51_M (SDIO_SLCHOST_SLCHOST_CONF51_V << SDIO_SLCHOST_SLCHOST_CONF51_S) +#define SDIO_SLCHOST_SLCHOST_CONF51_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF51_S 24 + +/** SDIO_SLC_HOST_CONF_W13_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W13_REG (DR_REG_HOST_BASE + 0xb0) +/** SDIO_SLCHOST_SLCHOST_CONF52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF52 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF52_M (SDIO_SLCHOST_SLCHOST_CONF52_V << SDIO_SLCHOST_SLCHOST_CONF52_S) +#define SDIO_SLCHOST_SLCHOST_CONF52_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF52_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF53 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF53_M (SDIO_SLCHOST_SLCHOST_CONF53_V << SDIO_SLCHOST_SLCHOST_CONF53_S) +#define SDIO_SLCHOST_SLCHOST_CONF53_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF53_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF54 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF54_M (SDIO_SLCHOST_SLCHOST_CONF54_V << SDIO_SLCHOST_SLCHOST_CONF54_S) +#define SDIO_SLCHOST_SLCHOST_CONF54_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF54_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF55 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF55_M (SDIO_SLCHOST_SLCHOST_CONF55_V << SDIO_SLCHOST_SLCHOST_CONF55_S) +#define SDIO_SLCHOST_SLCHOST_CONF55_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF55_S 24 + +/** SDIO_SLC_HOST_CONF_W14_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W14_REG (DR_REG_HOST_BASE + 0xb4) +/** SDIO_SLCHOST_SLCHOST_CONF56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF56 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF56_M (SDIO_SLCHOST_SLCHOST_CONF56_V << SDIO_SLCHOST_SLCHOST_CONF56_S) +#define SDIO_SLCHOST_SLCHOST_CONF56_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF56_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF57 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF57_M (SDIO_SLCHOST_SLCHOST_CONF57_V << SDIO_SLCHOST_SLCHOST_CONF57_S) +#define SDIO_SLCHOST_SLCHOST_CONF57_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF57_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF58 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF58_M (SDIO_SLCHOST_SLCHOST_CONF58_V << SDIO_SLCHOST_SLCHOST_CONF58_S) +#define SDIO_SLCHOST_SLCHOST_CONF58_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF58_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF59 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF59_M (SDIO_SLCHOST_SLCHOST_CONF59_V << SDIO_SLCHOST_SLCHOST_CONF59_S) +#define SDIO_SLCHOST_SLCHOST_CONF59_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF59_S 24 + +/** SDIO_SLC_HOST_CONF_W15_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_W15_REG (DR_REG_HOST_BASE + 0xb8) +/** SDIO_SLCHOST_SLCHOST_CONF60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF60 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF60_M (SDIO_SLCHOST_SLCHOST_CONF60_V << SDIO_SLCHOST_SLCHOST_CONF60_S) +#define SDIO_SLCHOST_SLCHOST_CONF60_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF60_S 0 +/** SDIO_SLCHOST_SLCHOST_CONF61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF61 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF61_M (SDIO_SLCHOST_SLCHOST_CONF61_V << SDIO_SLCHOST_SLCHOST_CONF61_S) +#define SDIO_SLCHOST_SLCHOST_CONF61_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF61_S 8 +/** SDIO_SLCHOST_SLCHOST_CONF62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CONF62 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF62_M (SDIO_SLCHOST_SLCHOST_CONF62_V << SDIO_SLCHOST_SLCHOST_CONF62_S) +#define SDIO_SLCHOST_SLCHOST_CONF62_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF62_S 16 +/** SDIO_SLCHOST_SLCHOST_CONF63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ +#define SDIO_SLCHOST_SLCHOST_CONF63 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF63_M (SDIO_SLCHOST_SLCHOST_CONF63_V << SDIO_SLCHOST_SLCHOST_CONF63_S) +#define SDIO_SLCHOST_SLCHOST_CONF63_V 0x000000FFU +#define SDIO_SLCHOST_SLCHOST_CONF63_S 24 + +/** SDIO_SLC_HOST_CHECK_SUM0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM0_REG (DR_REG_HOST_BASE + 0xbc) +/** SDIO_SLCHOST_SLCHOST_CHECK_SUM0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_M (SDIO_SLCHOST_SLCHOST_CHECK_SUM0_V << SDIO_SLCHOST_SLCHOST_CHECK_SUM0_S) +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM0_S 0 + +/** SDIO_SLC_HOST_CHECK_SUM1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CHECK_SUM1_REG (DR_REG_HOST_BASE + 0xc0) +/** SDIO_SLCHOST_SLCHOST_CHECK_SUM1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_M (SDIO_SLCHOST_SLCHOST_CHECK_SUM1_V << SDIO_SLCHOST_SLCHOST_CHECK_SUM1_S) +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_CHECK_SUM1_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_RDATA_REG (DR_REG_HOST_BASE + 0xc4) +/** SDIO_SLCHOST_SLC1_TOKEN0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLCHOST_SLC1_TOKEN0_M (SDIO_SLCHOST_SLC1_TOKEN0_V << SDIO_SLCHOST_SLC1_TOKEN0_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1_TOKEN0_S 0 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID (BIT(12)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_S 12 +/** SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_M (SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V << SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S) +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLCHOST_HOSTSLCHOST_SLC1_TOKEN1_S 16 +/** SDIO_SLCHOST_SLC1_RX_PF_EOF : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_EOF 0x0000000FU +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_M (SDIO_SLCHOST_SLC1_RX_PF_EOF_V << SDIO_SLCHOST_SLC1_RX_PF_EOF_S) +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_V 0x0000000FU +#define SDIO_SLCHOST_SLC1_RX_PF_EOF_S 28 + +/** SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_HOST_BASE + 0xc8) +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WD_S 0 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_TOKEN_WDATA_REG (DR_REG_HOST_BASE + 0xcc) +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_WD : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WD_S 0 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_WD : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_V 0x00000FFFU +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WD_S 16 + +/** SDIO_SLC_HOST_TOKEN_CON_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_TOKEN_CON_REG (DR_REG_HOST_BASE + 0xd0) +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_DEC_S 0 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_DEC_S 1 +/** SDIO_SLCHOST_SLC0HOST_TOKEN0_WR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_M (SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_V << SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN0_WR_S 2 +/** SDIO_SLCHOST_SLC0HOST_TOKEN1_WR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_M (SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_V << SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_S) +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TOKEN1_WR_S 3 +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC (BIT(4)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_DEC_S 4 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC (BIT(5)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_DEC_S 5 +/** SDIO_SLCHOST_SLC1HOST_TOKEN0_WR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR (BIT(6)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_M (SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_V << SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN0_WR_S 6 +/** SDIO_SLCHOST_SLC1HOST_TOKEN1_WR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR (BIT(7)) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_M (SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_V << SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_S) +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TOKEN1_WR_S 7 +/** SDIO_SLCHOST_SLC0HOST_LEN_WR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_LEN_WR (BIT(8)) +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_M (SDIO_SLCHOST_SLC0HOST_LEN_WR_V << SDIO_SLCHOST_SLC0HOST_LEN_WR_S) +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_LEN_WR_S 8 + +/** SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_CLR_REG (DR_REG_HOST_BASE + 0xd4) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_CLR_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_CLR_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_M (SDIO_SLCHOST_GPIO_SDIO_INT_CLR_V << SDIO_SLCHOST_GPIO_SDIO_INT_CLR_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_CLR_REG (DR_REG_HOST_BASE + 0xd8) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_CLR_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_CLR_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_CLR_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_CLR_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_CLR_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_CLR_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_CLR_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_CLR_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_CLR_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_CLR_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_CLR_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_CLR_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_CLR_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_CLR_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_CLR_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_CLR_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_CLR_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_HOST_BASE + 0xdc) +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC1_INT_ENA_REG (DR_REG_HOST_BASE + 0xe0) +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_FUNC2_INT_ENA_REG (DR_REG_HOST_BASE + 0xe4) +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_FUNC2_INT_ENA_REG (DR_REG_HOST_BASE + 0xe8) +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA_REG (DR_REG_HOST_BASE + 0xec) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_M (SDIO_SLCHOST_GPIO_SDIO_INT_ENA_V << SDIO_SLCHOST_GPIO_SDIO_INT_ENA_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA_REG (DR_REG_HOST_BASE + 0xf0) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA_S 25 + +/** SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_RX_INFOR_REG (DR_REG_HOST_BASE + 0xf4) +/** SDIO_SLCHOST_SLC0HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_M (SDIO_SLCHOST_SLC0HOST_RX_INFOR_V << SDIO_SLCHOST_SLC0HOST_RX_INFOR_S) +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLCHOST_SLC0HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_RX_INFOR_REG (DR_REG_HOST_BASE + 0xf8) +/** SDIO_SLCHOST_SLC1HOST_RX_INFOR : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR 0x000FFFFFU +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_M (SDIO_SLCHOST_SLC1HOST_RX_INFOR_V << SDIO_SLCHOST_SLC1HOST_RX_INFOR_S) +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_V 0x000FFFFFU +#define SDIO_SLCHOST_SLC1HOST_RX_INFOR_S 0 + +/** SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_LEN_WD_REG (DR_REG_HOST_BASE + 0xfc) +/** SDIO_SLCHOST_SLC0HOST_LEN_WD : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_LEN_WD 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_M (SDIO_SLCHOST_SLC0HOST_LEN_WD_V << SDIO_SLCHOST_SLC0HOST_LEN_WD_S) +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC0HOST_LEN_WD_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_WDATA_REG (DR_REG_HOST_BASE + 0x100) +/** SDIO_SLCHOST_SLC_APBWIN_WDATA : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_WDATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_M (SDIO_SLCHOST_SLC_APBWIN_WDATA_V << SDIO_SLCHOST_SLC_APBWIN_WDATA_S) +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_WDATA_S 0 + +/** SDIO_SLC_HOST_SLC_APBWIN_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_CONF_REG (DR_REG_HOST_BASE + 0x104) +/** SDIO_SLCHOST_SLC_APBWIN_ADDR : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_ADDR 0x0FFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_M (SDIO_SLCHOST_SLC_APBWIN_ADDR_V << SDIO_SLCHOST_SLC_APBWIN_ADDR_S) +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_V 0x0FFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_ADDR_S 0 +/** SDIO_SLCHOST_SLC_APBWIN_WR : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_WR (BIT(28)) +#define SDIO_SLCHOST_SLC_APBWIN_WR_M (SDIO_SLCHOST_SLC_APBWIN_WR_V << SDIO_SLCHOST_SLC_APBWIN_WR_S) +#define SDIO_SLCHOST_SLC_APBWIN_WR_V 0x00000001U +#define SDIO_SLCHOST_SLC_APBWIN_WR_S 28 +/** SDIO_SLCHOST_SLC_APBWIN_START : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_START (BIT(29)) +#define SDIO_SLCHOST_SLC_APBWIN_START_M (SDIO_SLCHOST_SLC_APBWIN_START_V << SDIO_SLCHOST_SLC_APBWIN_START_S) +#define SDIO_SLCHOST_SLC_APBWIN_START_V 0x00000001U +#define SDIO_SLCHOST_SLC_APBWIN_START_S 29 + +/** SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC_APBWIN_RDATA_REG (DR_REG_HOST_BASE + 0x108) +/** SDIO_SLCHOST_SLC_APBWIN_RDATA : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC_APBWIN_RDATA 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_M (SDIO_SLCHOST_SLC_APBWIN_RDATA_V << SDIO_SLCHOST_SLC_APBWIN_RDATA_S) +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLC_APBWIN_RDATA_S 0 + +/** SDIO_SLC_HOST_RDCLR0_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR0_REG (DR_REG_HOST_BASE + 0x10c) +/** SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 +/** SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_RDCLR1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_RDCLR1_REG (DR_REG_HOST_BASE + 0x110) +/** SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT7_CLRADDR_S 0 +/** SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_M (SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V << SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S) +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_V 0x000001FFU +#define SDIO_SLCHOST_SLCHOST_SLC1_BIT6_CLRADDR_S 9 + +/** SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC0HOST_INT_ENA1_REG (DR_REG_HOST_BASE + 0x114) +/** SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_M (SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_V << SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLCHOST_GPIO_SDIO_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_M (SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_V << SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_S) +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_GPIO_SDIO_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_SLC1HOST_INT_ENA1_REG (DR_REG_HOST_BASE + 0x118) +/** SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_1TO0_INT_ENA1_S 8 +/** SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_1TO0_INT_ENA1_S 9 +/** SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN0_0TO1_INT_ENA1_S 10 +/** SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_M (SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V << SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TOKEN1_0TO1_INT_ENA1_S 11 +/** SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_SOF_INT_ENA1_S 12 +/** SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_EOF_INT_ENA1_S 13 +/** SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1 (BIT(14)) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_RX_START_INT_ENA1_S 14 +/** SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1 (BIT(15)) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_M (SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_V << SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1HOST_TX_START_INT_ENA1_S 15 +/** SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1 (BIT(16)) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_UDF_INT_ENA1_S 16 +/** SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1 (BIT(17)) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_TX_OVF_INT_ENA1_S 17 +/** SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_M (SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V << SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_RX_PF_VALID_INT_ENA1_S 18 +/** SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1 (BIT(19)) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT0_INT_ENA1_S 19 +/** SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1 (BIT(20)) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT1_INT_ENA1_S 20 +/** SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1 (BIT(21)) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT2_INT_ENA1_S 21 +/** SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1 (BIT(22)) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_M (SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V << SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_EXT_BIT3_INT_ENA1_S 22 +/** SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_S 23 +/** SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_M (SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V << SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_HOST_RD_RETRY_INT_ENA1_S 24 +/** SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1 (BIT(25)) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_M (SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V << SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S) +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_V 0x00000001U +#define SDIO_SLCHOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1_S 25 + +/** SDIO_SLC_HOST_DATE_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_DATE_REG (DR_REG_HOST_BASE + 0x178) +/** SDIO_SLCHOST_SLCHOST_DATE : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_DATE 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_DATE_M (SDIO_SLCHOST_SLCHOST_DATE_V << SDIO_SLCHOST_SLCHOST_DATE_S) +#define SDIO_SLCHOST_SLCHOST_DATE_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_DATE_S 0 + +/** SDIO_SLC_HOST_ID_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_ID_REG (DR_REG_HOST_BASE + 0x17c) +/** SDIO_SLCHOST_SLCHOST_ID : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ +#define SDIO_SLCHOST_SLCHOST_ID 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_ID_M (SDIO_SLCHOST_SLCHOST_ID_V << SDIO_SLCHOST_SLCHOST_ID_S) +#define SDIO_SLCHOST_SLCHOST_ID_V 0xFFFFFFFFU +#define SDIO_SLCHOST_SLCHOST_ID_S 0 + +/** SDIO_SLC_HOST_CONF_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_CONF_REG (DR_REG_HOST_BASE + 0x1f0) +/** SDIO_SLCHOST_FRC_SDIO11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_SDIO11 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO11_M (SDIO_SLCHOST_FRC_SDIO11_V << SDIO_SLCHOST_FRC_SDIO11_S) +#define SDIO_SLCHOST_FRC_SDIO11_V 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO11_S 0 +/** SDIO_SLCHOST_FRC_SDIO20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_SDIO20 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO20_M (SDIO_SLCHOST_FRC_SDIO20_V << SDIO_SLCHOST_FRC_SDIO20_S) +#define SDIO_SLCHOST_FRC_SDIO20_V 0x0000001FU +#define SDIO_SLCHOST_FRC_SDIO20_S 5 +/** SDIO_SLCHOST_FRC_NEG_SAMP : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_NEG_SAMP 0x0000001FU +#define SDIO_SLCHOST_FRC_NEG_SAMP_M (SDIO_SLCHOST_FRC_NEG_SAMP_V << SDIO_SLCHOST_FRC_NEG_SAMP_S) +#define SDIO_SLCHOST_FRC_NEG_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_FRC_NEG_SAMP_S 10 +/** SDIO_SLCHOST_FRC_POS_SAMP : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_POS_SAMP 0x0000001FU +#define SDIO_SLCHOST_FRC_POS_SAMP_M (SDIO_SLCHOST_FRC_POS_SAMP_V << SDIO_SLCHOST_FRC_POS_SAMP_S) +#define SDIO_SLCHOST_FRC_POS_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_FRC_POS_SAMP_S 15 +/** SDIO_SLCHOST_FRC_QUICK_IN : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_FRC_QUICK_IN 0x0000001FU +#define SDIO_SLCHOST_FRC_QUICK_IN_M (SDIO_SLCHOST_FRC_QUICK_IN_V << SDIO_SLCHOST_FRC_QUICK_IN_S) +#define SDIO_SLCHOST_FRC_QUICK_IN_V 0x0000001FU +#define SDIO_SLCHOST_FRC_QUICK_IN_S 20 +/** SDIO_SLCHOST_SDIO20_INT_DELAY : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO20_INT_DELAY (BIT(25)) +#define SDIO_SLCHOST_SDIO20_INT_DELAY_M (SDIO_SLCHOST_SDIO20_INT_DELAY_V << SDIO_SLCHOST_SDIO20_INT_DELAY_S) +#define SDIO_SLCHOST_SDIO20_INT_DELAY_V 0x00000001U +#define SDIO_SLCHOST_SDIO20_INT_DELAY_S 25 +/** SDIO_SLCHOST_SDIO_PAD_PULLUP : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_PAD_PULLUP (BIT(26)) +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_M (SDIO_SLCHOST_SDIO_PAD_PULLUP_V << SDIO_SLCHOST_SDIO_PAD_PULLUP_S) +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_V 0x00000001U +#define SDIO_SLCHOST_SDIO_PAD_PULLUP_S 26 +/** SDIO_SLCHOST_HSPEED_CON_EN : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_HSPEED_CON_EN (BIT(27)) +#define SDIO_SLCHOST_HSPEED_CON_EN_M (SDIO_SLCHOST_HSPEED_CON_EN_V << SDIO_SLCHOST_HSPEED_CON_EN_S) +#define SDIO_SLCHOST_HSPEED_CON_EN_V 0x00000001U +#define SDIO_SLCHOST_HSPEED_CON_EN_S 27 + +/** SDIO_SLC_HOST_INF_ST_REG register + * *******Description*********** + */ +#define SDIO_SLC_HOST_INF_ST_REG (DR_REG_HOST_BASE + 0x1f4) +/** SDIO_SLCHOST_SDIO20_MODE : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO20_MODE 0x0000001FU +#define SDIO_SLCHOST_SDIO20_MODE_M (SDIO_SLCHOST_SDIO20_MODE_V << SDIO_SLCHOST_SDIO20_MODE_S) +#define SDIO_SLCHOST_SDIO20_MODE_V 0x0000001FU +#define SDIO_SLCHOST_SDIO20_MODE_S 0 +/** SDIO_SLCHOST_SDIO_NEG_SAMP : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_NEG_SAMP 0x0000001FU +#define SDIO_SLCHOST_SDIO_NEG_SAMP_M (SDIO_SLCHOST_SDIO_NEG_SAMP_V << SDIO_SLCHOST_SDIO_NEG_SAMP_S) +#define SDIO_SLCHOST_SDIO_NEG_SAMP_V 0x0000001FU +#define SDIO_SLCHOST_SDIO_NEG_SAMP_S 5 +/** SDIO_SLCHOST_SDIO_QUICK_IN : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ +#define SDIO_SLCHOST_SDIO_QUICK_IN 0x0000001FU +#define SDIO_SLCHOST_SDIO_QUICK_IN_M (SDIO_SLCHOST_SDIO_QUICK_IN_V << SDIO_SLCHOST_SDIO_QUICK_IN_S) +#define SDIO_SLCHOST_SDIO_QUICK_IN_V 0x0000001FU +#define SDIO_SLCHOST_SDIO_QUICK_IN_S 10 +/** SDIO_SLCHOST_DLL_ON_SW : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ +#define SDIO_SLCHOST_DLL_ON_SW (BIT(15)) +#define SDIO_SLCHOST_DLL_ON_SW_M (SDIO_SLCHOST_DLL_ON_SW_V << SDIO_SLCHOST_DLL_ON_SW_S) +#define SDIO_SLCHOST_DLL_ON_SW_V 0x00000001U +#define SDIO_SLCHOST_DLL_ON_SW_S 15 +/** SDIO_SLCHOST_DLL_ON : R/W; bitpos: [16]; default: 0; + * Software dll on + */ +#define SDIO_SLCHOST_DLL_ON (BIT(16)) +#define SDIO_SLCHOST_DLL_ON_M (SDIO_SLCHOST_DLL_ON_V << SDIO_SLCHOST_DLL_ON_S) +#define SDIO_SLCHOST_DLL_ON_V 0x00000001U +#define SDIO_SLCHOST_DLL_ON_S 16 +/** SDIO_SLCHOST_CLK_MODE_SW : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ +#define SDIO_SLCHOST_CLK_MODE_SW (BIT(17)) +#define SDIO_SLCHOST_CLK_MODE_SW_M (SDIO_SLCHOST_CLK_MODE_SW_V << SDIO_SLCHOST_CLK_MODE_SW_S) +#define SDIO_SLCHOST_CLK_MODE_SW_V 0x00000001U +#define SDIO_SLCHOST_CLK_MODE_SW_S 17 +/** SDIO_SLCHOST_CLK_MODE : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ +#define SDIO_SLCHOST_CLK_MODE 0x00000003U +#define SDIO_SLCHOST_CLK_MODE_M (SDIO_SLCHOST_CLK_MODE_V << SDIO_SLCHOST_CLK_MODE_S) +#define SDIO_SLCHOST_CLK_MODE_V 0x00000003U +#define SDIO_SLCHOST_CLK_MODE_S 18 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h b/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h new file mode 100644 index 0000000000..94964cd0c7 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_host_struct.h @@ -0,0 +1,2738 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: ********Registers */ +/** Type of slc_host_func2_0 register + * *******Description*********** + */ +typedef union { + struct { + uint32_t reserved_0:24; + /** slchost_slc_func2_int : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_func2_int:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_host_func2_0_reg_t; + +/** Type of slc_host_func2_1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_func2_int_en : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_func2_int_en:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_1_reg_t; + +/** Type of slc_host_func2_2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_func1_mdstat : R/W; bitpos: [0]; default: 1; + * *******Description*********** + */ + uint32_t slchost_slc_func1_mdstat:1; + uint32_t reserved_1:31; + }; + uint32_t val; +} sdio_slc_host_func2_2_reg_t; + +/** Type of slc_host_gpio_status0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_int0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status0_reg_t; + +/** Type of slc_host_gpio_status1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_int1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_status1_reg_t; + +/** Type of slc_host_gpio_in0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_in0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_in0:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in0_reg_t; + +/** Type of slc_host_gpio_in1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_gpio_sdio_in1 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_in1:32; + }; + uint32_t val; +} sdio_slc_host_gpio_in1_reg_t; + +/** Type of slc_host_slc0host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0:12; + /** slchost_slc0_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid:1; + uint32_t reserved_13:3; + /** slchost_hostslchost_slc0_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_token1:12; + /** slchost_slc0_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_rdata_reg_t; + +/** Type of slc_host_slc0_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc0_host_pf_reg_t; + +/** Type of slc_host_slc1_host_pf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_pf_data : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_pf_data:32; + }; + uint32_t val; +} sdio_slc_host_slc1_host_pf_reg_t; + +/** Type of slc_host_slc0host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_raw:1; + /** slchost_slc0_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_raw:1; + /** slchost_slc0_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_raw:1; + /** slchost_slc0_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_raw:1; + /** slchost_slc0_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_raw:1; + /** slchost_slc0_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_raw:1; + /** slchost_slc0_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_raw:1; + /** slchost_slc0_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_raw:1; + /** slchost_slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_raw:1; + /** slchost_slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_raw:1; + /** slchost_slc0_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_raw:1; + /** slchost_slc0_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_raw:1; + /** slchost_slc0host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_raw:1; + /** slchost_slc0host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_raw:1; + /** slchost_slc0host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_raw:1; + /** slchost_slc0host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_raw:1; + /** slchost_slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_raw:1; + /** slchost_slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_raw:1; + /** slchost_slc0_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_raw:1; + /** slchost_slc0_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_raw:1; + /** slchost_slc0_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_raw:1; + /** slchost_slc0_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_raw:1; + /** slchost_slc0_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_raw:1; + /** slchost_slc0_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_raw:1; + /** slchost_slc0_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_raw:1; + /** slchost_gpio_sdio_int_raw : R/WTC/SS/SC; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_raw_reg_t; + +/** Type of slc_host_slc1host_int_raw register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_raw:1; + /** slchost_slc1_tohost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_raw:1; + /** slchost_slc1_tohost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_raw:1; + /** slchost_slc1_tohost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_raw:1; + /** slchost_slc1_tohost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_raw:1; + /** slchost_slc1_tohost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_raw:1; + /** slchost_slc1_tohost_bit6_int_raw : R/WTC/SS/SC; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_raw:1; + /** slchost_slc1_tohost_bit7_int_raw : R/WTC/SS/SC; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_raw:1; + /** slchost_slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_raw:1; + /** slchost_slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_raw:1; + /** slchost_slc1_token0_0to1_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_raw:1; + /** slchost_slc1_token1_0to1_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_raw:1; + /** slchost_slc1host_rx_sof_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_raw:1; + /** slchost_slc1host_rx_eof_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_raw:1; + /** slchost_slc1host_rx_start_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_raw:1; + /** slchost_slc1host_tx_start_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_raw:1; + /** slchost_slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_raw:1; + /** slchost_slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_raw:1; + /** slchost_slc1_rx_pf_valid_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_raw:1; + /** slchost_slc1_ext_bit0_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_raw:1; + /** slchost_slc1_ext_bit1_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_raw:1; + /** slchost_slc1_ext_bit2_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_raw:1; + /** slchost_slc1_ext_bit3_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_raw:1; + /** slchost_slc1_wifi_rx_new_packet_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_raw:1; + /** slchost_slc1_host_rd_retry_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_raw:1; + /** slchost_slc1_bt_rx_new_packet_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_raw:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_raw_reg_t; + +/** Type of slc_host_slc0host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_st:1; + /** slchost_slc0_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_st:1; + /** slchost_slc0_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_st:1; + /** slchost_slc0_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_st:1; + /** slchost_slc0_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_st:1; + /** slchost_slc0_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_st:1; + /** slchost_slc0_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_st:1; + /** slchost_slc0_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_st:1; + /** slchost_slc0_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_st:1; + /** slchost_slc0_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_st:1; + /** slchost_slc0_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_st:1; + /** slchost_slc0_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_st:1; + /** slchost_slc0host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_st:1; + /** slchost_slc0host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_st:1; + /** slchost_slc0host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_st:1; + /** slchost_slc0host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_st:1; + /** slchost_slc0_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_st:1; + /** slchost_slc0_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_st:1; + /** slchost_slc0_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_st:1; + /** slchost_slc0_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_st:1; + /** slchost_slc0_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_st:1; + /** slchost_slc0_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_st:1; + /** slchost_slc0_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_st:1; + /** slchost_slc0_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_st:1; + /** slchost_slc0_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_st:1; + /** slchost_gpio_sdio_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_st_reg_t; + +/** Type of slc_host_slc1host_int_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_st : RO; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_st:1; + /** slchost_slc1_tohost_bit1_int_st : RO; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_st:1; + /** slchost_slc1_tohost_bit2_int_st : RO; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_st:1; + /** slchost_slc1_tohost_bit3_int_st : RO; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_st:1; + /** slchost_slc1_tohost_bit4_int_st : RO; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_st:1; + /** slchost_slc1_tohost_bit5_int_st : RO; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_st:1; + /** slchost_slc1_tohost_bit6_int_st : RO; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_st:1; + /** slchost_slc1_tohost_bit7_int_st : RO; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_st:1; + /** slchost_slc1_token0_1to0_int_st : RO; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_st:1; + /** slchost_slc1_token1_1to0_int_st : RO; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_st:1; + /** slchost_slc1_token0_0to1_int_st : RO; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_st:1; + /** slchost_slc1_token1_0to1_int_st : RO; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_st:1; + /** slchost_slc1host_rx_sof_int_st : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_st:1; + /** slchost_slc1host_rx_eof_int_st : RO; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_st:1; + /** slchost_slc1host_rx_start_int_st : RO; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_st:1; + /** slchost_slc1host_tx_start_int_st : RO; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_st:1; + /** slchost_slc1_rx_udf_int_st : RO; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_st:1; + /** slchost_slc1_tx_ovf_int_st : RO; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_st:1; + /** slchost_slc1_rx_pf_valid_int_st : RO; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_st:1; + /** slchost_slc1_ext_bit0_int_st : RO; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_st:1; + /** slchost_slc1_ext_bit1_int_st : RO; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_st:1; + /** slchost_slc1_ext_bit2_int_st : RO; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_st:1; + /** slchost_slc1_ext_bit3_int_st : RO; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_st:1; + /** slchost_slc1_wifi_rx_new_packet_int_st : RO; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_st:1; + /** slchost_slc1_host_rd_retry_int_st : RO; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_st:1; + /** slchost_slc1_bt_rx_new_packet_int_st : RO; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_st:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_st_reg_t; + +/** Type of slc_host_pkt_len register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len:20; + /** slchost_hostslchost_slc0_len_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len_reg_t; + +/** Type of slc_host_state_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_state0 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state0:8; + /** slchost_slchost_state1 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state1:8; + /** slchost_slchost_state2 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state2:8; + /** slchost_slchost_state3 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state3:8; + }; + uint32_t val; +} sdio_slc_host_state_w0_reg_t; + +/** Type of slc_host_state_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_state4 : RO; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state4:8; + /** slchost_slchost_state5 : RO; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state5:8; + /** slchost_slchost_state6 : RO; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state6:8; + /** slchost_slchost_state7 : RO; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_state7:8; + }; + uint32_t val; +} sdio_slc_host_state_w1_reg_t; + +/** Type of slc_host_conf_w0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf0 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf0:8; + /** slchost_slchost_conf1 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf1:8; + /** slchost_slchost_conf2 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf2:8; + /** slchost_slchost_conf3 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf3:8; + }; + uint32_t val; +} sdio_slc_host_conf_w0_reg_t; + +/** Type of slc_host_conf_w1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf4 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf4:8; + /** slchost_slchost_conf5 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf5:8; + /** slchost_slchost_conf6 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf6:8; + /** slchost_slchost_conf7 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf7:8; + }; + uint32_t val; +} sdio_slc_host_conf_w1_reg_t; + +/** Type of slc_host_conf_w2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf8 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf8:8; + /** slchost_slchost_conf9 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf9:8; + /** slchost_slchost_conf10 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf10:8; + /** slchost_slchost_conf11 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf11:8; + }; + uint32_t val; +} sdio_slc_host_conf_w2_reg_t; + +/** Type of slc_host_conf_w3 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf12 : R/W; bitpos: [7:0]; default: 192; + * *******Description*********** + */ + uint32_t slchost_slchost_conf12:8; + /** slchost_slchost_conf13 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf13:8; + /** slchost_slchost_conf14 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf14:8; + /** slchost_slchost_conf15 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf15:8; + }; + uint32_t val; +} sdio_slc_host_conf_w3_reg_t; + +/** Type of slc_host_conf_w4 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf16 : R/W; bitpos: [7:0]; default: 255; + * *******Description*********** + */ + uint32_t slchost_slchost_conf16:8; + /** slchost_slchost_conf17 : R/W; bitpos: [15:8]; default: 1; + * *******Description*********** + */ + uint32_t slchost_slchost_conf17:8; + /** slchost_slchost_conf18 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf18:8; + /** slchost_slchost_conf19 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf19:8; + }; + uint32_t val; +} sdio_slc_host_conf_w4_reg_t; + +/** Type of slc_host_conf_w5 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf20 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf20:8; + /** slchost_slchost_conf21 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf21:8; + /** slchost_slchost_conf22 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf22:8; + /** slchost_slchost_conf23 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf23:8; + }; + uint32_t val; +} sdio_slc_host_conf_w5_reg_t; + +/** Type of slc_host_win_cmd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_win_cmd : R/W; bitpos: [15:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_win_cmd:16; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_host_win_cmd_reg_t; + +/** Type of slc_host_conf_w6 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf24 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf24:8; + /** slchost_slchost_conf25 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf25:8; + /** slchost_slchost_conf26 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf26:8; + /** slchost_slchost_conf27 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf27:8; + }; + uint32_t val; +} sdio_slc_host_conf_w6_reg_t; + +/** Type of slc_host_conf_w7 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf28 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf28:8; + /** slchost_slchost_conf29 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf29:8; + /** slchost_slchost_conf30 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf30:8; + /** slchost_slchost_conf31 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf31:8; + }; + uint32_t val; +} sdio_slc_host_conf_w7_reg_t; + +/** Type of slc_host_pkt_len0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len0 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len0:20; + /** slchost_hostslchost_slc0_len0_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len0_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len0_reg_t; + +/** Type of slc_host_pkt_len1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len1 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len1:20; + /** slchost_hostslchost_slc0_len1_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len1_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len1_reg_t; + +/** Type of slc_host_pkt_len2 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_hostslchost_slc0_len2 : RO; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len2:20; + /** slchost_hostslchost_slc0_len2_check : RO; bitpos: [31:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc0_len2_check:12; + }; + uint32_t val; +} sdio_slc_host_pkt_len2_reg_t; + +/** Type of slc_host_conf_w8 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf32 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf32:8; + /** slchost_slchost_conf33 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf33:8; + /** slchost_slchost_conf34 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf34:8; + /** slchost_slchost_conf35 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf35:8; + }; + uint32_t val; +} sdio_slc_host_conf_w8_reg_t; + +/** Type of slc_host_conf_w9 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf36 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf36:8; + /** slchost_slchost_conf37 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf37:8; + /** slchost_slchost_conf38 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf38:8; + /** slchost_slchost_conf39 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf39:8; + }; + uint32_t val; +} sdio_slc_host_conf_w9_reg_t; + +/** Type of slc_host_conf_w10 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf40 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf40:8; + /** slchost_slchost_conf41 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf41:8; + /** slchost_slchost_conf42 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf42:8; + /** slchost_slchost_conf43 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf43:8; + }; + uint32_t val; +} sdio_slc_host_conf_w10_reg_t; + +/** Type of slc_host_conf_w11 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf44 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf44:8; + /** slchost_slchost_conf45 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf45:8; + /** slchost_slchost_conf46 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf46:8; + /** slchost_slchost_conf47 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf47:8; + }; + uint32_t val; +} sdio_slc_host_conf_w11_reg_t; + +/** Type of slc_host_conf_w12 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf48 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf48:8; + /** slchost_slchost_conf49 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf49:8; + /** slchost_slchost_conf50 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf50:8; + /** slchost_slchost_conf51 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf51:8; + }; + uint32_t val; +} sdio_slc_host_conf_w12_reg_t; + +/** Type of slc_host_conf_w13 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf52 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf52:8; + /** slchost_slchost_conf53 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf53:8; + /** slchost_slchost_conf54 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf54:8; + /** slchost_slchost_conf55 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf55:8; + }; + uint32_t val; +} sdio_slc_host_conf_w13_reg_t; + +/** Type of slc_host_conf_w14 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf56 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf56:8; + /** slchost_slchost_conf57 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf57:8; + /** slchost_slchost_conf58 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf58:8; + /** slchost_slchost_conf59 : R/W; bitpos: [31:24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf59:8; + }; + uint32_t val; +} sdio_slc_host_conf_w14_reg_t; + +/** Type of slc_host_conf_w15 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_conf60 : R/W; bitpos: [7:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf60:8; + /** slchost_slchost_conf61 : R/W; bitpos: [15:8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf61:8; + /** slchost_slchost_conf62 : R/W; bitpos: [23:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_conf62:8; + /** slchost_slchost_conf63 : R/W; bitpos: [31:24]; default: 0; + * Bit [27:24] used for reg_slc_apbwin_addr[31:28] + */ + uint32_t slchost_slchost_conf63:8; + }; + uint32_t val; +} sdio_slc_host_conf_w15_reg_t; + +/** Type of slc_host_check_sum0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_check_sum0 : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slchost_check_sum0:32; + }; + uint32_t val; +} sdio_slc_host_check_sum0_reg_t; + +/** Type of slc_host_check_sum1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_check_sum1 : RO; bitpos: [31:0]; default: 319; + * *******Description*********** + */ + uint32_t slchost_slchost_check_sum1:32; + }; + uint32_t val; +} sdio_slc_host_check_sum1_reg_t; + +/** Type of slc_host_slc1host_token_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_token0 : RO; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0:12; + /** slchost_slc1_rx_pf_valid : RO; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid:1; + uint32_t reserved_13:3; + /** slchost_hostslchost_slc1_token1 : RO; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hostslchost_slc1_token1:12; + /** slchost_slc1_rx_pf_eof : RO; bitpos: [31:28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_eof:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_rdata_reg_t; + +/** Type of slc_host_slc0host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_wd:12; + uint32_t reserved_12:4; + /** slchost_slc0host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc0host_token_wdata_reg_t; + +/** Type of slc_host_slc1host_token_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1host_token0_wd : R/W; bitpos: [11:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_wd:12; + uint32_t reserved_12:4; + /** slchost_slc1host_token1_wd : R/W; bitpos: [27:16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_wd:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_slc1host_token_wdata_reg_t; + +/** Type of slc_host_token_con register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_token0_dec : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_dec:1; + /** slchost_slc0host_token1_dec : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_dec:1; + /** slchost_slc0host_token0_wr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token0_wr:1; + /** slchost_slc0host_token1_wr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_token1_wr:1; + /** slchost_slc1host_token0_dec : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_dec:1; + /** slchost_slc1host_token1_dec : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_dec:1; + /** slchost_slc1host_token0_wr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token0_wr:1; + /** slchost_slc1host_token1_wr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_token1_wr:1; + /** slchost_slc0host_len_wr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_len_wr:1; + uint32_t reserved_9:23; + }; + uint32_t val; +} sdio_slc_host_token_con_reg_t; + +/** Type of slc_host_slc0host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_clr:1; + /** slchost_slc0_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_clr:1; + /** slchost_slc0_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_clr:1; + /** slchost_slc0_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_clr:1; + /** slchost_slc0_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_clr:1; + /** slchost_slc0_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_clr:1; + /** slchost_slc0_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_clr:1; + /** slchost_slc0_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_clr:1; + /** slchost_slc0_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_clr:1; + /** slchost_slc0_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_clr:1; + /** slchost_slc0_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_clr:1; + /** slchost_slc0_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_clr:1; + /** slchost_slc0host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_clr:1; + /** slchost_slc0host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_clr:1; + /** slchost_slc0host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_clr:1; + /** slchost_slc0host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_clr:1; + /** slchost_slc0_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_clr:1; + /** slchost_slc0_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_clr:1; + /** slchost_slc0_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_clr:1; + /** slchost_slc0_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_clr:1; + /** slchost_slc0_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_clr:1; + /** slchost_slc0_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_clr:1; + /** slchost_slc0_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_clr:1; + /** slchost_slc0_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_clr:1; + /** slchost_slc0_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_clr:1; + /** slchost_gpio_sdio_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_clr_reg_t; + +/** Type of slc_host_slc1host_int_clr register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_clr:1; + /** slchost_slc1_tohost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_clr:1; + /** slchost_slc1_tohost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_clr:1; + /** slchost_slc1_tohost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_clr:1; + /** slchost_slc1_tohost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_clr:1; + /** slchost_slc1_tohost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_clr:1; + /** slchost_slc1_tohost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_clr:1; + /** slchost_slc1_tohost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_clr:1; + /** slchost_slc1_token0_1to0_int_clr : WT; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_clr:1; + /** slchost_slc1_token1_1to0_int_clr : WT; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_clr:1; + /** slchost_slc1_token0_0to1_int_clr : WT; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_clr:1; + /** slchost_slc1_token1_0to1_int_clr : WT; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_clr:1; + /** slchost_slc1host_rx_sof_int_clr : WT; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_clr:1; + /** slchost_slc1host_rx_eof_int_clr : WT; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_clr:1; + /** slchost_slc1host_rx_start_int_clr : WT; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_clr:1; + /** slchost_slc1host_tx_start_int_clr : WT; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_clr:1; + /** slchost_slc1_rx_udf_int_clr : WT; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_clr:1; + /** slchost_slc1_tx_ovf_int_clr : WT; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_clr:1; + /** slchost_slc1_rx_pf_valid_int_clr : WT; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_clr:1; + /** slchost_slc1_ext_bit0_int_clr : WT; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_clr:1; + /** slchost_slc1_ext_bit1_int_clr : WT; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_clr:1; + /** slchost_slc1_ext_bit2_int_clr : WT; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_clr:1; + /** slchost_slc1_ext_bit3_int_clr : WT; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_clr:1; + /** slchost_slc1_wifi_rx_new_packet_int_clr : WT; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_clr:1; + /** slchost_slc1_host_rd_retry_int_clr : WT; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_clr:1; + /** slchost_slc1_bt_rx_new_packet_int_clr : WT; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_clr:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_clr_reg_t; + +/** Type of slc_host_slc0host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn1_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit0_int_ena:1; + /** slchost_fn1_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit1_int_ena:1; + /** slchost_fn1_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit2_int_ena:1; + /** slchost_fn1_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit3_int_ena:1; + /** slchost_fn1_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit4_int_ena:1; + /** slchost_fn1_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit5_int_ena:1; + /** slchost_fn1_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit6_int_ena:1; + /** slchost_fn1_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tohost_bit7_int_ena:1; + /** slchost_fn1_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token0_1to0_int_ena:1; + /** slchost_fn1_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token1_1to0_int_ena:1; + /** slchost_fn1_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token0_0to1_int_ena:1; + /** slchost_fn1_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_token1_0to1_int_ena:1; + /** slchost_fn1_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_sof_int_ena:1; + /** slchost_fn1_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_eof_int_ena:1; + /** slchost_fn1_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_rx_start_int_ena:1; + /** slchost_fn1_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0host_tx_start_int_ena:1; + /** slchost_fn1_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_udf_int_ena:1; + /** slchost_fn1_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_tx_ovf_int_ena:1; + /** slchost_fn1_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_pf_valid_int_ena:1; + /** slchost_fn1_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit0_int_ena:1; + /** slchost_fn1_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit1_int_ena:1; + /** slchost_fn1_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit2_int_ena:1; + /** slchost_fn1_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_ext_bit3_int_ena:1; + /** slchost_fn1_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_rx_new_packet_int_ena:1; + /** slchost_fn1_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc0_host_rd_retry_int_ena:1; + /** slchost_fn1_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func1_int_ena_reg_t; + +/** Type of slc_host_slc1host_func1_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn1_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit0_int_ena:1; + /** slchost_fn1_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit1_int_ena:1; + /** slchost_fn1_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit2_int_ena:1; + /** slchost_fn1_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit3_int_ena:1; + /** slchost_fn1_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit4_int_ena:1; + /** slchost_fn1_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit5_int_ena:1; + /** slchost_fn1_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit6_int_ena:1; + /** slchost_fn1_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tohost_bit7_int_ena:1; + /** slchost_fn1_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token0_1to0_int_ena:1; + /** slchost_fn1_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token1_1to0_int_ena:1; + /** slchost_fn1_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token0_0to1_int_ena:1; + /** slchost_fn1_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_token1_0to1_int_ena:1; + /** slchost_fn1_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_sof_int_ena:1; + /** slchost_fn1_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_eof_int_ena:1; + /** slchost_fn1_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_rx_start_int_ena:1; + /** slchost_fn1_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1host_tx_start_int_ena:1; + /** slchost_fn1_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_rx_udf_int_ena:1; + /** slchost_fn1_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_tx_ovf_int_ena:1; + /** slchost_fn1_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_rx_pf_valid_int_ena:1; + /** slchost_fn1_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit0_int_ena:1; + /** slchost_fn1_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit1_int_ena:1; + /** slchost_fn1_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit2_int_ena:1; + /** slchost_fn1_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_ext_bit3_int_ena:1; + /** slchost_fn1_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_fn1_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_host_rd_retry_int_ena:1; + /** slchost_fn1_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn1_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func1_int_ena_reg_t; + +/** Type of slc_host_slc0host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn2_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit0_int_ena:1; + /** slchost_fn2_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit1_int_ena:1; + /** slchost_fn2_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit2_int_ena:1; + /** slchost_fn2_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit3_int_ena:1; + /** slchost_fn2_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit4_int_ena:1; + /** slchost_fn2_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit5_int_ena:1; + /** slchost_fn2_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit6_int_ena:1; + /** slchost_fn2_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tohost_bit7_int_ena:1; + /** slchost_fn2_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token0_1to0_int_ena:1; + /** slchost_fn2_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token1_1to0_int_ena:1; + /** slchost_fn2_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token0_0to1_int_ena:1; + /** slchost_fn2_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_token1_0to1_int_ena:1; + /** slchost_fn2_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_sof_int_ena:1; + /** slchost_fn2_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_eof_int_ena:1; + /** slchost_fn2_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_rx_start_int_ena:1; + /** slchost_fn2_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0host_tx_start_int_ena:1; + /** slchost_fn2_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_udf_int_ena:1; + /** slchost_fn2_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_tx_ovf_int_ena:1; + /** slchost_fn2_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_pf_valid_int_ena:1; + /** slchost_fn2_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit0_int_ena:1; + /** slchost_fn2_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit1_int_ena:1; + /** slchost_fn2_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit2_int_ena:1; + /** slchost_fn2_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_ext_bit3_int_ena:1; + /** slchost_fn2_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_rx_new_packet_int_ena:1; + /** slchost_fn2_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc0_host_rd_retry_int_ena:1; + /** slchost_fn2_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_func2_int_ena_reg_t; + +/** Type of slc_host_slc1host_func2_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_fn2_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit0_int_ena:1; + /** slchost_fn2_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit1_int_ena:1; + /** slchost_fn2_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit2_int_ena:1; + /** slchost_fn2_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit3_int_ena:1; + /** slchost_fn2_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit4_int_ena:1; + /** slchost_fn2_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit5_int_ena:1; + /** slchost_fn2_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit6_int_ena:1; + /** slchost_fn2_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tohost_bit7_int_ena:1; + /** slchost_fn2_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token0_1to0_int_ena:1; + /** slchost_fn2_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token1_1to0_int_ena:1; + /** slchost_fn2_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token0_0to1_int_ena:1; + /** slchost_fn2_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_token1_0to1_int_ena:1; + /** slchost_fn2_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_sof_int_ena:1; + /** slchost_fn2_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_eof_int_ena:1; + /** slchost_fn2_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_rx_start_int_ena:1; + /** slchost_fn2_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1host_tx_start_int_ena:1; + /** slchost_fn2_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_rx_udf_int_ena:1; + /** slchost_fn2_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_tx_ovf_int_ena:1; + /** slchost_fn2_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_rx_pf_valid_int_ena:1; + /** slchost_fn2_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit0_int_ena:1; + /** slchost_fn2_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit1_int_ena:1; + /** slchost_fn2_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit2_int_ena:1; + /** slchost_fn2_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_ext_bit3_int_ena:1; + /** slchost_fn2_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_fn2_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_host_rd_retry_int_ena:1; + /** slchost_fn2_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_fn2_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_func2_int_ena_reg_t; + +/** Type of slc_host_slc0host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_ena:1; + /** slchost_slc0_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_ena:1; + /** slchost_slc0_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_ena:1; + /** slchost_slc0_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_ena:1; + /** slchost_slc0_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_ena:1; + /** slchost_slc0_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_ena:1; + /** slchost_slc0_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_ena:1; + /** slchost_slc0_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_ena:1; + /** slchost_slc0_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_ena:1; + /** slchost_slc0_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_ena:1; + /** slchost_slc0_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_ena:1; + /** slchost_slc0_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_ena:1; + /** slchost_slc0host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_ena:1; + /** slchost_slc0host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_ena:1; + /** slchost_slc0host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_ena:1; + /** slchost_slc0host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_ena:1; + /** slchost_slc0_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_ena:1; + /** slchost_slc0_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_ena:1; + /** slchost_slc0_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_ena:1; + /** slchost_slc0_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_ena:1; + /** slchost_slc0_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_ena:1; + /** slchost_slc0_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_ena:1; + /** slchost_slc0_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_ena:1; + /** slchost_slc0_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_ena:1; + /** slchost_slc0_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_ena:1; + /** slchost_gpio_sdio_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena_reg_t; + +/** Type of slc_host_slc1host_int_ena register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_ena:1; + /** slchost_slc1_tohost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_ena:1; + /** slchost_slc1_tohost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_ena:1; + /** slchost_slc1_tohost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_ena:1; + /** slchost_slc1_tohost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_ena:1; + /** slchost_slc1_tohost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_ena:1; + /** slchost_slc1_tohost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_ena:1; + /** slchost_slc1_tohost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_ena:1; + /** slchost_slc1_token0_1to0_int_ena : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_ena:1; + /** slchost_slc1_token1_1to0_int_ena : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_ena:1; + /** slchost_slc1_token0_0to1_int_ena : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_ena:1; + /** slchost_slc1_token1_0to1_int_ena : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_ena:1; + /** slchost_slc1host_rx_sof_int_ena : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_ena:1; + /** slchost_slc1host_rx_eof_int_ena : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_ena:1; + /** slchost_slc1host_rx_start_int_ena : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_ena:1; + /** slchost_slc1host_tx_start_int_ena : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_ena:1; + /** slchost_slc1_rx_udf_int_ena : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_ena:1; + /** slchost_slc1_tx_ovf_int_ena : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_ena:1; + /** slchost_slc1_rx_pf_valid_int_ena : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_ena:1; + /** slchost_slc1_ext_bit0_int_ena : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_ena:1; + /** slchost_slc1_ext_bit1_int_ena : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_ena:1; + /** slchost_slc1_ext_bit2_int_ena : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_ena:1; + /** slchost_slc1_ext_bit3_int_ena : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_ena:1; + /** slchost_slc1_wifi_rx_new_packet_int_ena : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_ena:1; + /** slchost_slc1_host_rd_retry_int_ena : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_ena:1; + /** slchost_slc1_bt_rx_new_packet_int_ena : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_ena:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena_reg_t; + +/** Type of slc_host_slc0host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc0host_rx_infor_reg_t; + +/** Type of slc_host_slc1host_rx_infor register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1host_rx_infor : R/W; bitpos: [19:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_infor:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_slc1host_rx_infor_reg_t; + +/** Type of slc_host_slc0host_len_wd register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0host_len_wd : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_len_wd:32; + }; + uint32_t val; +} sdio_slc_host_slc0host_len_wd_reg_t; + +/** Type of slc_host_slc_apbwin_wdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_wdata : R/W; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_wdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_wdata_reg_t; + +/** Type of slc_host_slc_apbwin_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_addr : R/W; bitpos: [27:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_addr:28; + /** slchost_slc_apbwin_wr : R/W; bitpos: [28]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_wr:1; + /** slchost_slc_apbwin_start : R/W/SC; bitpos: [29]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_start:1; + uint32_t reserved_30:2; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_conf_reg_t; + +/** Type of slc_host_slc_apbwin_rdata register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc_apbwin_rdata : RO; bitpos: [31:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc_apbwin_rdata:32; + }; + uint32_t val; +} sdio_slc_host_slc_apbwin_rdata_reg_t; + +/** Type of slc_host_rdclr0 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_slc0_bit7_clraddr : R/W; bitpos: [8:0]; default: 68; + * *******Description*********** + */ + uint32_t slchost_slchost_slc0_bit7_clraddr:9; + /** slchost_slchost_slc0_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc0_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr0_reg_t; + +/** Type of slc_host_rdclr1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_slc1_bit7_clraddr : R/W; bitpos: [8:0]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc1_bit7_clraddr:9; + /** slchost_slchost_slc1_bit6_clraddr : R/W; bitpos: [17:9]; default: 480; + * *******Description*********** + */ + uint32_t slchost_slchost_slc1_bit6_clraddr:9; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_host_rdclr1_reg_t; + +/** Type of slc_host_slc0host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc0_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit0_int_ena1:1; + /** slchost_slc0_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit1_int_ena1:1; + /** slchost_slc0_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit2_int_ena1:1; + /** slchost_slc0_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit3_int_ena1:1; + /** slchost_slc0_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit4_int_ena1:1; + /** slchost_slc0_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit5_int_ena1:1; + /** slchost_slc0_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit6_int_ena1:1; + /** slchost_slc0_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tohost_bit7_int_ena1:1; + /** slchost_slc0_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_1to0_int_ena1:1; + /** slchost_slc0_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_1to0_int_ena1:1; + /** slchost_slc0_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token0_0to1_int_ena1:1; + /** slchost_slc0_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_token1_0to1_int_ena1:1; + /** slchost_slc0host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_sof_int_ena1:1; + /** slchost_slc0host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_eof_int_ena1:1; + /** slchost_slc0host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_rx_start_int_ena1:1; + /** slchost_slc0host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0host_tx_start_int_ena1:1; + /** slchost_slc0_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_udf_int_ena1:1; + /** slchost_slc0_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_tx_ovf_int_ena1:1; + /** slchost_slc0_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_pf_valid_int_ena1:1; + /** slchost_slc0_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit0_int_ena1:1; + /** slchost_slc0_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit1_int_ena1:1; + /** slchost_slc0_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit2_int_ena1:1; + /** slchost_slc0_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_ext_bit3_int_ena1:1; + /** slchost_slc0_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_rx_new_packet_int_ena1:1; + /** slchost_slc0_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc0_host_rd_retry_int_ena1:1; + /** slchost_gpio_sdio_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_gpio_sdio_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc0host_int_ena1_reg_t; + +/** Type of slc_host_slc1host_int_ena1 register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slc1_tohost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit0_int_ena1:1; + /** slchost_slc1_tohost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit1_int_ena1:1; + /** slchost_slc1_tohost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit2_int_ena1:1; + /** slchost_slc1_tohost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit3_int_ena1:1; + /** slchost_slc1_tohost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit4_int_ena1:1; + /** slchost_slc1_tohost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit5_int_ena1:1; + /** slchost_slc1_tohost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit6_int_ena1:1; + /** slchost_slc1_tohost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tohost_bit7_int_ena1:1; + /** slchost_slc1_token0_1to0_int_ena1 : R/W; bitpos: [8]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_1to0_int_ena1:1; + /** slchost_slc1_token1_1to0_int_ena1 : R/W; bitpos: [9]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_1to0_int_ena1:1; + /** slchost_slc1_token0_0to1_int_ena1 : R/W; bitpos: [10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token0_0to1_int_ena1:1; + /** slchost_slc1_token1_0to1_int_ena1 : R/W; bitpos: [11]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_token1_0to1_int_ena1:1; + /** slchost_slc1host_rx_sof_int_ena1 : R/W; bitpos: [12]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_sof_int_ena1:1; + /** slchost_slc1host_rx_eof_int_ena1 : R/W; bitpos: [13]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_eof_int_ena1:1; + /** slchost_slc1host_rx_start_int_ena1 : R/W; bitpos: [14]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_rx_start_int_ena1:1; + /** slchost_slc1host_tx_start_int_ena1 : R/W; bitpos: [15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1host_tx_start_int_ena1:1; + /** slchost_slc1_rx_udf_int_ena1 : R/W; bitpos: [16]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_udf_int_ena1:1; + /** slchost_slc1_tx_ovf_int_ena1 : R/W; bitpos: [17]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_tx_ovf_int_ena1:1; + /** slchost_slc1_rx_pf_valid_int_ena1 : R/W; bitpos: [18]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_rx_pf_valid_int_ena1:1; + /** slchost_slc1_ext_bit0_int_ena1 : R/W; bitpos: [19]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit0_int_ena1:1; + /** slchost_slc1_ext_bit1_int_ena1 : R/W; bitpos: [20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit1_int_ena1:1; + /** slchost_slc1_ext_bit2_int_ena1 : R/W; bitpos: [21]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit2_int_ena1:1; + /** slchost_slc1_ext_bit3_int_ena1 : R/W; bitpos: [22]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_ext_bit3_int_ena1:1; + /** slchost_slc1_wifi_rx_new_packet_int_ena1 : R/W; bitpos: [23]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_wifi_rx_new_packet_int_ena1:1; + /** slchost_slc1_host_rd_retry_int_ena1 : R/W; bitpos: [24]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_host_rd_retry_int_ena1:1; + /** slchost_slc1_bt_rx_new_packet_int_ena1 : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_slc1_bt_rx_new_packet_int_ena1:1; + uint32_t reserved_26:6; + }; + uint32_t val; +} sdio_slc_host_slc1host_int_ena1_reg_t; + +/** Type of slc_host_date register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_date : R/W; bitpos: [31:0]; default: 554043136; + * *******Description*********** + */ + uint32_t slchost_slchost_date:32; + }; + uint32_t val; +} sdio_slc_host_date_reg_t; + +/** Type of slc_host_id register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_slchost_id : R/W; bitpos: [31:0]; default: 1536; + * *******Description*********** + */ + uint32_t slchost_slchost_id:32; + }; + uint32_t val; +} sdio_slc_host_id_reg_t; + +/** Type of slc_host_conf register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_frc_sdio11 : R/W; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_sdio11:5; + /** slchost_frc_sdio20 : R/W; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_sdio20:5; + /** slchost_frc_neg_samp : R/W; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_neg_samp:5; + /** slchost_frc_pos_samp : R/W; bitpos: [19:15]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_pos_samp:5; + /** slchost_frc_quick_in : R/W; bitpos: [24:20]; default: 0; + * *******Description*********** + */ + uint32_t slchost_frc_quick_in:5; + /** slchost_sdio20_int_delay : R/W; bitpos: [25]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio20_int_delay:1; + /** slchost_sdio_pad_pullup : R/W; bitpos: [26]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_pad_pullup:1; + /** slchost_hspeed_con_en : R/W; bitpos: [27]; default: 0; + * *******Description*********** + */ + uint32_t slchost_hspeed_con_en:1; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_host_conf_reg_t; + +/** Type of slc_host_inf_st register + * *******Description*********** + */ +typedef union { + struct { + /** slchost_sdio20_mode : RO; bitpos: [4:0]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio20_mode:5; + /** slchost_sdio_neg_samp : RO; bitpos: [9:5]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_neg_samp:5; + /** slchost_sdio_quick_in : RO; bitpos: [14:10]; default: 0; + * *******Description*********** + */ + uint32_t slchost_sdio_quick_in:5; + /** slchost_dll_on_sw : R/W; bitpos: [15]; default: 0; + * dll is controlled by software + */ + uint32_t slchost_dll_on_sw:1; + /** slchost_dll_on : R/W; bitpos: [16]; default: 0; + * Software dll on + */ + uint32_t slchost_dll_on:1; + /** slchost_clk_mode_sw : R/W; bitpos: [17]; default: 0; + * dll clock mode is controlled by software + */ + uint32_t slchost_clk_mode_sw:1; + /** slchost_clk_mode : R/W; bitpos: [19:18]; default: 0; + * Software set clock mode + */ + uint32_t slchost_clk_mode:2; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_host_inf_st_reg_t; + + +typedef struct { + uint32_t reserved_000[4]; + volatile sdio_slc_host_func2_0_reg_t slc_host_func2_0; + volatile sdio_slc_host_func2_1_reg_t slc_host_func2_1; + uint32_t reserved_018[2]; + volatile sdio_slc_host_func2_2_reg_t slc_host_func2_2; + uint32_t reserved_024[4]; + volatile sdio_slc_host_gpio_status0_reg_t slc_host_gpio_status0; + volatile sdio_slc_host_gpio_status1_reg_t slc_host_gpio_status1; + volatile sdio_slc_host_gpio_in0_reg_t slc_host_gpio_in0; + volatile sdio_slc_host_gpio_in1_reg_t slc_host_gpio_in1; + volatile sdio_slc_host_slc0host_token_rdata_reg_t slc_host_slc0host_token_rdata; + volatile sdio_slc_host_slc0_host_pf_reg_t slc_host_slc0_host_pf; + volatile sdio_slc_host_slc1_host_pf_reg_t slc_host_slc1_host_pf; + volatile sdio_slc_host_slc0host_int_raw_reg_t slc_host_slc0host_int_raw; + volatile sdio_slc_host_slc1host_int_raw_reg_t slc_host_slc1host_int_raw; + volatile sdio_slc_host_slc0host_int_st_reg_t slc_host_slc0host_int_st; + volatile sdio_slc_host_slc1host_int_st_reg_t slc_host_slc1host_int_st; + volatile sdio_slc_host_pkt_len_reg_t slc_host_pkt_len; + volatile sdio_slc_host_state_w0_reg_t slc_host_state_w0; + volatile sdio_slc_host_state_w1_reg_t slc_host_state_w1; + volatile sdio_slc_host_conf_w0_reg_t slc_host_conf_w0; + volatile sdio_slc_host_conf_w1_reg_t slc_host_conf_w1; + volatile sdio_slc_host_conf_w2_reg_t slc_host_conf_w2; + volatile sdio_slc_host_conf_w3_reg_t slc_host_conf_w3; + volatile sdio_slc_host_conf_w4_reg_t slc_host_conf_w4; + volatile sdio_slc_host_conf_w5_reg_t slc_host_conf_w5; + volatile sdio_slc_host_win_cmd_reg_t slc_host_win_cmd; + volatile sdio_slc_host_conf_w6_reg_t slc_host_conf_w6; + volatile sdio_slc_host_conf_w7_reg_t slc_host_conf_w7; + volatile sdio_slc_host_pkt_len0_reg_t slc_host_pkt_len0; + volatile sdio_slc_host_pkt_len1_reg_t slc_host_pkt_len1; + volatile sdio_slc_host_pkt_len2_reg_t slc_host_pkt_len2; + volatile sdio_slc_host_conf_w8_reg_t slc_host_conf_w8; + volatile sdio_slc_host_conf_w9_reg_t slc_host_conf_w9; + volatile sdio_slc_host_conf_w10_reg_t slc_host_conf_w10; + volatile sdio_slc_host_conf_w11_reg_t slc_host_conf_w11; + volatile sdio_slc_host_conf_w12_reg_t slc_host_conf_w12; + volatile sdio_slc_host_conf_w13_reg_t slc_host_conf_w13; + volatile sdio_slc_host_conf_w14_reg_t slc_host_conf_w14; + volatile sdio_slc_host_conf_w15_reg_t slc_host_conf_w15; + volatile sdio_slc_host_check_sum0_reg_t slc_host_check_sum0; + volatile sdio_slc_host_check_sum1_reg_t slc_host_check_sum1; + volatile sdio_slc_host_slc1host_token_rdata_reg_t slc_host_slc1host_token_rdata; + volatile sdio_slc_host_slc0host_token_wdata_reg_t slc_host_slc0host_token_wdata; + volatile sdio_slc_host_slc1host_token_wdata_reg_t slc_host_slc1host_token_wdata; + volatile sdio_slc_host_token_con_reg_t slc_host_token_con; + volatile sdio_slc_host_slc0host_int_clr_reg_t slc_host_slc0host_int_clr; + volatile sdio_slc_host_slc1host_int_clr_reg_t slc_host_slc1host_int_clr; + volatile sdio_slc_host_slc0host_func1_int_ena_reg_t slc_host_slc0host_func1_int_ena; + volatile sdio_slc_host_slc1host_func1_int_ena_reg_t slc_host_slc1host_func1_int_ena; + volatile sdio_slc_host_slc0host_func2_int_ena_reg_t slc_host_slc0host_func2_int_ena; + volatile sdio_slc_host_slc1host_func2_int_ena_reg_t slc_host_slc1host_func2_int_ena; + volatile sdio_slc_host_slc0host_int_ena_reg_t slc_host_slc0host_int_ena; + volatile sdio_slc_host_slc1host_int_ena_reg_t slc_host_slc1host_int_ena; + volatile sdio_slc_host_slc0host_rx_infor_reg_t slc_host_slc0host_rx_infor; + volatile sdio_slc_host_slc1host_rx_infor_reg_t slc_host_slc1host_rx_infor; + volatile sdio_slc_host_slc0host_len_wd_reg_t slc_host_slc0host_len_wd; + volatile sdio_slc_host_slc_apbwin_wdata_reg_t slc_host_slc_apbwin_wdata; + volatile sdio_slc_host_slc_apbwin_conf_reg_t slc_host_slc_apbwin_conf; + volatile sdio_slc_host_slc_apbwin_rdata_reg_t slc_host_slc_apbwin_rdata; + volatile sdio_slc_host_rdclr0_reg_t slc_host_rdclr0; + volatile sdio_slc_host_rdclr1_reg_t slc_host_rdclr1; + volatile sdio_slc_host_slc0host_int_ena1_reg_t slc_host_slc0host_int_ena1; + volatile sdio_slc_host_slc1host_int_ena1_reg_t slc_host_slc1host_int_ena1; + uint32_t reserved_11c[23]; + volatile sdio_slc_host_date_reg_t slc_host_date; + volatile sdio_slc_host_id_reg_t slc_host_id; + uint32_t reserved_180[28]; + volatile sdio_slc_host_conf_reg_t slc_host_conf; + volatile sdio_slc_host_inf_st_reg_t slc_host_inf_st; +} host_dev_t; + +extern host_dev_t HOST; + +#ifndef __cplusplus +_Static_assert(sizeof(host_dev_t) == 0x1f8, "Invalid size of host_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_reg.h b/components/soc/esp32c61/register/soc/sdio_slc_reg.h new file mode 100644 index 0000000000..ed573412c2 --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_reg.h @@ -0,0 +1,4382 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/soc.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** SDIO_SLC_CONF0_REG register + * Sdio slave DMA configuration register. + */ +#define SDIO_SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0) +/** SDIO_SLC0_TX_RST : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ +#define SDIO_SLC0_TX_RST (BIT(0)) +#define SDIO_SLC0_TX_RST_M (SDIO_SLC0_TX_RST_V << SDIO_SLC0_TX_RST_S) +#define SDIO_SLC0_TX_RST_V 0x00000001U +#define SDIO_SLC0_TX_RST_S 0 +/** SDIO_SLC0_RX_RST : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ +#define SDIO_SLC0_RX_RST (BIT(1)) +#define SDIO_SLC0_RX_RST_M (SDIO_SLC0_RX_RST_V << SDIO_SLC0_RX_RST_S) +#define SDIO_SLC0_RX_RST_V 0x00000001U +#define SDIO_SLC0_RX_RST_S 1 +/** SDIO_SLC_AHBM_FIFO_RST : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_FIFO_RST (BIT(2)) +#define SDIO_SLC_AHBM_FIFO_RST_M (SDIO_SLC_AHBM_FIFO_RST_V << SDIO_SLC_AHBM_FIFO_RST_S) +#define SDIO_SLC_AHBM_FIFO_RST_V 0x00000001U +#define SDIO_SLC_AHBM_FIFO_RST_S 2 +/** SDIO_SLC_AHBM_RST : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ +#define SDIO_SLC_AHBM_RST (BIT(3)) +#define SDIO_SLC_AHBM_RST_M (SDIO_SLC_AHBM_RST_V << SDIO_SLC_AHBM_RST_S) +#define SDIO_SLC_AHBM_RST_V 0x00000001U +#define SDIO_SLC_AHBM_RST_S 3 +/** SDIO_SLC0_TX_LOOP_TEST : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_TX_LOOP_TEST (BIT(4)) +#define SDIO_SLC0_TX_LOOP_TEST_M (SDIO_SLC0_TX_LOOP_TEST_V << SDIO_SLC0_TX_LOOP_TEST_S) +#define SDIO_SLC0_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_TX_LOOP_TEST_S 4 +/** SDIO_SLC0_RX_LOOP_TEST : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ +#define SDIO_SLC0_RX_LOOP_TEST (BIT(5)) +#define SDIO_SLC0_RX_LOOP_TEST_M (SDIO_SLC0_RX_LOOP_TEST_V << SDIO_SLC0_RX_LOOP_TEST_S) +#define SDIO_SLC0_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC0_RX_LOOP_TEST_S 5 +/** SDIO_SLC0_RX_AUTO_WRBACK : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ +#define SDIO_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SDIO_SLC0_RX_AUTO_WRBACK_M (SDIO_SLC0_RX_AUTO_WRBACK_V << SDIO_SLC0_RX_AUTO_WRBACK_S) +#define SDIO_SLC0_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC0_RX_AUTO_WRBACK_S 6 +/** SDIO_SLC0_RX_NO_RESTART_CLR : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ +#define SDIO_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SDIO_SLC0_RX_NO_RESTART_CLR_M (SDIO_SLC0_RX_NO_RESTART_CLR_V << SDIO_SLC0_RX_NO_RESTART_CLR_S) +#define SDIO_SLC0_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC0_RX_NO_RESTART_CLR_S 7 +/** SDIO_SLC0_RXDSCR_BURST_EN : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SDIO_SLC0_RXDSCR_BURST_EN_M (SDIO_SLC0_RXDSCR_BURST_EN_V << SDIO_SLC0_RXDSCR_BURST_EN_S) +#define SDIO_SLC0_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDSCR_BURST_EN_S 8 +/** SDIO_SLC0_RXDATA_BURST_EN : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ +#define SDIO_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SDIO_SLC0_RXDATA_BURST_EN_M (SDIO_SLC0_RXDATA_BURST_EN_V << SDIO_SLC0_RXDATA_BURST_EN_S) +#define SDIO_SLC0_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_EN_S 9 +/** SDIO_SLC0_RXLINK_AUTO_RET : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SDIO_SLC0_RXLINK_AUTO_RET_M (SDIO_SLC0_RXLINK_AUTO_RET_V << SDIO_SLC0_RXLINK_AUTO_RET_S) +#define SDIO_SLC0_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_RXLINK_AUTO_RET_S 10 +/** SDIO_SLC0_TXLINK_AUTO_RET : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SDIO_SLC0_TXLINK_AUTO_RET_M (SDIO_SLC0_TXLINK_AUTO_RET_V << SDIO_SLC0_TXLINK_AUTO_RET_S) +#define SDIO_SLC0_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC0_TXLINK_AUTO_RET_S 11 +/** SDIO_SLC0_TXDSCR_BURST_EN : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ +#define SDIO_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SDIO_SLC0_TXDSCR_BURST_EN_M (SDIO_SLC0_TXDSCR_BURST_EN_V << SDIO_SLC0_TXDSCR_BURST_EN_S) +#define SDIO_SLC0_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDSCR_BURST_EN_S 12 +/** SDIO_SLC0_TXDATA_BURST_EN : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ +#define SDIO_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SDIO_SLC0_TXDATA_BURST_EN_M (SDIO_SLC0_TXDATA_BURST_EN_V << SDIO_SLC0_TXDATA_BURST_EN_S) +#define SDIO_SLC0_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_EN_S 13 +/** SDIO_SLC0_TOKEN_AUTO_CLR : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ +#define SDIO_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SDIO_SLC0_TOKEN_AUTO_CLR_M (SDIO_SLC0_TOKEN_AUTO_CLR_V << SDIO_SLC0_TOKEN_AUTO_CLR_S) +#define SDIO_SLC0_TOKEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN_AUTO_CLR_S 14 +/** SDIO_SLC0_TOKEN_SEL : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ +#define SDIO_SLC0_TOKEN_SEL (BIT(15)) +#define SDIO_SLC0_TOKEN_SEL_M (SDIO_SLC0_TOKEN_SEL_V << SDIO_SLC0_TOKEN_SEL_S) +#define SDIO_SLC0_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC0_TOKEN_SEL_S 15 +/** SDIO_SLC1_TX_RST : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ +#define SDIO_SLC1_TX_RST (BIT(16)) +#define SDIO_SLC1_TX_RST_M (SDIO_SLC1_TX_RST_V << SDIO_SLC1_TX_RST_S) +#define SDIO_SLC1_TX_RST_V 0x00000001U +#define SDIO_SLC1_TX_RST_S 16 +/** SDIO_SLC1_RX_RST : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ +#define SDIO_SLC1_RX_RST (BIT(17)) +#define SDIO_SLC1_RX_RST_M (SDIO_SLC1_RX_RST_V << SDIO_SLC1_RX_RST_S) +#define SDIO_SLC1_RX_RST_V 0x00000001U +#define SDIO_SLC1_RX_RST_S 17 +/** SDIO_SLC0_WR_RETRY_MASK_EN : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SDIO_SLC0_WR_RETRY_MASK_EN_M (SDIO_SLC0_WR_RETRY_MASK_EN_V << SDIO_SLC0_WR_RETRY_MASK_EN_S) +#define SDIO_SLC0_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_MASK_EN_S 18 +/** SDIO_SLC1_WR_RETRY_MASK_EN : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ +#define SDIO_SLC1_WR_RETRY_MASK_EN (BIT(19)) +#define SDIO_SLC1_WR_RETRY_MASK_EN_M (SDIO_SLC1_WR_RETRY_MASK_EN_V << SDIO_SLC1_WR_RETRY_MASK_EN_S) +#define SDIO_SLC1_WR_RETRY_MASK_EN_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_MASK_EN_S 19 +/** SDIO_SLC1_TX_LOOP_TEST : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_TX_LOOP_TEST (BIT(20)) +#define SDIO_SLC1_TX_LOOP_TEST_M (SDIO_SLC1_TX_LOOP_TEST_V << SDIO_SLC1_TX_LOOP_TEST_S) +#define SDIO_SLC1_TX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_TX_LOOP_TEST_S 20 +/** SDIO_SLC1_RX_LOOP_TEST : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ +#define SDIO_SLC1_RX_LOOP_TEST (BIT(21)) +#define SDIO_SLC1_RX_LOOP_TEST_M (SDIO_SLC1_RX_LOOP_TEST_V << SDIO_SLC1_RX_LOOP_TEST_S) +#define SDIO_SLC1_RX_LOOP_TEST_V 0x00000001U +#define SDIO_SLC1_RX_LOOP_TEST_S 21 +/** SDIO_SLC1_RX_AUTO_WRBACK : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ +#define SDIO_SLC1_RX_AUTO_WRBACK (BIT(22)) +#define SDIO_SLC1_RX_AUTO_WRBACK_M (SDIO_SLC1_RX_AUTO_WRBACK_V << SDIO_SLC1_RX_AUTO_WRBACK_S) +#define SDIO_SLC1_RX_AUTO_WRBACK_V 0x00000001U +#define SDIO_SLC1_RX_AUTO_WRBACK_S 22 +/** SDIO_SLC1_RX_NO_RESTART_CLR : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ +#define SDIO_SLC1_RX_NO_RESTART_CLR (BIT(23)) +#define SDIO_SLC1_RX_NO_RESTART_CLR_M (SDIO_SLC1_RX_NO_RESTART_CLR_V << SDIO_SLC1_RX_NO_RESTART_CLR_S) +#define SDIO_SLC1_RX_NO_RESTART_CLR_V 0x00000001U +#define SDIO_SLC1_RX_NO_RESTART_CLR_S 23 +/** SDIO_SLC1_RXDSCR_BURST_EN : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ +#define SDIO_SLC1_RXDSCR_BURST_EN (BIT(24)) +#define SDIO_SLC1_RXDSCR_BURST_EN_M (SDIO_SLC1_RXDSCR_BURST_EN_V << SDIO_SLC1_RXDSCR_BURST_EN_S) +#define SDIO_SLC1_RXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDSCR_BURST_EN_S 24 +/** SDIO_SLC1_RXDATA_BURST_EN : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ +#define SDIO_SLC1_RXDATA_BURST_EN (BIT(25)) +#define SDIO_SLC1_RXDATA_BURST_EN_M (SDIO_SLC1_RXDATA_BURST_EN_V << SDIO_SLC1_RXDATA_BURST_EN_S) +#define SDIO_SLC1_RXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_EN_S 25 +/** SDIO_SLC1_RXLINK_AUTO_RET : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_RXLINK_AUTO_RET (BIT(26)) +#define SDIO_SLC1_RXLINK_AUTO_RET_M (SDIO_SLC1_RXLINK_AUTO_RET_V << SDIO_SLC1_RXLINK_AUTO_RET_S) +#define SDIO_SLC1_RXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_RXLINK_AUTO_RET_S 26 +/** SDIO_SLC1_TXLINK_AUTO_RET : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ +#define SDIO_SLC1_TXLINK_AUTO_RET (BIT(27)) +#define SDIO_SLC1_TXLINK_AUTO_RET_M (SDIO_SLC1_TXLINK_AUTO_RET_V << SDIO_SLC1_TXLINK_AUTO_RET_S) +#define SDIO_SLC1_TXLINK_AUTO_RET_V 0x00000001U +#define SDIO_SLC1_TXLINK_AUTO_RET_S 27 +/** SDIO_SLC1_TXDSCR_BURST_EN : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ +#define SDIO_SLC1_TXDSCR_BURST_EN (BIT(28)) +#define SDIO_SLC1_TXDSCR_BURST_EN_M (SDIO_SLC1_TXDSCR_BURST_EN_V << SDIO_SLC1_TXDSCR_BURST_EN_S) +#define SDIO_SLC1_TXDSCR_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDSCR_BURST_EN_S 28 +/** SDIO_SLC1_TXDATA_BURST_EN : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ +#define SDIO_SLC1_TXDATA_BURST_EN (BIT(29)) +#define SDIO_SLC1_TXDATA_BURST_EN_M (SDIO_SLC1_TXDATA_BURST_EN_V << SDIO_SLC1_TXDATA_BURST_EN_S) +#define SDIO_SLC1_TXDATA_BURST_EN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_EN_S 29 +/** SDIO_SLC1_TOKEN_SEL : R/W; bitpos: [31]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_SEL (BIT(31)) +#define SDIO_SLC1_TOKEN_SEL_M (SDIO_SLC1_TOKEN_SEL_V << SDIO_SLC1_TOKEN_SEL_S) +#define SDIO_SLC1_TOKEN_SEL_V 0x00000001U +#define SDIO_SLC1_TOKEN_SEL_S 31 + +/** SDIO_SLC_SLC0INT_RAW_REG register + * Sdio slave DMA channel0 raw interrupt status register. + */ +#define SDIO_SLC_SLC0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) +/** SDIO_SLC_FRHOST_BIT0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_M (SDIO_SLC_FRHOST_BIT0_INT_RAW_V << SDIO_SLC_FRHOST_BIT0_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_M (SDIO_SLC_FRHOST_BIT1_INT_RAW_V << SDIO_SLC_FRHOST_BIT1_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_M (SDIO_SLC_FRHOST_BIT2_INT_RAW_V << SDIO_SLC_FRHOST_BIT2_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_M (SDIO_SLC_FRHOST_BIT3_INT_RAW_V << SDIO_SLC_FRHOST_BIT3_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_M (SDIO_SLC_FRHOST_BIT4_INT_RAW_V << SDIO_SLC_FRHOST_BIT4_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_M (SDIO_SLC_FRHOST_BIT5_INT_RAW_V << SDIO_SLC_FRHOST_BIT5_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_M (SDIO_SLC_FRHOST_BIT6_INT_RAW_V << SDIO_SLC_FRHOST_BIT6_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_M (SDIO_SLC_FRHOST_BIT7_INT_RAW_V << SDIO_SLC_FRHOST_BIT7_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_RAW_S 7 +/** SDIO_SLC0_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ +#define SDIO_SLC0_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC0_RX_START_INT_RAW_M (SDIO_SLC0_RX_START_INT_RAW_V << SDIO_SLC0_RX_START_INT_RAW_S) +#define SDIO_SLC0_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_RAW_S 8 +/** SDIO_SLC0_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ +#define SDIO_SLC0_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC0_TX_START_INT_RAW_M (SDIO_SLC0_TX_START_INT_RAW_V << SDIO_SLC0_TX_START_INT_RAW_S) +#define SDIO_SLC0_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_RAW_S 9 +/** SDIO_SLC0_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ +#define SDIO_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_RAW_M (SDIO_SLC0_RX_UDF_INT_RAW_V << SDIO_SLC0_RX_UDF_INT_RAW_S) +#define SDIO_SLC0_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC0_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ +#define SDIO_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_RAW_M (SDIO_SLC0_TX_OVF_INT_RAW_V << SDIO_SLC0_TX_OVF_INT_RAW_S) +#define SDIO_SLC0_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC0_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ +#define SDIO_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_RAW_M (SDIO_SLC0_TX_DONE_INT_RAW_V << SDIO_SLC0_TX_DONE_INT_RAW_S) +#define SDIO_SLC0_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_M (SDIO_SLC0_TX_SUC_EOF_INT_RAW_V << SDIO_SLC0_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC0_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ +#define SDIO_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_RAW_M (SDIO_SLC0_RX_DONE_INT_RAW_V << SDIO_SLC0_RX_DONE_INT_RAW_S) +#define SDIO_SLC0_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC0_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ +#define SDIO_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_RAW_M (SDIO_SLC0_RX_EOF_INT_RAW_V << SDIO_SLC0_RX_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC0_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_RAW_M (SDIO_SLC0_TOHOST_INT_RAW_V << SDIO_SLC0_TOHOST_INT_RAW_S) +#define SDIO_SLC0_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_RAW_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_M (SDIO_SLC0_HOST_RD_ACK_INT_RAW_V << SDIO_SLC0_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_M (SDIO_SLC0_TX_ERR_EOF_INT_RAW_V << SDIO_SLC0_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/** SDIO_CMD_DTC_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ +#define SDIO_CMD_DTC_INT_RAW (BIT(25)) +#define SDIO_CMD_DTC_INT_RAW_M (SDIO_CMD_DTC_INT_RAW_V << SDIO_CMD_DTC_INT_RAW_S) +#define SDIO_CMD_DTC_INT_RAW_V 0x00000001U +#define SDIO_CMD_DTC_INT_RAW_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_M (SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V << SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/** SDIO_HDA_RECV_DONE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ +#define SDIO_HDA_RECV_DONE_INT_RAW (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_RAW_M (SDIO_HDA_RECV_DONE_INT_RAW_V << SDIO_HDA_RECV_DONE_INT_RAW_S) +#define SDIO_HDA_RECV_DONE_INT_RAW_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_RAW_S 28 + +/** SDIO_SLC_SLC0INT_ST_REG register + * Sdio slave DMA channel0 masked interrupt status register. + */ +#define SDIO_SLC_SLC0INT_ST_REG (DR_REG_SLC_BASE + 0x8) +/** SDIO_SLC_FRHOST_BIT0_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_M (SDIO_SLC_FRHOST_BIT0_INT_ST_V << SDIO_SLC_FRHOST_BIT0_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_M (SDIO_SLC_FRHOST_BIT1_INT_ST_V << SDIO_SLC_FRHOST_BIT1_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_M (SDIO_SLC_FRHOST_BIT2_INT_ST_V << SDIO_SLC_FRHOST_BIT2_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_M (SDIO_SLC_FRHOST_BIT3_INT_ST_V << SDIO_SLC_FRHOST_BIT3_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_M (SDIO_SLC_FRHOST_BIT4_INT_ST_V << SDIO_SLC_FRHOST_BIT4_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_M (SDIO_SLC_FRHOST_BIT5_INT_ST_V << SDIO_SLC_FRHOST_BIT5_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_M (SDIO_SLC_FRHOST_BIT6_INT_ST_V << SDIO_SLC_FRHOST_BIT6_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_M (SDIO_SLC_FRHOST_BIT7_INT_ST_V << SDIO_SLC_FRHOST_BIT7_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST_S 7 +/** SDIO_SLC0_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST_M (SDIO_SLC0_RX_START_INT_ST_V << SDIO_SLC0_RX_START_INT_ST_S) +#define SDIO_SLC0_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST_S 8 +/** SDIO_SLC0_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST_M (SDIO_SLC0_TX_START_INT_ST_V << SDIO_SLC0_TX_START_INT_ST_S) +#define SDIO_SLC0_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST_M (SDIO_SLC0_RX_UDF_INT_ST_V << SDIO_SLC0_RX_UDF_INT_ST_S) +#define SDIO_SLC0_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST_M (SDIO_SLC0_TX_OVF_INT_ST_V << SDIO_SLC0_TX_OVF_INT_ST_S) +#define SDIO_SLC0_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST_M (SDIO_SLC0_TX_DONE_INT_ST_V << SDIO_SLC0_TX_DONE_INT_ST_S) +#define SDIO_SLC0_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_M (SDIO_SLC0_TX_SUC_EOF_INT_ST_V << SDIO_SLC0_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST_M (SDIO_SLC0_RX_DONE_INT_ST_V << SDIO_SLC0_RX_DONE_INT_ST_S) +#define SDIO_SLC0_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST_M (SDIO_SLC0_RX_EOF_INT_ST_V << SDIO_SLC0_RX_EOF_INT_ST_S) +#define SDIO_SLC0_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST_S 17 +/** SDIO_SLC0_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST_M (SDIO_SLC0_TOHOST_INT_ST_V << SDIO_SLC0_TOHOST_INT_ST_S) +#define SDIO_SLC0_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_M (SDIO_SLC0_HOST_RD_ACK_INT_ST_V << SDIO_SLC0_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_M (SDIO_SLC0_TX_ERR_EOF_INT_ST_V << SDIO_SLC0_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST_S 24 +/** SDIO_CMD_DTC_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST (BIT(25)) +#define SDIO_CMD_DTC_INT_ST_M (SDIO_CMD_DTC_INT_ST_V << SDIO_CMD_DTC_INT_ST_S) +#define SDIO_CMD_DTC_INT_ST_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST_M (SDIO_HDA_RECV_DONE_INT_ST_V << SDIO_HDA_RECV_DONE_INT_ST_S) +#define SDIO_HDA_RECV_DONE_INT_ST_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST_S 28 + +/** SDIO_SLC_SLC0INT_ENA_REG register + * Sdio slave DMA channel0 interrupt enable register. + */ +#define SDIO_SLC_SLC0INT_ENA_REG (DR_REG_SLC_BASE + 0xc) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_M (SDIO_SLC_FRHOST_BIT0_INT_ENA_V << SDIO_SLC_FRHOST_BIT0_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_M (SDIO_SLC_FRHOST_BIT1_INT_ENA_V << SDIO_SLC_FRHOST_BIT1_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_M (SDIO_SLC_FRHOST_BIT2_INT_ENA_V << SDIO_SLC_FRHOST_BIT2_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_M (SDIO_SLC_FRHOST_BIT3_INT_ENA_V << SDIO_SLC_FRHOST_BIT3_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_M (SDIO_SLC_FRHOST_BIT4_INT_ENA_V << SDIO_SLC_FRHOST_BIT4_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_M (SDIO_SLC_FRHOST_BIT5_INT_ENA_V << SDIO_SLC_FRHOST_BIT5_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_M (SDIO_SLC_FRHOST_BIT6_INT_ENA_V << SDIO_SLC_FRHOST_BIT6_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_M (SDIO_SLC_FRHOST_BIT7_INT_ENA_V << SDIO_SLC_FRHOST_BIT7_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA_S 7 +/** SDIO_SLC0_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA_M (SDIO_SLC0_RX_START_INT_ENA_V << SDIO_SLC0_RX_START_INT_ENA_S) +#define SDIO_SLC0_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA_S 8 +/** SDIO_SLC0_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA_M (SDIO_SLC0_TX_START_INT_ENA_V << SDIO_SLC0_TX_START_INT_ENA_S) +#define SDIO_SLC0_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA_M (SDIO_SLC0_RX_UDF_INT_ENA_V << SDIO_SLC0_RX_UDF_INT_ENA_S) +#define SDIO_SLC0_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA_M (SDIO_SLC0_TX_OVF_INT_ENA_V << SDIO_SLC0_TX_OVF_INT_ENA_S) +#define SDIO_SLC0_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA_M (SDIO_SLC0_TX_DONE_INT_ENA_V << SDIO_SLC0_TX_DONE_INT_ENA_S) +#define SDIO_SLC0_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA_M (SDIO_SLC0_RX_DONE_INT_ENA_V << SDIO_SLC0_RX_DONE_INT_ENA_S) +#define SDIO_SLC0_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA_M (SDIO_SLC0_RX_EOF_INT_ENA_V << SDIO_SLC0_RX_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA_M (SDIO_SLC0_TOHOST_INT_ENA_V << SDIO_SLC0_TOHOST_INT_ENA_S) +#define SDIO_SLC0_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/** SDIO_CMD_DTC_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA_M (SDIO_CMD_DTC_INT_ENA_V << SDIO_CMD_DTC_INT_ENA_S) +#define SDIO_CMD_DTC_INT_ENA_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA_M (SDIO_HDA_RECV_DONE_INT_ENA_V << SDIO_HDA_RECV_DONE_INT_ENA_S) +#define SDIO_HDA_RECV_DONE_INT_ENA_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA_S 28 + +/** SDIO_SLC_SLC0INT_CLR_REG register + * Sdio slave DMA channel0 interrupt clear register. + */ +#define SDIO_SLC_SLC0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) +/** SDIO_SLC_FRHOST_BIT0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_M (SDIO_SLC_FRHOST_BIT0_INT_CLR_V << SDIO_SLC_FRHOST_BIT0_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_M (SDIO_SLC_FRHOST_BIT1_INT_CLR_V << SDIO_SLC_FRHOST_BIT1_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_M (SDIO_SLC_FRHOST_BIT2_INT_CLR_V << SDIO_SLC_FRHOST_BIT2_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_M (SDIO_SLC_FRHOST_BIT3_INT_CLR_V << SDIO_SLC_FRHOST_BIT3_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_M (SDIO_SLC_FRHOST_BIT4_INT_CLR_V << SDIO_SLC_FRHOST_BIT4_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_M (SDIO_SLC_FRHOST_BIT5_INT_CLR_V << SDIO_SLC_FRHOST_BIT5_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_M (SDIO_SLC_FRHOST_BIT6_INT_CLR_V << SDIO_SLC_FRHOST_BIT6_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_M (SDIO_SLC_FRHOST_BIT7_INT_CLR_V << SDIO_SLC_FRHOST_BIT7_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_CLR_S 7 +/** SDIO_SLC0_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC0_RX_START_INT_CLR_M (SDIO_SLC0_RX_START_INT_CLR_V << SDIO_SLC0_RX_START_INT_CLR_S) +#define SDIO_SLC0_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_CLR_S 8 +/** SDIO_SLC0_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC0_TX_START_INT_CLR_M (SDIO_SLC0_TX_START_INT_CLR_V << SDIO_SLC0_TX_START_INT_CLR_S) +#define SDIO_SLC0_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_CLR_S 9 +/** SDIO_SLC0_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_CLR_M (SDIO_SLC0_RX_UDF_INT_CLR_V << SDIO_SLC0_RX_UDF_INT_CLR_S) +#define SDIO_SLC0_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC0_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_CLR_M (SDIO_SLC0_TX_OVF_INT_CLR_V << SDIO_SLC0_TX_OVF_INT_CLR_S) +#define SDIO_SLC0_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC0_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_CLR_M (SDIO_SLC0_TX_DONE_INT_CLR_V << SDIO_SLC0_TX_DONE_INT_CLR_S) +#define SDIO_SLC0_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_M (SDIO_SLC0_TX_SUC_EOF_INT_CLR_V << SDIO_SLC0_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC0_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_CLR_M (SDIO_SLC0_RX_DONE_INT_CLR_V << SDIO_SLC0_RX_DONE_INT_CLR_S) +#define SDIO_SLC0_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC0_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_CLR_M (SDIO_SLC0_RX_EOF_INT_CLR_V << SDIO_SLC0_RX_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC0_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_CLR_M (SDIO_SLC0_TOHOST_INT_CLR_V << SDIO_SLC0_TOHOST_INT_CLR_S) +#define SDIO_SLC0_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_CLR_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_M (SDIO_SLC0_HOST_RD_ACK_INT_CLR_V << SDIO_SLC0_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_M (SDIO_SLC0_TX_ERR_EOF_INT_CLR_V << SDIO_SLC0_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/** SDIO_CMD_DTC_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_CLR (BIT(25)) +#define SDIO_CMD_DTC_INT_CLR_M (SDIO_CMD_DTC_INT_CLR_V << SDIO_CMD_DTC_INT_CLR_S) +#define SDIO_CMD_DTC_INT_CLR_V 0x00000001U +#define SDIO_CMD_DTC_INT_CLR_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_M (SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V << SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/** SDIO_HDA_RECV_DONE_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_CLR (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_CLR_M (SDIO_HDA_RECV_DONE_INT_CLR_V << SDIO_HDA_RECV_DONE_INT_CLR_S) +#define SDIO_HDA_RECV_DONE_INT_CLR_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_CLR_S 28 + +/** SDIO_SLC_SLC1INT_RAW_REG register + * Sdio slave DMA channel1 raw interrupt status register. + */ +#define SDIO_SLC_SLC1INT_RAW_REG (DR_REG_SLC_BASE + 0x14) +/** SDIO_SLC_FRHOST_BIT8_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_RAW (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_M (SDIO_SLC_FRHOST_BIT8_INT_RAW_V << SDIO_SLC_FRHOST_BIT8_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_RAW_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_RAW (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_M (SDIO_SLC_FRHOST_BIT9_INT_RAW_V << SDIO_SLC_FRHOST_BIT9_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_RAW_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_RAW (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_M (SDIO_SLC_FRHOST_BIT10_INT_RAW_V << SDIO_SLC_FRHOST_BIT10_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_RAW_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_RAW (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_M (SDIO_SLC_FRHOST_BIT11_INT_RAW_V << SDIO_SLC_FRHOST_BIT11_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_RAW_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_RAW (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_M (SDIO_SLC_FRHOST_BIT12_INT_RAW_V << SDIO_SLC_FRHOST_BIT12_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_RAW_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_RAW (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_M (SDIO_SLC_FRHOST_BIT13_INT_RAW_V << SDIO_SLC_FRHOST_BIT13_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_RAW_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_RAW (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_M (SDIO_SLC_FRHOST_BIT14_INT_RAW_V << SDIO_SLC_FRHOST_BIT14_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_RAW_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_RAW (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_M (SDIO_SLC_FRHOST_BIT15_INT_RAW_V << SDIO_SLC_FRHOST_BIT15_INT_RAW_S) +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_RAW_S 7 +/** SDIO_SLC1_RX_START_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ +#define SDIO_SLC1_RX_START_INT_RAW (BIT(8)) +#define SDIO_SLC1_RX_START_INT_RAW_M (SDIO_SLC1_RX_START_INT_RAW_V << SDIO_SLC1_RX_START_INT_RAW_S) +#define SDIO_SLC1_RX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_RAW_S 8 +/** SDIO_SLC1_TX_START_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ +#define SDIO_SLC1_TX_START_INT_RAW (BIT(9)) +#define SDIO_SLC1_TX_START_INT_RAW_M (SDIO_SLC1_TX_START_INT_RAW_V << SDIO_SLC1_TX_START_INT_RAW_S) +#define SDIO_SLC1_TX_START_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_RAW_S 9 +/** SDIO_SLC1_RX_UDF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ +#define SDIO_SLC1_RX_UDF_INT_RAW (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_RAW_M (SDIO_SLC1_RX_UDF_INT_RAW_V << SDIO_SLC1_RX_UDF_INT_RAW_S) +#define SDIO_SLC1_RX_UDF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_RAW_S 10 +/** SDIO_SLC1_TX_OVF_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ +#define SDIO_SLC1_TX_OVF_INT_RAW (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_RAW_M (SDIO_SLC1_TX_OVF_INT_RAW_V << SDIO_SLC1_TX_OVF_INT_RAW_S) +#define SDIO_SLC1_TX_OVF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_RAW_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_RAW_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_M (SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V << SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_RAW_S 13 +/** SDIO_SLC1_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ +#define SDIO_SLC1_TX_DONE_INT_RAW (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_RAW_M (SDIO_SLC1_TX_DONE_INT_RAW_V << SDIO_SLC1_TX_DONE_INT_RAW_S) +#define SDIO_SLC1_TX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_RAW_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_M (SDIO_SLC1_TX_SUC_EOF_INT_RAW_V << SDIO_SLC1_TX_SUC_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_RAW_S 15 +/** SDIO_SLC1_RX_DONE_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ +#define SDIO_SLC1_RX_DONE_INT_RAW (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_RAW_M (SDIO_SLC1_RX_DONE_INT_RAW_V << SDIO_SLC1_RX_DONE_INT_RAW_S) +#define SDIO_SLC1_RX_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_RAW_S 16 +/** SDIO_SLC1_RX_EOF_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ +#define SDIO_SLC1_RX_EOF_INT_RAW (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_RAW_M (SDIO_SLC1_RX_EOF_INT_RAW_V << SDIO_SLC1_RX_EOF_INT_RAW_S) +#define SDIO_SLC1_RX_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_RAW_S 17 +/** SDIO_SLC1_TOHOST_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ +#define SDIO_SLC1_TOHOST_INT_RAW (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_RAW_M (SDIO_SLC1_TOHOST_INT_RAW_V << SDIO_SLC1_TOHOST_INT_RAW_S) +#define SDIO_SLC1_TOHOST_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_RAW_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_RAW_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_M (SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V << SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_RAW_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_RAW_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_M (SDIO_SLC1_HOST_RD_ACK_INT_RAW_V << SDIO_SLC1_HOST_RD_ACK_INT_RAW_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_RAW_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_M (SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V << SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_RAW_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_M (SDIO_SLC1_TX_ERR_EOF_INT_RAW_V << SDIO_SLC1_TX_ERR_EOF_INT_RAW_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_RAW_S 24 + +/** SDIO_SLC_SLC1INT_ST_REG register + * Sdio slave DMA channel1 masked interrupt status register. + */ +#define SDIO_SLC_SLC1INT_ST_REG (DR_REG_SLC_BASE + 0x18) +/** SDIO_SLC_FRHOST_BIT8_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_M (SDIO_SLC_FRHOST_BIT8_INT_ST_V << SDIO_SLC_FRHOST_BIT8_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_M (SDIO_SLC_FRHOST_BIT9_INT_ST_V << SDIO_SLC_FRHOST_BIT9_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_M (SDIO_SLC_FRHOST_BIT10_INT_ST_V << SDIO_SLC_FRHOST_BIT10_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_M (SDIO_SLC_FRHOST_BIT11_INT_ST_V << SDIO_SLC_FRHOST_BIT11_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_M (SDIO_SLC_FRHOST_BIT12_INT_ST_V << SDIO_SLC_FRHOST_BIT12_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_M (SDIO_SLC_FRHOST_BIT13_INT_ST_V << SDIO_SLC_FRHOST_BIT13_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_M (SDIO_SLC_FRHOST_BIT14_INT_ST_V << SDIO_SLC_FRHOST_BIT14_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_M (SDIO_SLC_FRHOST_BIT15_INT_ST_V << SDIO_SLC_FRHOST_BIT15_INT_ST_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST_S 7 +/** SDIO_SLC1_RX_START_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST_M (SDIO_SLC1_RX_START_INT_ST_V << SDIO_SLC1_RX_START_INT_ST_S) +#define SDIO_SLC1_RX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST_S 8 +/** SDIO_SLC1_TX_START_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST_M (SDIO_SLC1_TX_START_INT_ST_V << SDIO_SLC1_TX_START_INT_ST_S) +#define SDIO_SLC1_TX_START_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST_M (SDIO_SLC1_RX_UDF_INT_ST_V << SDIO_SLC1_RX_UDF_INT_ST_S) +#define SDIO_SLC1_RX_UDF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST_M (SDIO_SLC1_TX_OVF_INT_ST_V << SDIO_SLC1_TX_OVF_INT_ST_S) +#define SDIO_SLC1_TX_OVF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST_M (SDIO_SLC1_TX_DONE_INT_ST_V << SDIO_SLC1_TX_DONE_INT_ST_S) +#define SDIO_SLC1_TX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_M (SDIO_SLC1_TX_SUC_EOF_INT_ST_V << SDIO_SLC1_TX_SUC_EOF_INT_ST_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST_M (SDIO_SLC1_RX_DONE_INT_ST_V << SDIO_SLC1_RX_DONE_INT_ST_S) +#define SDIO_SLC1_RX_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST_M (SDIO_SLC1_RX_EOF_INT_ST_V << SDIO_SLC1_RX_EOF_INT_ST_S) +#define SDIO_SLC1_RX_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST_S 17 +/** SDIO_SLC1_TOHOST_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST_M (SDIO_SLC1_TOHOST_INT_ST_V << SDIO_SLC1_TOHOST_INT_ST_S) +#define SDIO_SLC1_TOHOST_INT_ST_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_M (SDIO_SLC1_HOST_RD_ACK_INT_ST_V << SDIO_SLC1_HOST_RD_ACK_INT_ST_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_M (SDIO_SLC1_TX_ERR_EOF_INT_ST_V << SDIO_SLC1_TX_ERR_EOF_INT_ST_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST_S 24 + +/** SDIO_SLC_SLC1INT_ENA_REG register + * Sdio slave DMA channel1 interrupt enable register. + */ +#define SDIO_SLC_SLC1INT_ENA_REG (DR_REG_SLC_BASE + 0x1c) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_M (SDIO_SLC_FRHOST_BIT8_INT_ENA_V << SDIO_SLC_FRHOST_BIT8_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_M (SDIO_SLC_FRHOST_BIT9_INT_ENA_V << SDIO_SLC_FRHOST_BIT9_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_M (SDIO_SLC_FRHOST_BIT10_INT_ENA_V << SDIO_SLC_FRHOST_BIT10_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_M (SDIO_SLC_FRHOST_BIT11_INT_ENA_V << SDIO_SLC_FRHOST_BIT11_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_M (SDIO_SLC_FRHOST_BIT12_INT_ENA_V << SDIO_SLC_FRHOST_BIT12_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_M (SDIO_SLC_FRHOST_BIT13_INT_ENA_V << SDIO_SLC_FRHOST_BIT13_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_M (SDIO_SLC_FRHOST_BIT14_INT_ENA_V << SDIO_SLC_FRHOST_BIT14_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_M (SDIO_SLC_FRHOST_BIT15_INT_ENA_V << SDIO_SLC_FRHOST_BIT15_INT_ENA_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA_S 7 +/** SDIO_SLC1_RX_START_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA_M (SDIO_SLC1_RX_START_INT_ENA_V << SDIO_SLC1_RX_START_INT_ENA_S) +#define SDIO_SLC1_RX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA_S 8 +/** SDIO_SLC1_TX_START_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA_M (SDIO_SLC1_TX_START_INT_ENA_V << SDIO_SLC1_TX_START_INT_ENA_S) +#define SDIO_SLC1_TX_START_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA_M (SDIO_SLC1_RX_UDF_INT_ENA_V << SDIO_SLC1_RX_UDF_INT_ENA_S) +#define SDIO_SLC1_RX_UDF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA_M (SDIO_SLC1_TX_OVF_INT_ENA_V << SDIO_SLC1_TX_OVF_INT_ENA_S) +#define SDIO_SLC1_TX_OVF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA_M (SDIO_SLC1_TX_DONE_INT_ENA_V << SDIO_SLC1_TX_DONE_INT_ENA_S) +#define SDIO_SLC1_TX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA_M (SDIO_SLC1_RX_DONE_INT_ENA_V << SDIO_SLC1_RX_DONE_INT_ENA_S) +#define SDIO_SLC1_RX_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA_M (SDIO_SLC1_RX_EOF_INT_ENA_V << SDIO_SLC1_RX_EOF_INT_ENA_S) +#define SDIO_SLC1_RX_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA_M (SDIO_SLC1_TOHOST_INT_ENA_V << SDIO_SLC1_TOHOST_INT_ENA_S) +#define SDIO_SLC1_TOHOST_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA_S 24 + +/** SDIO_SLC_SLC1INT_CLR_REG register + * Sdio slave DMA channel1 interrupt clear register. + */ +#define SDIO_SLC_SLC1INT_CLR_REG (DR_REG_SLC_BASE + 0x20) +/** SDIO_SLC_FRHOST_BIT8_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_CLR (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_M (SDIO_SLC_FRHOST_BIT8_INT_CLR_V << SDIO_SLC_FRHOST_BIT8_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_CLR_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_CLR (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_M (SDIO_SLC_FRHOST_BIT9_INT_CLR_V << SDIO_SLC_FRHOST_BIT9_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_CLR_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_CLR (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_M (SDIO_SLC_FRHOST_BIT10_INT_CLR_V << SDIO_SLC_FRHOST_BIT10_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_CLR_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_CLR (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_M (SDIO_SLC_FRHOST_BIT11_INT_CLR_V << SDIO_SLC_FRHOST_BIT11_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_CLR_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_CLR (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_M (SDIO_SLC_FRHOST_BIT12_INT_CLR_V << SDIO_SLC_FRHOST_BIT12_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_CLR_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_CLR (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_M (SDIO_SLC_FRHOST_BIT13_INT_CLR_V << SDIO_SLC_FRHOST_BIT13_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_CLR_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_CLR (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_M (SDIO_SLC_FRHOST_BIT14_INT_CLR_V << SDIO_SLC_FRHOST_BIT14_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_CLR_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_CLR (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_M (SDIO_SLC_FRHOST_BIT15_INT_CLR_V << SDIO_SLC_FRHOST_BIT15_INT_CLR_S) +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_CLR_S 7 +/** SDIO_SLC1_RX_START_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_CLR (BIT(8)) +#define SDIO_SLC1_RX_START_INT_CLR_M (SDIO_SLC1_RX_START_INT_CLR_V << SDIO_SLC1_RX_START_INT_CLR_S) +#define SDIO_SLC1_RX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_CLR_S 8 +/** SDIO_SLC1_TX_START_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_CLR (BIT(9)) +#define SDIO_SLC1_TX_START_INT_CLR_M (SDIO_SLC1_TX_START_INT_CLR_V << SDIO_SLC1_TX_START_INT_CLR_S) +#define SDIO_SLC1_TX_START_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_CLR_S 9 +/** SDIO_SLC1_RX_UDF_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_CLR (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_CLR_M (SDIO_SLC1_RX_UDF_INT_CLR_V << SDIO_SLC1_RX_UDF_INT_CLR_S) +#define SDIO_SLC1_RX_UDF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_CLR_S 10 +/** SDIO_SLC1_TX_OVF_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_CLR (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_CLR_M (SDIO_SLC1_TX_OVF_INT_CLR_V << SDIO_SLC1_TX_OVF_INT_CLR_S) +#define SDIO_SLC1_TX_OVF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_CLR_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_CLR_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_M (SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V << SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_CLR_S 13 +/** SDIO_SLC1_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_CLR (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_CLR_M (SDIO_SLC1_TX_DONE_INT_CLR_V << SDIO_SLC1_TX_DONE_INT_CLR_S) +#define SDIO_SLC1_TX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_CLR_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_M (SDIO_SLC1_TX_SUC_EOF_INT_CLR_V << SDIO_SLC1_TX_SUC_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_CLR_S 15 +/** SDIO_SLC1_RX_DONE_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_CLR (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_CLR_M (SDIO_SLC1_RX_DONE_INT_CLR_V << SDIO_SLC1_RX_DONE_INT_CLR_S) +#define SDIO_SLC1_RX_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_CLR_S 16 +/** SDIO_SLC1_RX_EOF_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_CLR (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_CLR_M (SDIO_SLC1_RX_EOF_INT_CLR_V << SDIO_SLC1_RX_EOF_INT_CLR_S) +#define SDIO_SLC1_RX_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_CLR_S 17 +/** SDIO_SLC1_TOHOST_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_CLR (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_CLR_M (SDIO_SLC1_TOHOST_INT_CLR_V << SDIO_SLC1_TOHOST_INT_CLR_S) +#define SDIO_SLC1_TOHOST_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_CLR_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_CLR_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_M (SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V << SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_CLR_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_CLR_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_M (SDIO_SLC1_HOST_RD_ACK_INT_CLR_V << SDIO_SLC1_HOST_RD_ACK_INT_CLR_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_CLR_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_M (SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V << SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_CLR_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_M (SDIO_SLC1_TX_ERR_EOF_INT_CLR_V << SDIO_SLC1_TX_ERR_EOF_INT_CLR_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_CLR_S 24 + +/** SDIO_SLC_RX_STATUS_REG register + * Sdio slave DMA rxfifo status register. + */ +#define SDIO_SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24) +/** SDIO_SLC0_RX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_FULL (BIT(0)) +#define SDIO_SLC0_RX_FULL_M (SDIO_SLC0_RX_FULL_V << SDIO_SLC0_RX_FULL_S) +#define SDIO_SLC0_RX_FULL_V 0x00000001U +#define SDIO_SLC0_RX_FULL_S 0 +/** SDIO_SLC0_RX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ +#define SDIO_SLC0_RX_EMPTY (BIT(1)) +#define SDIO_SLC0_RX_EMPTY_M (SDIO_SLC0_RX_EMPTY_V << SDIO_SLC0_RX_EMPTY_S) +#define SDIO_SLC0_RX_EMPTY_V 0x00000001U +#define SDIO_SLC0_RX_EMPTY_S 1 +/** SDIO_SLC0_RX_BUF_LEN : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ +#define SDIO_SLC0_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_M (SDIO_SLC0_RX_BUF_LEN_V << SDIO_SLC0_RX_BUF_LEN_S) +#define SDIO_SLC0_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC0_RX_BUF_LEN_S 2 +/** SDIO_SLC1_RX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_FULL (BIT(16)) +#define SDIO_SLC1_RX_FULL_M (SDIO_SLC1_RX_FULL_V << SDIO_SLC1_RX_FULL_S) +#define SDIO_SLC1_RX_FULL_V 0x00000001U +#define SDIO_SLC1_RX_FULL_S 16 +/** SDIO_SLC1_RX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ +#define SDIO_SLC1_RX_EMPTY (BIT(17)) +#define SDIO_SLC1_RX_EMPTY_M (SDIO_SLC1_RX_EMPTY_V << SDIO_SLC1_RX_EMPTY_S) +#define SDIO_SLC1_RX_EMPTY_V 0x00000001U +#define SDIO_SLC1_RX_EMPTY_S 17 +/** SDIO_SLC1_RX_BUF_LEN : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ +#define SDIO_SLC1_RX_BUF_LEN 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_M (SDIO_SLC1_RX_BUF_LEN_V << SDIO_SLC1_RX_BUF_LEN_S) +#define SDIO_SLC1_RX_BUF_LEN_V 0x00003FFFU +#define SDIO_SLC1_RX_BUF_LEN_S 18 + +/** SDIO_SLC_SLC0RXFIFO_PUSH_REG register + * Sdio slave DMA channel0 rxfifo debug register. + */ +#define SDIO_SLC_SLC0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) +/** SDIO_SLC0_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC0_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_M (SDIO_SLC0_RXFIFO_WDATA_V << SDIO_SLC0_RXFIFO_WDATA_S) +#define SDIO_SLC0_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC0_RXFIFO_WDATA_S 0 +/** SDIO_SLC0_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC0_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC0_RXFIFO_PUSH_M (SDIO_SLC0_RXFIFO_PUSH_V << SDIO_SLC0_RXFIFO_PUSH_S) +#define SDIO_SLC0_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC0_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_SLC1RXFIFO_PUSH_REG register + * Sdio slave DMA channel1 rxfifo debug register. + */ +#define SDIO_SLC_SLC1RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x2c) +/** SDIO_SLC1_RXFIFO_WDATA : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ +#define SDIO_SLC1_RXFIFO_WDATA 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_M (SDIO_SLC1_RXFIFO_WDATA_V << SDIO_SLC1_RXFIFO_WDATA_S) +#define SDIO_SLC1_RXFIFO_WDATA_V 0x000001FFU +#define SDIO_SLC1_RXFIFO_WDATA_S 0 +/** SDIO_SLC1_RXFIFO_PUSH : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ +#define SDIO_SLC1_RXFIFO_PUSH (BIT(16)) +#define SDIO_SLC1_RXFIFO_PUSH_M (SDIO_SLC1_RXFIFO_PUSH_V << SDIO_SLC1_RXFIFO_PUSH_S) +#define SDIO_SLC1_RXFIFO_PUSH_V 0x00000001U +#define SDIO_SLC1_RXFIFO_PUSH_S 16 + +/** SDIO_SLC_TX_STATUS_REG register + * Sdio slave DMA txfifo status register. + */ +#define SDIO_SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30) +/** SDIO_SLC0_TX_FULL : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_FULL (BIT(0)) +#define SDIO_SLC0_TX_FULL_M (SDIO_SLC0_TX_FULL_V << SDIO_SLC0_TX_FULL_S) +#define SDIO_SLC0_TX_FULL_V 0x00000001U +#define SDIO_SLC0_TX_FULL_S 0 +/** SDIO_SLC0_TX_EMPTY : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ +#define SDIO_SLC0_TX_EMPTY (BIT(1)) +#define SDIO_SLC0_TX_EMPTY_M (SDIO_SLC0_TX_EMPTY_V << SDIO_SLC0_TX_EMPTY_S) +#define SDIO_SLC0_TX_EMPTY_V 0x00000001U +#define SDIO_SLC0_TX_EMPTY_S 1 +/** SDIO_SLC1_TX_FULL : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_FULL (BIT(16)) +#define SDIO_SLC1_TX_FULL_M (SDIO_SLC1_TX_FULL_V << SDIO_SLC1_TX_FULL_S) +#define SDIO_SLC1_TX_FULL_V 0x00000001U +#define SDIO_SLC1_TX_FULL_S 16 +/** SDIO_SLC1_TX_EMPTY : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ +#define SDIO_SLC1_TX_EMPTY (BIT(17)) +#define SDIO_SLC1_TX_EMPTY_M (SDIO_SLC1_TX_EMPTY_V << SDIO_SLC1_TX_EMPTY_S) +#define SDIO_SLC1_TX_EMPTY_V 0x00000001U +#define SDIO_SLC1_TX_EMPTY_S 17 + +/** SDIO_SLC_SLC0TXFIFO_POP_REG register + * Sdio slave DMA channel0 txfifo debug register. + */ +#define SDIO_SLC_SLC0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) +/** SDIO_SLC0_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC0_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_M (SDIO_SLC0_TXFIFO_RDATA_V << SDIO_SLC0_TXFIFO_RDATA_S) +#define SDIO_SLC0_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC0_TXFIFO_RDATA_S 0 +/** SDIO_SLC0_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ +#define SDIO_SLC0_TXFIFO_POP (BIT(16)) +#define SDIO_SLC0_TXFIFO_POP_M (SDIO_SLC0_TXFIFO_POP_V << SDIO_SLC0_TXFIFO_POP_S) +#define SDIO_SLC0_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC0_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC1TXFIFO_POP_REG register + * Sdio slave DMA channel1 txfifo debug register. + */ +#define SDIO_SLC_SLC1TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x38) +/** SDIO_SLC1_TXFIFO_RDATA : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ +#define SDIO_SLC1_TXFIFO_RDATA 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_M (SDIO_SLC1_TXFIFO_RDATA_V << SDIO_SLC1_TXFIFO_RDATA_S) +#define SDIO_SLC1_TXFIFO_RDATA_V 0x000007FFU +#define SDIO_SLC1_TXFIFO_RDATA_S 0 +/** SDIO_SLC1_TXFIFO_POP : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ +#define SDIO_SLC1_TXFIFO_POP (BIT(16)) +#define SDIO_SLC1_TXFIFO_POP_M (SDIO_SLC1_TXFIFO_POP_V << SDIO_SLC1_TXFIFO_POP_S) +#define SDIO_SLC1_TXFIFO_POP_V 0x00000001U +#define SDIO_SLC1_TXFIFO_POP_S 16 + +/** SDIO_SLC_SLC0RX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC0RX_LINK_REG (DR_REG_SLC_BASE + 0x3c) +/** SDIO_SLC0_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ +#define SDIO_SLC0_RXLINK_STOP (BIT(28)) +#define SDIO_SLC0_RXLINK_STOP_M (SDIO_SLC0_RXLINK_STOP_V << SDIO_SLC0_RXLINK_STOP_S) +#define SDIO_SLC0_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_RXLINK_STOP_S 28 +/** SDIO_SLC0_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC0_RXLINK_START (BIT(29)) +#define SDIO_SLC0_RXLINK_START_M (SDIO_SLC0_RXLINK_START_V << SDIO_SLC0_RXLINK_START_S) +#define SDIO_SLC0_RXLINK_START_V 0x00000001U +#define SDIO_SLC0_RXLINK_START_S 29 +/** SDIO_SLC0_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ +#define SDIO_SLC0_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_RXLINK_RESTART_M (SDIO_SLC0_RXLINK_RESTART_V << SDIO_SLC0_RXLINK_RESTART_S) +#define SDIO_SLC0_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_RXLINK_RESTART_S 30 +/** SDIO_SLC0_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_RXLINK_PARK (BIT(31)) +#define SDIO_SLC0_RXLINK_PARK_M (SDIO_SLC0_RXLINK_PARK_V << SDIO_SLC0_RXLINK_PARK_S) +#define SDIO_SLC0_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0RX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC0RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x40) +/** SDIO_SLC0_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ +#define SDIO_SLC0_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_M (SDIO_SLC0_RXLINK_ADDR_V << SDIO_SLC0_RXLINK_ADDR_S) +#define SDIO_SLC0_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC0TX_LINK_REG register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC0TX_LINK_REG (DR_REG_SLC_BASE + 0x44) +/** SDIO_SLC0_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ +#define SDIO_SLC0_TXLINK_STOP (BIT(28)) +#define SDIO_SLC0_TXLINK_STOP_M (SDIO_SLC0_TXLINK_STOP_V << SDIO_SLC0_TXLINK_STOP_S) +#define SDIO_SLC0_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC0_TXLINK_STOP_S 28 +/** SDIO_SLC0_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC0_TXLINK_START (BIT(29)) +#define SDIO_SLC0_TXLINK_START_M (SDIO_SLC0_TXLINK_START_V << SDIO_SLC0_TXLINK_START_S) +#define SDIO_SLC0_TXLINK_START_V 0x00000001U +#define SDIO_SLC0_TXLINK_START_S 29 +/** SDIO_SLC0_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ +#define SDIO_SLC0_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC0_TXLINK_RESTART_M (SDIO_SLC0_TXLINK_RESTART_V << SDIO_SLC0_TXLINK_RESTART_S) +#define SDIO_SLC0_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC0_TXLINK_RESTART_S 30 +/** SDIO_SLC0_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ +#define SDIO_SLC0_TXLINK_PARK (BIT(31)) +#define SDIO_SLC0_TXLINK_PARK_M (SDIO_SLC0_TXLINK_PARK_V << SDIO_SLC0_TXLINK_PARK_S) +#define SDIO_SLC0_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC0_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC0TX_LINK_ADDR_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC0TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x48) +/** SDIO_SLC0_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ +#define SDIO_SLC0_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_M (SDIO_SLC0_TXLINK_ADDR_V << SDIO_SLC0_TXLINK_ADDR_S) +#define SDIO_SLC0_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1RX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +#define SDIO_SLC_SLC1RX_LINK_REG (DR_REG_SLC_BASE + 0x4c) +/** SDIO_SLC1_BT_PACKET : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ +#define SDIO_SLC1_BT_PACKET (BIT(20)) +#define SDIO_SLC1_BT_PACKET_M (SDIO_SLC1_BT_PACKET_V << SDIO_SLC1_BT_PACKET_S) +#define SDIO_SLC1_BT_PACKET_V 0x00000001U +#define SDIO_SLC1_BT_PACKET_S 20 +/** SDIO_SLC1_RXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ +#define SDIO_SLC1_RXLINK_STOP (BIT(28)) +#define SDIO_SLC1_RXLINK_STOP_M (SDIO_SLC1_RXLINK_STOP_V << SDIO_SLC1_RXLINK_STOP_S) +#define SDIO_SLC1_RXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_RXLINK_STOP_S 28 +/** SDIO_SLC1_RXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ +#define SDIO_SLC1_RXLINK_START (BIT(29)) +#define SDIO_SLC1_RXLINK_START_M (SDIO_SLC1_RXLINK_START_V << SDIO_SLC1_RXLINK_START_S) +#define SDIO_SLC1_RXLINK_START_V 0x00000001U +#define SDIO_SLC1_RXLINK_START_S 29 +/** SDIO_SLC1_RXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ +#define SDIO_SLC1_RXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_RXLINK_RESTART_M (SDIO_SLC1_RXLINK_RESTART_V << SDIO_SLC1_RXLINK_RESTART_S) +#define SDIO_SLC1_RXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_RXLINK_RESTART_S 30 +/** SDIO_SLC1_RXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_RXLINK_PARK (BIT(31)) +#define SDIO_SLC1_RXLINK_PARK_M (SDIO_SLC1_RXLINK_PARK_V << SDIO_SLC1_RXLINK_PARK_S) +#define SDIO_SLC1_RXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_RXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1RX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +#define SDIO_SLC_SLC1RX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x50) +/** SDIO_SLC1_RXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ +#define SDIO_SLC1_RXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_M (SDIO_SLC1_RXLINK_ADDR_V << SDIO_SLC1_RXLINK_ADDR_S) +#define SDIO_SLC1_RXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_ADDR_S 0 + +/** SDIO_SLC_SLC1TX_LINK_REG register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +#define SDIO_SLC_SLC1TX_LINK_REG (DR_REG_SLC_BASE + 0x54) +/** SDIO_SLC1_TXLINK_STOP : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ +#define SDIO_SLC1_TXLINK_STOP (BIT(28)) +#define SDIO_SLC1_TXLINK_STOP_M (SDIO_SLC1_TXLINK_STOP_V << SDIO_SLC1_TXLINK_STOP_S) +#define SDIO_SLC1_TXLINK_STOP_V 0x00000001U +#define SDIO_SLC1_TXLINK_STOP_S 28 +/** SDIO_SLC1_TXLINK_START : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ +#define SDIO_SLC1_TXLINK_START (BIT(29)) +#define SDIO_SLC1_TXLINK_START_M (SDIO_SLC1_TXLINK_START_V << SDIO_SLC1_TXLINK_START_S) +#define SDIO_SLC1_TXLINK_START_V 0x00000001U +#define SDIO_SLC1_TXLINK_START_S 29 +/** SDIO_SLC1_TXLINK_RESTART : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ +#define SDIO_SLC1_TXLINK_RESTART (BIT(30)) +#define SDIO_SLC1_TXLINK_RESTART_M (SDIO_SLC1_TXLINK_RESTART_V << SDIO_SLC1_TXLINK_RESTART_S) +#define SDIO_SLC1_TXLINK_RESTART_V 0x00000001U +#define SDIO_SLC1_TXLINK_RESTART_S 30 +/** SDIO_SLC1_TXLINK_PARK : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ +#define SDIO_SLC1_TXLINK_PARK (BIT(31)) +#define SDIO_SLC1_TXLINK_PARK_M (SDIO_SLC1_TXLINK_PARK_V << SDIO_SLC1_TXLINK_PARK_S) +#define SDIO_SLC1_TXLINK_PARK_V 0x00000001U +#define SDIO_SLC1_TXLINK_PARK_S 31 + +/** SDIO_SLC_SLC1TX_LINK_ADDR_REG register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLC1TX_LINK_ADDR_REG (DR_REG_SLC_BASE + 0x58) +/** SDIO_SLC1_TXLINK_ADDR : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ +#define SDIO_SLC1_TXLINK_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_M (SDIO_SLC1_TXLINK_ADDR_V << SDIO_SLC1_TXLINK_ADDR_S) +#define SDIO_SLC1_TXLINK_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_ADDR_S 0 + +/** SDIO_SLC_SLCINTVEC_TOHOST_REG register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +#define SDIO_SLC_SLCINTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x5c) +/** SDIO_SLC0_TOHOST_INTVEC : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ +#define SDIO_SLC0_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_M (SDIO_SLC0_TOHOST_INTVEC_V << SDIO_SLC0_TOHOST_INTVEC_S) +#define SDIO_SLC0_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC0_TOHOST_INTVEC_S 0 +/** SDIO_SLC1_TOHOST_INTVEC : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ +#define SDIO_SLC1_TOHOST_INTVEC 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_M (SDIO_SLC1_TOHOST_INTVEC_V << SDIO_SLC1_TOHOST_INTVEC_S) +#define SDIO_SLC1_TOHOST_INTVEC_V 0x000000FFU +#define SDIO_SLC1_TOHOST_INTVEC_S 16 + +/** SDIO_SLC_SLC0TOKEN0_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC0TOKEN0_REG (DR_REG_SLC_BASE + 0x60) +/** SDIO_SLC0_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_M (SDIO_SLC0_TOKEN0_WDATA_V << SDIO_SLC0_TOKEN0_WDATA_S) +#define SDIO_SLC0_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_WDATA_S 0 +/** SDIO_SLC0_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ +#define SDIO_SLC0_TOKEN0_WR (BIT(12)) +#define SDIO_SLC0_TOKEN0_WR_M (SDIO_SLC0_TOKEN0_WR_V << SDIO_SLC0_TOKEN0_WR_S) +#define SDIO_SLC0_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN0_WR_S 12 +/** SDIO_SLC0_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ +#define SDIO_SLC0_TOKEN0_INC (BIT(13)) +#define SDIO_SLC0_TOKEN0_INC_M (SDIO_SLC0_TOKEN0_INC_V << SDIO_SLC0_TOKEN0_INC_S) +#define SDIO_SLC0_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_S 13 +/** SDIO_SLC0_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ +#define SDIO_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN0_INC_MORE_M (SDIO_SLC0_TOKEN0_INC_MORE_V << SDIO_SLC0_TOKEN0_INC_MORE_S) +#define SDIO_SLC0_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN0 0x00000FFFU +#define SDIO_SLC0_TOKEN0_M (SDIO_SLC0_TOKEN0_V << SDIO_SLC0_TOKEN0_S) +#define SDIO_SLC0_TOKEN0_V 0x00000FFFU +#define SDIO_SLC0_TOKEN0_S 16 + +/** SDIO_SLC_SLC0TOKEN1_REG register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC0TOKEN1_REG (DR_REG_SLC_BASE + 0x64) +/** SDIO_SLC0_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC0_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_M (SDIO_SLC0_TOKEN1_WDATA_V << SDIO_SLC0_TOKEN1_WDATA_S) +#define SDIO_SLC0_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_WDATA_S 0 +/** SDIO_SLC0_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ +#define SDIO_SLC0_TOKEN1_WR (BIT(12)) +#define SDIO_SLC0_TOKEN1_WR_M (SDIO_SLC0_TOKEN1_WR_V << SDIO_SLC0_TOKEN1_WR_S) +#define SDIO_SLC0_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC0_TOKEN1_WR_S 12 +/** SDIO_SLC0_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ +#define SDIO_SLC0_TOKEN1_INC (BIT(13)) +#define SDIO_SLC0_TOKEN1_INC_M (SDIO_SLC0_TOKEN1_INC_V << SDIO_SLC0_TOKEN1_INC_S) +#define SDIO_SLC0_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_S 13 +/** SDIO_SLC0_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ +#define SDIO_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC0_TOKEN1_INC_MORE_M (SDIO_SLC0_TOKEN1_INC_MORE_V << SDIO_SLC0_TOKEN1_INC_MORE_S) +#define SDIO_SLC0_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC0_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC0_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ +#define SDIO_SLC0_TOKEN1 0x00000FFFU +#define SDIO_SLC0_TOKEN1_M (SDIO_SLC0_TOKEN1_V << SDIO_SLC0_TOKEN1_S) +#define SDIO_SLC0_TOKEN1_V 0x00000FFFU +#define SDIO_SLC0_TOKEN1_S 16 + +/** SDIO_SLC_SLC1TOKEN0_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +#define SDIO_SLC_SLC1TOKEN0_REG (DR_REG_SLC_BASE + 0x68) +/** SDIO_SLC1_TOKEN0_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN0_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_M (SDIO_SLC1_TOKEN0_WDATA_V << SDIO_SLC1_TOKEN0_WDATA_S) +#define SDIO_SLC1_TOKEN0_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_WDATA_S 0 +/** SDIO_SLC1_TOKEN0_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ +#define SDIO_SLC1_TOKEN0_WR (BIT(12)) +#define SDIO_SLC1_TOKEN0_WR_M (SDIO_SLC1_TOKEN0_WR_V << SDIO_SLC1_TOKEN0_WR_S) +#define SDIO_SLC1_TOKEN0_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN0_WR_S 12 +/** SDIO_SLC1_TOKEN0_INC : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ +#define SDIO_SLC1_TOKEN0_INC (BIT(13)) +#define SDIO_SLC1_TOKEN0_INC_M (SDIO_SLC1_TOKEN0_INC_V << SDIO_SLC1_TOKEN0_INC_S) +#define SDIO_SLC1_TOKEN0_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_S 13 +/** SDIO_SLC1_TOKEN0_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ +#define SDIO_SLC1_TOKEN0_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN0_INC_MORE_M (SDIO_SLC1_TOKEN0_INC_MORE_V << SDIO_SLC1_TOKEN0_INC_MORE_S) +#define SDIO_SLC1_TOKEN0_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN0_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN0 0x00000FFFU +#define SDIO_SLC1_TOKEN0_M (SDIO_SLC1_TOKEN0_V << SDIO_SLC1_TOKEN0_S) +#define SDIO_SLC1_TOKEN0_V 0x00000FFFU +#define SDIO_SLC1_TOKEN0_S 16 + +/** SDIO_SLC_SLC1TOKEN1_REG register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +#define SDIO_SLC_SLC1TOKEN1_REG (DR_REG_SLC_BASE + 0x6c) +/** SDIO_SLC1_TOKEN1_WDATA : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ +#define SDIO_SLC1_TOKEN1_WDATA 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_M (SDIO_SLC1_TOKEN1_WDATA_V << SDIO_SLC1_TOKEN1_WDATA_S) +#define SDIO_SLC1_TOKEN1_WDATA_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_WDATA_S 0 +/** SDIO_SLC1_TOKEN1_WR : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ +#define SDIO_SLC1_TOKEN1_WR (BIT(12)) +#define SDIO_SLC1_TOKEN1_WR_M (SDIO_SLC1_TOKEN1_WR_V << SDIO_SLC1_TOKEN1_WR_S) +#define SDIO_SLC1_TOKEN1_WR_V 0x00000001U +#define SDIO_SLC1_TOKEN1_WR_S 12 +/** SDIO_SLC1_TOKEN1_INC : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ +#define SDIO_SLC1_TOKEN1_INC (BIT(13)) +#define SDIO_SLC1_TOKEN1_INC_M (SDIO_SLC1_TOKEN1_INC_V << SDIO_SLC1_TOKEN1_INC_S) +#define SDIO_SLC1_TOKEN1_INC_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_S 13 +/** SDIO_SLC1_TOKEN1_INC_MORE : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ +#define SDIO_SLC1_TOKEN1_INC_MORE (BIT(14)) +#define SDIO_SLC1_TOKEN1_INC_MORE_M (SDIO_SLC1_TOKEN1_INC_MORE_V << SDIO_SLC1_TOKEN1_INC_MORE_S) +#define SDIO_SLC1_TOKEN1_INC_MORE_V 0x00000001U +#define SDIO_SLC1_TOKEN1_INC_MORE_S 14 +/** SDIO_SLC1_TOKEN1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ +#define SDIO_SLC1_TOKEN1 0x00000FFFU +#define SDIO_SLC1_TOKEN1_M (SDIO_SLC1_TOKEN1_V << SDIO_SLC1_TOKEN1_S) +#define SDIO_SLC1_TOKEN1_V 0x00000FFFU +#define SDIO_SLC1_TOKEN1_S 16 + +/** SDIO_SLC_CONF1_REG register + * Sdio slave DMA configuration1 register. + */ +#define SDIO_SLC_CONF1_REG (DR_REG_SLC_BASE + 0x70) +/** SDIO_SLC0_CHECK_OWNER : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ +#define SDIO_SLC0_CHECK_OWNER (BIT(0)) +#define SDIO_SLC0_CHECK_OWNER_M (SDIO_SLC0_CHECK_OWNER_V << SDIO_SLC0_CHECK_OWNER_S) +#define SDIO_SLC0_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC0_CHECK_OWNER_S 0 +/** SDIO_SLC0_TX_CHECK_SUM_EN : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ +#define SDIO_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SDIO_SLC0_TX_CHECK_SUM_EN_M (SDIO_SLC0_TX_CHECK_SUM_EN_V << SDIO_SLC0_TX_CHECK_SUM_EN_S) +#define SDIO_SLC0_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_TX_CHECK_SUM_EN_S 1 +/** SDIO_SLC0_RX_CHECK_SUM_EN : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ +#define SDIO_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SDIO_SLC0_RX_CHECK_SUM_EN_M (SDIO_SLC0_RX_CHECK_SUM_EN_V << SDIO_SLC0_RX_CHECK_SUM_EN_S) +#define SDIO_SLC0_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC0_RX_CHECK_SUM_EN_S 2 +/** SDIO_SDIO_CMD_HOLD_EN : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ +#define SDIO_SDIO_CMD_HOLD_EN (BIT(3)) +#define SDIO_SDIO_CMD_HOLD_EN_M (SDIO_SDIO_CMD_HOLD_EN_V << SDIO_SDIO_CMD_HOLD_EN_S) +#define SDIO_SDIO_CMD_HOLD_EN_V 0x00000001U +#define SDIO_SDIO_CMD_HOLD_EN_S 3 +/** SDIO_SLC0_LEN_AUTO_CLR : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ +#define SDIO_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SDIO_SLC0_LEN_AUTO_CLR_M (SDIO_SLC0_LEN_AUTO_CLR_V << SDIO_SLC0_LEN_AUTO_CLR_S) +#define SDIO_SLC0_LEN_AUTO_CLR_V 0x00000001U +#define SDIO_SLC0_LEN_AUTO_CLR_S 4 +/** SDIO_SLC0_TX_STITCH_EN : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ +#define SDIO_SLC0_TX_STITCH_EN (BIT(5)) +#define SDIO_SLC0_TX_STITCH_EN_M (SDIO_SLC0_TX_STITCH_EN_V << SDIO_SLC0_TX_STITCH_EN_S) +#define SDIO_SLC0_TX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_TX_STITCH_EN_S 5 +/** SDIO_SLC0_RX_STITCH_EN : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ +#define SDIO_SLC0_RX_STITCH_EN (BIT(6)) +#define SDIO_SLC0_RX_STITCH_EN_M (SDIO_SLC0_RX_STITCH_EN_V << SDIO_SLC0_RX_STITCH_EN_S) +#define SDIO_SLC0_RX_STITCH_EN_V 0x00000001U +#define SDIO_SLC0_RX_STITCH_EN_S 6 +/** SDIO_SLC1_CHECK_OWNER : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ +#define SDIO_SLC1_CHECK_OWNER (BIT(16)) +#define SDIO_SLC1_CHECK_OWNER_M (SDIO_SLC1_CHECK_OWNER_V << SDIO_SLC1_CHECK_OWNER_S) +#define SDIO_SLC1_CHECK_OWNER_V 0x00000001U +#define SDIO_SLC1_CHECK_OWNER_S 16 +/** SDIO_SLC1_TX_CHECK_SUM_EN : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ +#define SDIO_SLC1_TX_CHECK_SUM_EN (BIT(17)) +#define SDIO_SLC1_TX_CHECK_SUM_EN_M (SDIO_SLC1_TX_CHECK_SUM_EN_V << SDIO_SLC1_TX_CHECK_SUM_EN_S) +#define SDIO_SLC1_TX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_TX_CHECK_SUM_EN_S 17 +/** SDIO_SLC1_RX_CHECK_SUM_EN : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ +#define SDIO_SLC1_RX_CHECK_SUM_EN (BIT(18)) +#define SDIO_SLC1_RX_CHECK_SUM_EN_M (SDIO_SLC1_RX_CHECK_SUM_EN_V << SDIO_SLC1_RX_CHECK_SUM_EN_S) +#define SDIO_SLC1_RX_CHECK_SUM_EN_V 0x00000001U +#define SDIO_SLC1_RX_CHECK_SUM_EN_S 18 +/** SDIO_HOST_INT_LEVEL_SEL : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ +#define SDIO_HOST_INT_LEVEL_SEL (BIT(19)) +#define SDIO_HOST_INT_LEVEL_SEL_M (SDIO_HOST_INT_LEVEL_SEL_V << SDIO_HOST_INT_LEVEL_SEL_S) +#define SDIO_HOST_INT_LEVEL_SEL_V 0x00000001U +#define SDIO_HOST_INT_LEVEL_SEL_S 19 +/** SDIO_SDIO_CLK_EN : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ +#define SDIO_SDIO_CLK_EN (BIT(22)) +#define SDIO_SDIO_CLK_EN_M (SDIO_SDIO_CLK_EN_V << SDIO_SDIO_CLK_EN_S) +#define SDIO_SDIO_CLK_EN_V 0x00000001U +#define SDIO_SDIO_CLK_EN_S 22 + +/** SDIO_SLC_SLC0_STATE0_REG register + * Sdio slave DMA channel0 status register. + */ +#define SDIO_SLC_SLC0_STATE0_REG (DR_REG_SLC_BASE + 0x74) +/** SDIO_SLC0_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC0_STATE0 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_M (SDIO_SLC0_STATE0_V << SDIO_SLC0_STATE0_S) +#define SDIO_SLC0_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE0_S 0 + +/** SDIO_SLC_SLC0_STATE1_REG register + * Sdio slave DMA channel0 status1 register. + */ +#define SDIO_SLC_SLC0_STATE1_REG (DR_REG_SLC_BASE + 0x78) +/** SDIO_SLC0_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC0_STATE1 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_M (SDIO_SLC0_STATE1_V << SDIO_SLC0_STATE1_S) +#define SDIO_SLC0_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC0_STATE1_S 0 + +/** SDIO_SLC_SLC1_STATE0_REG register + * Sdio slave DMA channel1 status register. + */ +#define SDIO_SLC_SLC1_STATE0_REG (DR_REG_SLC_BASE + 0x7c) +/** SDIO_SLC1_STATE0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ +#define SDIO_SLC1_STATE0 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_M (SDIO_SLC1_STATE0_V << SDIO_SLC1_STATE0_S) +#define SDIO_SLC1_STATE0_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE0_S 0 + +/** SDIO_SLC_SLC1_STATE1_REG register + * Sdio slave DMA channel1 status1 register. + */ +#define SDIO_SLC_SLC1_STATE1_REG (DR_REG_SLC_BASE + 0x80) +/** SDIO_SLC1_STATE1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ +#define SDIO_SLC1_STATE1 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_M (SDIO_SLC1_STATE1_V << SDIO_SLC1_STATE1_S) +#define SDIO_SLC1_STATE1_V 0xFFFFFFFFU +#define SDIO_SLC1_STATE1_S 0 + +/** SDIO_SLC_BRIDGE_CONF_REG register + * Sdio slave DMA bridge configuration register. + */ +#define SDIO_SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x84) +/** SDIO_SLC_TXEOF_ENA : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ +#define SDIO_SLC_TXEOF_ENA 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_M (SDIO_SLC_TXEOF_ENA_V << SDIO_SLC_TXEOF_ENA_S) +#define SDIO_SLC_TXEOF_ENA_V 0x0000003FU +#define SDIO_SLC_TXEOF_ENA_S 0 +/** SDIO_SLC_FIFO_MAP_ENA : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ +#define SDIO_SLC_FIFO_MAP_ENA 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_M (SDIO_SLC_FIFO_MAP_ENA_V << SDIO_SLC_FIFO_MAP_ENA_S) +#define SDIO_SLC_FIFO_MAP_ENA_V 0x0000000FU +#define SDIO_SLC_FIFO_MAP_ENA_S 8 +/** SDIO_SLC0_TX_DUMMY_MODE : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ +#define SDIO_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SDIO_SLC0_TX_DUMMY_MODE_M (SDIO_SLC0_TX_DUMMY_MODE_V << SDIO_SLC0_TX_DUMMY_MODE_S) +#define SDIO_SLC0_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC0_TX_DUMMY_MODE_S 12 +/** SDIO_SLC_HDA_MAP_128K : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ +#define SDIO_SLC_HDA_MAP_128K (BIT(13)) +#define SDIO_SLC_HDA_MAP_128K_M (SDIO_SLC_HDA_MAP_128K_V << SDIO_SLC_HDA_MAP_128K_S) +#define SDIO_SLC_HDA_MAP_128K_V 0x00000001U +#define SDIO_SLC_HDA_MAP_128K_S 13 +/** SDIO_SLC1_TX_DUMMY_MODE : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ +#define SDIO_SLC1_TX_DUMMY_MODE (BIT(14)) +#define SDIO_SLC1_TX_DUMMY_MODE_M (SDIO_SLC1_TX_DUMMY_MODE_V << SDIO_SLC1_TX_DUMMY_MODE_S) +#define SDIO_SLC1_TX_DUMMY_MODE_V 0x00000001U +#define SDIO_SLC1_TX_DUMMY_MODE_S 14 +/** SDIO_SLC_TX_PUSH_IDLE_NUM : R/W; bitpos: [31:16]; default: 10; + * reserved + */ +#define SDIO_SLC_TX_PUSH_IDLE_NUM 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_M (SDIO_SLC_TX_PUSH_IDLE_NUM_V << SDIO_SLC_TX_PUSH_IDLE_NUM_S) +#define SDIO_SLC_TX_PUSH_IDLE_NUM_V 0x0000FFFFU +#define SDIO_SLC_TX_PUSH_IDLE_NUM_S 16 + +/** SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x88) +/** SDIO_SLC0_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_M (SDIO_SLC0_TO_EOF_DES_ADDR_V << SDIO_SLC0_TO_EOF_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel0 receiving packet status register. + */ +#define SDIO_SLC_SLC0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x8c) +/** SDIO_SLC0_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x90) +/** SDIO_SLC0_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x94) +/** SDIO_SLC1_TO_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ +#define SDIO_SLC1_TO_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_M (SDIO_SLC1_TO_EOF_DES_ADDR_V << SDIO_SLC1_TO_EOF_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG register + * Sdio slave DMA channel1 receiving packet status register. + */ +#define SDIO_SLC_SLC1_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x98) +/** SDIO_SLC1_TX_SUC_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_M (SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V << SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_SUC_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +#define SDIO_SLC_SLC1_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x9c) +/** SDIO_SLC1_TO_EOF_BFR_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_M (SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V << SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S) +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TO_EOF_BFR_DES_ADDR_S 0 + +/** SDIO_SLC_AHB_TEST_REG register + * Sdio slave AHB test register. + */ +#define SDIO_SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0xa0) +/** SDIO_SLC_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ +#define SDIO_SLC_AHB_TESTMODE 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_M (SDIO_SLC_AHB_TESTMODE_V << SDIO_SLC_AHB_TESTMODE_S) +#define SDIO_SLC_AHB_TESTMODE_V 0x00000007U +#define SDIO_SLC_AHB_TESTMODE_S 0 +/** SDIO_SLC_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ +#define SDIO_SLC_AHB_TESTADDR 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_M (SDIO_SLC_AHB_TESTADDR_V << SDIO_SLC_AHB_TESTADDR_S) +#define SDIO_SLC_AHB_TESTADDR_V 0x00000003U +#define SDIO_SLC_AHB_TESTADDR_S 4 + +/** SDIO_SLC_SDIO_ST_REG register + * Sdio slave function status register. + */ +#define SDIO_SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0xa4) +/** SDIO_CMD_ST : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ +#define SDIO_CMD_ST 0x00000007U +#define SDIO_CMD_ST_M (SDIO_CMD_ST_V << SDIO_CMD_ST_S) +#define SDIO_CMD_ST_V 0x00000007U +#define SDIO_CMD_ST_S 0 +/** SDIO_FUNC_ST : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ +#define SDIO_FUNC_ST 0x0000000FU +#define SDIO_FUNC_ST_M (SDIO_FUNC_ST_V << SDIO_FUNC_ST_S) +#define SDIO_FUNC_ST_V 0x0000000FU +#define SDIO_FUNC_ST_S 4 +/** SDIO_SDIO_WAKEUP : RO; bitpos: [8]; default: 0; + * reserved + */ +#define SDIO_SDIO_WAKEUP (BIT(8)) +#define SDIO_SDIO_WAKEUP_M (SDIO_SDIO_WAKEUP_V << SDIO_SDIO_WAKEUP_S) +#define SDIO_SDIO_WAKEUP_V 0x00000001U +#define SDIO_SDIO_WAKEUP_S 8 +/** SDIO_BUS_ST : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ +#define SDIO_BUS_ST 0x00000007U +#define SDIO_BUS_ST_M (SDIO_BUS_ST_V << SDIO_BUS_ST_S) +#define SDIO_BUS_ST_V 0x00000007U +#define SDIO_BUS_ST_S 12 +/** SDIO_FUNC1_ACC_STATE : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ +#define SDIO_FUNC1_ACC_STATE 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_M (SDIO_FUNC1_ACC_STATE_V << SDIO_FUNC1_ACC_STATE_S) +#define SDIO_FUNC1_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC1_ACC_STATE_S 16 +/** SDIO_FUNC2_ACC_STATE : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ +#define SDIO_FUNC2_ACC_STATE 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_M (SDIO_FUNC2_ACC_STATE_V << SDIO_FUNC2_ACC_STATE_S) +#define SDIO_FUNC2_ACC_STATE_V 0x0000001FU +#define SDIO_FUNC2_ACC_STATE_S 24 + +/** SDIO_SLC_RX_DSCR_CONF_REG register + * Sdio slave sending descriptor configuration register. + */ +#define SDIO_SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xa8) +/** SDIO_SLC0_TOKEN_NO_REPLACE : R/W; bitpos: [0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SDIO_SLC0_TOKEN_NO_REPLACE_M (SDIO_SLC0_TOKEN_NO_REPLACE_V << SDIO_SLC0_TOKEN_NO_REPLACE_S) +#define SDIO_SLC0_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_TOKEN_NO_REPLACE_S 0 +/** SDIO_SLC0_INFOR_NO_REPLACE : R/W; bitpos: [1]; default: 1; + * reserved + */ +#define SDIO_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SDIO_SLC0_INFOR_NO_REPLACE_M (SDIO_SLC0_INFOR_NO_REPLACE_V << SDIO_SLC0_INFOR_NO_REPLACE_S) +#define SDIO_SLC0_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC0_INFOR_NO_REPLACE_S 1 +/** SDIO_SLC0_RX_FILL_MODE : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC0_RX_FILL_MODE (BIT(2)) +#define SDIO_SLC0_RX_FILL_MODE_M (SDIO_SLC0_RX_FILL_MODE_V << SDIO_SLC0_RX_FILL_MODE_S) +#define SDIO_SLC0_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC0_RX_FILL_MODE_S 2 +/** SDIO_SLC0_RX_EOF_MODE : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ +#define SDIO_SLC0_RX_EOF_MODE (BIT(3)) +#define SDIO_SLC0_RX_EOF_MODE_M (SDIO_SLC0_RX_EOF_MODE_V << SDIO_SLC0_RX_EOF_MODE_S) +#define SDIO_SLC0_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC0_RX_EOF_MODE_S 3 +/** SDIO_SLC0_RX_FILL_EN : R/W; bitpos: [4]; default: 1; + * reserved + */ +#define SDIO_SLC0_RX_FILL_EN (BIT(4)) +#define SDIO_SLC0_RX_FILL_EN_M (SDIO_SLC0_RX_FILL_EN_V << SDIO_SLC0_RX_FILL_EN_S) +#define SDIO_SLC0_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC0_RX_FILL_EN_S 4 +/** SDIO_SLC0_RD_RETRY_THRESHOLD : R/W; bitpos: [15:5]; default: 128; + * reserved + */ +#define SDIO_SLC0_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_M (SDIO_SLC0_RD_RETRY_THRESHOLD_V << SDIO_SLC0_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC0_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC0_RD_RETRY_THRESHOLD_S 5 +/** SDIO_SLC1_TOKEN_NO_REPLACE : R/W; bitpos: [16]; default: 1; + * reserved + */ +#define SDIO_SLC1_TOKEN_NO_REPLACE (BIT(16)) +#define SDIO_SLC1_TOKEN_NO_REPLACE_M (SDIO_SLC1_TOKEN_NO_REPLACE_V << SDIO_SLC1_TOKEN_NO_REPLACE_S) +#define SDIO_SLC1_TOKEN_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_TOKEN_NO_REPLACE_S 16 +/** SDIO_SLC1_INFOR_NO_REPLACE : R/W; bitpos: [17]; default: 1; + * reserved + */ +#define SDIO_SLC1_INFOR_NO_REPLACE (BIT(17)) +#define SDIO_SLC1_INFOR_NO_REPLACE_M (SDIO_SLC1_INFOR_NO_REPLACE_V << SDIO_SLC1_INFOR_NO_REPLACE_S) +#define SDIO_SLC1_INFOR_NO_REPLACE_V 0x00000001U +#define SDIO_SLC1_INFOR_NO_REPLACE_S 17 +/** SDIO_SLC1_RX_FILL_MODE : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ +#define SDIO_SLC1_RX_FILL_MODE (BIT(18)) +#define SDIO_SLC1_RX_FILL_MODE_M (SDIO_SLC1_RX_FILL_MODE_V << SDIO_SLC1_RX_FILL_MODE_S) +#define SDIO_SLC1_RX_FILL_MODE_V 0x00000001U +#define SDIO_SLC1_RX_FILL_MODE_S 18 +/** SDIO_SLC1_RX_EOF_MODE : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ +#define SDIO_SLC1_RX_EOF_MODE (BIT(19)) +#define SDIO_SLC1_RX_EOF_MODE_M (SDIO_SLC1_RX_EOF_MODE_V << SDIO_SLC1_RX_EOF_MODE_S) +#define SDIO_SLC1_RX_EOF_MODE_V 0x00000001U +#define SDIO_SLC1_RX_EOF_MODE_S 19 +/** SDIO_SLC1_RX_FILL_EN : R/W; bitpos: [20]; default: 1; + * reserved + */ +#define SDIO_SLC1_RX_FILL_EN (BIT(20)) +#define SDIO_SLC1_RX_FILL_EN_M (SDIO_SLC1_RX_FILL_EN_V << SDIO_SLC1_RX_FILL_EN_S) +#define SDIO_SLC1_RX_FILL_EN_V 0x00000001U +#define SDIO_SLC1_RX_FILL_EN_S 20 +/** SDIO_SLC1_RD_RETRY_THRESHOLD : R/W; bitpos: [31:21]; default: 128; + * reserved + */ +#define SDIO_SLC1_RD_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_M (SDIO_SLC1_RD_RETRY_THRESHOLD_V << SDIO_SLC1_RD_RETRY_THRESHOLD_S) +#define SDIO_SLC1_RD_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC1_RD_RETRY_THRESHOLD_S 21 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xac) +/** SDIO_SLC0_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_M (SDIO_SLC0_TXLINK_DSCR_V << SDIO_SLC0_TXLINK_DSCR_S) +#define SDIO_SLC0_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xb0) +/** SDIO_SLC0_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_M (SDIO_SLC0_TXLINK_DSCR_BF0_V << SDIO_SLC0_TXLINK_DSCR_BF0_S) +#define SDIO_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xb4) +/** SDIO_SLC0_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_M (SDIO_SLC0_TXLINK_DSCR_BF1_V << SDIO_SLC0_TXLINK_DSCR_BF1_S) +#define SDIO_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xb8) +/** SDIO_SLC0_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC0_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_M (SDIO_SLC0_RXLINK_DSCR_V << SDIO_SLC0_RXLINK_DSCR_S) +#define SDIO_SLC0_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xbc) +/** SDIO_SLC0_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_M (SDIO_SLC0_RXLINK_DSCR_BF0_V << SDIO_SLC0_RXLINK_DSCR_BF0_S) +#define SDIO_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xc0) +/** SDIO_SLC0_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_M (SDIO_SLC0_RXLINK_DSCR_BF1_V << SDIO_SLC0_RXLINK_DSCR_BF1_S) +#define SDIO_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC0_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xc4) +/** SDIO_SLC1_TXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_M (SDIO_SLC1_TXLINK_DSCR_V << SDIO_SLC1_TXLINK_DSCR_S) +#define SDIO_SLC1_TXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xc8) +/** SDIO_SLC1_TXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_M (SDIO_SLC1_TXLINK_DSCR_BF0_V << SDIO_SLC1_TXLINK_DSCR_BF0_S) +#define SDIO_SLC1_TXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xcc) +/** SDIO_SLC1_TXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_M (SDIO_SLC1_TXLINK_DSCR_BF1_V << SDIO_SLC1_TXLINK_DSCR_BF1_S) +#define SDIO_SLC1_TXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_TXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xd0) +/** SDIO_SLC1_RXLINK_DSCR : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ +#define SDIO_SLC1_RXLINK_DSCR 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_M (SDIO_SLC1_RXLINK_DSCR_V << SDIO_SLC1_RXLINK_DSCR_S) +#define SDIO_SLC1_RXLINK_DSCR_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG register + * ******* Description *********** + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xd4) +/** SDIO_SLC1_RXLINK_DSCR_BF0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF0 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_M (SDIO_SLC1_RXLINK_DSCR_BF0_V << SDIO_SLC1_RXLINK_DSCR_BF0_S) +#define SDIO_SLC1_RXLINK_DSCR_BF0_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF0_S 0 + +/** SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG register + * reserved + */ +#define SDIO_SLC_SLC1_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xd8) +/** SDIO_SLC1_RXLINK_DSCR_BF1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_RXLINK_DSCR_BF1 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_M (SDIO_SLC1_RXLINK_DSCR_BF1_V << SDIO_SLC1_RXLINK_DSCR_BF1_S) +#define SDIO_SLC1_RXLINK_DSCR_BF1_V 0xFFFFFFFFU +#define SDIO_SLC1_RXLINK_DSCR_BF1_S 0 + +/** SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xdc) +/** SDIO_SLC0_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG register + * reserved + */ +#define SDIO_SLC_SLC1_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xe0) +/** SDIO_SLC1_TX_ERR_EOF_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_M (SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V << SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S) +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC1_TX_ERR_EOF_DES_ADDR_S 0 + +/** SDIO_SLC_TOKEN_LAT_REG register + * reserved + */ +#define SDIO_SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xe4) +/** SDIO_SLC0_TOKEN : RO; bitpos: [11:0]; default: 0; + * reserved + */ +#define SDIO_SLC0_TOKEN 0x00000FFFU +#define SDIO_SLC0_TOKEN_M (SDIO_SLC0_TOKEN_V << SDIO_SLC0_TOKEN_S) +#define SDIO_SLC0_TOKEN_V 0x00000FFFU +#define SDIO_SLC0_TOKEN_S 0 +/** SDIO_SLC1_TOKEN : RO; bitpos: [27:16]; default: 0; + * reserved + */ +#define SDIO_SLC1_TOKEN 0x00000FFFU +#define SDIO_SLC1_TOKEN_M (SDIO_SLC1_TOKEN_V << SDIO_SLC1_TOKEN_S) +#define SDIO_SLC1_TOKEN_V 0x00000FFFU +#define SDIO_SLC1_TOKEN_S 16 + +/** SDIO_SLC_TX_DSCR_CONF_REG register + * reserved + */ +#define SDIO_SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xe8) +/** SDIO_SLC_WR_RETRY_THRESHOLD : R/W; bitpos: [10:0]; default: 128; + * reserved + */ +#define SDIO_SLC_WR_RETRY_THRESHOLD 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_M (SDIO_SLC_WR_RETRY_THRESHOLD_V << SDIO_SLC_WR_RETRY_THRESHOLD_S) +#define SDIO_SLC_WR_RETRY_THRESHOLD_V 0x000007FFU +#define SDIO_SLC_WR_RETRY_THRESHOLD_S 0 + +/** SDIO_SLC_CMD_INFOR0_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xec) +/** SDIO_CMD_CONTENT0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT0 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_M (SDIO_CMD_CONTENT0_V << SDIO_CMD_CONTENT0_S) +#define SDIO_CMD_CONTENT0_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT0_S 0 + +/** SDIO_SLC_CMD_INFOR1_REG register + * reserved + */ +#define SDIO_SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xf0) +/** SDIO_CMD_CONTENT1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ +#define SDIO_CMD_CONTENT1 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_M (SDIO_CMD_CONTENT1_V << SDIO_CMD_CONTENT1_S) +#define SDIO_CMD_CONTENT1_V 0xFFFFFFFFU +#define SDIO_CMD_CONTENT1_S 0 + +/** SDIO_SLC_SLC0_LEN_CONF_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xf4) +/** SDIO_SLC0_LEN_WDATA : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ +#define SDIO_SLC0_LEN_WDATA 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_M (SDIO_SLC0_LEN_WDATA_V << SDIO_SLC0_LEN_WDATA_S) +#define SDIO_SLC0_LEN_WDATA_V 0x000FFFFFU +#define SDIO_SLC0_LEN_WDATA_S 0 +/** SDIO_SLC0_LEN_WR : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ +#define SDIO_SLC0_LEN_WR (BIT(20)) +#define SDIO_SLC0_LEN_WR_M (SDIO_SLC0_LEN_WR_V << SDIO_SLC0_LEN_WR_S) +#define SDIO_SLC0_LEN_WR_V 0x00000001U +#define SDIO_SLC0_LEN_WR_S 20 +/** SDIO_SLC0_LEN_INC : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC (BIT(21)) +#define SDIO_SLC0_LEN_INC_M (SDIO_SLC0_LEN_INC_V << SDIO_SLC0_LEN_INC_S) +#define SDIO_SLC0_LEN_INC_V 0x00000001U +#define SDIO_SLC0_LEN_INC_S 21 +/** SDIO_SLC0_LEN_INC_MORE : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ +#define SDIO_SLC0_LEN_INC_MORE (BIT(22)) +#define SDIO_SLC0_LEN_INC_MORE_M (SDIO_SLC0_LEN_INC_MORE_V << SDIO_SLC0_LEN_INC_MORE_S) +#define SDIO_SLC0_LEN_INC_MORE_V 0x00000001U +#define SDIO_SLC0_LEN_INC_MORE_S 22 +/** SDIO_SLC0_RX_PACKET_LOAD_EN : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_M (SDIO_SLC0_RX_PACKET_LOAD_EN_V << SDIO_SLC0_RX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_S 23 +/** SDIO_SLC0_TX_PACKET_LOAD_EN : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_M (SDIO_SLC0_TX_PACKET_LOAD_EN_V << SDIO_SLC0_TX_PACKET_LOAD_EN_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_S 24 +/** SDIO_SLC0_RX_GET_USED_DSCR : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ +#define SDIO_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SDIO_SLC0_RX_GET_USED_DSCR_M (SDIO_SLC0_RX_GET_USED_DSCR_V << SDIO_SLC0_RX_GET_USED_DSCR_S) +#define SDIO_SLC0_RX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_RX_GET_USED_DSCR_S 25 +/** SDIO_SLC0_TX_GET_USED_DSCR : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ +#define SDIO_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SDIO_SLC0_TX_GET_USED_DSCR_M (SDIO_SLC0_TX_GET_USED_DSCR_V << SDIO_SLC0_TX_GET_USED_DSCR_S) +#define SDIO_SLC0_TX_GET_USED_DSCR_V 0x00000001U +#define SDIO_SLC0_TX_GET_USED_DSCR_S 26 +/** SDIO_SLC0_RX_NEW_PKT_IND : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ +#define SDIO_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SDIO_SLC0_RX_NEW_PKT_IND_M (SDIO_SLC0_RX_NEW_PKT_IND_V << SDIO_SLC0_RX_NEW_PKT_IND_S) +#define SDIO_SLC0_RX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_RX_NEW_PKT_IND_S 27 +/** SDIO_SLC0_TX_NEW_PKT_IND : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ +#define SDIO_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SDIO_SLC0_TX_NEW_PKT_IND_M (SDIO_SLC0_TX_NEW_PKT_IND_V << SDIO_SLC0_TX_NEW_PKT_IND_S) +#define SDIO_SLC0_TX_NEW_PKT_IND_V 0x00000001U +#define SDIO_SLC0_TX_NEW_PKT_IND_S 28 +/** SDIO_SLC0_RX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST (BIT(29)) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_RX_PACKET_LOAD_EN_ST_S 29 +/** SDIO_SLC0_TX_PACKET_LOAD_EN_ST : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST (BIT(30)) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_M (SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V << SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S) +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_V 0x00000001U +#define SDIO_SLC0_TX_PACKET_LOAD_EN_ST_S 30 + +/** SDIO_SLC_SLC0_LENGTH_REG register + * reserved + */ +#define SDIO_SLC_SLC0_LENGTH_REG (DR_REG_SLC_BASE + 0xf8) +/** SDIO_SLC0_LEN : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ +#define SDIO_SLC0_LEN 0x000FFFFFU +#define SDIO_SLC0_LEN_M (SDIO_SLC0_LEN_V << SDIO_SLC0_LEN_S) +#define SDIO_SLC0_LEN_V 0x000FFFFFU +#define SDIO_SLC0_LEN_S 0 + +/** SDIO_SLC_SLC0_TXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xfc) +/** SDIO_SLC0_TX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) +/** SDIO_SLC0_TX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) +/** SDIO_SLC0_RX_PKT_H_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKT_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +#define SDIO_SLC_SLC0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) +/** SDIO_SLC0_RX_PKT_E_DSCR_ADDR : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x10c) +/** SDIO_SLC0_TX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +#define SDIO_SLC_SLC0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x110) +/** SDIO_SLC0_TX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x114) +/** SDIO_SLC0_RX_PKT_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x118) +/** SDIO_SLC0_RX_PKT_END_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_M (SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V << SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +/** SDIO_SLC_SEQ_POSITION_REG register + * The position of receiving packet configuration register. + */ +#define SDIO_SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x11c) +/** SDIO_SLC0_SEQ_POSITION : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ +#define SDIO_SLC0_SEQ_POSITION 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_M (SDIO_SLC0_SEQ_POSITION_V << SDIO_SLC0_SEQ_POSITION_S) +#define SDIO_SLC0_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC0_SEQ_POSITION_S 0 +/** SDIO_SLC1_SEQ_POSITION : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ +#define SDIO_SLC1_SEQ_POSITION 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_M (SDIO_SLC1_SEQ_POSITION_V << SDIO_SLC1_SEQ_POSITION_S) +#define SDIO_SLC1_SEQ_POSITION_V 0x000000FFU +#define SDIO_SLC1_SEQ_POSITION_S 8 + +/** SDIO_SLC_SLC0_DSCR_REC_CONF_REG register + * Sdio slave DMA sending linked list limit configuration register. + */ +#define SDIO_SLC_SLC0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x120) +/** SDIO_SLC0_RX_DSCR_REC_LIM : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ +#define SDIO_SLC0_RX_DSCR_REC_LIM 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_M (SDIO_SLC0_RX_DSCR_REC_LIM_V << SDIO_SLC0_RX_DSCR_REC_LIM_S) +#define SDIO_SLC0_RX_DSCR_REC_LIM_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_REC_LIM_S 0 + +/** SDIO_SLC_SDIO_CRC_ST0_REG register + * Sdio slave receiving packet data crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x124) +/** SDIO_DAT0_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ +#define SDIO_DAT0_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_M (SDIO_DAT0_CRC_ERR_CNT_V << SDIO_DAT0_CRC_ERR_CNT_S) +#define SDIO_DAT0_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT0_CRC_ERR_CNT_S 0 +/** SDIO_DAT1_CRC_ERR_CNT : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ +#define SDIO_DAT1_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_M (SDIO_DAT1_CRC_ERR_CNT_V << SDIO_DAT1_CRC_ERR_CNT_S) +#define SDIO_DAT1_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT1_CRC_ERR_CNT_S 8 +/** SDIO_DAT2_CRC_ERR_CNT : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ +#define SDIO_DAT2_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_M (SDIO_DAT2_CRC_ERR_CNT_V << SDIO_DAT2_CRC_ERR_CNT_S) +#define SDIO_DAT2_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT2_CRC_ERR_CNT_S 16 +/** SDIO_DAT3_CRC_ERR_CNT : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ +#define SDIO_DAT3_CRC_ERR_CNT 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_M (SDIO_DAT3_CRC_ERR_CNT_V << SDIO_DAT3_CRC_ERR_CNT_S) +#define SDIO_DAT3_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_DAT3_CRC_ERR_CNT_S 24 + +/** SDIO_SLC_SDIO_CRC_ST1_REG register + * Sdio slave receiving command crc status register. + */ +#define SDIO_SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x128) +/** SDIO_CMD_CRC_ERR_CNT : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ +#define SDIO_CMD_CRC_ERR_CNT 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_M (SDIO_CMD_CRC_ERR_CNT_V << SDIO_CMD_CRC_ERR_CNT_S) +#define SDIO_CMD_CRC_ERR_CNT_V 0x000000FFU +#define SDIO_CMD_CRC_ERR_CNT_S 0 +/** SDIO_ERR_CNT_CLR : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ +#define SDIO_ERR_CNT_CLR (BIT(31)) +#define SDIO_ERR_CNT_CLR_M (SDIO_ERR_CNT_CLR_V << SDIO_ERR_CNT_CLR_S) +#define SDIO_ERR_CNT_CLR_V 0x00000001U +#define SDIO_ERR_CNT_CLR_S 31 + +/** SDIO_SLC_SLC0_EOF_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x12c) +/** SDIO_SLC0_EOF_START_DES_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_EOF_START_DES_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_M (SDIO_SLC0_EOF_START_DES_ADDR_V << SDIO_SLC0_EOF_START_DES_ADDR_S) +#define SDIO_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_EOF_START_DES_ADDR_S 0 + +/** SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x130) +/** SDIO_SLC0_RX_PUSH_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_M (SDIO_SLC0_RX_PUSH_DSCR_ADDR_V << SDIO_SLC0_RX_PUSH_DSCR_ADDR_S) +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +#define SDIO_SLC_SLC0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x134) +/** SDIO_SLC0_RX_DONE_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ +#define SDIO_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_M (SDIO_SLC0_RX_DONE_DSCR_ADDR_V << SDIO_SLC0_RX_DONE_DSCR_ADDR_S) +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_RX_DONE_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_SUB_START_DES_REG register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +#define SDIO_SLC_SLC0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x138) +/** SDIO_SLC0_SUB_PAC_START_DSCR_ADDR : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_M (SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V << SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S) +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFFU +#define SDIO_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +/** SDIO_SLC_SLC0_DSCR_CNT_REG register + * Sdio slave DMA channel0 descriptor status register. + */ +#define SDIO_SLC_SLC0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x13c) +/** SDIO_SLC0_RX_DSCR_CNT_LAT : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ +#define SDIO_SLC0_RX_DSCR_CNT_LAT 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_M (SDIO_SLC0_RX_DSCR_CNT_LAT_V << SDIO_SLC0_RX_DSCR_CNT_LAT_S) +#define SDIO_SLC0_RX_DSCR_CNT_LAT_V 0x000003FFU +#define SDIO_SLC0_RX_DSCR_CNT_LAT_S 0 +/** SDIO_SLC0_RX_GET_EOF_OCC : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ +#define SDIO_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SDIO_SLC0_RX_GET_EOF_OCC_M (SDIO_SLC0_RX_GET_EOF_OCC_V << SDIO_SLC0_RX_GET_EOF_OCC_S) +#define SDIO_SLC0_RX_GET_EOF_OCC_V 0x00000001U +#define SDIO_SLC0_RX_GET_EOF_OCC_S 16 + +/** SDIO_SLC_SLC0_LEN_LIM_CONF_REG register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +#define SDIO_SLC_SLC0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x140) +/** SDIO_SLC0_LEN_LIM : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ +#define SDIO_SLC0_LEN_LIM 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_M (SDIO_SLC0_LEN_LIM_V << SDIO_SLC0_LEN_LIM_S) +#define SDIO_SLC0_LEN_LIM_V 0x000FFFFFU +#define SDIO_SLC0_LEN_LIM_S 0 + +/** SDIO_SLC_SLC0INT_ST1_REG register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +#define SDIO_SLC_SLC0INT_ST1_REG (DR_REG_SLC_BASE + 0x144) +/** SDIO_SLC_FRHOST_BIT0_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_M (SDIO_SLC_FRHOST_BIT0_INT_ST1_V << SDIO_SLC_FRHOST_BIT0_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_M (SDIO_SLC_FRHOST_BIT1_INT_ST1_V << SDIO_SLC_FRHOST_BIT1_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_M (SDIO_SLC_FRHOST_BIT2_INT_ST1_V << SDIO_SLC_FRHOST_BIT2_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_M (SDIO_SLC_FRHOST_BIT3_INT_ST1_V << SDIO_SLC_FRHOST_BIT3_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_M (SDIO_SLC_FRHOST_BIT4_INT_ST1_V << SDIO_SLC_FRHOST_BIT4_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_M (SDIO_SLC_FRHOST_BIT5_INT_ST1_V << SDIO_SLC_FRHOST_BIT5_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_M (SDIO_SLC_FRHOST_BIT6_INT_ST1_V << SDIO_SLC_FRHOST_BIT6_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_M (SDIO_SLC_FRHOST_BIT7_INT_ST1_V << SDIO_SLC_FRHOST_BIT7_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ST1_S 7 +/** SDIO_SLC0_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ST1_M (SDIO_SLC0_RX_START_INT_ST1_V << SDIO_SLC0_RX_START_INT_ST1_S) +#define SDIO_SLC0_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ST1_S 8 +/** SDIO_SLC0_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ST1_M (SDIO_SLC0_TX_START_INT_ST1_V << SDIO_SLC0_TX_START_INT_ST1_S) +#define SDIO_SLC0_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ST1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ST1_M (SDIO_SLC0_RX_UDF_INT_ST1_V << SDIO_SLC0_RX_UDF_INT_ST1_S) +#define SDIO_SLC0_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ST1_M (SDIO_SLC0_TX_OVF_INT_ST1_V << SDIO_SLC0_TX_OVF_INT_ST1_S) +#define SDIO_SLC0_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ST1_M (SDIO_SLC0_TX_DONE_INT_ST1_V << SDIO_SLC0_TX_DONE_INT_ST1_S) +#define SDIO_SLC0_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_M (SDIO_SLC0_TX_SUC_EOF_INT_ST1_V << SDIO_SLC0_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ST1_M (SDIO_SLC0_RX_DONE_INT_ST1_V << SDIO_SLC0_RX_DONE_INT_ST1_S) +#define SDIO_SLC0_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ST1_M (SDIO_SLC0_RX_EOF_INT_ST1_V << SDIO_SLC0_RX_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC0_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ST1_M (SDIO_SLC0_TOHOST_INT_ST1_V << SDIO_SLC0_TOHOST_INT_ST1_S) +#define SDIO_SLC0_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ST1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_M (SDIO_SLC0_HOST_RD_ACK_INT_ST1_V << SDIO_SLC0_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_M (SDIO_SLC0_TX_ERR_EOF_INT_ST1_V << SDIO_SLC0_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/** SDIO_CMD_DTC_INT_ST1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ST1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ST1_M (SDIO_CMD_DTC_INT_ST1_V << SDIO_CMD_DTC_INT_ST1_S) +#define SDIO_CMD_DTC_INT_ST1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ST1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ST1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ST1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ST1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ST1_M (SDIO_HDA_RECV_DONE_INT_ST1_V << SDIO_HDA_RECV_DONE_INT_ST1_S) +#define SDIO_HDA_RECV_DONE_INT_ST1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ST1_S 28 + +/** SDIO_SLC_SLC0INT_ENA1_REG register + * Sdio slave DMA channel0 interrupt enable register1. + */ +#define SDIO_SLC_SLC0INT_ENA1_REG (DR_REG_SLC_BASE + 0x148) +/** SDIO_SLC_FRHOST_BIT0_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_M (SDIO_SLC_FRHOST_BIT0_INT_ENA1_V << SDIO_SLC_FRHOST_BIT0_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT0_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT1_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_M (SDIO_SLC_FRHOST_BIT1_INT_ENA1_V << SDIO_SLC_FRHOST_BIT1_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT1_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT2_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_M (SDIO_SLC_FRHOST_BIT2_INT_ENA1_V << SDIO_SLC_FRHOST_BIT2_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT2_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT3_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_M (SDIO_SLC_FRHOST_BIT3_INT_ENA1_V << SDIO_SLC_FRHOST_BIT3_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT3_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT4_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_M (SDIO_SLC_FRHOST_BIT4_INT_ENA1_V << SDIO_SLC_FRHOST_BIT4_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT4_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT5_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_M (SDIO_SLC_FRHOST_BIT5_INT_ENA1_V << SDIO_SLC_FRHOST_BIT5_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT5_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT6_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_M (SDIO_SLC_FRHOST_BIT6_INT_ENA1_V << SDIO_SLC_FRHOST_BIT6_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT6_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT7_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_M (SDIO_SLC_FRHOST_BIT7_INT_ENA1_V << SDIO_SLC_FRHOST_BIT7_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT7_INT_ENA1_S 7 +/** SDIO_SLC0_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC0_RX_START_INT_ENA1_M (SDIO_SLC0_RX_START_INT_ENA1_V << SDIO_SLC0_RX_START_INT_ENA1_S) +#define SDIO_SLC0_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_START_INT_ENA1_S 8 +/** SDIO_SLC0_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC0_TX_START_INT_ENA1_M (SDIO_SLC0_TX_START_INT_ENA1_V << SDIO_SLC0_TX_START_INT_ENA1_S) +#define SDIO_SLC0_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_START_INT_ENA1_S 9 +/** SDIO_SLC0_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ +#define SDIO_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC0_RX_UDF_INT_ENA1_M (SDIO_SLC0_RX_UDF_INT_ENA1_V << SDIO_SLC0_RX_UDF_INT_ENA1_S) +#define SDIO_SLC0_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC0_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ +#define SDIO_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC0_TX_OVF_INT_ENA1_M (SDIO_SLC0_TX_OVF_INT_ENA1_V << SDIO_SLC0_TX_OVF_INT_ENA1_S) +#define SDIO_SLC0_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC0_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC0_TX_DONE_INT_ENA1_M (SDIO_SLC0_TX_DONE_INT_ENA1_V << SDIO_SLC0_TX_DONE_INT_ENA1_S) +#define SDIO_SLC0_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC0_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC0_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ +#define SDIO_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC0_RX_DONE_INT_ENA1_M (SDIO_SLC0_RX_DONE_INT_ENA1_V << SDIO_SLC0_RX_DONE_INT_ENA1_S) +#define SDIO_SLC0_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC0_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC0_RX_EOF_INT_ENA1_M (SDIO_SLC0_RX_EOF_INT_ENA1_V << SDIO_SLC0_RX_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC0_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ +#define SDIO_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC0_TOHOST_INT_ENA1_M (SDIO_SLC0_TOHOST_INT_ENA1_V << SDIO_SLC0_TOHOST_INT_ENA1_S) +#define SDIO_SLC0_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC0_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC0_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/** SDIO_CMD_DTC_INT_ENA1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ +#define SDIO_CMD_DTC_INT_ENA1 (BIT(25)) +#define SDIO_CMD_DTC_INT_ENA1_M (SDIO_CMD_DTC_INT_ENA1_V << SDIO_CMD_DTC_INT_ENA1_S) +#define SDIO_CMD_DTC_INT_ENA1_V 0x00000001U +#define SDIO_CMD_DTC_INT_ENA1_S 25 +/** SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_M (SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V << SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S) +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/** SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V << SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S) +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/** SDIO_HDA_RECV_DONE_INT_ENA1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ +#define SDIO_HDA_RECV_DONE_INT_ENA1 (BIT(28)) +#define SDIO_HDA_RECV_DONE_INT_ENA1_M (SDIO_HDA_RECV_DONE_INT_ENA1_V << SDIO_HDA_RECV_DONE_INT_ENA1_S) +#define SDIO_HDA_RECV_DONE_INT_ENA1_V 0x00000001U +#define SDIO_HDA_RECV_DONE_INT_ENA1_S 28 + +/** SDIO_SLC_SLC1INT_ST1_REG register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +#define SDIO_SLC_SLC1INT_ST1_REG (DR_REG_SLC_BASE + 0x14c) +/** SDIO_SLC_FRHOST_BIT8_INT_ST1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ST1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_M (SDIO_SLC_FRHOST_BIT8_INT_ST1_V << SDIO_SLC_FRHOST_BIT8_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ST1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ST1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ST1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_M (SDIO_SLC_FRHOST_BIT9_INT_ST1_V << SDIO_SLC_FRHOST_BIT9_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ST1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ST1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ST1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_M (SDIO_SLC_FRHOST_BIT10_INT_ST1_V << SDIO_SLC_FRHOST_BIT10_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ST1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ST1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ST1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_M (SDIO_SLC_FRHOST_BIT11_INT_ST1_V << SDIO_SLC_FRHOST_BIT11_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ST1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ST1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ST1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_M (SDIO_SLC_FRHOST_BIT12_INT_ST1_V << SDIO_SLC_FRHOST_BIT12_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ST1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ST1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ST1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_M (SDIO_SLC_FRHOST_BIT13_INT_ST1_V << SDIO_SLC_FRHOST_BIT13_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ST1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ST1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ST1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_M (SDIO_SLC_FRHOST_BIT14_INT_ST1_V << SDIO_SLC_FRHOST_BIT14_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ST1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ST1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ST1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_M (SDIO_SLC_FRHOST_BIT15_INT_ST1_V << SDIO_SLC_FRHOST_BIT15_INT_ST1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ST1_S 7 +/** SDIO_SLC1_RX_START_INT_ST1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ST1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ST1_M (SDIO_SLC1_RX_START_INT_ST1_V << SDIO_SLC1_RX_START_INT_ST1_S) +#define SDIO_SLC1_RX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ST1_S 8 +/** SDIO_SLC1_TX_START_INT_ST1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ST1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ST1_M (SDIO_SLC1_TX_START_INT_ST1_V << SDIO_SLC1_TX_START_INT_ST1_S) +#define SDIO_SLC1_TX_START_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ST1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ST1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ST1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ST1_M (SDIO_SLC1_RX_UDF_INT_ST1_V << SDIO_SLC1_RX_UDF_INT_ST1_S) +#define SDIO_SLC1_RX_UDF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ST1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ST1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ST1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ST1_M (SDIO_SLC1_TX_OVF_INT_ST1_V << SDIO_SLC1_TX_OVF_INT_ST1_S) +#define SDIO_SLC1_TX_OVF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ST1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ST1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ST1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ST1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ST1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ST1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ST1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ST1_M (SDIO_SLC1_TX_DONE_INT_ST1_V << SDIO_SLC1_TX_DONE_INT_ST1_S) +#define SDIO_SLC1_TX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ST1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ST1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_M (SDIO_SLC1_TX_SUC_EOF_INT_ST1_V << SDIO_SLC1_TX_SUC_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ST1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ST1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ST1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ST1_M (SDIO_SLC1_RX_DONE_INT_ST1_V << SDIO_SLC1_RX_DONE_INT_ST1_S) +#define SDIO_SLC1_RX_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ST1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ST1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ST1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ST1_M (SDIO_SLC1_RX_EOF_INT_ST1_V << SDIO_SLC1_RX_EOF_INT_ST1_S) +#define SDIO_SLC1_RX_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ST1_S 17 +/** SDIO_SLC1_TOHOST_INT_ST1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ST1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ST1_M (SDIO_SLC1_TOHOST_INT_ST1_V << SDIO_SLC1_TOHOST_INT_ST1_S) +#define SDIO_SLC1_TOHOST_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ST1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ST1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ST1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ST1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ST1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ST1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ST1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_M (SDIO_SLC1_HOST_RD_ACK_INT_ST1_V << SDIO_SLC1_HOST_RD_ACK_INT_ST1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ST1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ST1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ST1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ST1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_M (SDIO_SLC1_TX_ERR_EOF_INT_ST1_V << SDIO_SLC1_TX_ERR_EOF_INT_ST1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ST1_S 24 + +/** SDIO_SLC_SLC1INT_ENA1_REG register + * Sdio slave DMA channel1 interrupt enable register1. + */ +#define SDIO_SLC_SLC1INT_ENA1_REG (DR_REG_SLC_BASE + 0x150) +/** SDIO_SLC_FRHOST_BIT8_INT_ENA1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1 (BIT(0)) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_M (SDIO_SLC_FRHOST_BIT8_INT_ENA1_V << SDIO_SLC_FRHOST_BIT8_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT8_INT_ENA1_S 0 +/** SDIO_SLC_FRHOST_BIT9_INT_ENA1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1 (BIT(1)) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_M (SDIO_SLC_FRHOST_BIT9_INT_ENA1_V << SDIO_SLC_FRHOST_BIT9_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT9_INT_ENA1_S 1 +/** SDIO_SLC_FRHOST_BIT10_INT_ENA1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1 (BIT(2)) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_M (SDIO_SLC_FRHOST_BIT10_INT_ENA1_V << SDIO_SLC_FRHOST_BIT10_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT10_INT_ENA1_S 2 +/** SDIO_SLC_FRHOST_BIT11_INT_ENA1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1 (BIT(3)) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_M (SDIO_SLC_FRHOST_BIT11_INT_ENA1_V << SDIO_SLC_FRHOST_BIT11_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT11_INT_ENA1_S 3 +/** SDIO_SLC_FRHOST_BIT12_INT_ENA1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1 (BIT(4)) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_M (SDIO_SLC_FRHOST_BIT12_INT_ENA1_V << SDIO_SLC_FRHOST_BIT12_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT12_INT_ENA1_S 4 +/** SDIO_SLC_FRHOST_BIT13_INT_ENA1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1 (BIT(5)) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_M (SDIO_SLC_FRHOST_BIT13_INT_ENA1_V << SDIO_SLC_FRHOST_BIT13_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT13_INT_ENA1_S 5 +/** SDIO_SLC_FRHOST_BIT14_INT_ENA1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1 (BIT(6)) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_M (SDIO_SLC_FRHOST_BIT14_INT_ENA1_V << SDIO_SLC_FRHOST_BIT14_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT14_INT_ENA1_S 6 +/** SDIO_SLC_FRHOST_BIT15_INT_ENA1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1 (BIT(7)) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_M (SDIO_SLC_FRHOST_BIT15_INT_ENA1_V << SDIO_SLC_FRHOST_BIT15_INT_ENA1_S) +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_V 0x00000001U +#define SDIO_SLC_FRHOST_BIT15_INT_ENA1_S 7 +/** SDIO_SLC1_RX_START_INT_ENA1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_RX_START_INT_ENA1 (BIT(8)) +#define SDIO_SLC1_RX_START_INT_ENA1_M (SDIO_SLC1_RX_START_INT_ENA1_V << SDIO_SLC1_RX_START_INT_ENA1_S) +#define SDIO_SLC1_RX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_START_INT_ENA1_S 8 +/** SDIO_SLC1_TX_START_INT_ENA1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_START_INT_ENA1 (BIT(9)) +#define SDIO_SLC1_TX_START_INT_ENA1_M (SDIO_SLC1_TX_START_INT_ENA1_V << SDIO_SLC1_TX_START_INT_ENA1_S) +#define SDIO_SLC1_TX_START_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_START_INT_ENA1_S 9 +/** SDIO_SLC1_RX_UDF_INT_ENA1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ +#define SDIO_SLC1_RX_UDF_INT_ENA1 (BIT(10)) +#define SDIO_SLC1_RX_UDF_INT_ENA1_M (SDIO_SLC1_RX_UDF_INT_ENA1_V << SDIO_SLC1_RX_UDF_INT_ENA1_S) +#define SDIO_SLC1_RX_UDF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_UDF_INT_ENA1_S 10 +/** SDIO_SLC1_TX_OVF_INT_ENA1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ +#define SDIO_SLC1_TX_OVF_INT_ENA1 (BIT(11)) +#define SDIO_SLC1_TX_OVF_INT_ENA1_M (SDIO_SLC1_TX_OVF_INT_ENA1_V << SDIO_SLC1_TX_OVF_INT_ENA1_S) +#define SDIO_SLC1_TX_OVF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_OVF_INT_ENA1_S 11 +/** SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN0_1TO0_INT_ENA1_S 12 +/** SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_M (SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V << SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S) +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOKEN1_1TO0_INT_ENA1_S 13 +/** SDIO_SLC1_TX_DONE_INT_ENA1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ +#define SDIO_SLC1_TX_DONE_INT_ENA1 (BIT(14)) +#define SDIO_SLC1_TX_DONE_INT_ENA1_M (SDIO_SLC1_TX_DONE_INT_ENA1_V << SDIO_SLC1_TX_DONE_INT_ENA1_S) +#define SDIO_SLC1_TX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DONE_INT_ENA1_S 14 +/** SDIO_SLC1_TX_SUC_EOF_INT_ENA1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_M (SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V << SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_SUC_EOF_INT_ENA1_S 15 +/** SDIO_SLC1_RX_DONE_INT_ENA1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ +#define SDIO_SLC1_RX_DONE_INT_ENA1 (BIT(16)) +#define SDIO_SLC1_RX_DONE_INT_ENA1_M (SDIO_SLC1_RX_DONE_INT_ENA1_V << SDIO_SLC1_RX_DONE_INT_ENA1_S) +#define SDIO_SLC1_RX_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DONE_INT_ENA1_S 16 +/** SDIO_SLC1_RX_EOF_INT_ENA1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ +#define SDIO_SLC1_RX_EOF_INT_ENA1 (BIT(17)) +#define SDIO_SLC1_RX_EOF_INT_ENA1_M (SDIO_SLC1_RX_EOF_INT_ENA1_V << SDIO_SLC1_RX_EOF_INT_ENA1_S) +#define SDIO_SLC1_RX_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_EOF_INT_ENA1_S 17 +/** SDIO_SLC1_TOHOST_INT_ENA1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ +#define SDIO_SLC1_TOHOST_INT_ENA1 (BIT(18)) +#define SDIO_SLC1_TOHOST_INT_ENA1_M (SDIO_SLC1_TOHOST_INT_ENA1_V << SDIO_SLC1_TOHOST_INT_ENA1_S) +#define SDIO_SLC1_TOHOST_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TOHOST_INT_ENA1_S 18 +/** SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_S 19 +/** SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_M (SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V << SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S) +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_S 20 +/** SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_M (SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V << SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S) +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_DSCR_EMPTY_INT_ENA1_S 21 +/** SDIO_SLC1_HOST_RD_ACK_INT_ENA1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_M (SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V << SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S) +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_HOST_RD_ACK_INT_ENA1_S 22 +/** SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_M (SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V << SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S) +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_WR_RETRY_DONE_INT_ENA1_S 23 +/** SDIO_SLC1_TX_ERR_EOF_INT_ENA1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_M (SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V << SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S) +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_V 0x00000001U +#define SDIO_SLC1_TX_ERR_EOF_INT_ENA1_S 24 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x154) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC0_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x158) +/** SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x15c) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC0_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC0_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x160) +/** SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x164) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_TX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +#define SDIO_SLC_SLC1_TX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x168) +/** SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_START_REG register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x16c) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_SLC1_RX_SHAREMEM_END_REG register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +#define SDIO_SLC_SLC1_RX_SHAREMEM_END_REG (DR_REG_SLC_BASE + 0x170) +/** SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_M (SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V << SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S) +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_S 0 + +/** SDIO_SLC_HDA_TX_SHAREMEM_START_REG register + * Sdio slave HAD receiving address range register. + */ +#define SDIO_SLC_HDA_TX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x174) +/** SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_TX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_HDA_RX_SHAREMEM_START_REG register + * Sdio slave HAD sending address range register. + */ +#define SDIO_SLC_HDA_RX_SHAREMEM_START_REG (DR_REG_SLC_BASE + 0x178) +/** SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_M (SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V << SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S) +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_V 0xFFFFFFFFU +#define SDIO_SDIO_HDA_RX_SHAREMEM_START_ADDR_S 0 + +/** SDIO_SLC_BURST_LEN_REG register + * Sdio slave AHB burst type configuration register. + */ +#define SDIO_SLC_BURST_LEN_REG (DR_REG_SLC_BASE + 0x17c) +/** SDIO_SLC0_TXDATA_BURST_LEN : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_TXDATA_BURST_LEN (BIT(0)) +#define SDIO_SLC0_TXDATA_BURST_LEN_M (SDIO_SLC0_TXDATA_BURST_LEN_V << SDIO_SLC0_TXDATA_BURST_LEN_S) +#define SDIO_SLC0_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_TXDATA_BURST_LEN_S 0 +/** SDIO_SLC0_RXDATA_BURST_LEN : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC0_RXDATA_BURST_LEN (BIT(1)) +#define SDIO_SLC0_RXDATA_BURST_LEN_M (SDIO_SLC0_RXDATA_BURST_LEN_V << SDIO_SLC0_RXDATA_BURST_LEN_S) +#define SDIO_SLC0_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC0_RXDATA_BURST_LEN_S 1 +/** SDIO_SLC1_TXDATA_BURST_LEN : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_TXDATA_BURST_LEN (BIT(2)) +#define SDIO_SLC1_TXDATA_BURST_LEN_M (SDIO_SLC1_TXDATA_BURST_LEN_V << SDIO_SLC1_TXDATA_BURST_LEN_S) +#define SDIO_SLC1_TXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_TXDATA_BURST_LEN_S 2 +/** SDIO_SLC1_RXDATA_BURST_LEN : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ +#define SDIO_SLC1_RXDATA_BURST_LEN (BIT(3)) +#define SDIO_SLC1_RXDATA_BURST_LEN_M (SDIO_SLC1_RXDATA_BURST_LEN_V << SDIO_SLC1_RXDATA_BURST_LEN_S) +#define SDIO_SLC1_RXDATA_BURST_LEN_V 0x00000001U +#define SDIO_SLC1_RXDATA_BURST_LEN_S 3 + +/** SDIO_SLC_DATE_REG register + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE_REG (DR_REG_SLC_BASE + 0x1f8) +/** SDIO_SLC_DATE : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ +#define SDIO_SLC_DATE 0xFFFFFFFFU +#define SDIO_SLC_DATE_M (SDIO_SLC_DATE_V << SDIO_SLC_DATE_S) +#define SDIO_SLC_DATE_V 0xFFFFFFFFU +#define SDIO_SLC_DATE_S 0 + +/** SDIO_SLC_ID_REG register + * Sdio slave ID register. + */ +#define SDIO_SLC_ID_REG (DR_REG_SLC_BASE + 0x1fc) +/** SDIO_SLC_ID : R/W; bitpos: [31:0]; default: 256; + * reserved + */ +#define SDIO_SLC_ID 0xFFFFFFFFU +#define SDIO_SLC_ID_M (SDIO_SLC_ID_V << SDIO_SLC_ID_S) +#define SDIO_SLC_ID_V 0xFFFFFFFFU +#define SDIO_SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/sdio_slc_struct.h b/components/soc/esp32c61/register/soc/sdio_slc_struct.h new file mode 100644 index 0000000000..74bb9d69dd --- /dev/null +++ b/components/soc/esp32c61/register/soc/sdio_slc_struct.h @@ -0,0 +1,3345 @@ +/** + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#ifdef __cplusplus +extern "C" { +#endif + +/** Group: Configuration registers */ +/** Type of slc_conf0 register + * Sdio slave DMA configuration register. + */ +typedef union { + struct { + /** slc0_tx_rst : R/W; bitpos: [0]; default: 0; + * Set 1 to reset receiving fsm in dma channel0. + */ + uint32_t slc0_tx_rst:1; + /** slc0_rx_rst : R/W; bitpos: [1]; default: 0; + * Set 1 to reset transmitting fsm in dma channel0. + */ + uint32_t slc0_rx_rst:1; + /** slc_ahbm_fifo_rst : R/W; bitpos: [2]; default: 0; + * reset the command fifo of AHB bus of sdio slave + */ + uint32_t slc_ahbm_fifo_rst:1; + /** slc_ahbm_rst : R/W; bitpos: [3]; default: 0; + * reset the AHB bus of sdio slave + */ + uint32_t slc_ahbm_rst:1; + /** slc0_tx_loop_test : R/W; bitpos: [4]; default: 0; + * Loop around when the slave buffer finishes receiving packets. When set to 1, + * hardware will not change the owner bit in the linked list. + */ + uint32_t slc0_tx_loop_test:1; + /** slc0_rx_loop_test : R/W; bitpos: [5]; default: 0; + * Loop around when the slave buffer finishes sending packets. When set to 1, hardware + * will not change the owner bit in the linked list. + */ + uint32_t slc0_rx_loop_test:1; + /** slc0_rx_auto_wrback : R/W; bitpos: [6]; default: 0; + * Set 1 to enable change the owner bit of rx link descriptor + */ + uint32_t slc0_rx_auto_wrback:1; + /** slc0_rx_no_restart_clr : R/W; bitpos: [7]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc0_bt_rx_new_packet_int_raw or slc0_host_rd_retry_int_raw will be + * automatically cleared. + */ + uint32_t slc0_rx_no_restart_clr:1; + /** slc0_rxdscr_burst_en : R/W; bitpos: [8]; default: 1; + * 0- AHB burst type is single when slave read rx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read rx-descriptor from memory + * through slc0 + */ + uint32_t slc0_rxdscr_burst_en:1; + /** slc0_rxdata_burst_en : R/W; bitpos: [9]; default: 1; + * 0- AHB burst type is single when slave receives data from memory,1-AHB burst type + * is not single when slave receives data from memory + */ + uint32_t slc0_rxdata_burst_en:1; + /** slc0_rxlink_auto_ret : R/W; bitpos: [10]; default: 1; + * enable the function that when host reading packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_rxlink_auto_ret:1; + /** slc0_txlink_auto_ret : R/W; bitpos: [11]; default: 1; + * enable the function that when host sending packet retries, slc1 will automatically + * jump to the start descriptor of the previous packet. + */ + uint32_t slc0_txlink_auto_ret:1; + /** slc0_txdscr_burst_en : R/W; bitpos: [12]; default: 1; + * 0- AHB burst type is single when slave read tx-descriptor from memory through + * slc0,1-AHB burst type is not single when slave read tx-descriptor from memory + * through slc0 + */ + uint32_t slc0_txdscr_burst_en:1; + /** slc0_txdata_burst_en : R/W; bitpos: [13]; default: 1; + * 0- AHB burst type is single when slave send data to memory,1-AHB burst type is not + * single when slave send data to memory + */ + uint32_t slc0_txdata_burst_en:1; + /** slc0_token_auto_clr : R/W; bitpos: [14]; default: 1; + * auto clear slc0_token1 enable + */ + uint32_t slc0_token_auto_clr:1; + /** slc0_token_sel : R/W; bitpos: [15]; default: 1; + * 0: choose to save slc0_token0's value, 1: choose to save the accumulative value of + * slc0_token1 + */ + uint32_t slc0_token_sel:1; + /** slc1_tx_rst : R/W; bitpos: [16]; default: 0; + * Set 1 to reset receiving fsm in dma slc0. + */ + uint32_t slc1_tx_rst:1; + /** slc1_rx_rst : R/W; bitpos: [17]; default: 0; + * Set 1 to reset sending fsm in dma slc0. + */ + uint32_t slc1_rx_rst:1; + /** slc0_wr_retry_mask_en : R/W; bitpos: [18]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc0_wr_retry_mask_en:1; + /** slc1_wr_retry_mask_en : R/W; bitpos: [19]; default: 1; + * Set this bit to generate an interrupt when host sending retry finishes and prevent + * host still retrying after one successful retry through dma channel0 + */ + uint32_t slc1_wr_retry_mask_en:1; + /** slc1_tx_loop_test : R/W; bitpos: [20]; default: 1; + * owner control when slc1 writes back tx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_tx_loop_test:1; + /** slc1_rx_loop_test : R/W; bitpos: [21]; default: 1; + * owner control when slc1 writes back rx descriptor: 0- cpu is owner, 1-dma is owner. + */ + uint32_t slc1_rx_loop_test:1; + /** slc1_rx_auto_wrback : R/W; bitpos: [22]; default: 0; + * Set 1 to enable change the owner bit of the transmitting buffer's linked list when + * transmitting data. + */ + uint32_t slc1_rx_auto_wrback:1; + /** slc1_rx_no_restart_clr : R/W; bitpos: [23]; default: 0; + * Set this bit to disable the function that when slave starts to send data to host, + * the slc1_bt_rx_new_packet_int_raw, slc1_wifi_rx_new_packet_int_raw or + * slc1_host_rd_retry_int_raw will be automatically cleared. + */ + uint32_t slc1_rx_no_restart_clr:1; + /** slc1_rxdscr_burst_en : R/W; bitpos: [24]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for sending + * data,1-AHB burst type is not single when dma channel1 fetches linked list for + * sending data + */ + uint32_t slc1_rxdscr_burst_en:1; + /** slc1_rxdata_burst_en : R/W; bitpos: [25]; default: 1; + * 0- AHB burst type is single when slave receives data through dma channel1,1-AHB + * burst type is not single when slave receives data through dma channel1 + */ + uint32_t slc1_rxdata_burst_en:1; + /** slc1_rxlink_auto_ret : R/W; bitpos: [26]; default: 1; + * enable the function that when host reading packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_rxlink_auto_ret:1; + /** slc1_txlink_auto_ret : R/W; bitpos: [27]; default: 1; + * enable the function that when host sending packet retries, dma channel1 will + * automatically jump to the start descriptor of the previous packet. + */ + uint32_t slc1_txlink_auto_ret:1; + /** slc1_txdscr_burst_en : R/W; bitpos: [28]; default: 1; + * 0- AHB burst type is single when dma channel1 fetches linked list for receiving + * data, 1-AHB burst type is not single when dma channel1 fetches linked list for + * receiving data + */ + uint32_t slc1_txdscr_burst_en:1; + /** slc1_txdata_burst_en : R/W; bitpos: [29]; default: 1; + * 0- AHB burst type is single when slave sends data to memory through dma channel1, + * 1-AHB burst type is not single when slave sends data to memory through dma channel1. + */ + uint32_t slc1_txdata_burst_en:1; + uint32_t reserved_30:1; + /** slc1_token_sel : R/W; bitpos: [31]; default: 1; + * reserved + */ + uint32_t slc1_token_sel:1; + }; + uint32_t val; +} sdio_slc_conf0_reg_t; + +/** Type of slc_slc0rxfifo_push register + * Sdio slave DMA channel0 rxfifo debug register. + */ +typedef union { + struct { + /** slc0_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc0_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc0_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc0_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc0_rxfifo through APB bus + * successfully. + */ + uint32_t slc0_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0rxfifo_push_reg_t; + +/** Type of slc_slc1rxfifo_push register + * Sdio slave DMA channel1 rxfifo debug register. + */ +typedef union { + struct { + /** slc1_rxfifo_wdata : R/W; bitpos: [8:0]; default: 0; + * The data used to sent into rxfifo through APB bus. + */ + uint32_t slc1_rxfifo_wdata:9; + uint32_t reserved_9:7; + /** slc1_rxfifo_push : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to send slc1_rxfifo_wdata into rxfifo through APB bus. This bit is + * cleared automatically after sending one data to slc1_rxfifo through APB bus + * successfully. + */ + uint32_t slc1_rxfifo_push:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1rxfifo_push_reg_t; + +/** Type of slc_slc0rx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 sending packets. + */ + uint32_t slc0_rxlink_stop:1; + /** slc0_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc0_rxlink_start:1; + /** slc0_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 sending + * packets. + */ + uint32_t slc0_rxlink_restart:1; + /** slc0_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel0 in idle state + */ + uint32_t slc0_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0rx_link_reg_t; + +/** Type of slc_slc0rx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc0_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's sending linked list. + */ + uint32_t slc0_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0rx_link_addr_reg_t; + +/** Type of slc_slc0tx_link register + * Sdio slave DMA channel0 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc0_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel0 receiving packets. + */ + uint32_t slc0_txlink_stop:1; + /** slc0_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel0 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc0_txlink_start:1; + /** slc0_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel0 receiving + * packets. + */ + uint32_t slc0_txlink_restart:1; + /** slc0_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel0 in idle state + */ + uint32_t slc0_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc0tx_link_reg_t; + +/** Type of slc_slc0tx_link_addr register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel0's receiving linked list. + */ + uint32_t slc0_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc0tx_link_addr_reg_t; + +/** Type of slc_slc1rx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * sending data. + */ +typedef union { + struct { + uint32_t reserved_0:20; + /** slc1_bt_packet : R/W; bitpos: [20]; default: 1; + * Configure the packet type for slave to send: 0- wifi packet, 1- blue-tooth packet. + */ + uint32_t slc1_bt_packet:1; + uint32_t reserved_21:7; + /** slc1_rxlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 sending packets. + */ + uint32_t slc1_rxlink_stop:1; + /** slc1_rxlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 sending packets. Sending + * will start from address indicated by SLC0_RXLINK_ADDR. + */ + uint32_t slc1_rxlink_start:1; + /** slc1_rxlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 sending + * packets. + */ + uint32_t slc1_rxlink_restart:1; + /** slc1_rxlink_park : RO; bitpos: [31]; default: 1; + * The status bit for sending link list fsm of dma channel1 in idle state + */ + uint32_t slc1_rxlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1rx_link_reg_t; + +/** Type of slc_slc1rx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of sending link list. + */ +typedef union { + struct { + /** slc1_rxlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's sending linked list. + */ + uint32_t slc1_rxlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1rx_link_addr_reg_t; + +/** Type of slc_slc1tx_link register + * Sdio slave DMA channel1 configuration and status register of link list for slave + * receiving data. + */ +typedef union { + struct { + uint32_t reserved_0:28; + /** slc1_txlink_stop : R/W/SC; bitpos: [28]; default: 0; + * Set 1 to stop the linked list operation for dma channel1 receiving packets. + */ + uint32_t slc1_txlink_stop:1; + /** slc1_txlink_start : R/W/SC; bitpos: [29]; default: 0; + * Set 1 to start the linked list operation for dma channel1 receiving packets. + * Sending will start from address indicated by SLC0_TXLINK_ADDR. + */ + uint32_t slc1_txlink_start:1; + /** slc1_txlink_restart : R/W/SC; bitpos: [30]; default: 0; + * Set 1 to restart and continue the linked list operation for dma channel1 receiving + * packets. + */ + uint32_t slc1_txlink_restart:1; + /** slc1_txlink_park : RO; bitpos: [31]; default: 1; + * The status bit for receiving link list fsm of dma channel1 in idle state + */ + uint32_t slc1_txlink_park:1; + }; + uint32_t val; +} sdio_slc_slc1tx_link_reg_t; + +/** Type of slc_slc1tx_link_addr register + * Sdio slave DMA channel1 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc1_txlink_addr : R/W; bitpos: [31:0]; default: 0; + * The initial address of dma channel1's receiving linked list. + */ + uint32_t slc1_txlink_addr:32; + }; + uint32_t val; +} sdio_slc_slc1tx_link_addr_reg_t; + +/** Type of slc_slcintvec_tohost register + * Sdio slave DMA channel0 address of first descriptor of receiving linked list. + */ +typedef union { + struct { + /** slc0_tohost_intvec : WT; bitpos: [7:0]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel0. + */ + uint32_t slc0_tohost_intvec:8; + uint32_t reserved_8:8; + /** slc1_tohost_intvec : WT; bitpos: [23:16]; default: 0; + * The interrupt vector for slave to interrupt host through dma channel1. + */ + uint32_t slc1_tohost_intvec:8; + uint32_t reserved_24:8; + }; + uint32_t val; +} sdio_slc_slcintvec_tohost_reg_t; + +/** Type of slc_slc0token0 register + * Sdio slave DMA channel0 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc0_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token0_wdata:12; + /** slc0_token0_wr : WT; bitpos: [12]; default: 0; + * update slc0_token0_wdata into slc0 token0. + */ + uint32_t slc0_token0_wr:1; + /** slc0_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to slc0_token0. + */ + uint32_t slc0_token0_inc:1; + /** slc0_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN0_SLC0_TOKEN0_WDATA to + * SDIO_SLC0TOKEN0_SLC0_TOKEN0. + */ + uint32_t slc0_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token0_reg_t; + +/** Type of slc_slc0token1 register + * Sdio slave DMA channel0 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc0_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc0_token1_wdata:12; + /** slc0_token1_wr : WT; bitpos: [12]; default: 0; + * update slc0_token1_wdata into slc0 token1 + */ + uint32_t slc0_token1_wr:1; + /** slc0_token1_inc : WT; bitpos: [13]; default: 0; + * slc0_token1 becomes to 1 when auto clear slc0_token1, else add 1 to slc0_token1 + */ + uint32_t slc0_token1_inc:1; + /** slc0_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC0TOKEN1_SLC0_TOKEN1_WDATA to + * SDIO_SLC0TOKEN1_SLC0_TOKEN1. + */ + uint32_t slc0_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc0_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel0. + */ + uint32_t slc0_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc0token1_reg_t; + +/** Type of slc_slc1token0 register + * Sdio slave DMA channel1 receiving buffer configuration and status register. + */ +typedef union { + struct { + /** slc1_token0_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token0_wdata:12; + /** slc1_token0_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token0_wdata into SLC1 token0. + */ + uint32_t slc1_token0_wr:1; + /** slc1_token0_inc : WT; bitpos: [13]; default: 0; + * Add 1 to SLC1_token0. + */ + uint32_t slc1_token0_inc:1; + /** slc1_token0_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN0_SLC1_TOKEN0_WDATA to + * SDIO_SLC1TOKEN0_SLC1_TOKEN0. + */ + uint32_t slc1_token0_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token0 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token0:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token0_reg_t; + +/** Type of slc_slc1token1 register + * Sdio slave DMA channel1 receiving buffer configuration and status register1. + */ +typedef union { + struct { + /** slc1_token1_wdata : WT; bitpos: [11:0]; default: 0; + * The number of available receiving buffers. + */ + uint32_t slc1_token1_wdata:12; + /** slc1_token1_wr : WT; bitpos: [12]; default: 0; + * update SLC1_token1_wdata into SLC1 token1 + */ + uint32_t slc1_token1_wr:1; + /** slc1_token1_inc : WT; bitpos: [13]; default: 0; + * SLC1_token1 becomes to 1 when auto clear SLC1_token1, else add 1 to SLC1_token1 + */ + uint32_t slc1_token1_inc:1; + /** slc1_token1_inc_more : WT; bitpos: [14]; default: 0; + * Set this bit to add the value of SDIO_SLC1TOKEN1_SLC1_TOKEN1_WDATA to + * SDIO_SLC1TOKEN1_SLC1_TOKEN1. + */ + uint32_t slc1_token1_inc_more:1; + uint32_t reserved_15:1; + /** slc1_token1 : RO; bitpos: [27:16]; default: 0; + * The accumulated number of buffers for receiving packets through dma channel1. + */ + uint32_t slc1_token1:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_slc1token1_reg_t; + +/** Type of slc_conf1 register + * Sdio slave DMA configuration1 register. + */ +typedef union { + struct { + /** slc0_check_owner : R/W; bitpos: [0]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel0. + */ + uint32_t slc0_check_owner:1; + /** slc0_tx_check_sum_en : R/W; bitpos: [1]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel0. + */ + uint32_t slc0_tx_check_sum_en:1; + /** slc0_rx_check_sum_en : R/W; bitpos: [2]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel0. + */ + uint32_t slc0_rx_check_sum_en:1; + /** sdio_cmd_hold_en : R/W; bitpos: [3]; default: 1; + * Allow host to send another cmd53 during last cmd53 operating time. + */ + uint32_t sdio_cmd_hold_en:1; + /** slc0_len_auto_clr : R/W; bitpos: [4]; default: 1; + * Set 1 to automatically clear the length of buffers used to send packets ot host + * after host reads this length. (not recommended to use,should be set to 0) + */ + uint32_t slc0_len_auto_clr:1; + /** slc0_tx_stitch_en : R/W; bitpos: [5]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 receiving linked list . + */ + uint32_t slc0_tx_stitch_en:1; + /** slc0_rx_stitch_en : R/W; bitpos: [6]; default: 1; + * Set 1 to enable the stitch mode of dma channel0 sending linked list . + */ + uint32_t slc0_rx_stitch_en:1; + uint32_t reserved_7:9; + /** slc1_check_owner : R/W; bitpos: [16]; default: 0; + * Set 1 to check the owner bit of descriptors used by dma channel1. + */ + uint32_t slc1_check_owner:1; + /** slc1_tx_check_sum_en : R/W; bitpos: [17]; default: 0; + * Set 1 to enable check sum function during slave receiving packets through dma + * channel1. + */ + uint32_t slc1_tx_check_sum_en:1; + /** slc1_rx_check_sum_en : R/W; bitpos: [18]; default: 0; + * Set 1 to enable check sum function during slave sending packets through dma + * channel1. + */ + uint32_t slc1_rx_check_sum_en:1; + /** host_int_level_sel : R/W; bitpos: [19]; default: 0; + * Set the polarity of interrupt generated to host: 0-low active, 1-high active. + */ + uint32_t host_int_level_sel:1; + uint32_t reserved_20:2; + /** sdio_clk_en : R/W; bitpos: [22]; default: 0; + * Sdio slave dma registers' clock gating enable bit: 0-the sdio slave dma registers' + * clock is on during apb operation, 1- the sdio slave dma registers' clock is always + * on. + */ + uint32_t sdio_clk_en:1; + uint32_t reserved_23:9; + }; + uint32_t val; +} sdio_slc_conf1_reg_t; + +/** Type of slc_bridge_conf register + * Sdio slave DMA bridge configuration register. + */ +typedef union { + struct { + /** slc_txeof_ena : R/W; bitpos: [5:0]; default: 32; + * Configure the end-of-frame address of receiving packet. The priority from high to + * low is: if txeof_ena[0] is 1, end-of-frame address is 0xfff, if txeof_ena[1] is 1, + * end-of-frame address is 0x1fff, if txeof_ena[2] is 1, end-of-frame address is + * 0x3fff, if txeof_ena[3] is 1, end-of-frame address is 0x7fff, if txeof_ena[4] is 1, + * end-of-frame address is 0xffff, if txeof_ena[5] is 1, end-of-frame address is + * 0x1f7ff. Make sure the end-of-frame address is within the address range set by + * fifo_map_ena, otherwise the packet will be transferred without end-of-frame flag, + * which can cause unpredictable consequence. + */ + uint32_t slc_txeof_ena:6; + uint32_t reserved_6:2; + /** slc_fifo_map_ena : R/W; bitpos: [11:8]; default: 7; + * Configure the address range allocated to transfer packets using SDIO func1 and + * func2. The address range is from 0x400 to 0-0x3fff, 1-0x7fff, 3-0xffff, 7-0x1ffff, + * others-not allowed. + */ + uint32_t slc_fifo_map_ena:4; + /** slc0_tx_dummy_mode : R/W; bitpos: [12]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel0. + */ + uint32_t slc0_tx_dummy_mode:1; + /** slc_hda_map_128k : R/W; bitpos: [13]; default: 1; + * If hda_map_128k is 0, map high 4 bit address to hda_4msb. When hda_map_128k is 1, + * if hda_word_en (slchost_conf12[0]) is 0, map high 4 bit address to {hda_4msb[3:1], + * addr_ext_func[16]}. Else if hda_word_en is 1, map high 4 bit address to + * {hda_4msb[3:1], addr_ext_func[14]}. + */ + uint32_t slc_hda_map_128k:1; + /** slc1_tx_dummy_mode : R/W; bitpos: [14]; default: 1; + * Set 1 not to transfer check sum data into memory through dma channel1. + */ + uint32_t slc1_tx_dummy_mode:1; + uint32_t reserved_15:1; + /** slc_tx_push_idle_num : R/W; bitpos: [31:16]; default: 10; + * reserved + */ + uint32_t slc_tx_push_idle_num:16; + }; + uint32_t val; +} sdio_slc_bridge_conf_reg_t; + +/** Type of slc_slc0_to_eof_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel0. + */ + uint32_t slc0_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_des_addr_reg_t; + +/** Type of slc_slc0_tx_eof_des_addr register + * Sdio slave DMA channel0 receiving packet status register. + */ +typedef union { + struct { + /** slc0_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel0. + */ + uint32_t slc0_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_eof_des_addr_reg_t; + +/** Type of slc_slc0_to_eof_bfr_des_addr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel0. + */ + uint32_t slc0_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last sent packet through dma channel1. + */ + uint32_t slc1_to_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_des_addr_reg_t; + +/** Type of slc_slc1_tx_eof_des_addr register + * Sdio slave DMA channel1 receiving packet status register. + */ +typedef union { + struct { + /** slc1_tx_suc_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully received packet through dma + * channel1. + */ + uint32_t slc1_tx_suc_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_eof_des_addr_reg_t; + +/** Type of slc_slc1_to_eof_bfr_des_addr register + * Sdio slave DMA channel1 start address of sending linked list register. + */ +typedef union { + struct { + /** slc1_to_eof_bfr_des_addr : RO; bitpos: [31:0]; default: 0; + * The descriptor address of the last successfully sent buffer packet through dma + * channel1. + */ + uint32_t slc1_to_eof_bfr_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_to_eof_bfr_des_addr_reg_t; + +/** Type of slc_rx_dscr_conf register + * Sdio slave sending descriptor configuration register. + */ +typedef union { + struct { + /** slc0_token_no_replace : R/W; bitpos: [0]; default: 0; + * reserved + */ + uint32_t slc0_token_no_replace:1; + /** slc0_infor_no_replace : R/W; bitpos: [1]; default: 1; + * reserved + */ + uint32_t slc0_infor_no_replace:1; + /** slc0_rx_fill_mode : R/W; bitpos: [2]; default: 0; + * slc0 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc0_rx_fill_mode:1; + /** slc0_rx_eof_mode : R/W; bitpos: [3]; default: 1; + * 0-slc0 rx_push_eof, 1-slc0 rx_pop_eof + */ + uint32_t slc0_rx_eof_mode:1; + /** slc0_rx_fill_en : R/W; bitpos: [4]; default: 1; + * reserved + */ + uint32_t slc0_rx_fill_en:1; + /** slc0_rd_retry_threshold : R/W; bitpos: [15:5]; default: 128; + * reserved + */ + uint32_t slc0_rd_retry_threshold:11; + /** slc1_token_no_replace : R/W; bitpos: [16]; default: 1; + * reserved + */ + uint32_t slc1_token_no_replace:1; + /** slc1_infor_no_replace : R/W; bitpos: [17]; default: 1; + * reserved + */ + uint32_t slc1_infor_no_replace:1; + /** slc1_rx_fill_mode : R/W; bitpos: [18]; default: 0; + * slc1 rx pop end control: 0-automatically end when pop finish, 1- end when the next + * pop doesn't occur after 255 cycles since the current pop + */ + uint32_t slc1_rx_fill_mode:1; + /** slc1_rx_eof_mode : R/W; bitpos: [19]; default: 1; + * 0-slc1 rx_push_eof, 1-slc1 rx_pop_eof + */ + uint32_t slc1_rx_eof_mode:1; + /** slc1_rx_fill_en : R/W; bitpos: [20]; default: 1; + * reserved + */ + uint32_t slc1_rx_fill_en:1; + /** slc1_rd_retry_threshold : R/W; bitpos: [31:21]; default: 128; + * reserved + */ + uint32_t slc1_rd_retry_threshold:11; + }; + uint32_t val; +} sdio_slc_rx_dscr_conf_reg_t; + +/** Type of slc_tx_dscr_conf register + * reserved + */ +typedef union { + struct { + /** slc_wr_retry_threshold : R/W; bitpos: [10:0]; default: 128; + * reserved + */ + uint32_t slc_wr_retry_threshold:11; + uint32_t reserved_11:21; + }; + uint32_t val; +} sdio_slc_tx_dscr_conf_reg_t; + +/** Type of slc_slc0_len_conf register + * reserved + */ +typedef union { + struct { + /** slc0_len_wdata : WT; bitpos: [19:0]; default: 0; + * The packet length sent by dma channel0. + */ + uint32_t slc0_len_wdata:20; + /** slc0_len_wr : WT; bitpos: [20]; default: 0; + * Set this bit to set SLC0_LEN as SDIO_SLC0_LEN_WDATA. + */ + uint32_t slc0_len_wr:1; + /** slc0_len_inc : WT; bitpos: [21]; default: 0; + * Set this bit to add 1 to SLC0_LEN. + */ + uint32_t slc0_len_inc:1; + /** slc0_len_inc_more : WT; bitpos: [22]; default: 0; + * Set this bit to add the value of SDIO_SLC0_LEN_WDATA to SLC0_LEN. + */ + uint32_t slc0_len_inc_more:1; + /** slc0_rx_packet_load_en : WT; bitpos: [23]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * sending packets. + */ + uint32_t slc0_rx_packet_load_en:1; + /** slc0_tx_packet_load_en : WT; bitpos: [24]; default: 0; + * Write 1 to stitch new linked lists to current linked lists when dma channel0 + * receiving packets. + */ + uint32_t slc0_tx_packet_load_en:1; + /** slc0_rx_get_used_dscr : WT; bitpos: [25]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 sending packets. + */ + uint32_t slc0_rx_get_used_dscr:1; + /** slc0_tx_get_used_dscr : WT; bitpos: [26]; default: 0; + * Write 1 to get the current descriptor address when dma channel0 receiving packets. + */ + uint32_t slc0_tx_get_used_dscr:1; + /** slc0_rx_new_pkt_ind : RO; bitpos: [27]; default: 0; + * Represents a new packet is sent by dma channel0. + */ + uint32_t slc0_rx_new_pkt_ind:1; + /** slc0_tx_new_pkt_ind : RO; bitpos: [28]; default: 1; + * Represents a new packet is received by dma channel0. + */ + uint32_t slc0_tx_new_pkt_ind:1; + /** slc0_rx_packet_load_en_st : R/WTC/SC; bitpos: [29]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * sending packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_rx_packet_load_en_st:1; + /** slc0_tx_packet_load_en_st : R/WTC/SC; bitpos: [30]; default: 0; + * Represents whether the dma channel0 can be stitched to new linked lists when + * receiving packets. 0- allowed, 1- not allowed. + */ + uint32_t slc0_tx_packet_load_en_st:1; + uint32_t reserved_31:1; + }; + uint32_t val; +} sdio_slc_slc0_len_conf_reg_t; + +/** Type of slc_slc0_txpkt_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of receiving linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_tx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_h_dscr_reg_t; + +/** Type of slc_slc0_txpkt_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list register. + */ +typedef union { + struct { + /** slc0_tx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure end address of receiving linked list to be stitched to the current linked + * list of dma channel0. + */ + uint32_t slc0_tx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpkt_e_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_h_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the start address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_h_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_h_dscr_reg_t; + +/** Type of slc_slc0_rxpkt_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list register. + */ +typedef union { + struct { + /** slc0_rx_pkt_e_dscr_addr : R/W; bitpos: [31:0]; default: 0; + * Configure the end address of sending linked list to be stitched to the current + * linked list of dma channel0. + */ + uint32_t slc0_rx_pkt_e_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpkt_e_dscr_reg_t; + +/** Type of slc_slc0_txpktu_h_dscr register + * Sdio slave DMA channel0 start address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last received packet through dma + * channel0. + */ + uint32_t slc0_tx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_h_dscr_reg_t; + +/** Type of slc_slc0_txpktu_e_dscr register + * Sdio slave DMA channel0 end address of receiving linked list status register. + */ +typedef union { + struct { + /** slc0_tx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last received packet through dma channel0. + */ + uint32_t slc0_tx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_txpktu_e_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_h_dscr register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_h_dscr_reg_t; + +/** Type of slc_slc0_rxpktu_e_dscr register + * Sdio slave DMA channel0 end address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_pkt_end_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The end address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_rx_pkt_end_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxpktu_e_dscr_reg_t; + +/** Type of slc_seq_position register + * The position of receiving packet configuration register. + */ +typedef union { + struct { + /** slc0_seq_position : R/W; bitpos: [7:0]; default: 9; + * Configure the position of the receiving packet through dma channel0. + */ + uint32_t slc0_seq_position:8; + /** slc1_seq_position : R/W; bitpos: [15:8]; default: 5; + * Configure the position of the receiving packet through dma channel1. + */ + uint32_t slc1_seq_position:8; + uint32_t reserved_16:16; + }; + uint32_t val; +} sdio_slc_seq_position_reg_t; + +/** Type of slc_slc0_dscr_rec_conf register + * Sdio slave DMA sending linked list limit configuration register. + */ +typedef union { + struct { + /** slc0_rx_dscr_rec_lim : R/W; bitpos: [9:0]; default: 1023; + * Configure the limit number of descriptors used to send one packet through dma + * channel0 in stitch mode. + */ + uint32_t slc0_rx_dscr_rec_lim:10; + uint32_t reserved_10:22; + }; + uint32_t val; +} sdio_slc_slc0_dscr_rec_conf_reg_t; + +/** Type of slc_sdio_crc_st1 register + * Sdio slave receiving command crc status register. + */ +typedef union { + struct { + /** cmd_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received command crc errors. + */ + uint32_t cmd_crc_err_cnt:8; + uint32_t reserved_8:23; + /** err_cnt_clr : R/W; bitpos: [31]; default: 0; + * Set 1 to clear the cmd_crc_err_cnt, dat0_crc_err_cnt, dat1_crc_err_cnt, + * dat2_crc_err_cnt and dat3_crc_err_cnt. + */ + uint32_t err_cnt_clr:1; + }; + uint32_t val; +} sdio_slc_sdio_crc_st1_reg_t; + +/** Type of slc_slc0_len_lim_conf register + * Sdio slave DMA channel0 buffer limit configuration register. + */ +typedef union { + struct { + /** slc0_len_lim : R/W; bitpos: [19:0]; default: 21504; + * Every time when the number of buffers loaded for sending packets reaches the number + * of slc0_len_lim, the current number of buffers loaded is saved into the registers + * of slc0_len0, slc0_len1 and slc0_len2. + */ + uint32_t slc0_len_lim:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_len_lim_conf_reg_t; + +/** Type of slc_slc0_tx_sharemem_start register + * Sdio slave DMA channel0 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_start_reg_t; + +/** Type of slc_slc0_tx_sharemem_end register + * Sdio slave DMA channel0 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel0. + */ + uint32_t sdio_slc0_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_sharemem_end_reg_t; + +/** Type of slc_slc0_rx_sharemem_start register + * Sdio slave DMA channel0 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_start_reg_t; + +/** Type of slc_slc0_rx_sharemem_end register + * Sdio slave DMA channel0 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc0_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel0. + */ + uint32_t sdio_slc0_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_rx_sharemem_end_reg_t; + +/** Type of slc_slc1_tx_sharemem_start register + * Sdio slave DMA channel1 address range of receiving linked list register. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_start_reg_t; + +/** Type of slc_slc1_tx_sharemem_end register + * Sdio slave DMA channel1 address range of receiving linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_tx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to receive packet through dma + * channel1. + */ + uint32_t sdio_slc1_tx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_sharemem_end_reg_t; + +/** Type of slc_slc1_rx_sharemem_start register + * Sdio slave DMA channel1 address range of sending linked list register. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * The start address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_start_reg_t; + +/** Type of slc_slc1_rx_sharemem_end register + * Sdio slave DMA channel1 address range of sending linked list register1. + */ +typedef union { + struct { + /** sdio_slc1_rx_sharemem_end_addr : R/W; bitpos: [31:0]; default: 4294967295; + * The end address boundary of descriptor can be used to send packet through dma + * channel1. + */ + uint32_t sdio_slc1_rx_sharemem_end_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_rx_sharemem_end_reg_t; + +/** Type of slc_hda_tx_sharemem_start register + * Sdio slave HAD receiving address range register. + */ +typedef union { + struct { + /** sdio_hda_tx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * receiving packets. + */ + uint32_t sdio_hda_tx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_tx_sharemem_start_reg_t; + +/** Type of slc_hda_rx_sharemem_start register + * Sdio slave HAD sending address range register. + */ +typedef union { + struct { + /** sdio_hda_rx_sharemem_start_addr : R/W; bitpos: [31:0]; default: 0; + * Use 31 to 20 bit of this field as the higher 20 bits of 32-bit address for HAD + * sending packets. + */ + uint32_t sdio_hda_rx_sharemem_start_addr:32; + }; + uint32_t val; +} sdio_slc_hda_rx_sharemem_start_reg_t; + +/** Type of slc_burst_len register + * Sdio slave AHB burst type configuration register. + */ +typedef union { + struct { + /** slc0_txdata_burst_len : R/W; bitpos: [0]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_txdata_burst_len:1; + /** slc0_rxdata_burst_len : R/W; bitpos: [1]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc0_rxdata_burst_len:1; + /** slc1_txdata_burst_len : R/W; bitpos: [2]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_txdata_burst_len:1; + /** slc1_rxdata_burst_len : R/W; bitpos: [3]; default: 1; + * AHB burst type: 0-incr4,1-incr8 + */ + uint32_t slc1_rxdata_burst_len:1; + uint32_t reserved_4:28; + }; + uint32_t val; +} sdio_slc_burst_len_reg_t; + + +/** Group: Interrupt registers */ +/** Type of slc_slc0int_raw register + * Sdio slave DMA channel0 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 0 for host to interrupt slave. + */ + uint32_t slc_frhost_bit0_int_raw:1; + /** slc_frhost_bit1_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 1 for host to interrupt slave. + */ + uint32_t slc_frhost_bit1_int_raw:1; + /** slc_frhost_bit2_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 2 for host to interrupt slave. + */ + uint32_t slc_frhost_bit2_int_raw:1; + /** slc_frhost_bit3_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 3 for host to interrupt slave. + */ + uint32_t slc_frhost_bit3_int_raw:1; + /** slc_frhost_bit4_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 4 for host to interrupt slave. + */ + uint32_t slc_frhost_bit4_int_raw:1; + /** slc_frhost_bit5_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 5 for host to interrupt slave. + */ + uint32_t slc_frhost_bit5_int_raw:1; + /** slc_frhost_bit6_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 6 for host to interrupt slave. + */ + uint32_t slc_frhost_bit6_int_raw:1; + /** slc_frhost_bit7_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 7 for host to interrupt slave. + */ + uint32_t slc_frhost_bit7_int_raw:1; + /** slc0_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel0 sending initialization + */ + uint32_t slc0_rx_start_int_raw:1; + /** slc0_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel0 receiving initialization + */ + uint32_t slc0_tx_start_int_raw:1; + /** slc0_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel0 sending buffer underflow. + */ + uint32_t slc0_rx_udf_int_raw:1; + /** slc0_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel0 receiving buffer overflow. + */ + uint32_t slc0_tx_ovf_int_raw:1; + /** slc0_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc0_token0_1to0_int_raw:1; + /** slc0_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc0_token1_1to0_int_raw:1; + /** slc0_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data to one single buffer. + */ + uint32_t slc0_tx_done_int_raw:1; + /** slc0_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel0 finishing receiving data + */ + uint32_t slc0_tx_suc_eof_int_raw:1; + /** slc0_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data from one single buffer + */ + uint32_t slc0_rx_done_int_raw:1; + /** slc0_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel0 finishing sending data + */ + uint32_t slc0_rx_eof_int_raw:1; + /** slc0_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc0_tohost_int_raw:1; + /** slc0_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel0 receiving descriptor error. + */ + uint32_t slc0_tx_dscr_err_int_raw:1; + /** slc0_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel0 sending descriptor error. + */ + uint32_t slc0_rx_dscr_err_int_raw:1; + /** slc0_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel0. + */ + uint32_t slc0_tx_dscr_empty_int_raw:1; + /** slc0_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel0. + */ + uint32_t slc0_host_rd_ack_int_raw:1; + /** slc0_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel0. + */ + uint32_t slc0_wr_retry_done_int_raw:1; + /** slc0_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel0. + */ + uint32_t slc0_tx_err_eof_int_raw:1; + /** cmd_dtc_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The raw interrupt bit for sdio slave to detect command from host. + */ + uint32_t cmd_dtc_int_raw:1; + /** slc0_rx_quick_eof_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The raw interrupt for the linked list used reaches the number of + * slc0_rx_dscr_rec_lim when in stitch mode, or for every sending data transfer done. + */ + uint32_t slc0_rx_quick_eof_int_raw:1; + /** slc0_host_pop_eof_err_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The raw interrupt bit for the eof bit error of slave receiving data through dma + * channel0. + */ + uint32_t slc0_host_pop_eof_err_int_raw:1; + /** hda_recv_done_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw interrupt bit for slave finishes receiving one cmd53 function's all block + * data. + */ + uint32_t hda_recv_done_int_raw:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_raw_reg_t; + +/** Type of slc_slc0int_st register + * Sdio slave DMA channel0 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st:1; + /** slc_frhost_bit1_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st:1; + /** slc_frhost_bit2_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st:1; + /** slc_frhost_bit3_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st:1; + /** slc_frhost_bit4_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st:1; + /** slc_frhost_bit5_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st:1; + /** slc_frhost_bit6_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st:1; + /** slc_frhost_bit7_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st:1; + /** slc0_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st:1; + /** slc0_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st:1; + /** slc0_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st:1; + /** slc0_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st:1; + /** slc0_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st:1; + /** slc0_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st:1; + /** slc0_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st:1; + /** slc0_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st:1; + /** slc0_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st:1; + /** slc0_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st:1; + /** slc0_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st:1; + /** slc0_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st:1; + /** slc0_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st:1; + /** slc0_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st:1; + /** slc0_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st:1; + /** slc0_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st:1; + /** slc0_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st:1; + /** cmd_dtc_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st:1; + /** slc0_rx_quick_eof_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st:1; + /** slc0_host_pop_eof_err_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st:1; + /** hda_recv_done_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st_reg_t; + +/** Type of slc_slc0int_ena register + * Sdio slave DMA channel0 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena:1; + /** slc_frhost_bit1_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena:1; + /** slc_frhost_bit2_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena:1; + /** slc_frhost_bit3_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena:1; + /** slc_frhost_bit4_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena:1; + /** slc_frhost_bit5_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena:1; + /** slc_frhost_bit6_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena:1; + /** slc_frhost_bit7_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena:1; + /** slc0_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena:1; + /** slc0_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena:1; + /** slc0_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena:1; + /** slc0_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena:1; + /** slc0_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena:1; + /** slc0_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena:1; + /** slc0_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena:1; + /** slc0_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena:1; + /** slc0_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena:1; + /** slc0_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena:1; + /** slc0_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena:1; + /** slc0_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena:1; + /** slc0_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena:1; + /** slc0_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena:1; + /** slc0_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena:1; + /** slc0_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena:1; + /** slc0_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena:1; + /** cmd_dtc_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena:1; + /** slc0_rx_quick_eof_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena:1; + /** slc0_host_pop_eof_err_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena:1; + /** hda_recv_done_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena_reg_t; + +/** Type of slc_slc0int_clr register + * Sdio slave DMA channel0 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_clr:1; + /** slc_frhost_bit1_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_clr:1; + /** slc_frhost_bit2_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_clr:1; + /** slc_frhost_bit3_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_clr:1; + /** slc_frhost_bit4_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_clr:1; + /** slc_frhost_bit5_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_clr:1; + /** slc_frhost_bit6_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_clr:1; + /** slc_frhost_bit7_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_clr:1; + /** slc0_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_clr:1; + /** slc0_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_clr:1; + /** slc0_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_clr:1; + /** slc0_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_clr:1; + /** slc0_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_clr:1; + /** slc0_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_clr:1; + /** slc0_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_clr:1; + /** slc0_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_clr:1; + /** slc0_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_clr:1; + /** slc0_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_clr:1; + /** slc0_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_clr:1; + /** slc0_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_clr:1; + /** slc0_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_clr:1; + /** slc0_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_clr:1; + /** slc0_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_clr:1; + /** slc0_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_clr:1; + /** slc0_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_clr:1; + /** cmd_dtc_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_clr:1; + /** slc0_rx_quick_eof_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_clr:1; + /** slc0_host_pop_eof_err_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_clr:1; + /** hda_recv_done_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_clr:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_clr_reg_t; + +/** Type of slc_slc1int_raw register + * Sdio slave DMA channel1 raw interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit 8 for host to interrupt slave. + */ + uint32_t slc_frhost_bit8_int_raw:1; + /** slc_frhost_bit9_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit 9 for host to interrupt slave. + */ + uint32_t slc_frhost_bit9_int_raw:1; + /** slc_frhost_bit10_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit 10 for host to interrupt slave. + */ + uint32_t slc_frhost_bit10_int_raw:1; + /** slc_frhost_bit11_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit 11 for host to interrupt slave. + */ + uint32_t slc_frhost_bit11_int_raw:1; + /** slc_frhost_bit12_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit 12 for host to interrupt slave. + */ + uint32_t slc_frhost_bit12_int_raw:1; + /** slc_frhost_bit13_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit 13 for host to interrupt slave. + */ + uint32_t slc_frhost_bit13_int_raw:1; + /** slc_frhost_bit14_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit 14 for host to interrupt slave. + */ + uint32_t slc_frhost_bit14_int_raw:1; + /** slc_frhost_bit15_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit 15 for host to interrupt slave. + */ + uint32_t slc_frhost_bit15_int_raw:1; + /** slc1_rx_start_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit of registering dma channel1 sending initialization + */ + uint32_t slc1_rx_start_int_raw:1; + /** slc1_tx_start_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw interrupt bit of registering dma channel1 receiving initialization + */ + uint32_t slc1_tx_start_int_raw:1; + /** slc1_rx_udf_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The raw interrupt bit of dma channel1 sending buffer underflow. + */ + uint32_t slc1_rx_udf_int_raw:1; + /** slc1_tx_ovf_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The raw interrupt bit of dma channel1 receiving buffer overflow. + */ + uint32_t slc1_tx_ovf_int_raw:1; + /** slc1_token0_1to0_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The raw interrupt bit for the value of slc0_token0 becoming to zero. + */ + uint32_t slc1_token0_1to0_int_raw:1; + /** slc1_token1_1to0_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The raw interrupt bit for the value of slc0_token1 becoming to zero. + */ + uint32_t slc1_token1_1to0_int_raw:1; + /** slc1_tx_done_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data to one single buffer. + */ + uint32_t slc1_tx_done_int_raw:1; + /** slc1_tx_suc_eof_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The raw interrupt bit of dma channel1 finishing receiving data + */ + uint32_t slc1_tx_suc_eof_int_raw:1; + /** slc1_rx_done_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data from one single buffer + */ + uint32_t slc1_rx_done_int_raw:1; + /** slc1_rx_eof_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The raw interrupt bit of dma channel1 finishing sending data + */ + uint32_t slc1_rx_eof_int_raw:1; + /** slc1_tohost_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The raw interrupt bit for slave generating interrupt to host. + */ + uint32_t slc1_tohost_int_raw:1; + /** slc1_tx_dscr_err_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The raw interrupt bit of dma channel1 receiving descriptor error. + */ + uint32_t slc1_tx_dscr_err_int_raw:1; + /** slc1_rx_dscr_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The raw interrupt bit of dma channel1 sending descriptor error. + */ + uint32_t slc1_rx_dscr_err_int_raw:1; + /** slc1_tx_dscr_empty_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The raw interrupt bit of not enough buffer for slave receiving data from host + * through dma channel1. + */ + uint32_t slc1_tx_dscr_empty_int_raw:1; + /** slc1_host_rd_ack_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The raw interrupt bit for host to acknowledge retrying receiving data from slave + * successfully through dma channel1. + */ + uint32_t slc1_host_rd_ack_int_raw:1; + /** slc1_wr_retry_done_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The raw interrupt bit of host finishing retrying sending data to slave through dma + * channel1. + */ + uint32_t slc1_wr_retry_done_int_raw:1; + /** slc1_tx_err_eof_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The raw interrupt bit of data error during host sending data to slave through dma + * channel1. + */ + uint32_t slc1_tx_err_eof_int_raw:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_raw_reg_t; + +/** Type of slc_slc1int_st register + * Sdio slave DMA channel1 masked interrupt status register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st:1; + /** slc_frhost_bit9_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st:1; + /** slc_frhost_bit10_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st:1; + /** slc_frhost_bit11_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st:1; + /** slc_frhost_bit12_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st:1; + /** slc_frhost_bit13_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st:1; + /** slc_frhost_bit14_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st:1; + /** slc_frhost_bit15_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st:1; + /** slc1_rx_start_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st:1; + /** slc1_tx_start_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st:1; + /** slc1_rx_udf_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st:1; + /** slc1_tx_ovf_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st:1; + /** slc1_token0_1to0_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st:1; + /** slc1_token1_1to0_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st:1; + /** slc1_tx_done_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st:1; + /** slc1_tx_suc_eof_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st:1; + /** slc1_rx_done_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st:1; + /** slc1_rx_eof_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st:1; + /** slc1_tohost_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st:1; + /** slc1_tx_dscr_err_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st:1; + /** slc1_rx_dscr_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st:1; + /** slc1_tx_dscr_empty_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st:1; + /** slc1_host_rd_ack_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st:1; + /** slc1_wr_retry_done_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st:1; + /** slc1_tx_err_eof_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st_reg_t; + +/** Type of slc_slc1int_ena register + * Sdio slave DMA channel1 interrupt enable register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena:1; + /** slc_frhost_bit9_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena:1; + /** slc_frhost_bit10_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena:1; + /** slc_frhost_bit11_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena:1; + /** slc_frhost_bit12_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena:1; + /** slc_frhost_bit13_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena:1; + /** slc_frhost_bit14_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena:1; + /** slc_frhost_bit15_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena:1; + /** slc1_rx_start_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena:1; + /** slc1_tx_start_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena:1; + /** slc1_rx_udf_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena:1; + /** slc1_tx_ovf_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena:1; + /** slc1_token0_1to0_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena:1; + /** slc1_token1_1to0_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena:1; + /** slc1_tx_done_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena:1; + /** slc1_tx_suc_eof_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena:1; + /** slc1_rx_done_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena:1; + /** slc1_rx_eof_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena:1; + /** slc1_tohost_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena:1; + /** slc1_tx_dscr_err_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena:1; + /** slc1_rx_dscr_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena:1; + /** slc1_tx_dscr_empty_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena:1; + /** slc1_host_rd_ack_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena:1; + /** slc1_wr_retry_done_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena:1; + /** slc1_tx_err_eof_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena_reg_t; + +/** Type of slc_slc1int_clr register + * Sdio slave DMA channel1 interrupt clear register. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT0_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_clr:1; + /** slc_frhost_bit9_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT1_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_clr:1; + /** slc_frhost_bit10_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT2_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_clr:1; + /** slc_frhost_bit11_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT3_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_clr:1; + /** slc_frhost_bit12_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT4_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_clr:1; + /** slc_frhost_bit13_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT5_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_clr:1; + /** slc_frhost_bit14_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT6_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_clr:1; + /** slc_frhost_bit15_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear SLC_FRHOST_BIT7_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_clr:1; + /** slc1_rx_start_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_clr:1; + /** slc1_tx_start_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_clr:1; + /** slc1_rx_udf_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_clr:1; + /** slc1_tx_ovf_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_clr:1; + /** slc1_token0_1to0_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_clr:1; + /** slc1_token1_1to0_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_clr:1; + /** slc1_tx_done_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_clr:1; + /** slc1_tx_suc_eof_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_clr:1; + /** slc1_rx_done_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_clr:1; + /** slc1_rx_eof_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_clr:1; + /** slc1_tohost_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_clr:1; + /** slc1_tx_dscr_err_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_clr:1; + /** slc1_rx_dscr_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_clr:1; + /** slc1_tx_dscr_empty_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_clr:1; + /** slc1_host_rd_ack_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_clr:1; + /** slc1_wr_retry_done_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_clr:1; + /** slc1_tx_err_eof_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_clr:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_clr_reg_t; + +/** Type of slc_slc0int_st1 register + * Sdio slave DMA channel0 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_st1:1; + /** slc_frhost_bit1_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_st1:1; + /** slc_frhost_bit2_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_st1:1; + /** slc_frhost_bit3_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_st1:1; + /** slc_frhost_bit4_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_st1:1; + /** slc_frhost_bit5_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_st1:1; + /** slc_frhost_bit6_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_st1:1; + /** slc_frhost_bit7_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_st1:1; + /** slc0_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_st1:1; + /** slc0_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_st1:1; + /** slc0_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_st1:1; + /** slc0_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_st1:1; + /** slc0_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_st1:1; + /** slc0_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_st1:1; + /** slc0_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_st1:1; + /** slc0_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_st1:1; + /** slc0_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_st1:1; + /** slc0_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_st1:1; + /** slc0_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_st1:1; + /** slc0_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_st1:1; + /** slc0_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_st1:1; + /** slc0_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_st1:1; + /** slc0_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_st1:1; + /** slc0_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_st1:1; + /** slc0_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_st1:1; + /** cmd_dtc_int_st1 : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_st1:1; + /** slc0_rx_quick_eof_int_st1 : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_st1:1; + /** slc0_host_pop_eof_err_int_st1 : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_st1:1; + /** hda_recv_done_int_st1 : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_st1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_st1_reg_t; + +/** Type of slc_slc0int_ena1 register + * Sdio slave DMA channel0 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit0_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit0_int_ena1:1; + /** slc_frhost_bit1_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit1_int_ena1:1; + /** slc_frhost_bit2_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit2_int_ena1:1; + /** slc_frhost_bit3_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit3_int_ena1:1; + /** slc_frhost_bit4_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit4_int_ena1:1; + /** slc_frhost_bit5_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit5_int_ena1:1; + /** slc_frhost_bit6_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit6_int_ena1:1; + /** slc_frhost_bit7_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit7_int_ena1:1; + /** slc0_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SLC0_RX_START_INT_ST interrupt. + */ + uint32_t slc0_rx_start_int_ena1:1; + /** slc0_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SLC0_TX_START_INT_ST interrupt. + */ + uint32_t slc0_tx_start_int_ena1:1; + /** slc0_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SLC0_RX_UDF_INT interrupt. + */ + uint32_t slc0_rx_udf_int_ena1:1; + /** slc0_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SLC0_TX_OVF_INT interrupt. + */ + uint32_t slc0_tx_ovf_int_ena1:1; + /** slc0_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc0_token0_1to0_int_ena1:1; + /** slc0_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SLC0_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc0_token1_1to0_int_ena1:1; + /** slc0_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DONE_INT_ST interrupt. + */ + uint32_t slc0_tx_done_int_ena1:1; + /** slc0_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SLC0_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc0_tx_suc_eof_int_ena1:1; + /** slc0_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DONE_INT interrupt. + */ + uint32_t slc0_rx_done_int_ena1:1; + /** slc0_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SLC0_RX_EOF_INT interrupt. + */ + uint32_t slc0_rx_eof_int_ena1:1; + /** slc0_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SLC0_TOHOST_INT interrupt. + */ + uint32_t slc0_tohost_int_ena1:1; + /** slc0_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_tx_dscr_err_int_ena1:1; + /** slc0_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SLC0_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc0_rx_dscr_err_int_ena1:1; + /** slc0_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SLC0_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc0_tx_dscr_empty_int_ena1:1; + /** slc0_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc0_host_rd_ack_int_ena1:1; + /** slc0_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SLC0_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc0_wr_retry_done_int_ena1:1; + /** slc0_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SLC0_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc0_tx_err_eof_int_ena1:1; + /** cmd_dtc_int_ena1 : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit1 for CMD_DTC_INT interrupt. + */ + uint32_t cmd_dtc_int_ena1:1; + /** slc0_rx_quick_eof_int_ena1 : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit1 for SLC0_RX_QUICK_EOF_INT interrupt. + */ + uint32_t slc0_rx_quick_eof_int_ena1:1; + /** slc0_host_pop_eof_err_int_ena1 : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit1 for SLC0_HOST_POP_EOF_ERR_INT interrupt. + */ + uint32_t slc0_host_pop_eof_err_int_ena1:1; + /** hda_recv_done_int_ena1 : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit1 for HDA_RECV_DONE_INT interrupt. + */ + uint32_t hda_recv_done_int_ena1:1; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_slc0int_ena1_reg_t; + +/** Type of slc_slc1int_st1 register + * Sdio slave DMA channel1 masked interrupt status register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_st1 : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_st1:1; + /** slc_frhost_bit9_int_st1 : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_st1:1; + /** slc_frhost_bit10_int_st1 : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_st1:1; + /** slc_frhost_bit11_int_st1 : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_st1:1; + /** slc_frhost_bit12_int_st1 : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_st1:1; + /** slc_frhost_bit13_int_st1 : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_st1:1; + /** slc_frhost_bit14_int_st1 : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_st1:1; + /** slc_frhost_bit15_int_st1 : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_st1:1; + /** slc1_rx_start_int_st1 : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_st1:1; + /** slc1_tx_start_int_st1 : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_st1:1; + /** slc1_rx_udf_int_st1 : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_st1:1; + /** slc1_tx_ovf_int_st1 : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_st1:1; + /** slc1_token0_1to0_int_st1 : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_st1:1; + /** slc1_token1_1to0_int_st1 : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit1 for SLC1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_st1:1; + /** slc1_tx_done_int_st1 : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_st1:1; + /** slc1_tx_suc_eof_int_st1 : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_st1:1; + /** slc1_rx_done_int_st1 : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_st1:1; + /** slc1_rx_eof_int_st1 : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_st1:1; + /** slc1_tohost_int_st1 : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit1 for SLC1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_st1:1; + /** slc1_tx_dscr_err_int_st1 : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_st1:1; + /** slc1_rx_dscr_err_int_st1 : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit1 for SLC1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_st1:1; + /** slc1_tx_dscr_empty_int_st1 : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_st1:1; + /** slc1_host_rd_ack_int_st1 : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit1 for SLC1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_st1:1; + /** slc1_wr_retry_done_int_st1 : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit1 for SLC1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_st1:1; + /** slc1_tx_err_eof_int_st1 : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit1 for SLC1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_st1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_st1_reg_t; + +/** Type of slc_slc1int_ena1 register + * Sdio slave DMA channel1 interrupt enable register1. + */ +typedef union { + struct { + /** slc_frhost_bit8_int_ena1 : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit10_INT interrupt. + */ + uint32_t slc_frhost_bit8_int_ena1:1; + /** slc_frhost_bit9_int_ena1 : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit11_INT interrupt. + */ + uint32_t slc_frhost_bit9_int_ena1:1; + /** slc_frhost_bit10_int_ena1 : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit12_INT interrupt. + */ + uint32_t slc_frhost_bit10_int_ena1:1; + /** slc_frhost_bit11_int_ena1 : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit13_INT interrupt. + */ + uint32_t slc_frhost_bit11_int_ena1:1; + /** slc_frhost_bit12_int_ena1 : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit14_INT interrupt. + */ + uint32_t slc_frhost_bit12_int_ena1:1; + /** slc_frhost_bit13_int_ena1 : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit15_INT interrupt. + */ + uint32_t slc_frhost_bit13_int_ena1:1; + /** slc_frhost_bit14_int_ena1 : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit16_INT interrupt. + */ + uint32_t slc_frhost_bit14_int_ena1:1; + /** slc_frhost_bit15_int_ena1 : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit1 for SLC_FRHOST_bit17_INT interrupt. + */ + uint32_t slc_frhost_bit15_int_ena1:1; + /** slc1_rx_start_int_ena1 : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit1 for SCL1_RX_START_INT_ST interrupt. + */ + uint32_t slc1_rx_start_int_ena1:1; + /** slc1_tx_start_int_ena1 : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit1 for SCL1_TX_START_INT_ST interrupt. + */ + uint32_t slc1_tx_start_int_ena1:1; + /** slc1_rx_udf_int_ena1 : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit1 for SCL1_RX_UDF_INT interrupt. + */ + uint32_t slc1_rx_udf_int_ena1:1; + /** slc1_tx_ovf_int_ena1 : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit1 for SCL1_TX_OVF_INT interrupt. + */ + uint32_t slc1_tx_ovf_int_ena1:1; + /** slc1_token0_1to0_int_ena1 : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN0_1TO0_INT interrupt. + */ + uint32_t slc1_token0_1to0_int_ena1:1; + /** slc1_token1_1to0_int_ena1 : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit1 for SCL1_TOKEN1_1TO0_INT interrupt. + */ + uint32_t slc1_token1_1to0_int_ena1:1; + /** slc1_tx_done_int_ena1 : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DONE_INT_ST interrupt. + */ + uint32_t slc1_tx_done_int_ena1:1; + /** slc1_tx_suc_eof_int_ena1 : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit1 for SCL1_TX_SUC_EOF_INT interrupt. + */ + uint32_t slc1_tx_suc_eof_int_ena1:1; + /** slc1_rx_done_int_ena1 : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DONE_INT interrupt. + */ + uint32_t slc1_rx_done_int_ena1:1; + /** slc1_rx_eof_int_ena1 : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit1 for SCL1_RX_EOF_INT interrupt. + */ + uint32_t slc1_rx_eof_int_ena1:1; + /** slc1_tohost_int_ena1 : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit1 for SCL1_TOHOST_INT interrupt. + */ + uint32_t slc1_tohost_int_ena1:1; + /** slc1_tx_dscr_err_int_ena1 : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_tx_dscr_err_int_ena1:1; + /** slc1_rx_dscr_err_int_ena1 : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit1 for SCL1_RX_DSCR_ERR_INT interrupt. + */ + uint32_t slc1_rx_dscr_err_int_ena1:1; + /** slc1_tx_dscr_empty_int_ena1 : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit1 for SCL1_TX_DSCR_EMPTY_INT interrupt. + */ + uint32_t slc1_tx_dscr_empty_int_ena1:1; + /** slc1_host_rd_ack_int_ena1 : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit1 for SCL1_HOST_RD_ACK_INT interrupt. + */ + uint32_t slc1_host_rd_ack_int_ena1:1; + /** slc1_wr_retry_done_int_ena1 : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit1 for SCL1_WR_RETRY_DONE_INT interrupt. + */ + uint32_t slc1_wr_retry_done_int_ena1:1; + /** slc1_tx_err_eof_int_ena1 : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit1 for SCL1_TX_ERR_EOF_INT interrupt. + */ + uint32_t slc1_tx_err_eof_int_ena1:1; + uint32_t reserved_25:7; + }; + uint32_t val; +} sdio_slc_slc1int_ena1_reg_t; + + +/** Group: Status registers */ +/** Type of slc_rx_status register + * Sdio slave DMA rxfifo status register. + */ +typedef union { + struct { + /** slc0_rx_full : RO; bitpos: [0]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_full:1; + /** slc0_rx_empty : RO; bitpos: [1]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel0. + */ + uint32_t slc0_rx_empty:1; + /** slc0_rx_buf_len : RO; bitpos: [15:2]; default: 0; + * the current buffer length during slave sending data to host through dma channel0. + */ + uint32_t slc0_rx_buf_len:14; + /** slc1_rx_full : RO; bitpos: [16]; default: 0; + * The status bit for rxfifo full during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_full:1; + /** slc1_rx_empty : RO; bitpos: [17]; default: 1; + * The status bit for rxfifo empty during slave sending data to host through dma + * channel1. + */ + uint32_t slc1_rx_empty:1; + /** slc1_rx_buf_len : RO; bitpos: [31:18]; default: 0; + * the current buffer length during slave sending data to host through dma channel1. + */ + uint32_t slc1_rx_buf_len:14; + }; + uint32_t val; +} sdio_slc_rx_status_reg_t; + +/** Type of slc_tx_status register + * Sdio slave DMA txfifo status register. + */ +typedef union { + struct { + /** slc0_tx_full : RO; bitpos: [0]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_full:1; + /** slc0_tx_empty : RO; bitpos: [1]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel0. + */ + uint32_t slc0_tx_empty:1; + uint32_t reserved_2:14; + /** slc1_tx_full : RO; bitpos: [16]; default: 0; + * The status bit for txfifo full during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_full:1; + /** slc1_tx_empty : RO; bitpos: [17]; default: 1; + * The status bit for txfifo empty during slave receiving data from host through dma + * channel1. + */ + uint32_t slc1_tx_empty:1; + uint32_t reserved_18:14; + }; + uint32_t val; +} sdio_slc_tx_status_reg_t; + +/** Type of slc_slc0_state0 register + * Sdio slave DMA channel0 status register. + */ +typedef union { + struct { + /** slc0_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc0_state0:32; + }; + uint32_t val; +} sdio_slc_slc0_state0_reg_t; + +/** Type of slc_slc0_state1 register + * Sdio slave DMA channel0 status1 register. + */ +typedef union { + struct { + /** slc0_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc0_state1:32; + }; + uint32_t val; +} sdio_slc_slc0_state1_reg_t; + +/** Type of slc_slc1_state0 register + * Sdio slave DMA channel1 status register. + */ +typedef union { + struct { + /** slc1_state0 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current receiving descriptor address, [20:19] receiving descriptor fsm + * state, [23:21] receiving fsm state, [30:24] the count value of data received in + * txfifo + */ + uint32_t slc1_state0:32; + }; + uint32_t val; +} sdio_slc_slc1_state0_reg_t; + +/** Type of slc_slc1_state1 register + * Sdio slave DMA channel1 status1 register. + */ +typedef union { + struct { + /** slc1_state1 : RO; bitpos: [31:0]; default: 0; + * [18:0] the current sending descriptor address, [20:19] sending descriptor fsm + * state, [23:21] sending fsm state, [30:24] the count value of data to be sent in + * rxfifo + */ + uint32_t slc1_state1:32; + }; + uint32_t val; +} sdio_slc_slc1_state1_reg_t; + +/** Type of slc_sdio_st register + * Sdio slave function status register. + */ +typedef union { + struct { + /** cmd_st : RO; bitpos: [2:0]; default: 0; + * The sdio command fsm state. + */ + uint32_t cmd_st:3; + uint32_t reserved_3:1; + /** func_st : RO; bitpos: [7:4]; default: 0; + * The sdio cmd52/53 function fsm state. + */ + uint32_t func_st:4; + /** sdio_wakeup : RO; bitpos: [8]; default: 0; + * reserved + */ + uint32_t sdio_wakeup:1; + uint32_t reserved_9:3; + /** bus_st : RO; bitpos: [14:12]; default: 0; + * The sdio bus fsm state. + */ + uint32_t bus_st:3; + uint32_t reserved_15:1; + /** func1_acc_state : RO; bitpos: [20:16]; default: 0; + * The sdio func1 fsm state. + */ + uint32_t func1_acc_state:5; + uint32_t reserved_21:3; + /** func2_acc_state : RO; bitpos: [28:24]; default: 0; + * The sdio func2 fsm state. + */ + uint32_t func2_acc_state:5; + uint32_t reserved_29:3; + }; + uint32_t val; +} sdio_slc_sdio_st_reg_t; + +/** Type of slc_slc0_txlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc0 link descriptor, or known as the next descriptor address + */ + uint32_t slc0_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc0_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc0_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc0_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_txlink_dscr register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf0 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_txlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_txlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_txlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_txlink_dscr_bf1_reg_t; + +/** Type of slc_slc1_rxlink_dscr register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr : RO; bitpos: [31:0]; default: 0; + * the third word of slc1 link descriptor, or known as the next descriptor address + */ + uint32_t slc1_rxlink_dscr:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf0 register + * ******* Description *********** + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf0:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf0_reg_t; + +/** Type of slc_slc1_rxlink_dscr_bf1 register + * reserved + */ +typedef union { + struct { + /** slc1_rxlink_dscr_bf1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_rxlink_dscr_bf1:32; + }; + uint32_t val; +} sdio_slc_slc1_rxlink_dscr_bf1_reg_t; + +/** Type of slc_slc0_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc0_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc0_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_tx_erreof_des_addr_reg_t; + +/** Type of slc_slc1_tx_erreof_des_addr register + * reserved + */ +typedef union { + struct { + /** slc1_tx_err_eof_des_addr : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t slc1_tx_err_eof_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc1_tx_erreof_des_addr_reg_t; + +/** Type of slc_token_lat register + * reserved + */ +typedef union { + struct { + /** slc0_token : RO; bitpos: [11:0]; default: 0; + * reserved + */ + uint32_t slc0_token:12; + uint32_t reserved_12:4; + /** slc1_token : RO; bitpos: [27:16]; default: 0; + * reserved + */ + uint32_t slc1_token:12; + uint32_t reserved_28:4; + }; + uint32_t val; +} sdio_slc_token_lat_reg_t; + +/** Type of slc_cmd_infor0 register + * reserved + */ +typedef union { + struct { + /** cmd_content0 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content0:32; + }; + uint32_t val; +} sdio_slc_cmd_infor0_reg_t; + +/** Type of slc_cmd_infor1 register + * reserved + */ +typedef union { + struct { + /** cmd_content1 : RO; bitpos: [31:0]; default: 0; + * reserved + */ + uint32_t cmd_content1:32; + }; + uint32_t val; +} sdio_slc_cmd_infor1_reg_t; + +/** Type of slc_slc0_length register + * reserved + */ +typedef union { + struct { + /** slc0_len : RO; bitpos: [19:0]; default: 0; + * Indicates the paclet length sent by the slave through dma channel0. + */ + uint32_t slc0_len:20; + uint32_t reserved_20:12; + }; + uint32_t val; +} sdio_slc_slc0_length_reg_t; + +/** Type of slc_sdio_crc_st0 register + * Sdio slave receiving packet data crc status register. + */ +typedef union { + struct { + /** dat0_crc_err_cnt : RO; bitpos: [7:0]; default: 0; + * The count value of received packet data crc errors on sd_data0 line. + */ + uint32_t dat0_crc_err_cnt:8; + /** dat1_crc_err_cnt : RO; bitpos: [15:8]; default: 0; + * The count value of received packet data crc errors on sd_data1 line. + */ + uint32_t dat1_crc_err_cnt:8; + /** dat2_crc_err_cnt : RO; bitpos: [23:16]; default: 0; + * The count value of received packet data crc errors on sd_data2 line. + */ + uint32_t dat2_crc_err_cnt:8; + /** dat3_crc_err_cnt : RO; bitpos: [31:24]; default: 0; + * The count value of received packet data crc errors on sd_data3 line. + */ + uint32_t dat3_crc_err_cnt:8; + }; + uint32_t val; +} sdio_slc_sdio_crc_st0_reg_t; + +/** Type of slc_slc0_eof_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_eof_start_des_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_eof_start_des_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_eof_start_des_reg_t; + +/** Type of slc_slc0_push_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_rx_push_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 gets a link descriptor, aligned with word + */ + uint32_t slc0_rx_push_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_push_dscr_addr_reg_t; + +/** Type of slc_slc0_done_dscr_addr register + * Sdio slave DMA channel0 address of sending linked list status register1. + */ +typedef union { + struct { + /** slc0_rx_done_dscr_addr : RO; bitpos: [31:0]; default: 0; + * the current descriptor address when slc0 finishes reading data from one buffer, + * aligned with word + */ + uint32_t slc0_rx_done_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_done_dscr_addr_reg_t; + +/** Type of slc_slc0_sub_start_des register + * Sdio slave DMA channel0 start address of sending linked list status register. + */ +typedef union { + struct { + /** slc0_sub_pac_start_dscr_addr : RO; bitpos: [31:0]; default: 0; + * The start address of the linked list of the last sent packet through dma channel0. + */ + uint32_t slc0_sub_pac_start_dscr_addr:32; + }; + uint32_t val; +} sdio_slc_slc0_sub_start_des_reg_t; + +/** Type of slc_slc0_dscr_cnt register + * Sdio slave DMA channel0 descriptor status register. + */ +typedef union { + struct { + /** slc0_rx_dscr_cnt_lat : RO; bitpos: [9:0]; default: 0; + * The number of descriptors got by dma channel0 for sending packets. + */ + uint32_t slc0_rx_dscr_cnt_lat:10; + uint32_t reserved_10:6; + /** slc0_rx_get_eof_occ : RO; bitpos: [16]; default: 0; + * The status of last packet finishing sending to host. + */ + uint32_t slc0_rx_get_eof_occ:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0_dscr_cnt_reg_t; + + +/** Group: Debud registers */ +/** Type of slc_slc0txfifo_pop register + * Sdio slave DMA channel0 txfifo debug register. + */ +typedef union { + struct { + /** slc0_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc0_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc0_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc0_txfifo through APB bus successfully. + */ + uint32_t slc0_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc0txfifo_pop_reg_t; + +/** Type of slc_slc1txfifo_pop register + * Sdio slave DMA channel1 txfifo debug register. + */ +typedef union { + struct { + /** slc1_txfifo_rdata : RO; bitpos: [10:0]; default: 1024; + * This field saves the data read from txfifo through APB bus. + */ + uint32_t slc1_txfifo_rdata:11; + uint32_t reserved_11:5; + /** slc1_txfifo_pop : R/W/SC; bitpos: [16]; default: 0; + * Set this bit to read data from txfifo through APB bus. This bit is cleared + * automatically after reading one data from slc1_txfifo through APB bus successfully. + */ + uint32_t slc1_txfifo_pop:1; + uint32_t reserved_17:15; + }; + uint32_t val; +} sdio_slc_slc1txfifo_pop_reg_t; + +/** Type of slc_ahb_test register + * Sdio slave AHB test register. + */ +typedef union { + struct { + /** slc_ahb_testmode : R/W; bitpos: [2:0]; default: 0; + * set bit2 to 1 to enable sdio slave ahb test. + */ + uint32_t slc_ahb_testmode:3; + uint32_t reserved_3:1; + /** slc_ahb_testaddr : R/W; bitpos: [5:4]; default: 0; + * Configure AHB test address. + */ + uint32_t slc_ahb_testaddr:2; + uint32_t reserved_6:26; + }; + uint32_t val; +} sdio_slc_ahb_test_reg_t; + + +/** Group: Version registers */ +/** Type of slc_date register + * Sdio slave DMA version register. + */ +typedef union { + struct { + /** slc_date : R/W; bitpos: [31:0]; default: 554182400; + * Sdio slave DMA version register. + */ + uint32_t slc_date:32; + }; + uint32_t val; +} sdio_slc_date_reg_t; + +/** Type of slc_id register + * Sdio slave ID register. + */ +typedef union { + struct { + /** slc_id : R/W; bitpos: [31:0]; default: 256; + * reserved + */ + uint32_t slc_id:32; + }; + uint32_t val; +} sdio_slc_id_reg_t; + + +typedef struct { + volatile sdio_slc_conf0_reg_t slc_conf0; + volatile sdio_slc_slc0int_raw_reg_t slc_slc0int_raw; + volatile sdio_slc_slc0int_st_reg_t slc_slc0int_st; + volatile sdio_slc_slc0int_ena_reg_t slc_slc0int_ena; + volatile sdio_slc_slc0int_clr_reg_t slc_slc0int_clr; + volatile sdio_slc_slc1int_raw_reg_t slc_slc1int_raw; + volatile sdio_slc_slc1int_st_reg_t slc_slc1int_st; + volatile sdio_slc_slc1int_ena_reg_t slc_slc1int_ena; + volatile sdio_slc_slc1int_clr_reg_t slc_slc1int_clr; + volatile sdio_slc_rx_status_reg_t slc_rx_status; + volatile sdio_slc_slc0rxfifo_push_reg_t slc_slc0rxfifo_push; + volatile sdio_slc_slc1rxfifo_push_reg_t slc_slc1rxfifo_push; + volatile sdio_slc_tx_status_reg_t slc_tx_status; + volatile sdio_slc_slc0txfifo_pop_reg_t slc_slc0txfifo_pop; + volatile sdio_slc_slc1txfifo_pop_reg_t slc_slc1txfifo_pop; + volatile sdio_slc_slc0rx_link_reg_t slc_slc0rx_link; + volatile sdio_slc_slc0rx_link_addr_reg_t slc_slc0rx_link_addr; + volatile sdio_slc_slc0tx_link_reg_t slc_slc0tx_link; + volatile sdio_slc_slc0tx_link_addr_reg_t slc_slc0tx_link_addr; + volatile sdio_slc_slc1rx_link_reg_t slc_slc1rx_link; + volatile sdio_slc_slc1rx_link_addr_reg_t slc_slc1rx_link_addr; + volatile sdio_slc_slc1tx_link_reg_t slc_slc1tx_link; + volatile sdio_slc_slc1tx_link_addr_reg_t slc_slc1tx_link_addr; + volatile sdio_slc_slcintvec_tohost_reg_t slc_slcintvec_tohost; + volatile sdio_slc_slc0token0_reg_t slc_slc0token0; + volatile sdio_slc_slc0token1_reg_t slc_slc0token1; + volatile sdio_slc_slc1token0_reg_t slc_slc1token0; + volatile sdio_slc_slc1token1_reg_t slc_slc1token1; + volatile sdio_slc_conf1_reg_t slc_conf1; + volatile sdio_slc_slc0_state0_reg_t slc_slc0_state0; + volatile sdio_slc_slc0_state1_reg_t slc_slc0_state1; + volatile sdio_slc_slc1_state0_reg_t slc_slc1_state0; + volatile sdio_slc_slc1_state1_reg_t slc_slc1_state1; + volatile sdio_slc_bridge_conf_reg_t slc_bridge_conf; + volatile sdio_slc_slc0_to_eof_des_addr_reg_t slc_slc0_to_eof_des_addr; + volatile sdio_slc_slc0_tx_eof_des_addr_reg_t slc_slc0_tx_eof_des_addr; + volatile sdio_slc_slc0_to_eof_bfr_des_addr_reg_t slc_slc0_to_eof_bfr_des_addr; + volatile sdio_slc_slc1_to_eof_des_addr_reg_t slc_slc1_to_eof_des_addr; + volatile sdio_slc_slc1_tx_eof_des_addr_reg_t slc_slc1_tx_eof_des_addr; + volatile sdio_slc_slc1_to_eof_bfr_des_addr_reg_t slc_slc1_to_eof_bfr_des_addr; + volatile sdio_slc_ahb_test_reg_t slc_ahb_test; + volatile sdio_slc_sdio_st_reg_t slc_sdio_st; + volatile sdio_slc_rx_dscr_conf_reg_t slc_rx_dscr_conf; + volatile sdio_slc_slc0_txlink_dscr_reg_t slc_slc0_txlink_dscr; + volatile sdio_slc_slc0_txlink_dscr_bf0_reg_t slc_slc0_txlink_dscr_bf0; + volatile sdio_slc_slc0_txlink_dscr_bf1_reg_t slc_slc0_txlink_dscr_bf1; + volatile sdio_slc_slc0_rxlink_dscr_reg_t slc_slc0_rxlink_dscr; + volatile sdio_slc_slc0_rxlink_dscr_bf0_reg_t slc_slc0_rxlink_dscr_bf0; + volatile sdio_slc_slc0_rxlink_dscr_bf1_reg_t slc_slc0_rxlink_dscr_bf1; + volatile sdio_slc_slc1_txlink_dscr_reg_t slc_slc1_txlink_dscr; + volatile sdio_slc_slc1_txlink_dscr_bf0_reg_t slc_slc1_txlink_dscr_bf0; + volatile sdio_slc_slc1_txlink_dscr_bf1_reg_t slc_slc1_txlink_dscr_bf1; + volatile sdio_slc_slc1_rxlink_dscr_reg_t slc_slc1_rxlink_dscr; + volatile sdio_slc_slc1_rxlink_dscr_bf0_reg_t slc_slc1_rxlink_dscr_bf0; + volatile sdio_slc_slc1_rxlink_dscr_bf1_reg_t slc_slc1_rxlink_dscr_bf1; + volatile sdio_slc_slc0_tx_erreof_des_addr_reg_t slc_slc0_tx_erreof_des_addr; + volatile sdio_slc_slc1_tx_erreof_des_addr_reg_t slc_slc1_tx_erreof_des_addr; + volatile sdio_slc_token_lat_reg_t slc_token_lat; + volatile sdio_slc_tx_dscr_conf_reg_t slc_tx_dscr_conf; + volatile sdio_slc_cmd_infor0_reg_t slc_cmd_infor0; + volatile sdio_slc_cmd_infor1_reg_t slc_cmd_infor1; + volatile sdio_slc_slc0_len_conf_reg_t slc_slc0_len_conf; + volatile sdio_slc_slc0_length_reg_t slc_slc0_length; + volatile sdio_slc_slc0_txpkt_h_dscr_reg_t slc_slc0_txpkt_h_dscr; + volatile sdio_slc_slc0_txpkt_e_dscr_reg_t slc_slc0_txpkt_e_dscr; + volatile sdio_slc_slc0_rxpkt_h_dscr_reg_t slc_slc0_rxpkt_h_dscr; + volatile sdio_slc_slc0_rxpkt_e_dscr_reg_t slc_slc0_rxpkt_e_dscr; + volatile sdio_slc_slc0_txpktu_h_dscr_reg_t slc_slc0_txpktu_h_dscr; + volatile sdio_slc_slc0_txpktu_e_dscr_reg_t slc_slc0_txpktu_e_dscr; + volatile sdio_slc_slc0_rxpktu_h_dscr_reg_t slc_slc0_rxpktu_h_dscr; + volatile sdio_slc_slc0_rxpktu_e_dscr_reg_t slc_slc0_rxpktu_e_dscr; + volatile sdio_slc_seq_position_reg_t slc_seq_position; + volatile sdio_slc_slc0_dscr_rec_conf_reg_t slc_slc0_dscr_rec_conf; + volatile sdio_slc_sdio_crc_st0_reg_t slc_sdio_crc_st0; + volatile sdio_slc_sdio_crc_st1_reg_t slc_sdio_crc_st1; + volatile sdio_slc_slc0_eof_start_des_reg_t slc_slc0_eof_start_des; + volatile sdio_slc_slc0_push_dscr_addr_reg_t slc_slc0_push_dscr_addr; + volatile sdio_slc_slc0_done_dscr_addr_reg_t slc_slc0_done_dscr_addr; + volatile sdio_slc_slc0_sub_start_des_reg_t slc_slc0_sub_start_des; + volatile sdio_slc_slc0_dscr_cnt_reg_t slc_slc0_dscr_cnt; + volatile sdio_slc_slc0_len_lim_conf_reg_t slc_slc0_len_lim_conf; + volatile sdio_slc_slc0int_st1_reg_t slc_slc0int_st1; + volatile sdio_slc_slc0int_ena1_reg_t slc_slc0int_ena1; + volatile sdio_slc_slc1int_st1_reg_t slc_slc1int_st1; + volatile sdio_slc_slc1int_ena1_reg_t slc_slc1int_ena1; + volatile sdio_slc_slc0_tx_sharemem_start_reg_t slc_slc0_tx_sharemem_start; + volatile sdio_slc_slc0_tx_sharemem_end_reg_t slc_slc0_tx_sharemem_end; + volatile sdio_slc_slc0_rx_sharemem_start_reg_t slc_slc0_rx_sharemem_start; + volatile sdio_slc_slc0_rx_sharemem_end_reg_t slc_slc0_rx_sharemem_end; + volatile sdio_slc_slc1_tx_sharemem_start_reg_t slc_slc1_tx_sharemem_start; + volatile sdio_slc_slc1_tx_sharemem_end_reg_t slc_slc1_tx_sharemem_end; + volatile sdio_slc_slc1_rx_sharemem_start_reg_t slc_slc1_rx_sharemem_start; + volatile sdio_slc_slc1_rx_sharemem_end_reg_t slc_slc1_rx_sharemem_end; + volatile sdio_slc_hda_tx_sharemem_start_reg_t slc_hda_tx_sharemem_start; + volatile sdio_slc_hda_rx_sharemem_start_reg_t slc_hda_rx_sharemem_start; + volatile sdio_slc_burst_len_reg_t slc_burst_len; + uint32_t reserved_180[30]; + volatile sdio_slc_date_reg_t slc_date; + volatile sdio_slc_id_reg_t slc_id; +} slc_dev_t; + +extern slc_dev_t SLC; + +#ifndef __cplusplus +_Static_assert(sizeof(slc_dev_t) == 0x200, "Invalid size of slc_dev_t structure"); +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c61/register/soc/soc_etm_reg.h b/components/soc/esp32c61/register/soc/soc_etm_reg.h index faea3b3cf5..5d62fd5a1d 100644 --- a/components/soc/esp32c61/register/soc/soc_etm_reg.h +++ b/components/soc/esp32c61/register/soc/soc_etm_reg.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -15,8 +15,8 @@ extern "C" { * Channel enable status register */ #define SOC_ETM_CH_ENA_AD0_REG (DR_REG_SOC_ETM_BASE + 0x0) -/** SOC_ETM_CH_ENABLED0 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel0 enable status. +/** SOC_ETM_CH_ENABLED0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status. * 0: Disable * 1: Enable */ @@ -24,8 +24,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED0_M (SOC_ETM_CH_ENABLED0_V << SOC_ETM_CH_ENABLED0_S) #define SOC_ETM_CH_ENABLED0_V 0x00000001U #define SOC_ETM_CH_ENABLED0_S 0 -/** SOC_ETM_CH_ENABLED1 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel1 enable status. +/** SOC_ETM_CH_ENABLED1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status. * 0: Disable * 1: Enable */ @@ -33,8 +33,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED1_M (SOC_ETM_CH_ENABLED1_V << SOC_ETM_CH_ENABLED1_S) #define SOC_ETM_CH_ENABLED1_V 0x00000001U #define SOC_ETM_CH_ENABLED1_S 1 -/** SOC_ETM_CH_ENABLED2 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel2 enable status. +/** SOC_ETM_CH_ENABLED2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status. * 0: Disable * 1: Enable */ @@ -42,8 +42,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED2_M (SOC_ETM_CH_ENABLED2_V << SOC_ETM_CH_ENABLED2_S) #define SOC_ETM_CH_ENABLED2_V 0x00000001U #define SOC_ETM_CH_ENABLED2_S 2 -/** SOC_ETM_CH_ENABLED3 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel3 enable status. +/** SOC_ETM_CH_ENABLED3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status. * 0: Disable * 1: Enable */ @@ -51,8 +51,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED3_M (SOC_ETM_CH_ENABLED3_V << SOC_ETM_CH_ENABLED3_S) #define SOC_ETM_CH_ENABLED3_V 0x00000001U #define SOC_ETM_CH_ENABLED3_S 3 -/** SOC_ETM_CH_ENABLED4 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel4 enable status. +/** SOC_ETM_CH_ENABLED4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status. * 0: Disable * 1: Enable */ @@ -60,8 +60,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED4_M (SOC_ETM_CH_ENABLED4_V << SOC_ETM_CH_ENABLED4_S) #define SOC_ETM_CH_ENABLED4_V 0x00000001U #define SOC_ETM_CH_ENABLED4_S 4 -/** SOC_ETM_CH_ENABLED5 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel5 enable status. +/** SOC_ETM_CH_ENABLED5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status. * 0: Disable * 1: Enable */ @@ -69,8 +69,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED5_M (SOC_ETM_CH_ENABLED5_V << SOC_ETM_CH_ENABLED5_S) #define SOC_ETM_CH_ENABLED5_V 0x00000001U #define SOC_ETM_CH_ENABLED5_S 5 -/** SOC_ETM_CH_ENABLED6 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel6 enable status. +/** SOC_ETM_CH_ENABLED6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status. * 0: Disable * 1: Enable */ @@ -78,8 +78,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED6_M (SOC_ETM_CH_ENABLED6_V << SOC_ETM_CH_ENABLED6_S) #define SOC_ETM_CH_ENABLED6_V 0x00000001U #define SOC_ETM_CH_ENABLED6_S 6 -/** SOC_ETM_CH_ENABLED7 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel7 enable status. +/** SOC_ETM_CH_ENABLED7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status. * 0: Disable * 1: Enable */ @@ -87,8 +87,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED7_M (SOC_ETM_CH_ENABLED7_V << SOC_ETM_CH_ENABLED7_S) #define SOC_ETM_CH_ENABLED7_V 0x00000001U #define SOC_ETM_CH_ENABLED7_S 7 -/** SOC_ETM_CH_ENABLED8 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel8 enable status. +/** SOC_ETM_CH_ENABLED8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status. * 0: Disable * 1: Enable */ @@ -96,8 +96,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED8_M (SOC_ETM_CH_ENABLED8_V << SOC_ETM_CH_ENABLED8_S) #define SOC_ETM_CH_ENABLED8_V 0x00000001U #define SOC_ETM_CH_ENABLED8_S 8 -/** SOC_ETM_CH_ENABLED9 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel9 enable status. +/** SOC_ETM_CH_ENABLED9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status. * 0: Disable * 1: Enable */ @@ -105,8 +105,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED9_M (SOC_ETM_CH_ENABLED9_V << SOC_ETM_CH_ENABLED9_S) #define SOC_ETM_CH_ENABLED9_V 0x00000001U #define SOC_ETM_CH_ENABLED9_S 9 -/** SOC_ETM_CH_ENABLED10 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel10 enable status. +/** SOC_ETM_CH_ENABLED10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status. * 0: Disable * 1: Enable */ @@ -114,8 +114,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED10_M (SOC_ETM_CH_ENABLED10_V << SOC_ETM_CH_ENABLED10_S) #define SOC_ETM_CH_ENABLED10_V 0x00000001U #define SOC_ETM_CH_ENABLED10_S 10 -/** SOC_ETM_CH_ENABLED11 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel11 enable status. +/** SOC_ETM_CH_ENABLED11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status. * 0: Disable * 1: Enable */ @@ -123,8 +123,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED11_M (SOC_ETM_CH_ENABLED11_V << SOC_ETM_CH_ENABLED11_S) #define SOC_ETM_CH_ENABLED11_V 0x00000001U #define SOC_ETM_CH_ENABLED11_S 11 -/** SOC_ETM_CH_ENABLED12 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel12 enable status. +/** SOC_ETM_CH_ENABLED12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status. * 0: Disable * 1: Enable */ @@ -132,8 +132,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED12_M (SOC_ETM_CH_ENABLED12_V << SOC_ETM_CH_ENABLED12_S) #define SOC_ETM_CH_ENABLED12_V 0x00000001U #define SOC_ETM_CH_ENABLED12_S 12 -/** SOC_ETM_CH_ENABLED13 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel13 enable status. +/** SOC_ETM_CH_ENABLED13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status. * 0: Disable * 1: Enable */ @@ -141,8 +141,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED13_M (SOC_ETM_CH_ENABLED13_V << SOC_ETM_CH_ENABLED13_S) #define SOC_ETM_CH_ENABLED13_V 0x00000001U #define SOC_ETM_CH_ENABLED13_S 13 -/** SOC_ETM_CH_ENABLED14 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel14 enable status. +/** SOC_ETM_CH_ENABLED14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status. * 0: Disable * 1: Enable */ @@ -150,8 +150,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED14_M (SOC_ETM_CH_ENABLED14_V << SOC_ETM_CH_ENABLED14_S) #define SOC_ETM_CH_ENABLED14_V 0x00000001U #define SOC_ETM_CH_ENABLED14_S 14 -/** SOC_ETM_CH_ENABLED15 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel15 enable status. +/** SOC_ETM_CH_ENABLED15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status. * 0: Disable * 1: Enable */ @@ -159,8 +159,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED15_M (SOC_ETM_CH_ENABLED15_V << SOC_ETM_CH_ENABLED15_S) #define SOC_ETM_CH_ENABLED15_V 0x00000001U #define SOC_ETM_CH_ENABLED15_S 15 -/** SOC_ETM_CH_ENABLED16 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel16 enable status. +/** SOC_ETM_CH_ENABLED16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status. * 0: Disable * 1: Enable */ @@ -168,8 +168,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED16_M (SOC_ETM_CH_ENABLED16_V << SOC_ETM_CH_ENABLED16_S) #define SOC_ETM_CH_ENABLED16_V 0x00000001U #define SOC_ETM_CH_ENABLED16_S 16 -/** SOC_ETM_CH_ENABLED17 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel17 enable status. +/** SOC_ETM_CH_ENABLED17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status. * 0: Disable * 1: Enable */ @@ -177,8 +177,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED17_M (SOC_ETM_CH_ENABLED17_V << SOC_ETM_CH_ENABLED17_S) #define SOC_ETM_CH_ENABLED17_V 0x00000001U #define SOC_ETM_CH_ENABLED17_S 17 -/** SOC_ETM_CH_ENABLED18 : R/WTC/WS; bitpos: [18]; default: 0; - * Represents channel18 enable status. +/** SOC_ETM_CH_ENABLED18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status. * 0: Disable * 1: Enable */ @@ -186,8 +186,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED18_M (SOC_ETM_CH_ENABLED18_V << SOC_ETM_CH_ENABLED18_S) #define SOC_ETM_CH_ENABLED18_V 0x00000001U #define SOC_ETM_CH_ENABLED18_S 18 -/** SOC_ETM_CH_ENABLED19 : R/WTC/WS; bitpos: [19]; default: 0; - * Represents channel19 enable status. +/** SOC_ETM_CH_ENABLED19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status. * 0: Disable * 1: Enable */ @@ -195,8 +195,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED19_M (SOC_ETM_CH_ENABLED19_V << SOC_ETM_CH_ENABLED19_S) #define SOC_ETM_CH_ENABLED19_V 0x00000001U #define SOC_ETM_CH_ENABLED19_S 19 -/** SOC_ETM_CH_ENABLED20 : R/WTC/WS; bitpos: [20]; default: 0; - * Represents channel20 enable status. +/** SOC_ETM_CH_ENABLED20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status. * 0: Disable * 1: Enable */ @@ -204,8 +204,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED20_M (SOC_ETM_CH_ENABLED20_V << SOC_ETM_CH_ENABLED20_S) #define SOC_ETM_CH_ENABLED20_V 0x00000001U #define SOC_ETM_CH_ENABLED20_S 20 -/** SOC_ETM_CH_ENABLED21 : R/WTC/WS; bitpos: [21]; default: 0; - * Represents channel21 enable status. +/** SOC_ETM_CH_ENABLED21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status. * 0: Disable * 1: Enable */ @@ -213,8 +213,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED21_M (SOC_ETM_CH_ENABLED21_V << SOC_ETM_CH_ENABLED21_S) #define SOC_ETM_CH_ENABLED21_V 0x00000001U #define SOC_ETM_CH_ENABLED21_S 21 -/** SOC_ETM_CH_ENABLED22 : R/WTC/WS; bitpos: [22]; default: 0; - * Represents channel22 enable status. +/** SOC_ETM_CH_ENABLED22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status. * 0: Disable * 1: Enable */ @@ -222,8 +222,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED22_M (SOC_ETM_CH_ENABLED22_V << SOC_ETM_CH_ENABLED22_S) #define SOC_ETM_CH_ENABLED22_V 0x00000001U #define SOC_ETM_CH_ENABLED22_S 22 -/** SOC_ETM_CH_ENABLED23 : R/WTC/WS; bitpos: [23]; default: 0; - * Represents channel23 enable status. +/** SOC_ETM_CH_ENABLED23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status. * 0: Disable * 1: Enable */ @@ -231,8 +231,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED23_M (SOC_ETM_CH_ENABLED23_V << SOC_ETM_CH_ENABLED23_S) #define SOC_ETM_CH_ENABLED23_V 0x00000001U #define SOC_ETM_CH_ENABLED23_S 23 -/** SOC_ETM_CH_ENABLED24 : R/WTC/WS; bitpos: [24]; default: 0; - * Represents channel24 enable status. +/** SOC_ETM_CH_ENABLED24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status. * 0: Disable * 1: Enable */ @@ -240,8 +240,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED24_M (SOC_ETM_CH_ENABLED24_V << SOC_ETM_CH_ENABLED24_S) #define SOC_ETM_CH_ENABLED24_V 0x00000001U #define SOC_ETM_CH_ENABLED24_S 24 -/** SOC_ETM_CH_ENABLED25 : R/WTC/WS; bitpos: [25]; default: 0; - * Represents channel25 enable status. +/** SOC_ETM_CH_ENABLED25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status. * 0: Disable * 1: Enable */ @@ -249,8 +249,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED25_M (SOC_ETM_CH_ENABLED25_V << SOC_ETM_CH_ENABLED25_S) #define SOC_ETM_CH_ENABLED25_V 0x00000001U #define SOC_ETM_CH_ENABLED25_S 25 -/** SOC_ETM_CH_ENABLED26 : R/WTC/WS; bitpos: [26]; default: 0; - * Represents channel26 enable status. +/** SOC_ETM_CH_ENABLED26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status. * 0: Disable * 1: Enable */ @@ -258,8 +258,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED26_M (SOC_ETM_CH_ENABLED26_V << SOC_ETM_CH_ENABLED26_S) #define SOC_ETM_CH_ENABLED26_V 0x00000001U #define SOC_ETM_CH_ENABLED26_S 26 -/** SOC_ETM_CH_ENABLED27 : R/WTC/WS; bitpos: [27]; default: 0; - * Represents channel27 enable status. +/** SOC_ETM_CH_ENABLED27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status. * 0: Disable * 1: Enable */ @@ -267,8 +267,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED27_M (SOC_ETM_CH_ENABLED27_V << SOC_ETM_CH_ENABLED27_S) #define SOC_ETM_CH_ENABLED27_V 0x00000001U #define SOC_ETM_CH_ENABLED27_S 27 -/** SOC_ETM_CH_ENABLED28 : R/WTC/WS; bitpos: [28]; default: 0; - * Represents channel28 enable status. +/** SOC_ETM_CH_ENABLED28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status. * 0: Disable * 1: Enable */ @@ -276,8 +276,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED28_M (SOC_ETM_CH_ENABLED28_V << SOC_ETM_CH_ENABLED28_S) #define SOC_ETM_CH_ENABLED28_V 0x00000001U #define SOC_ETM_CH_ENABLED28_S 28 -/** SOC_ETM_CH_ENABLED29 : R/WTC/WS; bitpos: [29]; default: 0; - * Represents channel29 enable status. +/** SOC_ETM_CH_ENABLED29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status. * 0: Disable * 1: Enable */ @@ -285,8 +285,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED29_M (SOC_ETM_CH_ENABLED29_V << SOC_ETM_CH_ENABLED29_S) #define SOC_ETM_CH_ENABLED29_V 0x00000001U #define SOC_ETM_CH_ENABLED29_S 29 -/** SOC_ETM_CH_ENABLED30 : R/WTC/WS; bitpos: [30]; default: 0; - * Represents channel30 enable status. +/** SOC_ETM_CH_ENABLED30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status. * 0: Disable * 1: Enable */ @@ -294,8 +294,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED30_M (SOC_ETM_CH_ENABLED30_V << SOC_ETM_CH_ENABLED30_S) #define SOC_ETM_CH_ENABLED30_V 0x00000001U #define SOC_ETM_CH_ENABLED30_S 30 -/** SOC_ETM_CH_ENABLED31 : R/WTC/WS; bitpos: [31]; default: 0; - * Represents channel31 enable status. +/** SOC_ETM_CH_ENABLED31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status. * 0: Disable * 1: Enable */ @@ -305,12 +305,12 @@ extern "C" { #define SOC_ETM_CH_ENABLED31_S 31 /** SOC_ETM_CH_ENA_AD0_SET_REG register - * Channel enable register + * Channel enable set register */ #define SOC_ETM_CH_ENA_AD0_SET_REG (DR_REG_SOC_ETM_BASE + 0x4) /** SOC_ETM_CH_ENABLE0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel0. - * 0: Invalid. No effect + * Configures whether or not to enable ch0. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE0 (BIT(0)) @@ -318,8 +318,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE0_V 0x00000001U #define SOC_ETM_CH_ENABLE0_S 0 /** SOC_ETM_CH_ENABLE1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel1. - * 0: Invalid. No effect + * Configures whether or not to enable ch1. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE1 (BIT(1)) @@ -327,8 +327,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE1_V 0x00000001U #define SOC_ETM_CH_ENABLE1_S 1 /** SOC_ETM_CH_ENABLE2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel2. - * 0: Invalid. No effect + * Configures whether or not to enable ch2. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE2 (BIT(2)) @@ -336,8 +336,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE2_V 0x00000001U #define SOC_ETM_CH_ENABLE2_S 2 /** SOC_ETM_CH_ENABLE3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel3. - * 0: Invalid. No effect + * Configures whether or not to enable ch3. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE3 (BIT(3)) @@ -345,8 +345,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE3_V 0x00000001U #define SOC_ETM_CH_ENABLE3_S 3 /** SOC_ETM_CH_ENABLE4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel4. - * 0: Invalid. No effect + * Configures whether or not to enable ch4. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE4 (BIT(4)) @@ -354,8 +354,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE4_V 0x00000001U #define SOC_ETM_CH_ENABLE4_S 4 /** SOC_ETM_CH_ENABLE5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel5. - * 0: Invalid. No effect + * Configures whether or not to enable ch5. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE5 (BIT(5)) @@ -363,8 +363,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE5_V 0x00000001U #define SOC_ETM_CH_ENABLE5_S 5 /** SOC_ETM_CH_ENABLE6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel6. - * 0: Invalid. No effect + * Configures whether or not to enable ch6. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE6 (BIT(6)) @@ -372,8 +372,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE6_V 0x00000001U #define SOC_ETM_CH_ENABLE6_S 6 /** SOC_ETM_CH_ENABLE7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel7. - * 0: Invalid. No effect + * Configures whether or not to enable ch7. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE7 (BIT(7)) @@ -381,8 +381,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE7_V 0x00000001U #define SOC_ETM_CH_ENABLE7_S 7 /** SOC_ETM_CH_ENABLE8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel8. - * 0: Invalid. No effect + * Configures whether or not to enable ch8. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE8 (BIT(8)) @@ -390,8 +390,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE8_V 0x00000001U #define SOC_ETM_CH_ENABLE8_S 8 /** SOC_ETM_CH_ENABLE9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel9. - * 0: Invalid. No effect + * Configures whether or not to enable ch9. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE9 (BIT(9)) @@ -399,8 +399,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE9_V 0x00000001U #define SOC_ETM_CH_ENABLE9_S 9 /** SOC_ETM_CH_ENABLE10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel10. - * 0: Invalid. No effect + * Configures whether or not to enable ch10. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE10 (BIT(10)) @@ -408,8 +408,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE10_V 0x00000001U #define SOC_ETM_CH_ENABLE10_S 10 /** SOC_ETM_CH_ENABLE11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel11. - * 0: Invalid. No effect + * Configures whether or not to enable ch11. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE11 (BIT(11)) @@ -417,8 +417,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE11_V 0x00000001U #define SOC_ETM_CH_ENABLE11_S 11 /** SOC_ETM_CH_ENABLE12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel12. - * 0: Invalid. No effect + * Configures whether or not to enable ch12. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE12 (BIT(12)) @@ -426,8 +426,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE12_V 0x00000001U #define SOC_ETM_CH_ENABLE12_S 12 /** SOC_ETM_CH_ENABLE13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel13. - * 0: Invalid. No effect + * Configures whether or not to enable ch13. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE13 (BIT(13)) @@ -435,8 +435,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE13_V 0x00000001U #define SOC_ETM_CH_ENABLE13_S 13 /** SOC_ETM_CH_ENABLE14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel14. - * 0: Invalid. No effect + * Configures whether or not to enable ch14. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE14 (BIT(14)) @@ -444,8 +444,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE14_V 0x00000001U #define SOC_ETM_CH_ENABLE14_S 14 /** SOC_ETM_CH_ENABLE15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel15. - * 0: Invalid. No effect + * Configures whether or not to enable ch15. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE15 (BIT(15)) @@ -453,8 +453,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE15_V 0x00000001U #define SOC_ETM_CH_ENABLE15_S 15 /** SOC_ETM_CH_ENABLE16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel16. - * 0: Invalid. No effect + * Configures whether or not to enable ch16. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE16 (BIT(16)) @@ -462,8 +462,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE16_V 0x00000001U #define SOC_ETM_CH_ENABLE16_S 16 /** SOC_ETM_CH_ENABLE17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel17. - * 0: Invalid. No effect + * Configures whether or not to enable ch17. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE17 (BIT(17)) @@ -471,8 +471,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE17_V 0x00000001U #define SOC_ETM_CH_ENABLE17_S 17 /** SOC_ETM_CH_ENABLE18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to enable channel18. - * 0: Invalid. No effect + * Configures whether or not to enable ch18. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE18 (BIT(18)) @@ -480,8 +480,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE18_V 0x00000001U #define SOC_ETM_CH_ENABLE18_S 18 /** SOC_ETM_CH_ENABLE19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to enable channel19. - * 0: Invalid. No effect + * Configures whether or not to enable ch19. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE19 (BIT(19)) @@ -489,8 +489,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE19_V 0x00000001U #define SOC_ETM_CH_ENABLE19_S 19 /** SOC_ETM_CH_ENABLE20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to enable channel20. - * 0: Invalid. No effect + * Configures whether or not to enable ch20. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE20 (BIT(20)) @@ -498,8 +498,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE20_V 0x00000001U #define SOC_ETM_CH_ENABLE20_S 20 /** SOC_ETM_CH_ENABLE21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to enable channel21. - * 0: Invalid. No effect + * Configures whether or not to enable ch21. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE21 (BIT(21)) @@ -507,8 +507,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE21_V 0x00000001U #define SOC_ETM_CH_ENABLE21_S 21 /** SOC_ETM_CH_ENABLE22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to enable channel22. - * 0: Invalid. No effect + * Configures whether or not to enable ch22. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE22 (BIT(22)) @@ -516,8 +516,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE22_V 0x00000001U #define SOC_ETM_CH_ENABLE22_S 22 /** SOC_ETM_CH_ENABLE23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to enable channel23. - * 0: Invalid. No effect + * Configures whether or not to enable ch23. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE23 (BIT(23)) @@ -525,8 +525,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE23_V 0x00000001U #define SOC_ETM_CH_ENABLE23_S 23 /** SOC_ETM_CH_ENABLE24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to enable channel24. - * 0: Invalid. No effect + * Configures whether or not to enable ch24. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE24 (BIT(24)) @@ -534,8 +534,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE24_V 0x00000001U #define SOC_ETM_CH_ENABLE24_S 24 /** SOC_ETM_CH_ENABLE25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to enable channel25. - * 0: Invalid. No effect + * Configures whether or not to enable ch25. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE25 (BIT(25)) @@ -543,8 +543,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE25_V 0x00000001U #define SOC_ETM_CH_ENABLE25_S 25 /** SOC_ETM_CH_ENABLE26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to enable channel26. - * 0: Invalid. No effect + * Configures whether or not to enable ch26. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE26 (BIT(26)) @@ -552,8 +552,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE26_V 0x00000001U #define SOC_ETM_CH_ENABLE26_S 26 /** SOC_ETM_CH_ENABLE27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to enable channel27. - * 0: Invalid. No effect + * Configures whether or not to enable ch27. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE27 (BIT(27)) @@ -561,8 +561,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE27_V 0x00000001U #define SOC_ETM_CH_ENABLE27_S 27 /** SOC_ETM_CH_ENABLE28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to enable channel28. - * 0: Invalid. No effect + * Configures whether or not to enable ch28. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE28 (BIT(28)) @@ -570,8 +570,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE28_V 0x00000001U #define SOC_ETM_CH_ENABLE28_S 28 /** SOC_ETM_CH_ENABLE29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to enable channel29. - * 0: Invalid. No effect + * Configures whether or not to enable ch29. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE29 (BIT(29)) @@ -579,8 +579,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE29_V 0x00000001U #define SOC_ETM_CH_ENABLE29_S 29 /** SOC_ETM_CH_ENABLE30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to enable channel30. - * 0: Invalid. No effect + * Configures whether or not to enable ch30. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE30 (BIT(30)) @@ -588,8 +588,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE30_V 0x00000001U #define SOC_ETM_CH_ENABLE30_S 30 /** SOC_ETM_CH_ENABLE31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to enable channel31. - * 0: Invalid. No effect + * Configures whether or not to enable ch31. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE31 (BIT(31)) @@ -598,12 +598,12 @@ extern "C" { #define SOC_ETM_CH_ENABLE31_S 31 /** SOC_ETM_CH_ENA_AD0_CLR_REG register - * Channel disable register + * Channel enable clear register */ #define SOC_ETM_CH_ENA_AD0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x8) /** SOC_ETM_CH_DISABLE0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel0. - * 0: Invalid. No effect + * Configures whether or not to clear ch0 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE0 (BIT(0)) @@ -611,8 +611,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE0_V 0x00000001U #define SOC_ETM_CH_DISABLE0_S 0 /** SOC_ETM_CH_DISABLE1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel1. - * 0: Invalid. No effect + * Configures whether or not to clear ch1 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE1 (BIT(1)) @@ -620,8 +620,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE1_V 0x00000001U #define SOC_ETM_CH_DISABLE1_S 1 /** SOC_ETM_CH_DISABLE2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel2. - * 0: Invalid. No effect + * Configures whether or not to clear ch2 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE2 (BIT(2)) @@ -629,8 +629,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE2_V 0x00000001U #define SOC_ETM_CH_DISABLE2_S 2 /** SOC_ETM_CH_DISABLE3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel3. - * 0: Invalid. No effect + * Configures whether or not to clear ch3 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE3 (BIT(3)) @@ -638,8 +638,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE3_V 0x00000001U #define SOC_ETM_CH_DISABLE3_S 3 /** SOC_ETM_CH_DISABLE4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel4. - * 0: Invalid. No effect + * Configures whether or not to clear ch4 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE4 (BIT(4)) @@ -647,8 +647,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE4_V 0x00000001U #define SOC_ETM_CH_DISABLE4_S 4 /** SOC_ETM_CH_DISABLE5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel5. - * 0: Invalid. No effect + * Configures whether or not to clear ch5 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE5 (BIT(5)) @@ -656,8 +656,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE5_V 0x00000001U #define SOC_ETM_CH_DISABLE5_S 5 /** SOC_ETM_CH_DISABLE6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel6. - * 0: Invalid. No effect + * Configures whether or not to clear ch6 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE6 (BIT(6)) @@ -665,8 +665,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE6_V 0x00000001U #define SOC_ETM_CH_DISABLE6_S 6 /** SOC_ETM_CH_DISABLE7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel7. - * 0: Invalid. No effect + * Configures whether or not to clear ch7 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE7 (BIT(7)) @@ -674,8 +674,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE7_V 0x00000001U #define SOC_ETM_CH_DISABLE7_S 7 /** SOC_ETM_CH_DISABLE8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel8. - * 0: Invalid. No effect + * Configures whether or not to clear ch8 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE8 (BIT(8)) @@ -683,8 +683,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE8_V 0x00000001U #define SOC_ETM_CH_DISABLE8_S 8 /** SOC_ETM_CH_DISABLE9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel9. - * 0: Invalid. No effect + * Configures whether or not to clear ch9 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE9 (BIT(9)) @@ -692,8 +692,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE9_V 0x00000001U #define SOC_ETM_CH_DISABLE9_S 9 /** SOC_ETM_CH_DISABLE10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel10. - * 0: Invalid. No effect + * Configures whether or not to clear ch10 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE10 (BIT(10)) @@ -701,8 +701,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE10_V 0x00000001U #define SOC_ETM_CH_DISABLE10_S 10 /** SOC_ETM_CH_DISABLE11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel11. - * 0: Invalid. No effect + * Configures whether or not to clear ch11 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE11 (BIT(11)) @@ -710,8 +710,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE11_V 0x00000001U #define SOC_ETM_CH_DISABLE11_S 11 /** SOC_ETM_CH_DISABLE12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel12. - * 0: Invalid. No effect + * Configures whether or not to clear ch12 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE12 (BIT(12)) @@ -719,8 +719,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE12_V 0x00000001U #define SOC_ETM_CH_DISABLE12_S 12 /** SOC_ETM_CH_DISABLE13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel13. - * 0: Invalid. No effect + * Configures whether or not to clear ch13 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE13 (BIT(13)) @@ -728,8 +728,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE13_V 0x00000001U #define SOC_ETM_CH_DISABLE13_S 13 /** SOC_ETM_CH_DISABLE14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel14. - * 0: Invalid. No effect + * Configures whether or not to clear ch14 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE14 (BIT(14)) @@ -737,8 +737,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE14_V 0x00000001U #define SOC_ETM_CH_DISABLE14_S 14 /** SOC_ETM_CH_DISABLE15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel15. - * 0: Invalid. No effect + * Configures whether or not to clear ch15 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE15 (BIT(15)) @@ -746,8 +746,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE15_V 0x00000001U #define SOC_ETM_CH_DISABLE15_S 15 /** SOC_ETM_CH_DISABLE16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel16. - * 0: Invalid. No effect + * Configures whether or not to clear ch16 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE16 (BIT(16)) @@ -755,8 +755,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE16_V 0x00000001U #define SOC_ETM_CH_DISABLE16_S 16 /** SOC_ETM_CH_DISABLE17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel17. - * 0: Invalid. No effect + * Configures whether or not to clear ch17 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE17 (BIT(17)) @@ -764,8 +764,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE17_V 0x00000001U #define SOC_ETM_CH_DISABLE17_S 17 /** SOC_ETM_CH_DISABLE18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to disable channel18. - * 0: Invalid. No effect + * Configures whether or not to clear ch18 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE18 (BIT(18)) @@ -773,8 +773,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE18_V 0x00000001U #define SOC_ETM_CH_DISABLE18_S 18 /** SOC_ETM_CH_DISABLE19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to disable channel19. - * 0: Invalid. No effect + * Configures whether or not to clear ch19 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE19 (BIT(19)) @@ -782,8 +782,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE19_V 0x00000001U #define SOC_ETM_CH_DISABLE19_S 19 /** SOC_ETM_CH_DISABLE20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to disable channel20. - * 0: Invalid. No effect + * Configures whether or not to clear ch20 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE20 (BIT(20)) @@ -791,8 +791,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE20_V 0x00000001U #define SOC_ETM_CH_DISABLE20_S 20 /** SOC_ETM_CH_DISABLE21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to disable channel21. - * 0: Invalid. No effect + * Configures whether or not to clear ch21 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE21 (BIT(21)) @@ -800,8 +800,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE21_V 0x00000001U #define SOC_ETM_CH_DISABLE21_S 21 /** SOC_ETM_CH_DISABLE22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to disable channel22. - * 0: Invalid. No effect + * Configures whether or not to clear ch22 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE22 (BIT(22)) @@ -809,8 +809,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE22_V 0x00000001U #define SOC_ETM_CH_DISABLE22_S 22 /** SOC_ETM_CH_DISABLE23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to disable channel23. - * 0: Invalid. No effect + * Configures whether or not to clear ch23 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE23 (BIT(23)) @@ -818,8 +818,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE23_V 0x00000001U #define SOC_ETM_CH_DISABLE23_S 23 /** SOC_ETM_CH_DISABLE24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to disable channel24. - * 0: Invalid. No effect + * Configures whether or not to clear ch24 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE24 (BIT(24)) @@ -827,8 +827,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE24_V 0x00000001U #define SOC_ETM_CH_DISABLE24_S 24 /** SOC_ETM_CH_DISABLE25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to disable channel25. - * 0: Invalid. No effect + * Configures whether or not to clear ch25 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE25 (BIT(25)) @@ -836,8 +836,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE25_V 0x00000001U #define SOC_ETM_CH_DISABLE25_S 25 /** SOC_ETM_CH_DISABLE26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to disable channel26. - * 0: Invalid. No effect + * Configures whether or not to clear ch26 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE26 (BIT(26)) @@ -845,8 +845,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE26_V 0x00000001U #define SOC_ETM_CH_DISABLE26_S 26 /** SOC_ETM_CH_DISABLE27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to disable channel27. - * 0: Invalid. No effect + * Configures whether or not to clear ch27 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE27 (BIT(27)) @@ -854,8 +854,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE27_V 0x00000001U #define SOC_ETM_CH_DISABLE27_S 27 /** SOC_ETM_CH_DISABLE28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to disable channel28. - * 0: Invalid. No effect + * Configures whether or not to clear ch28 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE28 (BIT(28)) @@ -863,8 +863,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE28_V 0x00000001U #define SOC_ETM_CH_DISABLE28_S 28 /** SOC_ETM_CH_DISABLE29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to disable channel29. - * 0: Invalid. No effect + * Configures whether or not to clear ch29 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE29 (BIT(29)) @@ -872,8 +872,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE29_V 0x00000001U #define SOC_ETM_CH_DISABLE29_S 29 /** SOC_ETM_CH_DISABLE30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to disable channel30. - * 0: Invalid. No effect + * Configures whether or not to clear ch30 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE30 (BIT(30)) @@ -881,8 +881,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE30_V 0x00000001U #define SOC_ETM_CH_DISABLE30_S 30 /** SOC_ETM_CH_DISABLE31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to disable channel31. - * 0: Invalid. No effect + * Configures whether or not to clear ch31 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE31 (BIT(31)) @@ -894,8 +894,8 @@ extern "C" { * Channel enable status register */ #define SOC_ETM_CH_ENA_AD1_REG (DR_REG_SOC_ETM_BASE + 0xc) -/** SOC_ETM_CH_ENABLED32 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel32 enable status. +/** SOC_ETM_CH_ENABLED32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status. * 0: Disable * 1: Enable */ @@ -903,8 +903,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED32_M (SOC_ETM_CH_ENABLED32_V << SOC_ETM_CH_ENABLED32_S) #define SOC_ETM_CH_ENABLED32_V 0x00000001U #define SOC_ETM_CH_ENABLED32_S 0 -/** SOC_ETM_CH_ENABLED33 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel33 enable status. +/** SOC_ETM_CH_ENABLED33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status. * 0: Disable * 1: Enable */ @@ -912,8 +912,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED33_M (SOC_ETM_CH_ENABLED33_V << SOC_ETM_CH_ENABLED33_S) #define SOC_ETM_CH_ENABLED33_V 0x00000001U #define SOC_ETM_CH_ENABLED33_S 1 -/** SOC_ETM_CH_ENABLED34 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel34 enable status. +/** SOC_ETM_CH_ENABLED34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status. * 0: Disable * 1: Enable */ @@ -921,8 +921,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED34_M (SOC_ETM_CH_ENABLED34_V << SOC_ETM_CH_ENABLED34_S) #define SOC_ETM_CH_ENABLED34_V 0x00000001U #define SOC_ETM_CH_ENABLED34_S 2 -/** SOC_ETM_CH_ENABLED35 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel35 enable status. +/** SOC_ETM_CH_ENABLED35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status. * 0: Disable * 1: Enable */ @@ -930,8 +930,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED35_M (SOC_ETM_CH_ENABLED35_V << SOC_ETM_CH_ENABLED35_S) #define SOC_ETM_CH_ENABLED35_V 0x00000001U #define SOC_ETM_CH_ENABLED35_S 3 -/** SOC_ETM_CH_ENABLED36 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel36 enable status. +/** SOC_ETM_CH_ENABLED36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status. * 0: Disable * 1: Enable */ @@ -939,8 +939,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED36_M (SOC_ETM_CH_ENABLED36_V << SOC_ETM_CH_ENABLED36_S) #define SOC_ETM_CH_ENABLED36_V 0x00000001U #define SOC_ETM_CH_ENABLED36_S 4 -/** SOC_ETM_CH_ENABLED37 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel37 enable status. +/** SOC_ETM_CH_ENABLED37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status. * 0: Disable * 1: Enable */ @@ -948,8 +948,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED37_M (SOC_ETM_CH_ENABLED37_V << SOC_ETM_CH_ENABLED37_S) #define SOC_ETM_CH_ENABLED37_V 0x00000001U #define SOC_ETM_CH_ENABLED37_S 5 -/** SOC_ETM_CH_ENABLED38 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel38 enable status. +/** SOC_ETM_CH_ENABLED38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status. * 0: Disable * 1: Enable */ @@ -957,8 +957,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED38_M (SOC_ETM_CH_ENABLED38_V << SOC_ETM_CH_ENABLED38_S) #define SOC_ETM_CH_ENABLED38_V 0x00000001U #define SOC_ETM_CH_ENABLED38_S 6 -/** SOC_ETM_CH_ENABLED39 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel39 enable status. +/** SOC_ETM_CH_ENABLED39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status. * 0: Disable * 1: Enable */ @@ -966,8 +966,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED39_M (SOC_ETM_CH_ENABLED39_V << SOC_ETM_CH_ENABLED39_S) #define SOC_ETM_CH_ENABLED39_V 0x00000001U #define SOC_ETM_CH_ENABLED39_S 7 -/** SOC_ETM_CH_ENABLED40 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel40 enable status. +/** SOC_ETM_CH_ENABLED40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status. * 0: Disable * 1: Enable */ @@ -975,8 +975,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED40_M (SOC_ETM_CH_ENABLED40_V << SOC_ETM_CH_ENABLED40_S) #define SOC_ETM_CH_ENABLED40_V 0x00000001U #define SOC_ETM_CH_ENABLED40_S 8 -/** SOC_ETM_CH_ENABLED41 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel41 enable status. +/** SOC_ETM_CH_ENABLED41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status. * 0: Disable * 1: Enable */ @@ -984,8 +984,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED41_M (SOC_ETM_CH_ENABLED41_V << SOC_ETM_CH_ENABLED41_S) #define SOC_ETM_CH_ENABLED41_V 0x00000001U #define SOC_ETM_CH_ENABLED41_S 9 -/** SOC_ETM_CH_ENABLED42 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel42 enable status. +/** SOC_ETM_CH_ENABLED42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status. * 0: Disable * 1: Enable */ @@ -993,8 +993,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED42_M (SOC_ETM_CH_ENABLED42_V << SOC_ETM_CH_ENABLED42_S) #define SOC_ETM_CH_ENABLED42_V 0x00000001U #define SOC_ETM_CH_ENABLED42_S 10 -/** SOC_ETM_CH_ENABLED43 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel43 enable status. +/** SOC_ETM_CH_ENABLED43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status. * 0: Disable * 1: Enable */ @@ -1002,8 +1002,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED43_M (SOC_ETM_CH_ENABLED43_V << SOC_ETM_CH_ENABLED43_S) #define SOC_ETM_CH_ENABLED43_V 0x00000001U #define SOC_ETM_CH_ENABLED43_S 11 -/** SOC_ETM_CH_ENABLED44 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel44 enable status. +/** SOC_ETM_CH_ENABLED44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status. * 0: Disable * 1: Enable */ @@ -1011,8 +1011,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED44_M (SOC_ETM_CH_ENABLED44_V << SOC_ETM_CH_ENABLED44_S) #define SOC_ETM_CH_ENABLED44_V 0x00000001U #define SOC_ETM_CH_ENABLED44_S 12 -/** SOC_ETM_CH_ENABLED45 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel45 enable status. +/** SOC_ETM_CH_ENABLED45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status. * 0: Disable * 1: Enable */ @@ -1020,8 +1020,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED45_M (SOC_ETM_CH_ENABLED45_V << SOC_ETM_CH_ENABLED45_S) #define SOC_ETM_CH_ENABLED45_V 0x00000001U #define SOC_ETM_CH_ENABLED45_S 13 -/** SOC_ETM_CH_ENABLED46 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel46 enable status. +/** SOC_ETM_CH_ENABLED46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status. * 0: Disable * 1: Enable */ @@ -1029,8 +1029,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED46_M (SOC_ETM_CH_ENABLED46_V << SOC_ETM_CH_ENABLED46_S) #define SOC_ETM_CH_ENABLED46_V 0x00000001U #define SOC_ETM_CH_ENABLED46_S 14 -/** SOC_ETM_CH_ENABLED47 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel47 enable status. +/** SOC_ETM_CH_ENABLED47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status. * 0: Disable * 1: Enable */ @@ -1038,8 +1038,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED47_M (SOC_ETM_CH_ENABLED47_V << SOC_ETM_CH_ENABLED47_S) #define SOC_ETM_CH_ENABLED47_V 0x00000001U #define SOC_ETM_CH_ENABLED47_S 15 -/** SOC_ETM_CH_ENABLED48 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel48 enable status. +/** SOC_ETM_CH_ENABLED48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status. * 0: Disable * 1: Enable */ @@ -1047,8 +1047,8 @@ extern "C" { #define SOC_ETM_CH_ENABLED48_M (SOC_ETM_CH_ENABLED48_V << SOC_ETM_CH_ENABLED48_S) #define SOC_ETM_CH_ENABLED48_V 0x00000001U #define SOC_ETM_CH_ENABLED48_S 16 -/** SOC_ETM_CH_ENABLED49 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel49 enable status. +/** SOC_ETM_CH_ENABLED49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status. * 0: Disable * 1: Enable */ @@ -1058,12 +1058,12 @@ extern "C" { #define SOC_ETM_CH_ENABLED49_S 17 /** SOC_ETM_CH_ENA_AD1_SET_REG register - * Channel enable register + * Channel enable set register */ #define SOC_ETM_CH_ENA_AD1_SET_REG (DR_REG_SOC_ETM_BASE + 0x10) /** SOC_ETM_CH_ENABLE32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel32. - * 0: Invalid. No effect + * Configures whether or not to enable ch32. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE32 (BIT(0)) @@ -1071,8 +1071,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE32_V 0x00000001U #define SOC_ETM_CH_ENABLE32_S 0 /** SOC_ETM_CH_ENABLE33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel33. - * 0: Invalid. No effect + * Configures whether or not to enable ch33. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE33 (BIT(1)) @@ -1080,8 +1080,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE33_V 0x00000001U #define SOC_ETM_CH_ENABLE33_S 1 /** SOC_ETM_CH_ENABLE34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel34. - * 0: Invalid. No effect + * Configures whether or not to enable ch34. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE34 (BIT(2)) @@ -1089,8 +1089,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE34_V 0x00000001U #define SOC_ETM_CH_ENABLE34_S 2 /** SOC_ETM_CH_ENABLE35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel35. - * 0: Invalid. No effect + * Configures whether or not to enable ch35. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE35 (BIT(3)) @@ -1098,8 +1098,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE35_V 0x00000001U #define SOC_ETM_CH_ENABLE35_S 3 /** SOC_ETM_CH_ENABLE36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel36. - * 0: Invalid. No effect + * Configures whether or not to enable ch36. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE36 (BIT(4)) @@ -1107,8 +1107,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE36_V 0x00000001U #define SOC_ETM_CH_ENABLE36_S 4 /** SOC_ETM_CH_ENABLE37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel37. - * 0: Invalid. No effect + * Configures whether or not to enable ch37. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE37 (BIT(5)) @@ -1116,8 +1116,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE37_V 0x00000001U #define SOC_ETM_CH_ENABLE37_S 5 /** SOC_ETM_CH_ENABLE38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel38. - * 0: Invalid. No effect + * Configures whether or not to enable ch38. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE38 (BIT(6)) @@ -1125,8 +1125,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE38_V 0x00000001U #define SOC_ETM_CH_ENABLE38_S 6 /** SOC_ETM_CH_ENABLE39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel39. - * 0: Invalid. No effect + * Configures whether or not to enable ch39. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE39 (BIT(7)) @@ -1134,8 +1134,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE39_V 0x00000001U #define SOC_ETM_CH_ENABLE39_S 7 /** SOC_ETM_CH_ENABLE40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel40. - * 0: Invalid. No effect + * Configures whether or not to enable ch40. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE40 (BIT(8)) @@ -1143,8 +1143,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE40_V 0x00000001U #define SOC_ETM_CH_ENABLE40_S 8 /** SOC_ETM_CH_ENABLE41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel41. - * 0: Invalid. No effect + * Configures whether or not to enable ch41. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE41 (BIT(9)) @@ -1152,8 +1152,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE41_V 0x00000001U #define SOC_ETM_CH_ENABLE41_S 9 /** SOC_ETM_CH_ENABLE42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel42. - * 0: Invalid. No effect + * Configures whether or not to enable ch42. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE42 (BIT(10)) @@ -1161,8 +1161,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE42_V 0x00000001U #define SOC_ETM_CH_ENABLE42_S 10 /** SOC_ETM_CH_ENABLE43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel43. - * 0: Invalid. No effect + * Configures whether or not to enable ch43. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE43 (BIT(11)) @@ -1170,8 +1170,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE43_V 0x00000001U #define SOC_ETM_CH_ENABLE43_S 11 /** SOC_ETM_CH_ENABLE44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel44. - * 0: Invalid. No effect + * Configures whether or not to enable ch44. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE44 (BIT(12)) @@ -1179,8 +1179,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE44_V 0x00000001U #define SOC_ETM_CH_ENABLE44_S 12 /** SOC_ETM_CH_ENABLE45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel45. - * 0: Invalid. No effect + * Configures whether or not to enable ch45. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE45 (BIT(13)) @@ -1188,8 +1188,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE45_V 0x00000001U #define SOC_ETM_CH_ENABLE45_S 13 /** SOC_ETM_CH_ENABLE46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel46. - * 0: Invalid. No effect + * Configures whether or not to enable ch46. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE46 (BIT(14)) @@ -1197,8 +1197,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE46_V 0x00000001U #define SOC_ETM_CH_ENABLE46_S 14 /** SOC_ETM_CH_ENABLE47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel47. - * 0: Invalid. No effect + * Configures whether or not to enable ch47. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE47 (BIT(15)) @@ -1206,8 +1206,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE47_V 0x00000001U #define SOC_ETM_CH_ENABLE47_S 15 /** SOC_ETM_CH_ENABLE48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel48. - * 0: Invalid. No effect + * Configures whether or not to enable ch48. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE48 (BIT(16)) @@ -1215,8 +1215,8 @@ extern "C" { #define SOC_ETM_CH_ENABLE48_V 0x00000001U #define SOC_ETM_CH_ENABLE48_S 16 /** SOC_ETM_CH_ENABLE49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel49. - * 0: Invalid. No effect + * Configures whether or not to enable ch49. + * 0: Invalid, No effect * 1: Enable */ #define SOC_ETM_CH_ENABLE49 (BIT(17)) @@ -1225,12 +1225,12 @@ extern "C" { #define SOC_ETM_CH_ENABLE49_S 17 /** SOC_ETM_CH_ENA_AD1_CLR_REG register - * Channel disable register + * Channel enable clear register */ #define SOC_ETM_CH_ENA_AD1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x14) /** SOC_ETM_CH_DISABLE32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel32. - * 0: Invalid. No effect + * Configures whether or not to clear ch32 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE32 (BIT(0)) @@ -1238,8 +1238,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE32_V 0x00000001U #define SOC_ETM_CH_DISABLE32_S 0 /** SOC_ETM_CH_DISABLE33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel33. - * 0: Invalid. No effect + * Configures whether or not to clear ch33 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE33 (BIT(1)) @@ -1247,8 +1247,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE33_V 0x00000001U #define SOC_ETM_CH_DISABLE33_S 1 /** SOC_ETM_CH_DISABLE34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel34. - * 0: Invalid. No effect + * Configures whether or not to clear ch34 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE34 (BIT(2)) @@ -1256,8 +1256,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE34_V 0x00000001U #define SOC_ETM_CH_DISABLE34_S 2 /** SOC_ETM_CH_DISABLE35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel35. - * 0: Invalid. No effect + * Configures whether or not to clear ch35 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE35 (BIT(3)) @@ -1265,8 +1265,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE35_V 0x00000001U #define SOC_ETM_CH_DISABLE35_S 3 /** SOC_ETM_CH_DISABLE36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel36. - * 0: Invalid. No effect + * Configures whether or not to clear ch36 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE36 (BIT(4)) @@ -1274,8 +1274,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE36_V 0x00000001U #define SOC_ETM_CH_DISABLE36_S 4 /** SOC_ETM_CH_DISABLE37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel37. - * 0: Invalid. No effect + * Configures whether or not to clear ch37 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE37 (BIT(5)) @@ -1283,8 +1283,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE37_V 0x00000001U #define SOC_ETM_CH_DISABLE37_S 5 /** SOC_ETM_CH_DISABLE38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel38. - * 0: Invalid. No effect + * Configures whether or not to clear ch38 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE38 (BIT(6)) @@ -1292,8 +1292,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE38_V 0x00000001U #define SOC_ETM_CH_DISABLE38_S 6 /** SOC_ETM_CH_DISABLE39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel39. - * 0: Invalid. No effect + * Configures whether or not to clear ch39 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE39 (BIT(7)) @@ -1301,8 +1301,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE39_V 0x00000001U #define SOC_ETM_CH_DISABLE39_S 7 /** SOC_ETM_CH_DISABLE40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel40. - * 0: Invalid. No effect + * Configures whether or not to clear ch40 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE40 (BIT(8)) @@ -1310,8 +1310,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE40_V 0x00000001U #define SOC_ETM_CH_DISABLE40_S 8 /** SOC_ETM_CH_DISABLE41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel41. - * 0: Invalid. No effect + * Configures whether or not to clear ch41 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE41 (BIT(9)) @@ -1319,8 +1319,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE41_V 0x00000001U #define SOC_ETM_CH_DISABLE41_S 9 /** SOC_ETM_CH_DISABLE42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel42. - * 0: Invalid. No effect + * Configures whether or not to clear ch42 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE42 (BIT(10)) @@ -1328,8 +1328,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE42_V 0x00000001U #define SOC_ETM_CH_DISABLE42_S 10 /** SOC_ETM_CH_DISABLE43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel43. - * 0: Invalid. No effect + * Configures whether or not to clear ch43 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE43 (BIT(11)) @@ -1337,8 +1337,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE43_V 0x00000001U #define SOC_ETM_CH_DISABLE43_S 11 /** SOC_ETM_CH_DISABLE44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel44. - * 0: Invalid. No effect + * Configures whether or not to clear ch44 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE44 (BIT(12)) @@ -1346,8 +1346,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE44_V 0x00000001U #define SOC_ETM_CH_DISABLE44_S 12 /** SOC_ETM_CH_DISABLE45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel45. - * 0: Invalid. No effect + * Configures whether or not to clear ch45 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE45 (BIT(13)) @@ -1355,8 +1355,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE45_V 0x00000001U #define SOC_ETM_CH_DISABLE45_S 13 /** SOC_ETM_CH_DISABLE46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel46. - * 0: Invalid. No effect + * Configures whether or not to clear ch46 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE46 (BIT(14)) @@ -1364,8 +1364,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE46_V 0x00000001U #define SOC_ETM_CH_DISABLE46_S 14 /** SOC_ETM_CH_DISABLE47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel47. - * 0: Invalid. No effect + * Configures whether or not to clear ch47 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE47 (BIT(15)) @@ -1373,8 +1373,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE47_V 0x00000001U #define SOC_ETM_CH_DISABLE47_S 15 /** SOC_ETM_CH_DISABLE48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel48. - * 0: Invalid. No effect + * Configures whether or not to clear ch48 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE48 (BIT(16)) @@ -1382,8 +1382,8 @@ extern "C" { #define SOC_ETM_CH_DISABLE48_V 0x00000001U #define SOC_ETM_CH_DISABLE48_S 16 /** SOC_ETM_CH_DISABLE49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel49. - * 0: Invalid. No effect + * Configures whether or not to clear ch49 enable. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_CH_DISABLE49 (BIT(17)) @@ -1392,11 +1392,11 @@ extern "C" { #define SOC_ETM_CH_DISABLE49_S 17 /** SOC_ETM_CH0_EVT_ID_REG register - * Channel0 event ID register + * Channel0 event id register */ #define SOC_ETM_CH0_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x18) /** SOC_ETM_CH0_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel0 event ID. + * Configures ch0_evt_id */ #define SOC_ETM_CH0_EVT_ID 0x0000007FU #define SOC_ETM_CH0_EVT_ID_M (SOC_ETM_CH0_EVT_ID_V << SOC_ETM_CH0_EVT_ID_S) @@ -1404,11 +1404,11 @@ extern "C" { #define SOC_ETM_CH0_EVT_ID_S 0 /** SOC_ETM_CH0_TASK_ID_REG register - * Channel0 task ID register + * Channel0 task id register */ #define SOC_ETM_CH0_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1c) /** SOC_ETM_CH0_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel0 task ID. + * Configures ch0_task_id */ #define SOC_ETM_CH0_TASK_ID 0x000000FFU #define SOC_ETM_CH0_TASK_ID_M (SOC_ETM_CH0_TASK_ID_V << SOC_ETM_CH0_TASK_ID_S) @@ -1416,11 +1416,11 @@ extern "C" { #define SOC_ETM_CH0_TASK_ID_S 0 /** SOC_ETM_CH1_EVT_ID_REG register - * Channel1 event ID register + * Channel1 event id register */ #define SOC_ETM_CH1_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x20) /** SOC_ETM_CH1_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel1 event ID. + * Configures ch1_evt_id */ #define SOC_ETM_CH1_EVT_ID 0x0000007FU #define SOC_ETM_CH1_EVT_ID_M (SOC_ETM_CH1_EVT_ID_V << SOC_ETM_CH1_EVT_ID_S) @@ -1428,11 +1428,11 @@ extern "C" { #define SOC_ETM_CH1_EVT_ID_S 0 /** SOC_ETM_CH1_TASK_ID_REG register - * Channel1 task ID register + * Channel1 task id register */ #define SOC_ETM_CH1_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x24) /** SOC_ETM_CH1_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel1 task ID. + * Configures ch1_task_id */ #define SOC_ETM_CH1_TASK_ID 0x000000FFU #define SOC_ETM_CH1_TASK_ID_M (SOC_ETM_CH1_TASK_ID_V << SOC_ETM_CH1_TASK_ID_S) @@ -1440,11 +1440,11 @@ extern "C" { #define SOC_ETM_CH1_TASK_ID_S 0 /** SOC_ETM_CH2_EVT_ID_REG register - * Channel2 event ID register + * Channel2 event id register */ #define SOC_ETM_CH2_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x28) /** SOC_ETM_CH2_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel2 event ID. + * Configures ch2_evt_id */ #define SOC_ETM_CH2_EVT_ID 0x0000007FU #define SOC_ETM_CH2_EVT_ID_M (SOC_ETM_CH2_EVT_ID_V << SOC_ETM_CH2_EVT_ID_S) @@ -1452,11 +1452,11 @@ extern "C" { #define SOC_ETM_CH2_EVT_ID_S 0 /** SOC_ETM_CH2_TASK_ID_REG register - * Channel2 task ID register + * Channel2 task id register */ #define SOC_ETM_CH2_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x2c) /** SOC_ETM_CH2_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel2 task ID. + * Configures ch2_task_id */ #define SOC_ETM_CH2_TASK_ID 0x000000FFU #define SOC_ETM_CH2_TASK_ID_M (SOC_ETM_CH2_TASK_ID_V << SOC_ETM_CH2_TASK_ID_S) @@ -1464,11 +1464,11 @@ extern "C" { #define SOC_ETM_CH2_TASK_ID_S 0 /** SOC_ETM_CH3_EVT_ID_REG register - * Channel3 event ID register + * Channel3 event id register */ #define SOC_ETM_CH3_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x30) /** SOC_ETM_CH3_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel3 event ID. + * Configures ch3_evt_id */ #define SOC_ETM_CH3_EVT_ID 0x0000007FU #define SOC_ETM_CH3_EVT_ID_M (SOC_ETM_CH3_EVT_ID_V << SOC_ETM_CH3_EVT_ID_S) @@ -1476,11 +1476,11 @@ extern "C" { #define SOC_ETM_CH3_EVT_ID_S 0 /** SOC_ETM_CH3_TASK_ID_REG register - * Channel3 task ID register + * Channel3 task id register */ #define SOC_ETM_CH3_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x34) /** SOC_ETM_CH3_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel3 task ID. + * Configures ch3_task_id */ #define SOC_ETM_CH3_TASK_ID 0x000000FFU #define SOC_ETM_CH3_TASK_ID_M (SOC_ETM_CH3_TASK_ID_V << SOC_ETM_CH3_TASK_ID_S) @@ -1488,11 +1488,11 @@ extern "C" { #define SOC_ETM_CH3_TASK_ID_S 0 /** SOC_ETM_CH4_EVT_ID_REG register - * Channel4 event ID register + * Channel4 event id register */ #define SOC_ETM_CH4_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x38) /** SOC_ETM_CH4_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel4 event ID. + * Configures ch4_evt_id */ #define SOC_ETM_CH4_EVT_ID 0x0000007FU #define SOC_ETM_CH4_EVT_ID_M (SOC_ETM_CH4_EVT_ID_V << SOC_ETM_CH4_EVT_ID_S) @@ -1500,11 +1500,11 @@ extern "C" { #define SOC_ETM_CH4_EVT_ID_S 0 /** SOC_ETM_CH4_TASK_ID_REG register - * Channel4 task ID register + * Channel4 task id register */ #define SOC_ETM_CH4_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x3c) /** SOC_ETM_CH4_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel4 task ID. + * Configures ch4_task_id */ #define SOC_ETM_CH4_TASK_ID 0x000000FFU #define SOC_ETM_CH4_TASK_ID_M (SOC_ETM_CH4_TASK_ID_V << SOC_ETM_CH4_TASK_ID_S) @@ -1512,11 +1512,11 @@ extern "C" { #define SOC_ETM_CH4_TASK_ID_S 0 /** SOC_ETM_CH5_EVT_ID_REG register - * Channel5 event ID register + * Channel5 event id register */ #define SOC_ETM_CH5_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x40) /** SOC_ETM_CH5_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel5 event ID. + * Configures ch5_evt_id */ #define SOC_ETM_CH5_EVT_ID 0x0000007FU #define SOC_ETM_CH5_EVT_ID_M (SOC_ETM_CH5_EVT_ID_V << SOC_ETM_CH5_EVT_ID_S) @@ -1524,11 +1524,11 @@ extern "C" { #define SOC_ETM_CH5_EVT_ID_S 0 /** SOC_ETM_CH5_TASK_ID_REG register - * Channel5 task ID register + * Channel5 task id register */ #define SOC_ETM_CH5_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x44) /** SOC_ETM_CH5_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel5 task ID. + * Configures ch5_task_id */ #define SOC_ETM_CH5_TASK_ID 0x000000FFU #define SOC_ETM_CH5_TASK_ID_M (SOC_ETM_CH5_TASK_ID_V << SOC_ETM_CH5_TASK_ID_S) @@ -1536,11 +1536,11 @@ extern "C" { #define SOC_ETM_CH5_TASK_ID_S 0 /** SOC_ETM_CH6_EVT_ID_REG register - * Channel6 event ID register + * Channel6 event id register */ #define SOC_ETM_CH6_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x48) /** SOC_ETM_CH6_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel6 event ID. + * Configures ch6_evt_id */ #define SOC_ETM_CH6_EVT_ID 0x0000007FU #define SOC_ETM_CH6_EVT_ID_M (SOC_ETM_CH6_EVT_ID_V << SOC_ETM_CH6_EVT_ID_S) @@ -1548,11 +1548,11 @@ extern "C" { #define SOC_ETM_CH6_EVT_ID_S 0 /** SOC_ETM_CH6_TASK_ID_REG register - * Channel6 task ID register + * Channel6 task id register */ #define SOC_ETM_CH6_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x4c) /** SOC_ETM_CH6_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel6 task ID. + * Configures ch6_task_id */ #define SOC_ETM_CH6_TASK_ID 0x000000FFU #define SOC_ETM_CH6_TASK_ID_M (SOC_ETM_CH6_TASK_ID_V << SOC_ETM_CH6_TASK_ID_S) @@ -1560,11 +1560,11 @@ extern "C" { #define SOC_ETM_CH6_TASK_ID_S 0 /** SOC_ETM_CH7_EVT_ID_REG register - * Channel7 event ID register + * Channel7 event id register */ #define SOC_ETM_CH7_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x50) /** SOC_ETM_CH7_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel7 event ID. + * Configures ch7_evt_id */ #define SOC_ETM_CH7_EVT_ID 0x0000007FU #define SOC_ETM_CH7_EVT_ID_M (SOC_ETM_CH7_EVT_ID_V << SOC_ETM_CH7_EVT_ID_S) @@ -1572,11 +1572,11 @@ extern "C" { #define SOC_ETM_CH7_EVT_ID_S 0 /** SOC_ETM_CH7_TASK_ID_REG register - * Channel7 task ID register + * Channel7 task id register */ #define SOC_ETM_CH7_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x54) /** SOC_ETM_CH7_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel7 task ID. + * Configures ch7_task_id */ #define SOC_ETM_CH7_TASK_ID 0x000000FFU #define SOC_ETM_CH7_TASK_ID_M (SOC_ETM_CH7_TASK_ID_V << SOC_ETM_CH7_TASK_ID_S) @@ -1584,11 +1584,11 @@ extern "C" { #define SOC_ETM_CH7_TASK_ID_S 0 /** SOC_ETM_CH8_EVT_ID_REG register - * Channel8 event ID register + * Channel8 event id register */ #define SOC_ETM_CH8_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x58) /** SOC_ETM_CH8_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel8 event ID. + * Configures ch8_evt_id */ #define SOC_ETM_CH8_EVT_ID 0x0000007FU #define SOC_ETM_CH8_EVT_ID_M (SOC_ETM_CH8_EVT_ID_V << SOC_ETM_CH8_EVT_ID_S) @@ -1596,11 +1596,11 @@ extern "C" { #define SOC_ETM_CH8_EVT_ID_S 0 /** SOC_ETM_CH8_TASK_ID_REG register - * Channel8 task ID register + * Channel8 task id register */ #define SOC_ETM_CH8_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x5c) /** SOC_ETM_CH8_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel8 task ID. + * Configures ch8_task_id */ #define SOC_ETM_CH8_TASK_ID 0x000000FFU #define SOC_ETM_CH8_TASK_ID_M (SOC_ETM_CH8_TASK_ID_V << SOC_ETM_CH8_TASK_ID_S) @@ -1608,11 +1608,11 @@ extern "C" { #define SOC_ETM_CH8_TASK_ID_S 0 /** SOC_ETM_CH9_EVT_ID_REG register - * Channel9 event ID register + * Channel9 event id register */ #define SOC_ETM_CH9_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x60) /** SOC_ETM_CH9_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel9 event ID. + * Configures ch9_evt_id */ #define SOC_ETM_CH9_EVT_ID 0x0000007FU #define SOC_ETM_CH9_EVT_ID_M (SOC_ETM_CH9_EVT_ID_V << SOC_ETM_CH9_EVT_ID_S) @@ -1620,11 +1620,11 @@ extern "C" { #define SOC_ETM_CH9_EVT_ID_S 0 /** SOC_ETM_CH9_TASK_ID_REG register - * Channel9 task ID register + * Channel9 task id register */ #define SOC_ETM_CH9_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x64) /** SOC_ETM_CH9_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel9 task ID. + * Configures ch9_task_id */ #define SOC_ETM_CH9_TASK_ID 0x000000FFU #define SOC_ETM_CH9_TASK_ID_M (SOC_ETM_CH9_TASK_ID_V << SOC_ETM_CH9_TASK_ID_S) @@ -1632,11 +1632,11 @@ extern "C" { #define SOC_ETM_CH9_TASK_ID_S 0 /** SOC_ETM_CH10_EVT_ID_REG register - * Channel10 event ID register + * Channel10 event id register */ #define SOC_ETM_CH10_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x68) /** SOC_ETM_CH10_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel10 event ID. + * Configures ch10_evt_id */ #define SOC_ETM_CH10_EVT_ID 0x0000007FU #define SOC_ETM_CH10_EVT_ID_M (SOC_ETM_CH10_EVT_ID_V << SOC_ETM_CH10_EVT_ID_S) @@ -1644,11 +1644,11 @@ extern "C" { #define SOC_ETM_CH10_EVT_ID_S 0 /** SOC_ETM_CH10_TASK_ID_REG register - * Channel10 task ID register + * Channel10 task id register */ #define SOC_ETM_CH10_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x6c) /** SOC_ETM_CH10_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel10 task ID. + * Configures ch10_task_id */ #define SOC_ETM_CH10_TASK_ID 0x000000FFU #define SOC_ETM_CH10_TASK_ID_M (SOC_ETM_CH10_TASK_ID_V << SOC_ETM_CH10_TASK_ID_S) @@ -1656,11 +1656,11 @@ extern "C" { #define SOC_ETM_CH10_TASK_ID_S 0 /** SOC_ETM_CH11_EVT_ID_REG register - * Channel11 event ID register + * Channel11 event id register */ #define SOC_ETM_CH11_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x70) /** SOC_ETM_CH11_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel11 event ID. + * Configures ch11_evt_id */ #define SOC_ETM_CH11_EVT_ID 0x0000007FU #define SOC_ETM_CH11_EVT_ID_M (SOC_ETM_CH11_EVT_ID_V << SOC_ETM_CH11_EVT_ID_S) @@ -1668,11 +1668,11 @@ extern "C" { #define SOC_ETM_CH11_EVT_ID_S 0 /** SOC_ETM_CH11_TASK_ID_REG register - * Channel11 task ID register + * Channel11 task id register */ #define SOC_ETM_CH11_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x74) /** SOC_ETM_CH11_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel11 task ID. + * Configures ch11_task_id */ #define SOC_ETM_CH11_TASK_ID 0x000000FFU #define SOC_ETM_CH11_TASK_ID_M (SOC_ETM_CH11_TASK_ID_V << SOC_ETM_CH11_TASK_ID_S) @@ -1680,11 +1680,11 @@ extern "C" { #define SOC_ETM_CH11_TASK_ID_S 0 /** SOC_ETM_CH12_EVT_ID_REG register - * Channel12 event ID register + * Channel12 event id register */ #define SOC_ETM_CH12_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x78) /** SOC_ETM_CH12_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel12 event ID. + * Configures ch12_evt_id */ #define SOC_ETM_CH12_EVT_ID 0x0000007FU #define SOC_ETM_CH12_EVT_ID_M (SOC_ETM_CH12_EVT_ID_V << SOC_ETM_CH12_EVT_ID_S) @@ -1692,11 +1692,11 @@ extern "C" { #define SOC_ETM_CH12_EVT_ID_S 0 /** SOC_ETM_CH12_TASK_ID_REG register - * Channel12 task ID register + * Channel12 task id register */ #define SOC_ETM_CH12_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x7c) /** SOC_ETM_CH12_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel12 task ID. + * Configures ch12_task_id */ #define SOC_ETM_CH12_TASK_ID 0x000000FFU #define SOC_ETM_CH12_TASK_ID_M (SOC_ETM_CH12_TASK_ID_V << SOC_ETM_CH12_TASK_ID_S) @@ -1704,11 +1704,11 @@ extern "C" { #define SOC_ETM_CH12_TASK_ID_S 0 /** SOC_ETM_CH13_EVT_ID_REG register - * Channel13 event ID register + * Channel13 event id register */ #define SOC_ETM_CH13_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x80) /** SOC_ETM_CH13_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel13 event ID. + * Configures ch13_evt_id */ #define SOC_ETM_CH13_EVT_ID 0x0000007FU #define SOC_ETM_CH13_EVT_ID_M (SOC_ETM_CH13_EVT_ID_V << SOC_ETM_CH13_EVT_ID_S) @@ -1716,11 +1716,11 @@ extern "C" { #define SOC_ETM_CH13_EVT_ID_S 0 /** SOC_ETM_CH13_TASK_ID_REG register - * Channel13 task ID register + * Channel13 task id register */ #define SOC_ETM_CH13_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x84) /** SOC_ETM_CH13_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel13 task ID. + * Configures ch13_task_id */ #define SOC_ETM_CH13_TASK_ID 0x000000FFU #define SOC_ETM_CH13_TASK_ID_M (SOC_ETM_CH13_TASK_ID_V << SOC_ETM_CH13_TASK_ID_S) @@ -1728,11 +1728,11 @@ extern "C" { #define SOC_ETM_CH13_TASK_ID_S 0 /** SOC_ETM_CH14_EVT_ID_REG register - * Channel14 event ID register + * Channel14 event id register */ #define SOC_ETM_CH14_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x88) /** SOC_ETM_CH14_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel14 event ID. + * Configures ch14_evt_id */ #define SOC_ETM_CH14_EVT_ID 0x0000007FU #define SOC_ETM_CH14_EVT_ID_M (SOC_ETM_CH14_EVT_ID_V << SOC_ETM_CH14_EVT_ID_S) @@ -1740,11 +1740,11 @@ extern "C" { #define SOC_ETM_CH14_EVT_ID_S 0 /** SOC_ETM_CH14_TASK_ID_REG register - * Channel14 task ID register + * Channel14 task id register */ #define SOC_ETM_CH14_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x8c) /** SOC_ETM_CH14_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel14 task ID. + * Configures ch14_task_id */ #define SOC_ETM_CH14_TASK_ID 0x000000FFU #define SOC_ETM_CH14_TASK_ID_M (SOC_ETM_CH14_TASK_ID_V << SOC_ETM_CH14_TASK_ID_S) @@ -1752,11 +1752,11 @@ extern "C" { #define SOC_ETM_CH14_TASK_ID_S 0 /** SOC_ETM_CH15_EVT_ID_REG register - * Channel15 event ID register + * Channel15 event id register */ #define SOC_ETM_CH15_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x90) /** SOC_ETM_CH15_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel15 event ID. + * Configures ch15_evt_id */ #define SOC_ETM_CH15_EVT_ID 0x0000007FU #define SOC_ETM_CH15_EVT_ID_M (SOC_ETM_CH15_EVT_ID_V << SOC_ETM_CH15_EVT_ID_S) @@ -1764,11 +1764,11 @@ extern "C" { #define SOC_ETM_CH15_EVT_ID_S 0 /** SOC_ETM_CH15_TASK_ID_REG register - * Channel15 task ID register + * Channel15 task id register */ #define SOC_ETM_CH15_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x94) /** SOC_ETM_CH15_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel15 task ID. + * Configures ch15_task_id */ #define SOC_ETM_CH15_TASK_ID 0x000000FFU #define SOC_ETM_CH15_TASK_ID_M (SOC_ETM_CH15_TASK_ID_V << SOC_ETM_CH15_TASK_ID_S) @@ -1776,11 +1776,11 @@ extern "C" { #define SOC_ETM_CH15_TASK_ID_S 0 /** SOC_ETM_CH16_EVT_ID_REG register - * Channel16 event ID register + * Channel16 event id register */ #define SOC_ETM_CH16_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x98) /** SOC_ETM_CH16_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel16 event ID. + * Configures ch16_evt_id */ #define SOC_ETM_CH16_EVT_ID 0x0000007FU #define SOC_ETM_CH16_EVT_ID_M (SOC_ETM_CH16_EVT_ID_V << SOC_ETM_CH16_EVT_ID_S) @@ -1788,11 +1788,11 @@ extern "C" { #define SOC_ETM_CH16_EVT_ID_S 0 /** SOC_ETM_CH16_TASK_ID_REG register - * Channel16 task ID register + * Channel16 task id register */ #define SOC_ETM_CH16_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x9c) /** SOC_ETM_CH16_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel16 task ID. + * Configures ch16_task_id */ #define SOC_ETM_CH16_TASK_ID 0x000000FFU #define SOC_ETM_CH16_TASK_ID_M (SOC_ETM_CH16_TASK_ID_V << SOC_ETM_CH16_TASK_ID_S) @@ -1800,11 +1800,11 @@ extern "C" { #define SOC_ETM_CH16_TASK_ID_S 0 /** SOC_ETM_CH17_EVT_ID_REG register - * Channel17 event ID register + * Channel17 event id register */ #define SOC_ETM_CH17_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa0) /** SOC_ETM_CH17_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel17 event ID. + * Configures ch17_evt_id */ #define SOC_ETM_CH17_EVT_ID 0x0000007FU #define SOC_ETM_CH17_EVT_ID_M (SOC_ETM_CH17_EVT_ID_V << SOC_ETM_CH17_EVT_ID_S) @@ -1812,11 +1812,11 @@ extern "C" { #define SOC_ETM_CH17_EVT_ID_S 0 /** SOC_ETM_CH17_TASK_ID_REG register - * Channel17 task ID register + * Channel17 task id register */ #define SOC_ETM_CH17_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xa4) /** SOC_ETM_CH17_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel17 task ID. + * Configures ch17_task_id */ #define SOC_ETM_CH17_TASK_ID 0x000000FFU #define SOC_ETM_CH17_TASK_ID_M (SOC_ETM_CH17_TASK_ID_V << SOC_ETM_CH17_TASK_ID_S) @@ -1824,11 +1824,11 @@ extern "C" { #define SOC_ETM_CH17_TASK_ID_S 0 /** SOC_ETM_CH18_EVT_ID_REG register - * Channel18 event ID register + * Channel18 event id register */ #define SOC_ETM_CH18_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xa8) /** SOC_ETM_CH18_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel18 event ID. + * Configures ch18_evt_id */ #define SOC_ETM_CH18_EVT_ID 0x0000007FU #define SOC_ETM_CH18_EVT_ID_M (SOC_ETM_CH18_EVT_ID_V << SOC_ETM_CH18_EVT_ID_S) @@ -1836,11 +1836,11 @@ extern "C" { #define SOC_ETM_CH18_EVT_ID_S 0 /** SOC_ETM_CH18_TASK_ID_REG register - * Channel18 task ID register + * Channel18 task id register */ #define SOC_ETM_CH18_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xac) /** SOC_ETM_CH18_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel18 task ID. + * Configures ch18_task_id */ #define SOC_ETM_CH18_TASK_ID 0x000000FFU #define SOC_ETM_CH18_TASK_ID_M (SOC_ETM_CH18_TASK_ID_V << SOC_ETM_CH18_TASK_ID_S) @@ -1848,11 +1848,11 @@ extern "C" { #define SOC_ETM_CH18_TASK_ID_S 0 /** SOC_ETM_CH19_EVT_ID_REG register - * Channel19 event ID register + * Channel19 event id register */ #define SOC_ETM_CH19_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb0) /** SOC_ETM_CH19_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel19 event ID. + * Configures ch19_evt_id */ #define SOC_ETM_CH19_EVT_ID 0x0000007FU #define SOC_ETM_CH19_EVT_ID_M (SOC_ETM_CH19_EVT_ID_V << SOC_ETM_CH19_EVT_ID_S) @@ -1860,11 +1860,11 @@ extern "C" { #define SOC_ETM_CH19_EVT_ID_S 0 /** SOC_ETM_CH19_TASK_ID_REG register - * Channel19 task ID register + * Channel19 task id register */ #define SOC_ETM_CH19_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xb4) /** SOC_ETM_CH19_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel19 task ID. + * Configures ch19_task_id */ #define SOC_ETM_CH19_TASK_ID 0x000000FFU #define SOC_ETM_CH19_TASK_ID_M (SOC_ETM_CH19_TASK_ID_V << SOC_ETM_CH19_TASK_ID_S) @@ -1872,11 +1872,11 @@ extern "C" { #define SOC_ETM_CH19_TASK_ID_S 0 /** SOC_ETM_CH20_EVT_ID_REG register - * Channel20 event ID register + * Channel20 event id register */ #define SOC_ETM_CH20_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xb8) /** SOC_ETM_CH20_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel20 event ID. + * Configures ch20_evt_id */ #define SOC_ETM_CH20_EVT_ID 0x0000007FU #define SOC_ETM_CH20_EVT_ID_M (SOC_ETM_CH20_EVT_ID_V << SOC_ETM_CH20_EVT_ID_S) @@ -1884,11 +1884,11 @@ extern "C" { #define SOC_ETM_CH20_EVT_ID_S 0 /** SOC_ETM_CH20_TASK_ID_REG register - * Channel20 task ID register + * Channel20 task id register */ #define SOC_ETM_CH20_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xbc) /** SOC_ETM_CH20_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel20 task ID. + * Configures ch20_task_id */ #define SOC_ETM_CH20_TASK_ID 0x000000FFU #define SOC_ETM_CH20_TASK_ID_M (SOC_ETM_CH20_TASK_ID_V << SOC_ETM_CH20_TASK_ID_S) @@ -1896,11 +1896,11 @@ extern "C" { #define SOC_ETM_CH20_TASK_ID_S 0 /** SOC_ETM_CH21_EVT_ID_REG register - * Channel21 event ID register + * Channel21 event id register */ #define SOC_ETM_CH21_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc0) /** SOC_ETM_CH21_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel21 event ID. + * Configures ch21_evt_id */ #define SOC_ETM_CH21_EVT_ID 0x0000007FU #define SOC_ETM_CH21_EVT_ID_M (SOC_ETM_CH21_EVT_ID_V << SOC_ETM_CH21_EVT_ID_S) @@ -1908,11 +1908,11 @@ extern "C" { #define SOC_ETM_CH21_EVT_ID_S 0 /** SOC_ETM_CH21_TASK_ID_REG register - * Channel21 task ID register + * Channel21 task id register */ #define SOC_ETM_CH21_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xc4) /** SOC_ETM_CH21_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel21 task ID. + * Configures ch21_task_id */ #define SOC_ETM_CH21_TASK_ID 0x000000FFU #define SOC_ETM_CH21_TASK_ID_M (SOC_ETM_CH21_TASK_ID_V << SOC_ETM_CH21_TASK_ID_S) @@ -1920,11 +1920,11 @@ extern "C" { #define SOC_ETM_CH21_TASK_ID_S 0 /** SOC_ETM_CH22_EVT_ID_REG register - * Channel22 event ID register + * Channel22 event id register */ #define SOC_ETM_CH22_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xc8) /** SOC_ETM_CH22_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel22 event ID. + * Configures ch22_evt_id */ #define SOC_ETM_CH22_EVT_ID 0x0000007FU #define SOC_ETM_CH22_EVT_ID_M (SOC_ETM_CH22_EVT_ID_V << SOC_ETM_CH22_EVT_ID_S) @@ -1932,11 +1932,11 @@ extern "C" { #define SOC_ETM_CH22_EVT_ID_S 0 /** SOC_ETM_CH22_TASK_ID_REG register - * Channel22 task ID register + * Channel22 task id register */ #define SOC_ETM_CH22_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xcc) /** SOC_ETM_CH22_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel22 task ID. + * Configures ch22_task_id */ #define SOC_ETM_CH22_TASK_ID 0x000000FFU #define SOC_ETM_CH22_TASK_ID_M (SOC_ETM_CH22_TASK_ID_V << SOC_ETM_CH22_TASK_ID_S) @@ -1944,11 +1944,11 @@ extern "C" { #define SOC_ETM_CH22_TASK_ID_S 0 /** SOC_ETM_CH23_EVT_ID_REG register - * Channel23 event ID register + * Channel23 event id register */ #define SOC_ETM_CH23_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd0) /** SOC_ETM_CH23_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel23 event ID. + * Configures ch23_evt_id */ #define SOC_ETM_CH23_EVT_ID 0x0000007FU #define SOC_ETM_CH23_EVT_ID_M (SOC_ETM_CH23_EVT_ID_V << SOC_ETM_CH23_EVT_ID_S) @@ -1956,11 +1956,11 @@ extern "C" { #define SOC_ETM_CH23_EVT_ID_S 0 /** SOC_ETM_CH23_TASK_ID_REG register - * Channel23 task ID register + * Channel23 task id register */ #define SOC_ETM_CH23_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xd4) /** SOC_ETM_CH23_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel23 task ID. + * Configures ch23_task_id */ #define SOC_ETM_CH23_TASK_ID 0x000000FFU #define SOC_ETM_CH23_TASK_ID_M (SOC_ETM_CH23_TASK_ID_V << SOC_ETM_CH23_TASK_ID_S) @@ -1968,11 +1968,11 @@ extern "C" { #define SOC_ETM_CH23_TASK_ID_S 0 /** SOC_ETM_CH24_EVT_ID_REG register - * Channel24 event ID register + * Channel24 event id register */ #define SOC_ETM_CH24_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xd8) /** SOC_ETM_CH24_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel24 event ID. + * Configures ch24_evt_id */ #define SOC_ETM_CH24_EVT_ID 0x0000007FU #define SOC_ETM_CH24_EVT_ID_M (SOC_ETM_CH24_EVT_ID_V << SOC_ETM_CH24_EVT_ID_S) @@ -1980,11 +1980,11 @@ extern "C" { #define SOC_ETM_CH24_EVT_ID_S 0 /** SOC_ETM_CH24_TASK_ID_REG register - * Channel24 task ID register + * Channel24 task id register */ #define SOC_ETM_CH24_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xdc) /** SOC_ETM_CH24_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel24 task ID. + * Configures ch24_task_id */ #define SOC_ETM_CH24_TASK_ID 0x000000FFU #define SOC_ETM_CH24_TASK_ID_M (SOC_ETM_CH24_TASK_ID_V << SOC_ETM_CH24_TASK_ID_S) @@ -1992,11 +1992,11 @@ extern "C" { #define SOC_ETM_CH24_TASK_ID_S 0 /** SOC_ETM_CH25_EVT_ID_REG register - * Channel25 event ID register + * Channel25 event id register */ #define SOC_ETM_CH25_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe0) /** SOC_ETM_CH25_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel25 event ID. + * Configures ch25_evt_id */ #define SOC_ETM_CH25_EVT_ID 0x0000007FU #define SOC_ETM_CH25_EVT_ID_M (SOC_ETM_CH25_EVT_ID_V << SOC_ETM_CH25_EVT_ID_S) @@ -2004,11 +2004,11 @@ extern "C" { #define SOC_ETM_CH25_EVT_ID_S 0 /** SOC_ETM_CH25_TASK_ID_REG register - * Channel25 task ID register + * Channel25 task id register */ #define SOC_ETM_CH25_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xe4) /** SOC_ETM_CH25_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel25 task ID. + * Configures ch25_task_id */ #define SOC_ETM_CH25_TASK_ID 0x000000FFU #define SOC_ETM_CH25_TASK_ID_M (SOC_ETM_CH25_TASK_ID_V << SOC_ETM_CH25_TASK_ID_S) @@ -2016,11 +2016,11 @@ extern "C" { #define SOC_ETM_CH25_TASK_ID_S 0 /** SOC_ETM_CH26_EVT_ID_REG register - * Channel26 event ID register + * Channel26 event id register */ #define SOC_ETM_CH26_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xe8) /** SOC_ETM_CH26_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel26 event ID. + * Configures ch26_evt_id */ #define SOC_ETM_CH26_EVT_ID 0x0000007FU #define SOC_ETM_CH26_EVT_ID_M (SOC_ETM_CH26_EVT_ID_V << SOC_ETM_CH26_EVT_ID_S) @@ -2028,11 +2028,11 @@ extern "C" { #define SOC_ETM_CH26_EVT_ID_S 0 /** SOC_ETM_CH26_TASK_ID_REG register - * Channel26 task ID register + * Channel26 task id register */ #define SOC_ETM_CH26_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xec) /** SOC_ETM_CH26_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel26 task ID. + * Configures ch26_task_id */ #define SOC_ETM_CH26_TASK_ID 0x000000FFU #define SOC_ETM_CH26_TASK_ID_M (SOC_ETM_CH26_TASK_ID_V << SOC_ETM_CH26_TASK_ID_S) @@ -2040,11 +2040,11 @@ extern "C" { #define SOC_ETM_CH26_TASK_ID_S 0 /** SOC_ETM_CH27_EVT_ID_REG register - * Channel27 event ID register + * Channel27 event id register */ #define SOC_ETM_CH27_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf0) /** SOC_ETM_CH27_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel27 event ID. + * Configures ch27_evt_id */ #define SOC_ETM_CH27_EVT_ID 0x0000007FU #define SOC_ETM_CH27_EVT_ID_M (SOC_ETM_CH27_EVT_ID_V << SOC_ETM_CH27_EVT_ID_S) @@ -2052,11 +2052,11 @@ extern "C" { #define SOC_ETM_CH27_EVT_ID_S 0 /** SOC_ETM_CH27_TASK_ID_REG register - * Channel27 task ID register + * Channel27 task id register */ #define SOC_ETM_CH27_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xf4) /** SOC_ETM_CH27_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel27 task ID. + * Configures ch27_task_id */ #define SOC_ETM_CH27_TASK_ID 0x000000FFU #define SOC_ETM_CH27_TASK_ID_M (SOC_ETM_CH27_TASK_ID_V << SOC_ETM_CH27_TASK_ID_S) @@ -2064,11 +2064,11 @@ extern "C" { #define SOC_ETM_CH27_TASK_ID_S 0 /** SOC_ETM_CH28_EVT_ID_REG register - * Channel28 event ID register + * Channel28 event id register */ #define SOC_ETM_CH28_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0xf8) /** SOC_ETM_CH28_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel28 event ID. + * Configures ch28_evt_id */ #define SOC_ETM_CH28_EVT_ID 0x0000007FU #define SOC_ETM_CH28_EVT_ID_M (SOC_ETM_CH28_EVT_ID_V << SOC_ETM_CH28_EVT_ID_S) @@ -2076,11 +2076,11 @@ extern "C" { #define SOC_ETM_CH28_EVT_ID_S 0 /** SOC_ETM_CH28_TASK_ID_REG register - * Channel28 task ID register + * Channel28 task id register */ #define SOC_ETM_CH28_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0xfc) /** SOC_ETM_CH28_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel28 task ID. + * Configures ch28_task_id */ #define SOC_ETM_CH28_TASK_ID 0x000000FFU #define SOC_ETM_CH28_TASK_ID_M (SOC_ETM_CH28_TASK_ID_V << SOC_ETM_CH28_TASK_ID_S) @@ -2088,11 +2088,11 @@ extern "C" { #define SOC_ETM_CH28_TASK_ID_S 0 /** SOC_ETM_CH29_EVT_ID_REG register - * Channel29 event ID register + * Channel29 event id register */ #define SOC_ETM_CH29_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x100) /** SOC_ETM_CH29_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel29 event ID. + * Configures ch29_evt_id */ #define SOC_ETM_CH29_EVT_ID 0x0000007FU #define SOC_ETM_CH29_EVT_ID_M (SOC_ETM_CH29_EVT_ID_V << SOC_ETM_CH29_EVT_ID_S) @@ -2100,11 +2100,11 @@ extern "C" { #define SOC_ETM_CH29_EVT_ID_S 0 /** SOC_ETM_CH29_TASK_ID_REG register - * Channel29 task ID register + * Channel29 task id register */ #define SOC_ETM_CH29_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x104) /** SOC_ETM_CH29_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel29 task ID. + * Configures ch29_task_id */ #define SOC_ETM_CH29_TASK_ID 0x000000FFU #define SOC_ETM_CH29_TASK_ID_M (SOC_ETM_CH29_TASK_ID_V << SOC_ETM_CH29_TASK_ID_S) @@ -2112,11 +2112,11 @@ extern "C" { #define SOC_ETM_CH29_TASK_ID_S 0 /** SOC_ETM_CH30_EVT_ID_REG register - * Channel30 event ID register + * Channel30 event id register */ #define SOC_ETM_CH30_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x108) /** SOC_ETM_CH30_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel30 event ID. + * Configures ch30_evt_id */ #define SOC_ETM_CH30_EVT_ID 0x0000007FU #define SOC_ETM_CH30_EVT_ID_M (SOC_ETM_CH30_EVT_ID_V << SOC_ETM_CH30_EVT_ID_S) @@ -2124,11 +2124,11 @@ extern "C" { #define SOC_ETM_CH30_EVT_ID_S 0 /** SOC_ETM_CH30_TASK_ID_REG register - * Channel30 task ID register + * Channel30 task id register */ #define SOC_ETM_CH30_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x10c) /** SOC_ETM_CH30_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel30 task ID. + * Configures ch30_task_id */ #define SOC_ETM_CH30_TASK_ID 0x000000FFU #define SOC_ETM_CH30_TASK_ID_M (SOC_ETM_CH30_TASK_ID_V << SOC_ETM_CH30_TASK_ID_S) @@ -2136,11 +2136,11 @@ extern "C" { #define SOC_ETM_CH30_TASK_ID_S 0 /** SOC_ETM_CH31_EVT_ID_REG register - * Channel31 event ID register + * Channel31 event id register */ #define SOC_ETM_CH31_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x110) /** SOC_ETM_CH31_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel31 event ID. + * Configures ch31_evt_id */ #define SOC_ETM_CH31_EVT_ID 0x0000007FU #define SOC_ETM_CH31_EVT_ID_M (SOC_ETM_CH31_EVT_ID_V << SOC_ETM_CH31_EVT_ID_S) @@ -2148,11 +2148,11 @@ extern "C" { #define SOC_ETM_CH31_EVT_ID_S 0 /** SOC_ETM_CH31_TASK_ID_REG register - * Channel31 task ID register + * Channel31 task id register */ #define SOC_ETM_CH31_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x114) /** SOC_ETM_CH31_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel31 task ID. + * Configures ch31_task_id */ #define SOC_ETM_CH31_TASK_ID 0x000000FFU #define SOC_ETM_CH31_TASK_ID_M (SOC_ETM_CH31_TASK_ID_V << SOC_ETM_CH31_TASK_ID_S) @@ -2160,11 +2160,11 @@ extern "C" { #define SOC_ETM_CH31_TASK_ID_S 0 /** SOC_ETM_CH32_EVT_ID_REG register - * Channel32 event ID register + * Channel32 event id register */ #define SOC_ETM_CH32_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x118) /** SOC_ETM_CH32_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel32 event ID. + * Configures ch32_evt_id */ #define SOC_ETM_CH32_EVT_ID 0x0000007FU #define SOC_ETM_CH32_EVT_ID_M (SOC_ETM_CH32_EVT_ID_V << SOC_ETM_CH32_EVT_ID_S) @@ -2172,11 +2172,11 @@ extern "C" { #define SOC_ETM_CH32_EVT_ID_S 0 /** SOC_ETM_CH32_TASK_ID_REG register - * Channel32 task ID register + * Channel32 task id register */ #define SOC_ETM_CH32_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x11c) /** SOC_ETM_CH32_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel32 task ID. + * Configures ch32_task_id */ #define SOC_ETM_CH32_TASK_ID 0x000000FFU #define SOC_ETM_CH32_TASK_ID_M (SOC_ETM_CH32_TASK_ID_V << SOC_ETM_CH32_TASK_ID_S) @@ -2184,11 +2184,11 @@ extern "C" { #define SOC_ETM_CH32_TASK_ID_S 0 /** SOC_ETM_CH33_EVT_ID_REG register - * Channel33 event ID register + * Channel33 event id register */ #define SOC_ETM_CH33_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x120) /** SOC_ETM_CH33_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel33 event ID. + * Configures ch33_evt_id */ #define SOC_ETM_CH33_EVT_ID 0x0000007FU #define SOC_ETM_CH33_EVT_ID_M (SOC_ETM_CH33_EVT_ID_V << SOC_ETM_CH33_EVT_ID_S) @@ -2196,11 +2196,11 @@ extern "C" { #define SOC_ETM_CH33_EVT_ID_S 0 /** SOC_ETM_CH33_TASK_ID_REG register - * Channel33 task ID register + * Channel33 task id register */ #define SOC_ETM_CH33_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x124) /** SOC_ETM_CH33_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel33 task ID. + * Configures ch33_task_id */ #define SOC_ETM_CH33_TASK_ID 0x000000FFU #define SOC_ETM_CH33_TASK_ID_M (SOC_ETM_CH33_TASK_ID_V << SOC_ETM_CH33_TASK_ID_S) @@ -2208,11 +2208,11 @@ extern "C" { #define SOC_ETM_CH33_TASK_ID_S 0 /** SOC_ETM_CH34_EVT_ID_REG register - * Channel34 event ID register + * Channel34 event id register */ #define SOC_ETM_CH34_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x128) /** SOC_ETM_CH34_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel34 event ID. + * Configures ch34_evt_id */ #define SOC_ETM_CH34_EVT_ID 0x0000007FU #define SOC_ETM_CH34_EVT_ID_M (SOC_ETM_CH34_EVT_ID_V << SOC_ETM_CH34_EVT_ID_S) @@ -2220,11 +2220,11 @@ extern "C" { #define SOC_ETM_CH34_EVT_ID_S 0 /** SOC_ETM_CH34_TASK_ID_REG register - * Channel34 task ID register + * Channel34 task id register */ #define SOC_ETM_CH34_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x12c) /** SOC_ETM_CH34_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel34 task ID. + * Configures ch34_task_id */ #define SOC_ETM_CH34_TASK_ID 0x000000FFU #define SOC_ETM_CH34_TASK_ID_M (SOC_ETM_CH34_TASK_ID_V << SOC_ETM_CH34_TASK_ID_S) @@ -2232,11 +2232,11 @@ extern "C" { #define SOC_ETM_CH34_TASK_ID_S 0 /** SOC_ETM_CH35_EVT_ID_REG register - * Channel35 event ID register + * Channel35 event id register */ #define SOC_ETM_CH35_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x130) /** SOC_ETM_CH35_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel35 event ID. + * Configures ch35_evt_id */ #define SOC_ETM_CH35_EVT_ID 0x0000007FU #define SOC_ETM_CH35_EVT_ID_M (SOC_ETM_CH35_EVT_ID_V << SOC_ETM_CH35_EVT_ID_S) @@ -2244,11 +2244,11 @@ extern "C" { #define SOC_ETM_CH35_EVT_ID_S 0 /** SOC_ETM_CH35_TASK_ID_REG register - * Channel35 task ID register + * Channel35 task id register */ #define SOC_ETM_CH35_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x134) /** SOC_ETM_CH35_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel35 task ID. + * Configures ch35_task_id */ #define SOC_ETM_CH35_TASK_ID 0x000000FFU #define SOC_ETM_CH35_TASK_ID_M (SOC_ETM_CH35_TASK_ID_V << SOC_ETM_CH35_TASK_ID_S) @@ -2256,11 +2256,11 @@ extern "C" { #define SOC_ETM_CH35_TASK_ID_S 0 /** SOC_ETM_CH36_EVT_ID_REG register - * Channel36 event ID register + * Channel36 event id register */ #define SOC_ETM_CH36_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x138) /** SOC_ETM_CH36_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel36 event ID. + * Configures ch36_evt_id */ #define SOC_ETM_CH36_EVT_ID 0x0000007FU #define SOC_ETM_CH36_EVT_ID_M (SOC_ETM_CH36_EVT_ID_V << SOC_ETM_CH36_EVT_ID_S) @@ -2268,11 +2268,11 @@ extern "C" { #define SOC_ETM_CH36_EVT_ID_S 0 /** SOC_ETM_CH36_TASK_ID_REG register - * Channel36 task ID register + * Channel36 task id register */ #define SOC_ETM_CH36_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x13c) /** SOC_ETM_CH36_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel36 task ID. + * Configures ch36_task_id */ #define SOC_ETM_CH36_TASK_ID 0x000000FFU #define SOC_ETM_CH36_TASK_ID_M (SOC_ETM_CH36_TASK_ID_V << SOC_ETM_CH36_TASK_ID_S) @@ -2280,11 +2280,11 @@ extern "C" { #define SOC_ETM_CH36_TASK_ID_S 0 /** SOC_ETM_CH37_EVT_ID_REG register - * Channel37 event ID register + * Channel37 event id register */ #define SOC_ETM_CH37_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x140) /** SOC_ETM_CH37_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel37 event ID. + * Configures ch37_evt_id */ #define SOC_ETM_CH37_EVT_ID 0x0000007FU #define SOC_ETM_CH37_EVT_ID_M (SOC_ETM_CH37_EVT_ID_V << SOC_ETM_CH37_EVT_ID_S) @@ -2292,11 +2292,11 @@ extern "C" { #define SOC_ETM_CH37_EVT_ID_S 0 /** SOC_ETM_CH37_TASK_ID_REG register - * Channel37 task ID register + * Channel37 task id register */ #define SOC_ETM_CH37_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x144) /** SOC_ETM_CH37_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel37 task ID. + * Configures ch37_task_id */ #define SOC_ETM_CH37_TASK_ID 0x000000FFU #define SOC_ETM_CH37_TASK_ID_M (SOC_ETM_CH37_TASK_ID_V << SOC_ETM_CH37_TASK_ID_S) @@ -2304,11 +2304,11 @@ extern "C" { #define SOC_ETM_CH37_TASK_ID_S 0 /** SOC_ETM_CH38_EVT_ID_REG register - * Channel38 event ID register + * Channel38 event id register */ #define SOC_ETM_CH38_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x148) /** SOC_ETM_CH38_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel38 event ID. + * Configures ch38_evt_id */ #define SOC_ETM_CH38_EVT_ID 0x0000007FU #define SOC_ETM_CH38_EVT_ID_M (SOC_ETM_CH38_EVT_ID_V << SOC_ETM_CH38_EVT_ID_S) @@ -2316,11 +2316,11 @@ extern "C" { #define SOC_ETM_CH38_EVT_ID_S 0 /** SOC_ETM_CH38_TASK_ID_REG register - * Channel38 task ID register + * Channel38 task id register */ #define SOC_ETM_CH38_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x14c) /** SOC_ETM_CH38_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel38 task ID. + * Configures ch38_task_id */ #define SOC_ETM_CH38_TASK_ID 0x000000FFU #define SOC_ETM_CH38_TASK_ID_M (SOC_ETM_CH38_TASK_ID_V << SOC_ETM_CH38_TASK_ID_S) @@ -2328,11 +2328,11 @@ extern "C" { #define SOC_ETM_CH38_TASK_ID_S 0 /** SOC_ETM_CH39_EVT_ID_REG register - * Channel39 event ID register + * Channel39 event id register */ #define SOC_ETM_CH39_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x150) /** SOC_ETM_CH39_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel39 event ID. + * Configures ch39_evt_id */ #define SOC_ETM_CH39_EVT_ID 0x0000007FU #define SOC_ETM_CH39_EVT_ID_M (SOC_ETM_CH39_EVT_ID_V << SOC_ETM_CH39_EVT_ID_S) @@ -2340,11 +2340,11 @@ extern "C" { #define SOC_ETM_CH39_EVT_ID_S 0 /** SOC_ETM_CH39_TASK_ID_REG register - * Channel39 task ID register + * Channel39 task id register */ #define SOC_ETM_CH39_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x154) /** SOC_ETM_CH39_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel39 task ID. + * Configures ch39_task_id */ #define SOC_ETM_CH39_TASK_ID 0x000000FFU #define SOC_ETM_CH39_TASK_ID_M (SOC_ETM_CH39_TASK_ID_V << SOC_ETM_CH39_TASK_ID_S) @@ -2352,11 +2352,11 @@ extern "C" { #define SOC_ETM_CH39_TASK_ID_S 0 /** SOC_ETM_CH40_EVT_ID_REG register - * Channel40 event ID register + * Channel40 event id register */ #define SOC_ETM_CH40_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x158) /** SOC_ETM_CH40_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel40 event ID. + * Configures ch40_evt_id */ #define SOC_ETM_CH40_EVT_ID 0x0000007FU #define SOC_ETM_CH40_EVT_ID_M (SOC_ETM_CH40_EVT_ID_V << SOC_ETM_CH40_EVT_ID_S) @@ -2364,11 +2364,11 @@ extern "C" { #define SOC_ETM_CH40_EVT_ID_S 0 /** SOC_ETM_CH40_TASK_ID_REG register - * Channel40 task ID register + * Channel40 task id register */ #define SOC_ETM_CH40_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x15c) /** SOC_ETM_CH40_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel40 task ID. + * Configures ch40_task_id */ #define SOC_ETM_CH40_TASK_ID 0x000000FFU #define SOC_ETM_CH40_TASK_ID_M (SOC_ETM_CH40_TASK_ID_V << SOC_ETM_CH40_TASK_ID_S) @@ -2376,11 +2376,11 @@ extern "C" { #define SOC_ETM_CH40_TASK_ID_S 0 /** SOC_ETM_CH41_EVT_ID_REG register - * Channel41 event ID register + * Channel41 event id register */ #define SOC_ETM_CH41_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x160) /** SOC_ETM_CH41_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel41 event ID. + * Configures ch41_evt_id */ #define SOC_ETM_CH41_EVT_ID 0x0000007FU #define SOC_ETM_CH41_EVT_ID_M (SOC_ETM_CH41_EVT_ID_V << SOC_ETM_CH41_EVT_ID_S) @@ -2388,11 +2388,11 @@ extern "C" { #define SOC_ETM_CH41_EVT_ID_S 0 /** SOC_ETM_CH41_TASK_ID_REG register - * Channel41 task ID register + * Channel41 task id register */ #define SOC_ETM_CH41_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x164) /** SOC_ETM_CH41_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel41 task ID. + * Configures ch41_task_id */ #define SOC_ETM_CH41_TASK_ID 0x000000FFU #define SOC_ETM_CH41_TASK_ID_M (SOC_ETM_CH41_TASK_ID_V << SOC_ETM_CH41_TASK_ID_S) @@ -2400,11 +2400,11 @@ extern "C" { #define SOC_ETM_CH41_TASK_ID_S 0 /** SOC_ETM_CH42_EVT_ID_REG register - * Channel42 event ID register + * Channel42 event id register */ #define SOC_ETM_CH42_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x168) /** SOC_ETM_CH42_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel42 event ID. + * Configures ch42_evt_id */ #define SOC_ETM_CH42_EVT_ID 0x0000007FU #define SOC_ETM_CH42_EVT_ID_M (SOC_ETM_CH42_EVT_ID_V << SOC_ETM_CH42_EVT_ID_S) @@ -2412,11 +2412,11 @@ extern "C" { #define SOC_ETM_CH42_EVT_ID_S 0 /** SOC_ETM_CH42_TASK_ID_REG register - * Channel42 task ID register + * Channel42 task id register */ #define SOC_ETM_CH42_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x16c) /** SOC_ETM_CH42_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel42 task ID. + * Configures ch42_task_id */ #define SOC_ETM_CH42_TASK_ID 0x000000FFU #define SOC_ETM_CH42_TASK_ID_M (SOC_ETM_CH42_TASK_ID_V << SOC_ETM_CH42_TASK_ID_S) @@ -2424,11 +2424,11 @@ extern "C" { #define SOC_ETM_CH42_TASK_ID_S 0 /** SOC_ETM_CH43_EVT_ID_REG register - * Channel43 event ID register + * Channel43 event id register */ #define SOC_ETM_CH43_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x170) /** SOC_ETM_CH43_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel43 event ID. + * Configures ch43_evt_id */ #define SOC_ETM_CH43_EVT_ID 0x0000007FU #define SOC_ETM_CH43_EVT_ID_M (SOC_ETM_CH43_EVT_ID_V << SOC_ETM_CH43_EVT_ID_S) @@ -2436,11 +2436,11 @@ extern "C" { #define SOC_ETM_CH43_EVT_ID_S 0 /** SOC_ETM_CH43_TASK_ID_REG register - * Channel43 task ID register + * Channel43 task id register */ #define SOC_ETM_CH43_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x174) /** SOC_ETM_CH43_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel43 task ID. + * Configures ch43_task_id */ #define SOC_ETM_CH43_TASK_ID 0x000000FFU #define SOC_ETM_CH43_TASK_ID_M (SOC_ETM_CH43_TASK_ID_V << SOC_ETM_CH43_TASK_ID_S) @@ -2448,11 +2448,11 @@ extern "C" { #define SOC_ETM_CH43_TASK_ID_S 0 /** SOC_ETM_CH44_EVT_ID_REG register - * Channel44 event ID register + * Channel44 event id register */ #define SOC_ETM_CH44_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x178) /** SOC_ETM_CH44_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel44 event ID. + * Configures ch44_evt_id */ #define SOC_ETM_CH44_EVT_ID 0x0000007FU #define SOC_ETM_CH44_EVT_ID_M (SOC_ETM_CH44_EVT_ID_V << SOC_ETM_CH44_EVT_ID_S) @@ -2460,11 +2460,11 @@ extern "C" { #define SOC_ETM_CH44_EVT_ID_S 0 /** SOC_ETM_CH44_TASK_ID_REG register - * Channel44 task ID register + * Channel44 task id register */ #define SOC_ETM_CH44_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x17c) /** SOC_ETM_CH44_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel44 task ID. + * Configures ch44_task_id */ #define SOC_ETM_CH44_TASK_ID 0x000000FFU #define SOC_ETM_CH44_TASK_ID_M (SOC_ETM_CH44_TASK_ID_V << SOC_ETM_CH44_TASK_ID_S) @@ -2472,11 +2472,11 @@ extern "C" { #define SOC_ETM_CH44_TASK_ID_S 0 /** SOC_ETM_CH45_EVT_ID_REG register - * Channel45 event ID register + * Channel45 event id register */ #define SOC_ETM_CH45_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x180) /** SOC_ETM_CH45_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel45 event ID. + * Configures ch45_evt_id */ #define SOC_ETM_CH45_EVT_ID 0x0000007FU #define SOC_ETM_CH45_EVT_ID_M (SOC_ETM_CH45_EVT_ID_V << SOC_ETM_CH45_EVT_ID_S) @@ -2484,11 +2484,11 @@ extern "C" { #define SOC_ETM_CH45_EVT_ID_S 0 /** SOC_ETM_CH45_TASK_ID_REG register - * Channel45 task ID register + * Channel45 task id register */ #define SOC_ETM_CH45_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x184) /** SOC_ETM_CH45_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel45 task ID. + * Configures ch45_task_id */ #define SOC_ETM_CH45_TASK_ID 0x000000FFU #define SOC_ETM_CH45_TASK_ID_M (SOC_ETM_CH45_TASK_ID_V << SOC_ETM_CH45_TASK_ID_S) @@ -2496,11 +2496,11 @@ extern "C" { #define SOC_ETM_CH45_TASK_ID_S 0 /** SOC_ETM_CH46_EVT_ID_REG register - * Channel46 event ID register + * Channel46 event id register */ #define SOC_ETM_CH46_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x188) /** SOC_ETM_CH46_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel46 event ID. + * Configures ch46_evt_id */ #define SOC_ETM_CH46_EVT_ID 0x0000007FU #define SOC_ETM_CH46_EVT_ID_M (SOC_ETM_CH46_EVT_ID_V << SOC_ETM_CH46_EVT_ID_S) @@ -2508,11 +2508,11 @@ extern "C" { #define SOC_ETM_CH46_EVT_ID_S 0 /** SOC_ETM_CH46_TASK_ID_REG register - * Channel46 task ID register + * Channel46 task id register */ #define SOC_ETM_CH46_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x18c) /** SOC_ETM_CH46_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel46 task ID. + * Configures ch46_task_id */ #define SOC_ETM_CH46_TASK_ID 0x000000FFU #define SOC_ETM_CH46_TASK_ID_M (SOC_ETM_CH46_TASK_ID_V << SOC_ETM_CH46_TASK_ID_S) @@ -2520,11 +2520,11 @@ extern "C" { #define SOC_ETM_CH46_TASK_ID_S 0 /** SOC_ETM_CH47_EVT_ID_REG register - * Channel47 event ID register + * Channel47 event id register */ #define SOC_ETM_CH47_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x190) /** SOC_ETM_CH47_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel47 event ID. + * Configures ch47_evt_id */ #define SOC_ETM_CH47_EVT_ID 0x0000007FU #define SOC_ETM_CH47_EVT_ID_M (SOC_ETM_CH47_EVT_ID_V << SOC_ETM_CH47_EVT_ID_S) @@ -2532,11 +2532,11 @@ extern "C" { #define SOC_ETM_CH47_EVT_ID_S 0 /** SOC_ETM_CH47_TASK_ID_REG register - * Channel47 task ID register + * Channel47 task id register */ #define SOC_ETM_CH47_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x194) /** SOC_ETM_CH47_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel47 task ID. + * Configures ch47_task_id */ #define SOC_ETM_CH47_TASK_ID 0x000000FFU #define SOC_ETM_CH47_TASK_ID_M (SOC_ETM_CH47_TASK_ID_V << SOC_ETM_CH47_TASK_ID_S) @@ -2544,11 +2544,11 @@ extern "C" { #define SOC_ETM_CH47_TASK_ID_S 0 /** SOC_ETM_CH48_EVT_ID_REG register - * Channel48 event ID register + * Channel48 event id register */ #define SOC_ETM_CH48_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x198) /** SOC_ETM_CH48_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel48 event ID. + * Configures ch48_evt_id */ #define SOC_ETM_CH48_EVT_ID 0x0000007FU #define SOC_ETM_CH48_EVT_ID_M (SOC_ETM_CH48_EVT_ID_V << SOC_ETM_CH48_EVT_ID_S) @@ -2556,11 +2556,11 @@ extern "C" { #define SOC_ETM_CH48_EVT_ID_S 0 /** SOC_ETM_CH48_TASK_ID_REG register - * Channel48 task ID register + * Channel48 task id register */ #define SOC_ETM_CH48_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x19c) /** SOC_ETM_CH48_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel48 task ID. + * Configures ch48_task_id */ #define SOC_ETM_CH48_TASK_ID 0x000000FFU #define SOC_ETM_CH48_TASK_ID_M (SOC_ETM_CH48_TASK_ID_V << SOC_ETM_CH48_TASK_ID_S) @@ -2568,11 +2568,11 @@ extern "C" { #define SOC_ETM_CH48_TASK_ID_S 0 /** SOC_ETM_CH49_EVT_ID_REG register - * Channel49 event ID register + * Channel49 event id register */ #define SOC_ETM_CH49_EVT_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a0) /** SOC_ETM_CH49_EVT_ID : R/W; bitpos: [6:0]; default: 0; - * Configures channel49 event ID. + * Configures ch49_evt_id */ #define SOC_ETM_CH49_EVT_ID 0x0000007FU #define SOC_ETM_CH49_EVT_ID_M (SOC_ETM_CH49_EVT_ID_V << SOC_ETM_CH49_EVT_ID_S) @@ -2580,11 +2580,11 @@ extern "C" { #define SOC_ETM_CH49_EVT_ID_S 0 /** SOC_ETM_CH49_TASK_ID_REG register - * Channel49 task ID register + * Channel49 task id register */ #define SOC_ETM_CH49_TASK_ID_REG (DR_REG_SOC_ETM_BASE + 0x1a4) /** SOC_ETM_CH49_TASK_ID : R/W; bitpos: [7:0]; default: 0; - * Configures channel49 task ID. + * Configures ch49_task_id */ #define SOC_ETM_CH49_TASK_ID 0x000000FFU #define SOC_ETM_CH49_TASK_ID_M (SOC_ETM_CH49_TASK_ID_V << SOC_ETM_CH49_TASK_ID_S) @@ -2592,11 +2592,11 @@ extern "C" { #define SOC_ETM_CH49_TASK_ID_S 0 /** SOC_ETM_EVT_ST0_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1a8) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_EVT_CH0_RISE_EDGE trigger status. + * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2605,7 +2605,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_S 0 /** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_EVT_CH1_RISE_EDGE trigger status. + * Represents GPIO_evt_ch1_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2614,7 +2614,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_S 1 /** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_EVT_CH2_RISE_EDGE trigger status. + * Represents GPIO_evt_ch2_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2623,7 +2623,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_S 2 /** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_EVT_CH3_RISE_EDGE trigger status. + * Represents GPIO_evt_ch3_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2632,7 +2632,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_S 3 /** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_EVT_CH4_RISE_EDGE trigger status. + * Represents GPIO_evt_ch4_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2641,7 +2641,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_S 4 /** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_EVT_CH5_RISE_EDGE trigger status. + * Represents GPIO_evt_ch5_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2650,7 +2650,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_S 5 /** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_EVT_CH6_RISE_EDGE trigger status. + * Represents GPIO_evt_ch6_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2659,7 +2659,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_S 6 /** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_EVT_CH7_RISE_EDGE trigger status. + * Represents GPIO_evt_ch7_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2668,7 +2668,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_S 7 /** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_EVT_CH0_FALL_EDGE trigger status. + * Represents GPIO_evt_ch0_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2677,7 +2677,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_S 8 /** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_EVT_CH1_FALL_EDGE trigger status. + * Represents GPIO_evt_ch1_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2686,7 +2686,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_S 9 /** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_EVT_CH2_FALL_EDGE trigger status. + * Represents GPIO_evt_ch2_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2695,7 +2695,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_S 10 /** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_EVT_CH3_FALL_EDGE trigger status. + * Represents GPIO_evt_ch3_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2704,7 +2704,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_S 11 /** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_EVT_CH4_FALL_EDGE trigger status. + * Represents GPIO_evt_ch4_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2713,7 +2713,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_S 12 /** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_EVT_CH5_FALL_EDGE trigger status. + * Represents GPIO_evt_ch5_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2722,7 +2722,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_S 13 /** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_EVT_CH6_FALL_EDGE trigger status. + * Represents GPIO_evt_ch6_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2731,7 +2731,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_S 14 /** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_EVT_CH7_FALL_EDGE trigger status. + * Represents GPIO_evt_ch7_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2740,7 +2740,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_S 15 /** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_EVT_CH0_ANY_EDGE trigger status. + * Represents GPIO_evt_ch0_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2749,7 +2749,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_S 16 /** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_EVT_CH1_ANY_EDGE trigger status. + * Represents GPIO_evt_ch1_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2758,7 +2758,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_S 17 /** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_EVT_CH2_ANY_EDGE trigger status. + * Represents GPIO_evt_ch2_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2767,7 +2767,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_S 18 /** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_EVT_CH3_ANY_EDGE trigger status. + * Represents GPIO_evt_ch3_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2776,7 +2776,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_S 19 /** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_EVT_CH4_ANY_EDGE trigger status. + * Represents GPIO_evt_ch4_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2785,7 +2785,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_S 20 /** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_EVT_CH5_ANY_EDGE trigger status. + * Represents GPIO_evt_ch5_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2794,7 +2794,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_S 21 /** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_EVT_CH6_ANY_EDGE trigger status. + * Represents GPIO_evt_ch6_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2803,7 +2803,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_S 22 /** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_EVT_CH7_ANY_EDGE trigger status. + * Represents GPIO_evt_ch7_any_edge trigger status. * 0: Not triggered * 1: Triggered */ @@ -2812,7 +2812,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_S 23 /** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents GPIO_EVT_ZERO_DET_POS0 trigger status. + * Represents GPIO_evt_zero_det_pos0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2821,7 +2821,7 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_S 24 /** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GPIO_EVT_ZERO_DET_NEG0 trigger status. + * Represents GPIO_evt_zero_det_neg0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2829,8 +2829,26 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_S 27 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. + * Represents LEDC_evt_duty_chng_end_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2839,7 +2857,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_S 28 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. + * Represents LEDC_evt_duty_chng_end_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2848,7 +2866,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_S 29 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. + * Represents LEDC_evt_duty_chng_end_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2857,7 +2875,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_S 30 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. + * Represents LEDC_evt_duty_chng_end_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -2867,12 +2885,12 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_S 31 /** SOC_ETM_EVT_ST0_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ac) /** SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR (BIT(0)) @@ -2880,8 +2898,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_RISE_EDGE_ST_CLR_S 0 /** SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR (BIT(1)) @@ -2889,8 +2907,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_RISE_EDGE_ST_CLR_S 1 /** SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR (BIT(2)) @@ -2898,8 +2916,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_RISE_EDGE_ST_CLR_S 2 /** SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR (BIT(3)) @@ -2907,8 +2925,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_RISE_EDGE_ST_CLR_S 3 /** SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR (BIT(4)) @@ -2916,8 +2934,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_RISE_EDGE_ST_CLR_S 4 /** SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR (BIT(5)) @@ -2925,8 +2943,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_RISE_EDGE_ST_CLR_S 5 /** SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR (BIT(6)) @@ -2934,8 +2952,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_RISE_EDGE_ST_CLR_S 6 /** SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR (BIT(7)) @@ -2943,8 +2961,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_RISE_EDGE_ST_CLR_S 7 /** SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR (BIT(8)) @@ -2952,8 +2970,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_FALL_EDGE_ST_CLR_S 8 /** SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR (BIT(9)) @@ -2961,8 +2979,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_FALL_EDGE_ST_CLR_S 9 /** SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR (BIT(10)) @@ -2970,8 +2988,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_FALL_EDGE_ST_CLR_S 10 /** SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR (BIT(11)) @@ -2979,8 +2997,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_FALL_EDGE_ST_CLR_S 11 /** SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR (BIT(12)) @@ -2988,8 +3006,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_FALL_EDGE_ST_CLR_S 12 /** SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR (BIT(13)) @@ -2997,8 +3015,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_FALL_EDGE_ST_CLR_S 13 /** SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR (BIT(14)) @@ -3006,8 +3024,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_FALL_EDGE_ST_CLR_S 14 /** SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR (BIT(15)) @@ -3015,8 +3033,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_FALL_EDGE_ST_CLR_S 15 /** SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR (BIT(16)) @@ -3024,8 +3042,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH0_ANY_EDGE_ST_CLR_S 16 /** SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR (BIT(17)) @@ -3033,8 +3051,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH1_ANY_EDGE_ST_CLR_S 17 /** SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR (BIT(18)) @@ -3042,8 +3060,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH2_ANY_EDGE_ST_CLR_S 18 /** SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR (BIT(19)) @@ -3051,8 +3069,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH3_ANY_EDGE_ST_CLR_S 19 /** SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR (BIT(20)) @@ -3060,8 +3078,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH4_ANY_EDGE_ST_CLR_S 20 /** SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR (BIT(21)) @@ -3069,8 +3087,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH5_ANY_EDGE_ST_CLR_S 21 /** SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR (BIT(22)) @@ -3078,8 +3096,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH6_ANY_EDGE_ST_CLR_S 22 /** SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR (BIT(23)) @@ -3087,8 +3105,8 @@ extern "C" { #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_CH7_ANY_EDGE_ST_CLR_S 23 /** SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_POS0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR (BIT(24)) @@ -3096,17 +3114,35 @@ extern "C" { #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_POS0_ST_CLR_S 24 /** SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_NEG0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR (BIT(25)) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S) #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_EVT_ZERO_DET_NEG0_ST_CLR_S 25 +/** SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR (BIT(26)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_POS1_ST_CLR_S 26 +/** SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR (BIT(27)) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_M (SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V << SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S) +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_V 0x00000001U +#define SOC_ETM_GPIO_EVT_ZERO_DET_NEG1_ST_CLR_S 27 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR (BIT(28)) @@ -3114,8 +3150,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH0_ST_CLR_S 28 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR (BIT(29)) @@ -3123,8 +3159,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH1_ST_CLR_S 29 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR (BIT(30)) @@ -3132,8 +3168,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH2_ST_CLR_S 30 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR (BIT(31)) @@ -3142,11 +3178,11 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH3_ST_CLR_S 31 /** SOC_ETM_EVT_ST1_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1b0) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. + * Represents LEDC_evt_duty_chng_end_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3155,7 +3191,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_S 0 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. + * Represents LEDC_evt_duty_chng_end_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3164,7 +3200,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_S 1 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3173,7 +3209,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_S 2 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3182,7 +3218,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_S 3 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3191,7 +3227,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_S 4 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3200,7 +3236,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_S 5 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3209,7 +3245,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_S 6 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3218,7 +3254,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_S 7 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER0 trigger status. + * Represents LEDC_evt_time_ovf_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3227,7 +3263,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_S 8 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER1 trigger status. + * Represents LEDC_evt_time_ovf_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3236,7 +3272,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_S 9 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER2 trigger status. + * Represents LEDC_evt_time_ovf_timer2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3245,7 +3281,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_S 10 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER3 trigger status. + * Represents LEDC_evt_time_ovf_timer3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3254,7 +3290,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_S 11 /** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_EVT_TIMER0_CMP trigger status. + * Represents LEDC_evt_timer0_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3263,7 +3299,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_S 12 /** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_EVT_TIMER1_CMP trigger status. + * Represents LEDC_evt_timer1_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3272,7 +3308,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_S 13 /** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_EVT_TIMER2_CMP trigger status. + * Represents LEDC_evt_timer2_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3281,7 +3317,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_S 14 /** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_EVT_TIMER3_CMP trigger status. + * Represents LEDC_evt_timer3_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3290,7 +3326,7 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_S 15 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG0_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3299,7 +3335,7 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_S 16 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG0_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3308,7 +3344,7 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_S 17 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG1_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3317,7 +3353,7 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_S 18 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG1_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3326,7 +3362,7 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_S 19 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP0 trigger status. + * Represents SYSTIMER_evt_cnt_cmp0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3335,7 +3371,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_S 20 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP1 trigger status. + * Represents SYSTIMER_evt_cnt_cmp1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3344,7 +3380,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_S 21 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP2 trigger status. + * Represents SYSTIMER_evt_cnt_cmp2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3353,7 +3389,7 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_S 22 /** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents ADC_EVT_CONV_CMPLT0 trigger status. + * Represents ADC_evt_conv_cmplt0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3362,7 +3398,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_S 23 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH0 trigger status. + * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3371,7 +3407,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_S 24 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH1 trigger status. + * Represents ADC_evt_eq_above_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3380,7 +3416,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_S 25 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH0 trigger status. + * Represents ADC_evt_eq_below_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3389,7 +3425,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_S 26 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH1 trigger status. + * Represents ADC_evt_eq_below_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3398,7 +3434,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_S 27 /** SOC_ETM_ADC_EVT_RESULT_DONE0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents ADC_EVT_RESULT_DONE0 trigger status. + * Represents ADC_evt_result_done0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3407,7 +3443,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_S 28 /** SOC_ETM_ADC_EVT_STOPPED0_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents ADC_EVT_STOPPED0 trigger status. + * Represents ADC_evt_stopped0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3416,7 +3452,7 @@ extern "C" { #define SOC_ETM_ADC_EVT_STOPPED0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_STOPPED0_ST_S 29 /** SOC_ETM_ADC_EVT_STARTED0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents ADC_EVT_STARTED0 trigger status. + * Represents ADC_evt_started0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3424,14 +3460,23 @@ extern "C" { #define SOC_ETM_ADC_EVT_STARTED0_ST_M (SOC_ETM_ADC_EVT_STARTED0_ST_V << SOC_ETM_ADC_EVT_STARTED0_ST_S) #define SOC_ETM_ADC_EVT_STARTED0_ST_V 0x00000001U #define SOC_ETM_ADC_EVT_STARTED0_ST_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_M (SOC_ETM_REGDMA_EVT_DONE0_ST_V << SOC_ETM_REGDMA_EVT_DONE0_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_S 31 /** SOC_ETM_EVT_ST1_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1b4) /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR (BIT(0)) @@ -3439,8 +3484,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH4_ST_CLR_S 0 /** SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR (BIT(1)) @@ -3448,8 +3493,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_DUTY_CHNG_END_CH5_ST_CLR_S 1 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR (BIT(2)) @@ -3457,8 +3502,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH0_ST_CLR_S 2 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR (BIT(3)) @@ -3466,8 +3511,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH1_ST_CLR_S 3 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR (BIT(4)) @@ -3475,8 +3520,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH2_ST_CLR_S 4 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR (BIT(5)) @@ -3484,8 +3529,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH3_ST_CLR_S 5 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR (BIT(6)) @@ -3493,8 +3538,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH4_ST_CLR_S 6 /** SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR (BIT(7)) @@ -3502,8 +3547,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_OVF_CNT_PLS_CH5_ST_CLR_S 7 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR (BIT(8)) @@ -3511,8 +3556,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER0_ST_CLR_S 8 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR (BIT(9)) @@ -3520,8 +3565,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER1_ST_CLR_S 9 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR (BIT(10)) @@ -3529,8 +3574,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER2_ST_CLR_S 10 /** SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR (BIT(11)) @@ -3538,8 +3583,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIME_OVF_TIMER3_ST_CLR_S 11 /** SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER0_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR (BIT(12)) @@ -3547,8 +3592,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER0_CMP_ST_CLR_S 12 /** SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER1_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR (BIT(13)) @@ -3556,8 +3601,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER1_CMP_ST_CLR_S 13 /** SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER2_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR (BIT(14)) @@ -3565,8 +3610,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER2_CMP_ST_CLR_S 14 /** SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER3_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR (BIT(15)) @@ -3574,8 +3619,8 @@ extern "C" { #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_EVT_TIMER3_CMP_ST_CLR_S 15 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(16)) @@ -3583,8 +3628,8 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER0_ST_CLR_S 16 /** SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(17)) @@ -3592,8 +3637,8 @@ extern "C" { #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_EVT_CNT_CMP_TIMER1_ST_CLR_S 17 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR (BIT(18)) @@ -3601,8 +3646,8 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER0_ST_CLR_S 18 /** SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR (BIT(19)) @@ -3610,8 +3655,8 @@ extern "C" { #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_EVT_CNT_CMP_TIMER1_ST_CLR_S 19 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR (BIT(20)) @@ -3619,8 +3664,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP0_ST_CLR_S 20 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR (BIT(21)) @@ -3628,8 +3673,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP1_ST_CLR_S 21 /** SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR (BIT(22)) @@ -3637,8 +3682,8 @@ extern "C" { #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_V 0x00000001U #define SOC_ETM_SYSTIMER_EVT_CNT_CMP2_ST_CLR_S 22 /** SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear ADC_EVT_CONV_CMPLT0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR (BIT(23)) @@ -3646,8 +3691,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_CONV_CMPLT0_ST_CLR_S 23 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR (BIT(24)) @@ -3655,8 +3700,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH0_ST_CLR_S 24 /** SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR (BIT(25)) @@ -3664,8 +3709,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_ABOVE_THRESH1_ST_CLR_S 25 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR (BIT(26)) @@ -3673,8 +3718,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH0_ST_CLR_S 26 /** SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR (BIT(27)) @@ -3682,8 +3727,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_EQ_BELOW_THRESH1_ST_CLR_S 27 /** SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear ADC_EVT_RESULT_DONE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_result_done0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR (BIT(28)) @@ -3691,8 +3736,8 @@ extern "C" { #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_RESULT_DONE0_ST_CLR_S 28 /** SOC_ETM_ADC_EVT_STOPPED0_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear ADC_EVT_STOPPED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_stopped0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR (BIT(29)) @@ -3700,21 +3745,93 @@ extern "C" { #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_STOPPED0_ST_CLR_S 29 /** SOC_ETM_ADC_EVT_STARTED0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear ADC_EVT_STARTED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_started0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR (BIT(30)) #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_M (SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V << SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S) #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_EVT_STARTED0_ST_CLR_S 30 +/** SOC_ETM_REGDMA_EVT_DONE0_ST_CLR : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR (BIT(31)) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE0_ST_CLR_S 31 /** SOC_ETM_EVT_ST2_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1b8) +/** SOC_ETM_REGDMA_EVT_DONE1_ST : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_M (SOC_ETM_REGDMA_EVT_DONE1_ST_V << SOC_ETM_REGDMA_EVT_DONE1_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_M (SOC_ETM_REGDMA_EVT_DONE2_ST_V << SOC_ETM_REGDMA_EVT_DONE2_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_M (SOC_ETM_REGDMA_EVT_DONE3_ST_V << SOC_ETM_REGDMA_EVT_DONE3_ST_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_M (SOC_ETM_REGDMA_EVT_ERR0_ST_V << SOC_ETM_REGDMA_EVT_ERR0_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_M (SOC_ETM_REGDMA_EVT_ERR1_ST_V << SOC_ETM_REGDMA_EVT_ERR1_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_M (SOC_ETM_REGDMA_EVT_ERR2_ST_V << SOC_ETM_REGDMA_EVT_ERR2_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_M (SOC_ETM_REGDMA_EVT_ERR3_ST_V << SOC_ETM_REGDMA_EVT_ERR3_ST_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_S 6 /** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents TMPSNSR_EVT_OVER_LIMIT trigger status. + * Represents TMPSNSR_evt_over_limit trigger status. * 0: Not triggered * 1: Triggered */ @@ -3723,7 +3840,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_S 7 /** SOC_ETM_I2S0_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents I2S0_EVT_RX_DONE trigger status. + * Represents I2S0_evt_rx_done trigger status. * 0: Not triggered * 1: Triggered */ @@ -3732,7 +3849,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_RX_DONE_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_RX_DONE_ST_S 8 /** SOC_ETM_I2S0_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents I2S0_EVT_TX_DONE trigger status. + * Represents I2S0_evt_tx_done trigger status. * 0: Not triggered * 1: Triggered */ @@ -3741,7 +3858,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_TX_DONE_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_TX_DONE_ST_S 9 /** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents I2S0_EVT_X_WORDS_RECEIVED trigger status. + * Represents I2S0_evt_x_words_received trigger status. * 0: Not triggered * 1: Triggered */ @@ -3750,7 +3867,7 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_S 10 /** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents I2S0_EVT_X_WORDS_SENT trigger status. + * Represents I2S0_evt_x_words_sent trigger status. * 0: Not triggered * 1: Triggered */ @@ -3758,8 +3875,71 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_HALT_ST (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_M (SOC_ETM_ULP_EVT_HALT_ST_V << SOC_ETM_ULP_EVT_HALT_ST_S) +#define SOC_ETM_ULP_EVT_HALT_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_M (SOC_ETM_ULP_EVT_START_INTR_ST_V << SOC_ETM_ULP_EVT_START_INTR_ST_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_S 18 /** SOC_ETM_RTC_EVT_TICK_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents RTC_EVT_TICK trigger status. + * Represents RTC_evt_tick trigger status. * 0: Not triggered * 1: Triggered */ @@ -3768,7 +3948,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_TICK_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_TICK_ST_S 19 /** SOC_ETM_RTC_EVT_OVF_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents RTC_EVT_OVF trigger status. + * Represents RTC_evt_ovf trigger status. * 0: Not triggered * 1: Triggered */ @@ -3777,7 +3957,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_OVF_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_OVF_ST_S 20 /** SOC_ETM_RTC_EVT_CMP_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents RTC_EVT_CMP trigger status. + * Represents RTC_evt_cmp trigger status. * 0: Not triggered * 1: Triggered */ @@ -3786,7 +3966,7 @@ extern "C" { #define SOC_ETM_RTC_EVT_CMP_ST_V 0x00000001U #define SOC_ETM_RTC_EVT_CMP_ST_S 21 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_in_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3795,7 +3975,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_S 22 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_in_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3803,8 +3983,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_S 24 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3813,7 +4002,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_S 25 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3821,8 +4010,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_S 27 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3831,7 +4029,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_S 28 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3839,8 +4037,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_S 30 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -3850,12 +4057,75 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_S 31 /** SOC_ETM_EVT_ST2_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1bc) +/** SOC_ETM_REGDMA_EVT_DONE1_ST_CLR : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR (BIT(0)) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE1_ST_CLR_S 0 +/** SOC_ETM_REGDMA_EVT_DONE2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR (BIT(1)) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE2_ST_CLR_S 1 +/** SOC_ETM_REGDMA_EVT_DONE3_ST_CLR : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR (BIT(2)) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_M (SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V << SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_DONE3_ST_CLR_S 2 +/** SOC_ETM_REGDMA_EVT_ERR0_ST_CLR : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR (BIT(3)) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR0_ST_CLR_S 3 +/** SOC_ETM_REGDMA_EVT_ERR1_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR (BIT(4)) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR1_ST_CLR_S 4 +/** SOC_ETM_REGDMA_EVT_ERR2_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR (BIT(5)) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR2_ST_CLR_S 5 +/** SOC_ETM_REGDMA_EVT_ERR3_ST_CLR : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR (BIT(6)) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_M (SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V << SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S) +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_EVT_ERR3_ST_CLR_S 6 /** SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear TMPSNSR_EVT_OVER_LIMIT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR (BIT(7)) @@ -3863,8 +4133,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_EVT_OVER_LIMIT_ST_CLR_S 7 /** SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear I2S0_EVT_RX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_rx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR (BIT(8)) @@ -3872,8 +4142,8 @@ extern "C" { #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_RX_DONE_ST_CLR_S 8 /** SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear I2S0_EVT_TX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_tx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR (BIT(9)) @@ -3881,8 +4151,8 @@ extern "C" { #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_TX_DONE_ST_CLR_S 9 /** SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_RECEIVED trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_received trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(10)) @@ -3890,17 +4160,80 @@ extern "C" { #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_RECEIVED_ST_CLR_S 10 /** SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_SENT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR (BIT(11)) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S) #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_EVT_X_WORDS_SENT_ST_CLR_S 11 +/** SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR (BIT(12)) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_RX_DONE_ST_CLR_S 12 +/** SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR (BIT(13)) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_M (SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V << SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_TX_DONE_ST_CLR_S 13 +/** SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR (BIT(14)) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_RECEIVED_ST_CLR_S 14 +/** SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR (BIT(15)) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_M (SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V << SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S) +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_EVT_X_WORDS_SENT_ST_CLR_S 15 +/** SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR (BIT(16)) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_ERR_INTR_ST_CLR_S 16 +/** SOC_ETM_ULP_EVT_HALT_ST_CLR : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_HALT_ST_CLR (BIT(17)) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_M (SOC_ETM_ULP_EVT_HALT_ST_CLR_V << SOC_ETM_ULP_EVT_HALT_ST_CLR_S) +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_HALT_ST_CLR_S 17 +/** SOC_ETM_ULP_EVT_START_INTR_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR (BIT(18)) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_M (SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V << SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S) +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_EVT_START_INTR_ST_CLR_S 18 /** SOC_ETM_RTC_EVT_TICK_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear RTC_EVT_TICK trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_tick trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_TICK_ST_CLR (BIT(19)) @@ -3908,8 +4241,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_TICK_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_TICK_ST_CLR_S 19 /** SOC_ETM_RTC_EVT_OVF_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear RTC_EVT_OVF trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_ovf trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_OVF_ST_CLR (BIT(20)) @@ -3917,8 +4250,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_OVF_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_OVF_ST_CLR_S 20 /** SOC_ETM_RTC_EVT_CMP_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear RTC_EVT_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_RTC_EVT_CMP_ST_CLR (BIT(21)) @@ -3926,8 +4259,8 @@ extern "C" { #define SOC_ETM_RTC_EVT_CMP_ST_CLR_V 0x00000001U #define SOC_ETM_RTC_EVT_CMP_ST_CLR_S 21 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR (BIT(22)) @@ -3935,17 +4268,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH0_ST_CLR_S 22 /** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR (BIT(23)) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH1_ST_CLR_S 23 +/** SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR (BIT(24)) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_DONE_CH2_ST_CLR_S 24 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR (BIT(25)) @@ -3953,17 +4295,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH0_ST_CLR_S 25 /** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR (BIT(26)) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH1_ST_CLR_S 26 +/** SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR (BIT(27)) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_SUC_EOF_CH2_ST_CLR_S 27 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR (BIT(28)) @@ -3971,17 +4322,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0_ST_CLR_S 28 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR (BIT(29)) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_EMPTY_CH2_ST_CLR_S 30 /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR (BIT(31)) @@ -3990,11 +4350,11 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH0_ST_CLR_S 31 /** SOC_ETM_EVT_ST3_REG register - * Event trigger status register + * Events trigger status register */ #define SOC_ETM_EVT_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1c0) /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4002,8 +4362,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_S 1 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_out_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4012,7 +4381,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_S 2 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_out_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4020,8 +4389,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_S 4 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4030,7 +4408,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_S 5 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4038,8 +4416,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_S 7 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4048,7 +4435,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_S 8 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4056,8 +4443,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_S 10 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4066,7 +4462,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_S 11 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4074,8 +4470,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_S 13 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4084,7 +4489,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_S 14 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4092,8 +4497,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_S 16 /** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents PMU_EVT_SLEEP_WEEKUP trigger status. + * Represents PMU_evt_sleep_weekup trigger status. * 0: Not triggered * 1: Triggered */ @@ -4103,21 +4517,30 @@ extern "C" { #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_S 17 /** SOC_ETM_EVT_ST3_CLR_REG register - * Event trigger status clear register + * Events trigger status clear register */ #define SOC_ETM_EVT_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1c4) /** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR (BIT(0)) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_IN_FIFO_FULL_CH2_ST_CLR_S 1 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR (BIT(2)) @@ -4125,17 +4548,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH0_ST_CLR_S 2 /** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR (BIT(3)) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH1_ST_CLR_S 3 +/** SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR (BIT(4)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_DONE_CH2_ST_CLR_S 4 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR (BIT(5)) @@ -4143,17 +4575,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH0_ST_CLR_S 5 /** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR (BIT(6)) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH1_ST_CLR_S 6 +/** SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR (BIT(7)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_EOF_CH2_ST_CLR_S 7 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR (BIT(8)) @@ -4161,17 +4602,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0_ST_CLR_S 8 /** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR (BIT(9)) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1_ST_CLR_S 9 +/** SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR (BIT(10)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_TOTAL_EOF_CH2_ST_CLR_S 10 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR (BIT(11)) @@ -4179,17 +4629,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0_ST_CLR_S 11 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR (BIT(12)) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1_ST_CLR_S 12 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR (BIT(13)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH2_ST_CLR_S 13 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR (BIT(14)) @@ -4197,17 +4656,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH0_ST_CLR_S 14 /** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR (BIT(15)) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH1_ST_CLR_S 15 +/** SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR (BIT(16)) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_EVT_OUT_FIFO_FULL_CH2_ST_CLR_S 16 /** SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear PMU_EVT_SLEEP_WEEKUP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR (BIT(17)) @@ -4216,11 +4684,11 @@ extern "C" { #define SOC_ETM_PMU_EVT_SLEEP_WEEKUP_ST_CLR_S 17 /** SOC_ETM_TASK_ST0_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST0_REG (DR_REG_SOC_ETM_BASE + 0x1c8) /** SOC_ETM_GPIO_TASK_CH0_SET_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_TASK_CH0_SET trigger status. + * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4229,7 +4697,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_SET_ST_S 0 /** SOC_ETM_GPIO_TASK_CH1_SET_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_TASK_CH1_SET trigger status. + * Represents GPIO_task_ch1_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4238,7 +4706,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_SET_ST_S 1 /** SOC_ETM_GPIO_TASK_CH2_SET_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_TASK_CH2_SET trigger status. + * Represents GPIO_task_ch2_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4247,7 +4715,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_SET_ST_S 2 /** SOC_ETM_GPIO_TASK_CH3_SET_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_TASK_CH3_SET trigger status. + * Represents GPIO_task_ch3_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4256,7 +4724,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_SET_ST_S 3 /** SOC_ETM_GPIO_TASK_CH4_SET_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_TASK_CH4_SET trigger status. + * Represents GPIO_task_ch4_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4265,7 +4733,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_SET_ST_S 4 /** SOC_ETM_GPIO_TASK_CH5_SET_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_TASK_CH5_SET trigger status. + * Represents GPIO_task_ch5_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4274,7 +4742,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_SET_ST_S 5 /** SOC_ETM_GPIO_TASK_CH6_SET_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_TASK_CH6_SET trigger status. + * Represents GPIO_task_ch6_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4283,7 +4751,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_SET_ST_S 6 /** SOC_ETM_GPIO_TASK_CH7_SET_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_TASK_CH7_SET trigger status. + * Represents GPIO_task_ch7_set trigger status. * 0: Not triggered * 1: Triggered */ @@ -4292,7 +4760,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_SET_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_SET_ST_S 7 /** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_TASK_CH0_CLEAR trigger status. + * Represents GPIO_task_ch0_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4301,7 +4769,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_S 8 /** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_TASK_CH1_CLEAR trigger status. + * Represents GPIO_task_ch1_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4310,7 +4778,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_S 9 /** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_TASK_CH2_CLEAR trigger status. + * Represents GPIO_task_ch2_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4319,7 +4787,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_S 10 /** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_TASK_CH3_CLEAR trigger status. + * Represents GPIO_task_ch3_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4328,7 +4796,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_S 11 /** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_TASK_CH4_CLEAR trigger status. + * Represents GPIO_task_ch4_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4337,7 +4805,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_S 12 /** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_TASK_CH5_CLEAR trigger status. + * Represents GPIO_task_ch5_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4346,7 +4814,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_S 13 /** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_TASK_CH6_CLEAR trigger status. + * Represents GPIO_task_ch6_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4355,7 +4823,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_S 14 /** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_TASK_CH7_CLEAR trigger status. + * Represents GPIO_task_ch7_clear trigger status. * 0: Not triggered * 1: Triggered */ @@ -4364,7 +4832,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_S 15 /** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_TASK_CH0_TOGGLE trigger status. + * Represents GPIO_task_ch0_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4373,7 +4841,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_S 16 /** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_TASK_CH1_TOGGLE trigger status. + * Represents GPIO_task_ch1_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4382,7 +4850,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_S 17 /** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_TASK_CH2_TOGGLE trigger status. + * Represents GPIO_task_ch2_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4391,7 +4859,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_S 18 /** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_TASK_CH3_TOGGLE trigger status. + * Represents GPIO_task_ch3_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4400,7 +4868,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_S 19 /** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_TASK_CH4_TOGGLE trigger status. + * Represents GPIO_task_ch4_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4409,7 +4877,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_S 20 /** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_TASK_CH5_TOGGLE trigger status. + * Represents GPIO_task_ch5_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4418,7 +4886,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_S 21 /** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_TASK_CH6_TOGGLE trigger status. + * Represents GPIO_task_ch6_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4427,7 +4895,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_S 22 /** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_TASK_CH7_TOGGLE trigger status. + * Represents GPIO_task_ch7_toggle trigger status. * 0: Not triggered * 1: Triggered */ @@ -4436,7 +4904,7 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_S 23 /** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER0_RES_UPDATE trigger status. + * Represents LEDC_task_timer0_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4445,7 +4913,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_S 24 /** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER1_RES_UPDATE trigger status. + * Represents LEDC_task_timer1_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4454,7 +4922,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_S 25 /** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER2_RES_UPDATE trigger status. + * Represents LEDC_task_timer2_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4463,7 +4931,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_S 26 /** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER3_RES_UPDATE trigger status. + * Represents LEDC_task_timer3_res_update trigger status. * 0: Not triggered * 1: Triggered */ @@ -4472,7 +4940,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_S 27 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. + * Represents LEDC_task_duty_scale_update_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4481,7 +4949,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_S 28 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. + * Represents LEDC_task_duty_scale_update_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4490,7 +4958,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_S 29 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. + * Represents LEDC_task_duty_scale_update_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4499,7 +4967,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_S 30 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. + * Represents LEDC_task_duty_scale_update_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4509,12 +4977,12 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_S 31 /** SOC_ETM_TASK_ST0_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST0_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1cc) /** SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR (BIT(0)) @@ -4522,8 +4990,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_SET_ST_CLR_S 0 /** SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR (BIT(1)) @@ -4531,8 +4999,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_SET_ST_CLR_S 1 /** SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR (BIT(2)) @@ -4540,8 +5008,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_SET_ST_CLR_S 2 /** SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR (BIT(3)) @@ -4549,8 +5017,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_SET_ST_CLR_S 3 /** SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR (BIT(4)) @@ -4558,8 +5026,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_SET_ST_CLR_S 4 /** SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR (BIT(5)) @@ -4567,8 +5035,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_SET_ST_CLR_S 5 /** SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR (BIT(6)) @@ -4576,8 +5044,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_SET_ST_CLR_S 6 /** SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_set trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR (BIT(7)) @@ -4585,8 +5053,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_SET_ST_CLR_S 7 /** SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR (BIT(8)) @@ -4594,8 +5062,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_CLEAR_ST_CLR_S 8 /** SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR (BIT(9)) @@ -4603,8 +5071,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_CLEAR_ST_CLR_S 9 /** SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR (BIT(10)) @@ -4612,8 +5080,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_CLEAR_ST_CLR_S 10 /** SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR (BIT(11)) @@ -4621,8 +5089,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_CLEAR_ST_CLR_S 11 /** SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR (BIT(12)) @@ -4630,8 +5098,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_CLEAR_ST_CLR_S 12 /** SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR (BIT(13)) @@ -4639,8 +5107,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_CLEAR_ST_CLR_S 13 /** SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR (BIT(14)) @@ -4648,8 +5116,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_CLEAR_ST_CLR_S 14 /** SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR (BIT(15)) @@ -4657,8 +5125,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_CLEAR_ST_CLR_S 15 /** SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR (BIT(16)) @@ -4666,8 +5134,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH0_TOGGLE_ST_CLR_S 16 /** SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR (BIT(17)) @@ -4675,8 +5143,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH1_TOGGLE_ST_CLR_S 17 /** SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR (BIT(18)) @@ -4684,8 +5152,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH2_TOGGLE_ST_CLR_S 18 /** SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR (BIT(19)) @@ -4693,8 +5161,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH3_TOGGLE_ST_CLR_S 19 /** SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR (BIT(20)) @@ -4702,8 +5170,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH4_TOGGLE_ST_CLR_S 20 /** SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR (BIT(21)) @@ -4711,8 +5179,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH5_TOGGLE_ST_CLR_S 21 /** SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR (BIT(22)) @@ -4720,8 +5188,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH6_TOGGLE_ST_CLR_S 22 /** SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR (BIT(23)) @@ -4729,8 +5197,8 @@ extern "C" { #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_V 0x00000001U #define SOC_ETM_GPIO_TASK_CH7_TOGGLE_ST_CLR_S 23 /** SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR (BIT(24)) @@ -4738,8 +5206,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RES_UPDATE_ST_CLR_S 24 /** SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR (BIT(25)) @@ -4747,8 +5215,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RES_UPDATE_ST_CLR_S 25 /** SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR (BIT(26)) @@ -4756,8 +5224,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RES_UPDATE_ST_CLR_S 26 /** SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR (BIT(27)) @@ -4765,8 +5233,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RES_UPDATE_ST_CLR_S 27 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR (BIT(28)) @@ -4774,8 +5242,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH0_ST_CLR_S 28 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR (BIT(29)) @@ -4783,8 +5251,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH1_ST_CLR_S 29 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR (BIT(30)) @@ -4792,8 +5260,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH2_ST_CLR_S 30 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR (BIT(31)) @@ -4802,11 +5270,11 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH3_ST_CLR_S 31 /** SOC_ETM_TASK_ST1_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST1_REG (DR_REG_SOC_ETM_BASE + 0x1d0) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. + * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4815,7 +5283,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_S 0 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. + * Represents LEDC_task_duty_scale_update_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4824,7 +5292,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_S 1 /** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_TIMER0_CAP trigger status. + * Represents LEDC_task_timer0_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4833,7 +5301,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_S 2 /** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_TIMER1_CAP trigger status. + * Represents LEDC_task_timer1_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4842,7 +5310,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_S 3 /** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_TIMER2_CAP trigger status. + * Represents LEDC_task_timer2_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4851,7 +5319,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_S 4 /** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_TIMER3_CAP trigger status. + * Represents LEDC_task_timer3_cap trigger status. * 0: Not triggered * 1: Triggered */ @@ -4860,7 +5328,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_S 5 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. + * Represents LEDC_task_sig_out_dis_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4869,7 +5337,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_S 6 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. + * Represents LEDC_task_sig_out_dis_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4878,7 +5346,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_S 7 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. + * Represents LEDC_task_sig_out_dis_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4887,7 +5355,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_S 8 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. + * Represents LEDC_task_sig_out_dis_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4896,7 +5364,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_S 9 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. + * Represents LEDC_task_sig_out_dis_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4905,7 +5373,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_S 10 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. + * Represents LEDC_task_sig_out_dis_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4914,7 +5382,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_S 11 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH0 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4923,7 +5391,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_S 12 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH1 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4932,7 +5400,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_S 13 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH2 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4941,7 +5409,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_S 14 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH3 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4950,7 +5418,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_S 15 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH4 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4959,7 +5427,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_S 16 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH5 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -4968,7 +5436,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_S 17 /** SOC_ETM_LEDC_TASK_TIMER0_RST_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents LEDC_TASK_TIMER0_RST trigger status. + * Represents LEDC_task_timer0_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4977,7 +5445,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_S 18 /** SOC_ETM_LEDC_TASK_TIMER1_RST_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents LEDC_TASK_TIMER1_RST trigger status. + * Represents LEDC_task_timer1_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4986,7 +5454,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_S 19 /** SOC_ETM_LEDC_TASK_TIMER2_RST_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents LEDC_TASK_TIMER2_RST trigger status. + * Represents LEDC_task_timer2_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -4995,7 +5463,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_S 20 /** SOC_ETM_LEDC_TASK_TIMER3_RST_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents LEDC_TASK_TIMER3_RST trigger status. + * Represents LEDC_task_timer3_rst trigger status. * 0: Not triggered * 1: Triggered */ @@ -5004,7 +5472,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_S 21 /** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents LEDC_TASK_TIMER0_RESUME trigger status. + * Represents LEDC_task_timer0_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5013,7 +5481,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_S 22 /** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents LEDC_TASK_TIMER1_RESUME trigger status. + * Represents LEDC_task_timer1_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5022,7 +5490,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_S 23 /** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER2_RESUME trigger status. + * Represents LEDC_task_timer2_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5031,7 +5499,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_S 24 /** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER3_RESUME trigger status. + * Represents LEDC_task_timer3_resume trigger status. * 0: Not triggered * 1: Triggered */ @@ -5040,7 +5508,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_S 25 /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER0_PAUSE trigger status. + * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5049,7 +5517,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_S 26 /** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER1_PAUSE trigger status. + * Represents LEDC_task_timer1_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5058,7 +5526,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_S 27 /** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_TIMER2_PAUSE trigger status. + * Represents LEDC_task_timer2_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5067,7 +5535,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_S 28 /** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_TIMER3_PAUSE trigger status. + * Represents LEDC_task_timer3_pause trigger status. * 0: Not triggered * 1: Triggered */ @@ -5076,7 +5544,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_S 29 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH0 trigger status. + * Represents LEDC_task_gamma_restart_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5085,7 +5553,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_S 30 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH1 trigger status. + * Represents LEDC_task_gamma_restart_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5095,12 +5563,12 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_S 31 /** SOC_ETM_TASK_ST1_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST1_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1d4) /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR (BIT(0)) @@ -5108,8 +5576,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH4_ST_CLR_S 0 /** SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR (BIT(1)) @@ -5117,8 +5585,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_DUTY_SCALE_UPDATE_CH5_ST_CLR_S 1 /** SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR (BIT(2)) @@ -5126,8 +5594,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_CAP_ST_CLR_S 2 /** SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR (BIT(3)) @@ -5135,8 +5603,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_CAP_ST_CLR_S 3 /** SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR (BIT(4)) @@ -5144,8 +5612,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_CAP_ST_CLR_S 4 /** SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR (BIT(5)) @@ -5153,8 +5621,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_CAP_ST_CLR_S 5 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR (BIT(6)) @@ -5162,8 +5630,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH0_ST_CLR_S 6 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR (BIT(7)) @@ -5171,8 +5639,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH1_ST_CLR_S 7 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR (BIT(8)) @@ -5180,8 +5648,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH2_ST_CLR_S 8 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR (BIT(9)) @@ -5189,8 +5657,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH3_ST_CLR_S 9 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR (BIT(10)) @@ -5198,8 +5666,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH4_ST_CLR_S 10 /** SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR (BIT(11)) @@ -5207,8 +5675,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_SIG_OUT_DIS_CH5_ST_CLR_S 11 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR (BIT(12)) @@ -5216,8 +5684,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH0_ST_CLR_S 12 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR (BIT(13)) @@ -5225,8 +5693,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH1_ST_CLR_S 13 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR (BIT(14)) @@ -5234,8 +5702,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH2_ST_CLR_S 14 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR (BIT(15)) @@ -5243,8 +5711,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH3_ST_CLR_S 15 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR (BIT(16)) @@ -5252,8 +5720,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH4_ST_CLR_S 16 /** SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR (BIT(17)) @@ -5261,8 +5729,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_OVF_CNT_RST_CH5_ST_CLR_S 17 /** SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR (BIT(18)) @@ -5270,8 +5738,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RST_ST_CLR_S 18 /** SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR (BIT(19)) @@ -5279,8 +5747,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RST_ST_CLR_S 19 /** SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR (BIT(20)) @@ -5288,8 +5756,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RST_ST_CLR_S 20 /** SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR (BIT(21)) @@ -5297,8 +5765,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RST_ST_CLR_S 21 /** SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR (BIT(22)) @@ -5306,8 +5774,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_RESUME_ST_CLR_S 22 /** SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR (BIT(23)) @@ -5315,8 +5783,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_RESUME_ST_CLR_S 23 /** SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR (BIT(24)) @@ -5324,8 +5792,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_RESUME_ST_CLR_S 24 /** SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR (BIT(25)) @@ -5333,8 +5801,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_RESUME_ST_CLR_S 25 /** SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR (BIT(26)) @@ -5342,8 +5810,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER0_PAUSE_ST_CLR_S 26 /** SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR (BIT(27)) @@ -5351,8 +5819,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER1_PAUSE_ST_CLR_S 27 /** SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR (BIT(28)) @@ -5360,8 +5828,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER2_PAUSE_ST_CLR_S 28 /** SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR (BIT(29)) @@ -5369,8 +5837,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_TIMER3_PAUSE_ST_CLR_S 29 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR (BIT(30)) @@ -5378,8 +5846,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH0_ST_CLR_S 30 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR (BIT(31)) @@ -5388,11 +5856,11 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH1_ST_CLR_S 31 /** SOC_ETM_TASK_ST2_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST2_REG (DR_REG_SOC_ETM_BASE + 0x1d8) /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH2 trigger status. + * Represents LEDC_task_gamma_restart_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5401,7 +5869,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_S 0 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH3 trigger status. + * Represents LEDC_task_gamma_restart_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5410,7 +5878,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_S 1 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH4 trigger status. + * Represents LEDC_task_gamma_restart_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5419,7 +5887,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_S 2 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH5 trigger status. + * Represents LEDC_task_gamma_restart_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5428,7 +5896,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_S 3 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. + * Represents LEDC_task_gamma_pause_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5437,7 +5905,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_S 4 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. + * Represents LEDC_task_gamma_pause_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5446,7 +5914,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_S 5 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. + * Represents LEDC_task_gamma_pause_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5455,7 +5923,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_S 6 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. + * Represents LEDC_task_gamma_pause_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5464,7 +5932,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_S 7 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. + * Represents LEDC_task_gamma_pause_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5473,7 +5941,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_S 8 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. + * Represents LEDC_task_gamma_pause_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5482,7 +5950,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_S 9 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH0 trigger status. + * Represents LEDC_task_gamma_resume_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5491,7 +5959,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_S 10 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH1 trigger status. + * Represents LEDC_task_gamma_resume_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5500,7 +5968,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_S 11 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH2 trigger status. + * Represents LEDC_task_gamma_resume_ch2 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5509,7 +5977,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_S 12 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH3 trigger status. + * Represents LEDC_task_gamma_resume_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5518,7 +5986,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_S 13 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH4 trigger status. + * Represents LEDC_task_gamma_resume_ch4 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5527,7 +5995,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_S 14 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH5 trigger status. + * Represents LEDC_task_gamma_resume_ch5 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5536,7 +6004,7 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_S 15 /** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER0 trigger status. + * Represents TG0_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5545,7 +6013,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_S 16 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG0_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5554,7 +6022,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_S 17 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG0_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5563,7 +6031,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_S 18 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG0_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5572,7 +6040,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_S 19 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [20]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5581,7 +6049,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_S 20 /** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [21]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER1 trigger status. + * Represents TG0_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5590,7 +6058,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_S 21 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [22]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG0_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5599,7 +6067,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_S 22 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [23]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG0_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5608,7 +6076,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_S 23 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [24]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG0_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5617,7 +6085,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_S 24 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [25]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG0_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5626,7 +6094,7 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_S 25 /** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST : R/WTC/SS; bitpos: [26]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER0 trigger status. + * Represents TG1_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5635,7 +6103,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_S 26 /** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST : R/WTC/SS; bitpos: [27]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG1_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5644,7 +6112,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_S 27 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG1_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5653,7 +6121,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_S 28 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG1_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5662,7 +6130,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_S 29 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST : R/WTC/SS; bitpos: [30]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG1_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5671,7 +6139,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_S 30 /** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER1 trigger status. + * Represents TG1_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5681,12 +6149,12 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_S 31 /** SOC_ETM_TASK_ST2_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST2_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1dc) /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR (BIT(0)) @@ -5694,8 +6162,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH2_ST_CLR_S 0 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR (BIT(1)) @@ -5703,8 +6171,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH3_ST_CLR_S 1 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR (BIT(2)) @@ -5712,8 +6180,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH4_ST_CLR_S 2 /** SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR (BIT(3)) @@ -5721,8 +6189,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESTART_CH5_ST_CLR_S 3 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR (BIT(4)) @@ -5730,8 +6198,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH0_ST_CLR_S 4 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR (BIT(5)) @@ -5739,8 +6207,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH1_ST_CLR_S 5 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR (BIT(6)) @@ -5748,8 +6216,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH2_ST_CLR_S 6 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR (BIT(7)) @@ -5757,8 +6225,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH3_ST_CLR_S 7 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR (BIT(8)) @@ -5766,8 +6234,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH4_ST_CLR_S 8 /** SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR (BIT(9)) @@ -5775,8 +6243,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_PAUSE_CH5_ST_CLR_S 9 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR (BIT(10)) @@ -5784,8 +6252,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH0_ST_CLR_S 10 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR (BIT(11)) @@ -5793,8 +6261,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH1_ST_CLR_S 11 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR (BIT(12)) @@ -5802,8 +6270,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH2_ST_CLR_S 12 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR (BIT(13)) @@ -5811,8 +6279,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH3_ST_CLR_S 13 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR (BIT(14)) @@ -5820,8 +6288,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH4_ST_CLR_S 14 /** SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR (BIT(15)) @@ -5829,8 +6297,8 @@ extern "C" { #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_V 0x00000001U #define SOC_ETM_LEDC_TASK_GAMMA_RESUME_CH5_ST_CLR_S 15 /** SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR (BIT(16)) @@ -5838,8 +6306,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER0_ST_CLR_S 16 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR (BIT(17)) @@ -5847,8 +6315,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER0_ST_CLR_S 17 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(18)) @@ -5856,8 +6324,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER0_ST_CLR_S 18 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(19)) @@ -5865,8 +6333,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 19 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(20)) @@ -5874,8 +6342,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER0_ST_CLR_S 20 /** SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR (BIT(21)) @@ -5883,8 +6351,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_START_TIMER1_ST_CLR_S 21 /** SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR (BIT(22)) @@ -5892,8 +6360,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_ALARM_START_TIMER1_ST_CLR_S 22 /** SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(23)) @@ -5901,8 +6369,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_STOP_TIMER1_ST_CLR_S 23 /** SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(24)) @@ -5910,8 +6378,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 24 /** SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(25)) @@ -5919,8 +6387,8 @@ extern "C" { #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG0_TASK_CNT_CAP_TIMER1_ST_CLR_S 25 /** SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR (BIT(26)) @@ -5928,8 +6396,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_START_TIMER0_ST_CLR_S 26 /** SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR (BIT(27)) @@ -5937,8 +6405,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER0_ST_CLR_S 27 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR (BIT(28)) @@ -5946,8 +6414,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER0_ST_CLR_S 28 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR (BIT(29)) @@ -5955,8 +6423,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER0_ST_CLR_S 29 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR (BIT(30)) @@ -5964,8 +6432,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER0_ST_CLR_S 30 /** SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR (BIT(31)) @@ -5974,11 +6442,11 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_START_TIMER1_ST_CLR_S 31 /** SOC_ETM_TASK_ST3_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST3_REG (DR_REG_SOC_ETM_BASE + 0x1e0) /** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG1_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5987,7 +6455,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_S 0 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST : R/WTC/SS; bitpos: [1]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG1_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -5996,7 +6464,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_S 1 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG1_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6005,7 +6473,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_S 2 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST : R/WTC/SS; bitpos: [3]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG1_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6014,7 +6482,7 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_S 3 /** SOC_ETM_ADC_TASK_SAMPLE0_ST : R/WTC/SS; bitpos: [4]; default: 0; - * Represents ADC_TASK_SAMPLE0 trigger status. + * Represents ADC_task_sample0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6022,8 +6490,17 @@ extern "C" { #define SOC_ETM_ADC_TASK_SAMPLE0_ST_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_S 5 /** SOC_ETM_ADC_TASK_START0_ST : R/WTC/SS; bitpos: [6]; default: 0; - * Represents ADC_TASK_START0 trigger status. + * Represents ADC_task_start0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6032,7 +6509,7 @@ extern "C" { #define SOC_ETM_ADC_TASK_START0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_START0_ST_S 6 /** SOC_ETM_ADC_TASK_STOP0_ST : R/WTC/SS; bitpos: [7]; default: 0; - * Represents ADC_TASK_STOP0 trigger status. + * Represents ADC_task_stop0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6040,8 +6517,44 @@ extern "C" { #define SOC_ETM_ADC_TASK_STOP0_ST_M (SOC_ETM_ADC_TASK_STOP0_ST_V << SOC_ETM_ADC_TASK_STOP0_ST_S) #define SOC_ETM_ADC_TASK_STOP0_ST_V 0x00000001U #define SOC_ETM_ADC_TASK_STOP0_ST_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START0_ST (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_M (SOC_ETM_REGDMA_TASK_START0_ST_V << SOC_ETM_REGDMA_TASK_START0_ST_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START1_ST (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_M (SOC_ETM_REGDMA_TASK_START1_ST_V << SOC_ETM_REGDMA_TASK_START1_ST_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START2_ST (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_M (SOC_ETM_REGDMA_TASK_START2_ST_V << SOC_ETM_REGDMA_TASK_START2_ST_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_REGDMA_TASK_START3_ST (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_M (SOC_ETM_REGDMA_TASK_START3_ST_V << SOC_ETM_REGDMA_TASK_START3_ST_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_S 11 /** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST : R/WTC/SS; bitpos: [12]; default: 0; - * Represents TMPSNSR_TASK_START_SAMPLE trigger status. + * Represents TMPSNSR_task_start_sample trigger status. * 0: Not triggered * 1: Triggered */ @@ -6050,7 +6563,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_S 12 /** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST : R/WTC/SS; bitpos: [13]; default: 0; - * Represents TMPSNSR_TASK_STOP_SAMPLE trigger status. + * Represents TMPSNSR_task_stop_sample trigger status. * 0: Not triggered * 1: Triggered */ @@ -6059,7 +6572,7 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_S 13 /** SOC_ETM_I2S0_TASK_START_RX_ST : R/WTC/SS; bitpos: [14]; default: 0; - * Represents I2S0_TASK_START_RX trigger status. + * Represents I2S0_task_start_rx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6068,7 +6581,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_RX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_RX_ST_S 14 /** SOC_ETM_I2S0_TASK_START_TX_ST : R/WTC/SS; bitpos: [15]; default: 0; - * Represents I2S0_TASK_START_TX trigger status. + * Represents I2S0_task_start_tx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6077,7 +6590,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_TX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_TX_ST_S 15 /** SOC_ETM_I2S0_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [16]; default: 0; - * Represents I2S0_TASK_STOP_RX trigger status. + * Represents I2S0_task_stop_rx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6086,7 +6599,7 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_RX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_RX_ST_S 16 /** SOC_ETM_I2S0_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [17]; default: 0; - * Represents I2S0_TASK_STOP_TX trigger status. + * Represents I2S0_task_stop_tx trigger status. * 0: Not triggered * 1: Triggered */ @@ -6094,8 +6607,98 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_TX_ST_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_S) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_TX_ST_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_M (SOC_ETM_I2S1_TASK_START_RX_ST_V << SOC_ETM_I2S1_TASK_START_RX_ST_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_M (SOC_ETM_I2S1_TASK_START_TX_ST_V << SOC_ETM_I2S1_TASK_START_TX_ST_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_M (SOC_ETM_ULP_TASK_INT_CPU_ST_V << SOC_ETM_ULP_TASK_INT_CPU_ST_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_S 23 +/** SOC_ETM_RTC_TASK_START_ST : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_START_ST (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_M (SOC_ETM_RTC_TASK_START_ST_V << SOC_ETM_RTC_TASK_START_ST_S) +#define SOC_ETM_RTC_TASK_START_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_STOP_ST (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_M (SOC_ETM_RTC_TASK_STOP_ST_V << SOC_ETM_RTC_TASK_STOP_ST_S) +#define SOC_ETM_RTC_TASK_STOP_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_CLR_ST (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_M (SOC_ETM_RTC_TASK_CLR_ST_V << SOC_ETM_RTC_TASK_CLR_ST_S) +#define SOC_ETM_RTC_TASK_CLR_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_S 27 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH0 trigger status. + * Represents GDMA_AHB_task_in_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6104,7 +6707,7 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_S 28 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH1 trigger status. + * Represents GDMA_AHB_task_in_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6112,8 +6715,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_S 30 /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH0 trigger status. + * Represents GDMA_AHB_task_out_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6123,12 +6735,12 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_S 31 /** SOC_ETM_TASK_ST3_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST3_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1e4) /** SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR (BIT(0)) @@ -6136,8 +6748,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_ALARM_START_TIMER1_ST_CLR_S 0 /** SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR (BIT(1)) @@ -6145,8 +6757,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_STOP_TIMER1_ST_CLR_S 1 /** SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR (BIT(2)) @@ -6154,8 +6766,8 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_RELOAD_TIMER1_ST_CLR_S 2 /** SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR (BIT(3)) @@ -6163,17 +6775,26 @@ extern "C" { #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_V 0x00000001U #define SOC_ETM_TG1_TASK_CNT_CAP_TIMER1_ST_CLR_S 3 /** SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear ADC_TASK_SAMPLE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_sample0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR (BIT(4)) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S) #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_SAMPLE0_ST_CLR_S 4 +/** SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR (BIT(5)) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_M (SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V << SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S) +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_V 0x00000001U +#define SOC_ETM_ADC_TASK_SAMPLE1_ST_CLR_S 5 /** SOC_ETM_ADC_TASK_START0_ST_CLR : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear ADC_TASK_START0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_start0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_START0_ST_CLR (BIT(6)) @@ -6181,17 +6802,53 @@ extern "C" { #define SOC_ETM_ADC_TASK_START0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_START0_ST_CLR_S 6 /** SOC_ETM_ADC_TASK_STOP0_ST_CLR : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear ADC_TASK_STOP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_stop0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_ADC_TASK_STOP0_ST_CLR (BIT(7)) #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_M (SOC_ETM_ADC_TASK_STOP0_ST_CLR_V << SOC_ETM_ADC_TASK_STOP0_ST_CLR_S) #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_V 0x00000001U #define SOC_ETM_ADC_TASK_STOP0_ST_CLR_S 7 +/** SOC_ETM_REGDMA_TASK_START0_ST_CLR : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR (BIT(8)) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_M (SOC_ETM_REGDMA_TASK_START0_ST_CLR_V << SOC_ETM_REGDMA_TASK_START0_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START0_ST_CLR_S 8 +/** SOC_ETM_REGDMA_TASK_START1_ST_CLR : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR (BIT(9)) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_M (SOC_ETM_REGDMA_TASK_START1_ST_CLR_V << SOC_ETM_REGDMA_TASK_START1_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START1_ST_CLR_S 9 +/** SOC_ETM_REGDMA_TASK_START2_ST_CLR : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR (BIT(10)) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_M (SOC_ETM_REGDMA_TASK_START2_ST_CLR_V << SOC_ETM_REGDMA_TASK_START2_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START2_ST_CLR_S 10 +/** SOC_ETM_REGDMA_TASK_START3_ST_CLR : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR (BIT(11)) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_M (SOC_ETM_REGDMA_TASK_START3_ST_CLR_V << SOC_ETM_REGDMA_TASK_START3_ST_CLR_S) +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_V 0x00000001U +#define SOC_ETM_REGDMA_TASK_START3_ST_CLR_S 11 /** SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_START_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR (BIT(12)) @@ -6199,8 +6856,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_START_SAMPLE_ST_CLR_S 12 /** SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_STOP_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR (BIT(13)) @@ -6208,8 +6865,8 @@ extern "C" { #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_V 0x00000001U #define SOC_ETM_TMPSNSR_TASK_STOP_SAMPLE_ST_CLR_S 13 /** SOC_ETM_I2S0_TASK_START_RX_ST_CLR : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR (BIT(14)) @@ -6217,8 +6874,8 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_RX_ST_CLR_S 14 /** SOC_ETM_I2S0_TASK_START_TX_ST_CLR : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR (BIT(15)) @@ -6226,8 +6883,8 @@ extern "C" { #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_START_TX_ST_CLR_S 15 /** SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR (BIT(16)) @@ -6235,17 +6892,107 @@ extern "C" { #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_RX_ST_CLR_S 16 /** SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR (BIT(17)) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S) #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_V 0x00000001U #define SOC_ETM_I2S0_TASK_STOP_TX_ST_CLR_S 17 +/** SOC_ETM_I2S1_TASK_START_RX_ST_CLR : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR (BIT(18)) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_RX_ST_CLR_S 18 +/** SOC_ETM_I2S1_TASK_START_TX_ST_CLR : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR (BIT(19)) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_START_TX_ST_CLR_S 19 +/** SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR (BIT(20)) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_RX_ST_CLR_S 20 +/** SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR (BIT(21)) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_M (SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V << SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S) +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_V 0x00000001U +#define SOC_ETM_I2S1_TASK_STOP_TX_ST_CLR_S 21 +/** SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR (BIT(22)) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_WAKEUP_CPU_ST_CLR_S 22 +/** SOC_ETM_ULP_TASK_INT_CPU_ST_CLR : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR (BIT(23)) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_M (SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V << SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S) +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_V 0x00000001U +#define SOC_ETM_ULP_TASK_INT_CPU_ST_CLR_S 23 +/** SOC_ETM_RTC_TASK_START_ST_CLR : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_START_ST_CLR (BIT(24)) +#define SOC_ETM_RTC_TASK_START_ST_CLR_M (SOC_ETM_RTC_TASK_START_ST_CLR_V << SOC_ETM_RTC_TASK_START_ST_CLR_S) +#define SOC_ETM_RTC_TASK_START_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_START_ST_CLR_S 24 +/** SOC_ETM_RTC_TASK_STOP_ST_CLR : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_STOP_ST_CLR (BIT(25)) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_M (SOC_ETM_RTC_TASK_STOP_ST_CLR_V << SOC_ETM_RTC_TASK_STOP_ST_CLR_S) +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_STOP_ST_CLR_S 25 +/** SOC_ETM_RTC_TASK_CLR_ST_CLR : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_CLR_ST_CLR (BIT(26)) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_M (SOC_ETM_RTC_TASK_CLR_ST_CLR_V << SOC_ETM_RTC_TASK_CLR_ST_CLR_S) +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_CLR_ST_CLR_S 26 +/** SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR (BIT(27)) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_M (SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V << SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S) +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_V 0x00000001U +#define SOC_ETM_RTC_TASK_TRIGGERFLW_ST_CLR_S 27 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR (BIT(28)) @@ -6253,17 +7000,26 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH0_ST_CLR_S 28 /** SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR (BIT(29)) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_IN_START_CH1_ST_CLR_S 29 +/** SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR (BIT(30)) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_IN_START_CH2_ST_CLR_S 30 /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR (BIT(31)) @@ -6272,11 +7028,11 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH0_ST_CLR_S 31 /** SOC_ETM_TASK_ST4_REG register - * Task trigger status register + * Tasks trigger status register */ #define SOC_ETM_TASK_ST4_REG (DR_REG_SOC_ETM_BASE + 0x1e8) /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH1 trigger status. + * Represents GDMA_AHB_task_out_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -6284,8 +7040,17 @@ extern "C" { #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_S 1 /** SOC_ETM_PMU_TASK_SLEEP_REQ_ST : R/WTC/SS; bitpos: [2]; default: 0; - * Represents PMU_TASK_SLEEP_REQ trigger status. + * Represents PMU_task_sleep_req trigger status. * 0: Not triggered * 1: Triggered */ @@ -6295,21 +7060,30 @@ extern "C" { #define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_S 2 /** SOC_ETM_TASK_ST4_CLR_REG register - * Task trigger status clear register + * Tasks trigger status clear register */ #define SOC_ETM_TASK_ST4_CLR_REG (DR_REG_SOC_ETM_BASE + 0x1ec) /** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR (BIT(0)) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S) #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_V 0x00000001U #define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH1_ST_CLR_S 0 +/** SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR (BIT(1)) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_M (SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V << SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S) +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_V 0x00000001U +#define SOC_ETM_GDMA_AHB_TASK_OUT_START_CH2_ST_CLR_S 1 /** SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear PMU_TASK_SLEEP_REQ trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_task_sleep_req trigger status. + * 0: Invalid, No effect * 1: Clear */ #define SOC_ETM_PMU_TASK_SLEEP_REQ_ST_CLR (BIT(2)) @@ -6332,11 +7106,11 @@ extern "C" { #define SOC_ETM_CLK_EN_S 0 /** SOC_ETM_DATE_REG register - * Version control register + * ETM date register */ #define SOC_ETM_DATE_REG (DR_REG_SOC_ETM_BASE + 0x1f4) /** SOC_ETM_DATE : R/W; bitpos: [27:0]; default: 36737361; - * Version control register. + * Configures the version. */ #define SOC_ETM_DATE 0x0FFFFFFFU #define SOC_ETM_DATE_M (SOC_ETM_DATE_V << SOC_ETM_DATE_S) diff --git a/components/soc/esp32c61/register/soc/soc_etm_struct.h b/components/soc/esp32c61/register/soc/soc_etm_struct.h index 397d823bd9..42dca6dc89 100644 --- a/components/soc/esp32c61/register/soc/soc_etm_struct.h +++ b/components/soc/esp32c61/register/soc/soc_etm_struct.h @@ -1,7 +1,7 @@ /** - * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * - * SPDX-License-Identifier: Apache-2.0 + * SPDX-License-Identifier: Apache-2.0 */ #pragma once @@ -16,194 +16,194 @@ extern "C" { */ typedef union { struct { - /** ch_enabled0 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel0 enable status. + /** ch_enabled0 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch0 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled0:1; - /** ch_enabled1 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel1 enable status. + /** ch_enabled1 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch1 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled1:1; - /** ch_enabled2 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel2 enable status. + /** ch_enabled2 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch2 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled2:1; - /** ch_enabled3 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel3 enable status. + /** ch_enabled3 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch3 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled3:1; - /** ch_enabled4 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel4 enable status. + /** ch_enabled4 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch4 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled4:1; - /** ch_enabled5 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel5 enable status. + /** ch_enabled5 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch5 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled5:1; - /** ch_enabled6 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel6 enable status. + /** ch_enabled6 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch6 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled6:1; - /** ch_enabled7 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel7 enable status. + /** ch_enabled7 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch7 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled7:1; - /** ch_enabled8 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel8 enable status. + /** ch_enabled8 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch8 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled8:1; - /** ch_enabled9 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel9 enable status. + /** ch_enabled9 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch9 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled9:1; - /** ch_enabled10 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel10 enable status. + /** ch_enabled10 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch10 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled10:1; - /** ch_enabled11 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel11 enable status. + /** ch_enabled11 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch11 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled11:1; - /** ch_enabled12 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel12 enable status. + /** ch_enabled12 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch12 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled12:1; - /** ch_enabled13 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel13 enable status. + /** ch_enabled13 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch13 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled13:1; - /** ch_enabled14 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel14 enable status. + /** ch_enabled14 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch14 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled14:1; - /** ch_enabled15 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel15 enable status. + /** ch_enabled15 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch15 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled15:1; - /** ch_enabled16 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel16 enable status. + /** ch_enabled16 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch16 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled16:1; - /** ch_enabled17 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel17 enable status. + /** ch_enabled17 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch17 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled17:1; - /** ch_enabled18 : R/WTC/WS; bitpos: [18]; default: 0; - * Represents channel18 enable status. + /** ch_enabled18 : R/WTC/WTS; bitpos: [18]; default: 0; + * Represents ch18 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled18:1; - /** ch_enabled19 : R/WTC/WS; bitpos: [19]; default: 0; - * Represents channel19 enable status. + /** ch_enabled19 : R/WTC/WTS; bitpos: [19]; default: 0; + * Represents ch19 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled19:1; - /** ch_enabled20 : R/WTC/WS; bitpos: [20]; default: 0; - * Represents channel20 enable status. + /** ch_enabled20 : R/WTC/WTS; bitpos: [20]; default: 0; + * Represents ch20 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled20:1; - /** ch_enabled21 : R/WTC/WS; bitpos: [21]; default: 0; - * Represents channel21 enable status. + /** ch_enabled21 : R/WTC/WTS; bitpos: [21]; default: 0; + * Represents ch21 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled21:1; - /** ch_enabled22 : R/WTC/WS; bitpos: [22]; default: 0; - * Represents channel22 enable status. + /** ch_enabled22 : R/WTC/WTS; bitpos: [22]; default: 0; + * Represents ch22 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled22:1; - /** ch_enabled23 : R/WTC/WS; bitpos: [23]; default: 0; - * Represents channel23 enable status. + /** ch_enabled23 : R/WTC/WTS; bitpos: [23]; default: 0; + * Represents ch23 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled23:1; - /** ch_enabled24 : R/WTC/WS; bitpos: [24]; default: 0; - * Represents channel24 enable status. + /** ch_enabled24 : R/WTC/WTS; bitpos: [24]; default: 0; + * Represents ch24 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled24:1; - /** ch_enabled25 : R/WTC/WS; bitpos: [25]; default: 0; - * Represents channel25 enable status. + /** ch_enabled25 : R/WTC/WTS; bitpos: [25]; default: 0; + * Represents ch25 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled25:1; - /** ch_enabled26 : R/WTC/WS; bitpos: [26]; default: 0; - * Represents channel26 enable status. + /** ch_enabled26 : R/WTC/WTS; bitpos: [26]; default: 0; + * Represents ch26 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled26:1; - /** ch_enabled27 : R/WTC/WS; bitpos: [27]; default: 0; - * Represents channel27 enable status. + /** ch_enabled27 : R/WTC/WTS; bitpos: [27]; default: 0; + * Represents ch27 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled27:1; - /** ch_enabled28 : R/WTC/WS; bitpos: [28]; default: 0; - * Represents channel28 enable status. + /** ch_enabled28 : R/WTC/WTS; bitpos: [28]; default: 0; + * Represents ch28 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled28:1; - /** ch_enabled29 : R/WTC/WS; bitpos: [29]; default: 0; - * Represents channel29 enable status. + /** ch_enabled29 : R/WTC/WTS; bitpos: [29]; default: 0; + * Represents ch29 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled29:1; - /** ch_enabled30 : R/WTC/WS; bitpos: [30]; default: 0; - * Represents channel30 enable status. + /** ch_enabled30 : R/WTC/WTS; bitpos: [30]; default: 0; + * Represents ch30 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled30:1; - /** ch_enabled31 : R/WTC/WS; bitpos: [31]; default: 0; - * Represents channel31 enable status. + /** ch_enabled31 : R/WTC/WTS; bitpos: [31]; default: 0; + * Represents ch31 enable status. * 0: Disable * 1: Enable */ @@ -217,110 +217,110 @@ typedef union { */ typedef union { struct { - /** ch_enabled32 : R/WTC/WS; bitpos: [0]; default: 0; - * Represents channel32 enable status. + /** ch_enabled32 : R/WTC/WTS; bitpos: [0]; default: 0; + * Represents ch32 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled32:1; - /** ch_enabled33 : R/WTC/WS; bitpos: [1]; default: 0; - * Represents channel33 enable status. + /** ch_enabled33 : R/WTC/WTS; bitpos: [1]; default: 0; + * Represents ch33 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled33:1; - /** ch_enabled34 : R/WTC/WS; bitpos: [2]; default: 0; - * Represents channel34 enable status. + /** ch_enabled34 : R/WTC/WTS; bitpos: [2]; default: 0; + * Represents ch34 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled34:1; - /** ch_enabled35 : R/WTC/WS; bitpos: [3]; default: 0; - * Represents channel35 enable status. + /** ch_enabled35 : R/WTC/WTS; bitpos: [3]; default: 0; + * Represents ch35 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled35:1; - /** ch_enabled36 : R/WTC/WS; bitpos: [4]; default: 0; - * Represents channel36 enable status. + /** ch_enabled36 : R/WTC/WTS; bitpos: [4]; default: 0; + * Represents ch36 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled36:1; - /** ch_enabled37 : R/WTC/WS; bitpos: [5]; default: 0; - * Represents channel37 enable status. + /** ch_enabled37 : R/WTC/WTS; bitpos: [5]; default: 0; + * Represents ch37 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled37:1; - /** ch_enabled38 : R/WTC/WS; bitpos: [6]; default: 0; - * Represents channel38 enable status. + /** ch_enabled38 : R/WTC/WTS; bitpos: [6]; default: 0; + * Represents ch38 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled38:1; - /** ch_enabled39 : R/WTC/WS; bitpos: [7]; default: 0; - * Represents channel39 enable status. + /** ch_enabled39 : R/WTC/WTS; bitpos: [7]; default: 0; + * Represents ch39 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled39:1; - /** ch_enabled40 : R/WTC/WS; bitpos: [8]; default: 0; - * Represents channel40 enable status. + /** ch_enabled40 : R/WTC/WTS; bitpos: [8]; default: 0; + * Represents ch40 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled40:1; - /** ch_enabled41 : R/WTC/WS; bitpos: [9]; default: 0; - * Represents channel41 enable status. + /** ch_enabled41 : R/WTC/WTS; bitpos: [9]; default: 0; + * Represents ch41 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled41:1; - /** ch_enabled42 : R/WTC/WS; bitpos: [10]; default: 0; - * Represents channel42 enable status. + /** ch_enabled42 : R/WTC/WTS; bitpos: [10]; default: 0; + * Represents ch42 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled42:1; - /** ch_enabled43 : R/WTC/WS; bitpos: [11]; default: 0; - * Represents channel43 enable status. + /** ch_enabled43 : R/WTC/WTS; bitpos: [11]; default: 0; + * Represents ch43 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled43:1; - /** ch_enabled44 : R/WTC/WS; bitpos: [12]; default: 0; - * Represents channel44 enable status. + /** ch_enabled44 : R/WTC/WTS; bitpos: [12]; default: 0; + * Represents ch44 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled44:1; - /** ch_enabled45 : R/WTC/WS; bitpos: [13]; default: 0; - * Represents channel45 enable status. + /** ch_enabled45 : R/WTC/WTS; bitpos: [13]; default: 0; + * Represents ch45 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled45:1; - /** ch_enabled46 : R/WTC/WS; bitpos: [14]; default: 0; - * Represents channel46 enable status. + /** ch_enabled46 : R/WTC/WTS; bitpos: [14]; default: 0; + * Represents ch46 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled46:1; - /** ch_enabled47 : R/WTC/WS; bitpos: [15]; default: 0; - * Represents channel47 enable status. + /** ch_enabled47 : R/WTC/WTS; bitpos: [15]; default: 0; + * Represents ch47 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled47:1; - /** ch_enabled48 : R/WTC/WS; bitpos: [16]; default: 0; - * Represents channel48 enable status. + /** ch_enabled48 : R/WTC/WTS; bitpos: [16]; default: 0; + * Represents ch48 enable status. * 0: Disable * 1: Enable */ uint32_t ch_enabled48:1; - /** ch_enabled49 : R/WTC/WS; bitpos: [17]; default: 0; - * Represents channel49 enable status. + /** ch_enabled49 : R/WTC/WTS; bitpos: [17]; default: 0; + * Represents ch49 enable status. * 0: Disable * 1: Enable */ @@ -331,187 +331,198 @@ typedef union { } soc_etm_ch_ena_ad1_reg_t; /** Type of evt_st0 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** gpio_evt_ch0_rise_edge_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_EVT_CH0_RISE_EDGE trigger status. + * Represents GPIO_evt_ch0_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_rise_edge_st:1; /** gpio_evt_ch1_rise_edge_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_EVT_CH1_RISE_EDGE trigger status. + * Represents GPIO_evt_ch1_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_rise_edge_st:1; /** gpio_evt_ch2_rise_edge_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_EVT_CH2_RISE_EDGE trigger status. + * Represents GPIO_evt_ch2_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_rise_edge_st:1; /** gpio_evt_ch3_rise_edge_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_EVT_CH3_RISE_EDGE trigger status. + * Represents GPIO_evt_ch3_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_rise_edge_st:1; /** gpio_evt_ch4_rise_edge_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_EVT_CH4_RISE_EDGE trigger status. + * Represents GPIO_evt_ch4_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_rise_edge_st:1; /** gpio_evt_ch5_rise_edge_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_EVT_CH5_RISE_EDGE trigger status. + * Represents GPIO_evt_ch5_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_rise_edge_st:1; /** gpio_evt_ch6_rise_edge_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_EVT_CH6_RISE_EDGE trigger status. + * Represents GPIO_evt_ch6_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_rise_edge_st:1; /** gpio_evt_ch7_rise_edge_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_EVT_CH7_RISE_EDGE trigger status. + * Represents GPIO_evt_ch7_rise_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_rise_edge_st:1; /** gpio_evt_ch0_fall_edge_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_EVT_CH0_FALL_EDGE trigger status. + * Represents GPIO_evt_ch0_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_fall_edge_st:1; /** gpio_evt_ch1_fall_edge_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_EVT_CH1_FALL_EDGE trigger status. + * Represents GPIO_evt_ch1_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_fall_edge_st:1; /** gpio_evt_ch2_fall_edge_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_EVT_CH2_FALL_EDGE trigger status. + * Represents GPIO_evt_ch2_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_fall_edge_st:1; /** gpio_evt_ch3_fall_edge_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_EVT_CH3_FALL_EDGE trigger status. + * Represents GPIO_evt_ch3_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_fall_edge_st:1; /** gpio_evt_ch4_fall_edge_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_EVT_CH4_FALL_EDGE trigger status. + * Represents GPIO_evt_ch4_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_fall_edge_st:1; /** gpio_evt_ch5_fall_edge_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_EVT_CH5_FALL_EDGE trigger status. + * Represents GPIO_evt_ch5_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_fall_edge_st:1; /** gpio_evt_ch6_fall_edge_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_EVT_CH6_FALL_EDGE trigger status. + * Represents GPIO_evt_ch6_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_fall_edge_st:1; /** gpio_evt_ch7_fall_edge_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_EVT_CH7_FALL_EDGE trigger status. + * Represents GPIO_evt_ch7_fall_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_fall_edge_st:1; /** gpio_evt_ch0_any_edge_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_EVT_CH0_ANY_EDGE trigger status. + * Represents GPIO_evt_ch0_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch0_any_edge_st:1; /** gpio_evt_ch1_any_edge_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_EVT_CH1_ANY_EDGE trigger status. + * Represents GPIO_evt_ch1_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch1_any_edge_st:1; /** gpio_evt_ch2_any_edge_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_EVT_CH2_ANY_EDGE trigger status. + * Represents GPIO_evt_ch2_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch2_any_edge_st:1; /** gpio_evt_ch3_any_edge_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_EVT_CH3_ANY_EDGE trigger status. + * Represents GPIO_evt_ch3_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch3_any_edge_st:1; /** gpio_evt_ch4_any_edge_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_EVT_CH4_ANY_EDGE trigger status. + * Represents GPIO_evt_ch4_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch4_any_edge_st:1; /** gpio_evt_ch5_any_edge_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_EVT_CH5_ANY_EDGE trigger status. + * Represents GPIO_evt_ch5_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch5_any_edge_st:1; /** gpio_evt_ch6_any_edge_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_EVT_CH6_ANY_EDGE trigger status. + * Represents GPIO_evt_ch6_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch6_any_edge_st:1; /** gpio_evt_ch7_any_edge_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_EVT_CH7_ANY_EDGE trigger status. + * Represents GPIO_evt_ch7_any_edge trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_ch7_any_edge_st:1; /** gpio_evt_zero_det_pos0_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents GPIO_EVT_ZERO_DET_POS0 trigger status. + * Represents GPIO_evt_zero_det_pos0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_zero_det_pos0_st:1; /** gpio_evt_zero_det_neg0_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GPIO_EVT_ZERO_DET_NEG0 trigger status. + * Represents GPIO_evt_zero_det_neg0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_evt_zero_det_neg0_st:1; - uint32_t reserved_26:2; + /** gpio_evt_zero_det_pos1_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents GPIO_evt_zero_det_pos1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gpio_evt_zero_det_pos1_st:1; + /** gpio_evt_zero_det_neg1_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GPIO_evt_zero_det_neg1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gpio_evt_zero_det_neg1_st:1; /** ledc_evt_duty_chng_end_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. + * Represents LEDC_evt_duty_chng_end_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch0_st:1; /** ledc_evt_duty_chng_end_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. + * Represents LEDC_evt_duty_chng_end_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch1_st:1; /** ledc_evt_duty_chng_end_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. + * Represents LEDC_evt_duty_chng_end_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch2_st:1; /** ledc_evt_duty_chng_end_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. + * Represents LEDC_evt_duty_chng_end_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -521,297 +532,399 @@ typedef union { } soc_etm_evt_st0_reg_t; /** Type of evt_st1 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** ledc_evt_duty_chng_end_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. + * Represents LEDC_evt_duty_chng_end_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch4_st:1; /** ledc_evt_duty_chng_end_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. + * Represents LEDC_evt_duty_chng_end_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_duty_chng_end_ch5_st:1; /** ledc_evt_ovf_cnt_pls_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch0_st:1; /** ledc_evt_ovf_cnt_pls_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch1_st:1; /** ledc_evt_ovf_cnt_pls_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch2_st:1; /** ledc_evt_ovf_cnt_pls_ch3_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch3_st:1; /** ledc_evt_ovf_cnt_pls_ch4_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch4_st:1; /** ledc_evt_ovf_cnt_pls_ch5_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. + * Represents LEDC_evt_ovf_cnt_pls_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_ovf_cnt_pls_ch5_st:1; /** ledc_evt_time_ovf_timer0_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER0 trigger status. + * Represents LEDC_evt_time_ovf_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer0_st:1; /** ledc_evt_time_ovf_timer1_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER1 trigger status. + * Represents LEDC_evt_time_ovf_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer1_st:1; /** ledc_evt_time_ovf_timer2_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER2 trigger status. + * Represents LEDC_evt_time_ovf_timer2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer2_st:1; /** ledc_evt_time_ovf_timer3_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_EVT_TIME_OVF_TIMER3 trigger status. + * Represents LEDC_evt_time_ovf_timer3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_time_ovf_timer3_st:1; /** ledc_evt_timer0_cmp_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_EVT_TIMER0_CMP trigger status. + * Represents LEDC_evt_timer0_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer0_cmp_st:1; /** ledc_evt_timer1_cmp_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_EVT_TIMER1_CMP trigger status. + * Represents LEDC_evt_timer1_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer1_cmp_st:1; /** ledc_evt_timer2_cmp_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_EVT_TIMER2_CMP trigger status. + * Represents LEDC_evt_timer2_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer2_cmp_st:1; /** ledc_evt_timer3_cmp_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_EVT_TIMER3_CMP trigger status. + * Represents LEDC_evt_timer3_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_evt_timer3_cmp_st:1; /** tg0_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG0_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_evt_cnt_cmp_timer0_st:1; /** tg0_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG0_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_evt_cnt_cmp_timer1_st:1; /** tg1_evt_cnt_cmp_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER0 trigger status. + * Represents TG1_evt_cnt_cmp_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_evt_cnt_cmp_timer0_st:1; /** tg1_evt_cnt_cmp_timer1_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG1_EVT_CNT_CMP_TIMER1 trigger status. + * Represents TG1_evt_cnt_cmp_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_evt_cnt_cmp_timer1_st:1; /** systimer_evt_cnt_cmp0_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP0 trigger status. + * Represents SYSTIMER_evt_cnt_cmp0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp0_st:1; /** systimer_evt_cnt_cmp1_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP1 trigger status. + * Represents SYSTIMER_evt_cnt_cmp1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp1_st:1; /** systimer_evt_cnt_cmp2_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents SYSTIMER_EVT_CNT_CMP2 trigger status. + * Represents SYSTIMER_evt_cnt_cmp2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t systimer_evt_cnt_cmp2_st:1; /** adc_evt_conv_cmplt0_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents ADC_EVT_CONV_CMPLT0 trigger status. + * Represents ADC_evt_conv_cmplt0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_conv_cmplt0_st:1; /** adc_evt_eq_above_thresh0_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH0 trigger status. + * Represents ADC_evt_eq_above_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_above_thresh0_st:1; /** adc_evt_eq_above_thresh1_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents ADC_EVT_EQ_ABOVE_THRESH1 trigger status. + * Represents ADC_evt_eq_above_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_above_thresh1_st:1; /** adc_evt_eq_below_thresh0_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH0 trigger status. + * Represents ADC_evt_eq_below_thresh0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_below_thresh0_st:1; /** adc_evt_eq_below_thresh1_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents ADC_EVT_EQ_BELOW_THRESH1 trigger status. + * Represents ADC_evt_eq_below_thresh1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_eq_below_thresh1_st:1; /** adc_evt_result_done0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents ADC_EVT_RESULT_DONE0 trigger status. + * Represents ADC_evt_result_done0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_result_done0_st:1; /** adc_evt_stopped0_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents ADC_EVT_STOPPED0 trigger status. + * Represents ADC_evt_stopped0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_stopped0_st:1; /** adc_evt_started0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents ADC_EVT_STARTED0 trigger status. + * Represents ADC_evt_started0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_evt_started0_st:1; - uint32_t reserved_31:1; + /** regdma_evt_done0_st : R/WTC/SS; bitpos: [31]; default: 0; + * Represents REGDMA_evt_done0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done0_st:1; }; uint32_t val; } soc_etm_evt_st1_reg_t; /** Type of evt_st2 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { - uint32_t reserved_0:7; + /** regdma_evt_done1_st : R/WTC/SS; bitpos: [0]; default: 0; + * Represents REGDMA_evt_done1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done1_st:1; + /** regdma_evt_done2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents REGDMA_evt_done2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done2_st:1; + /** regdma_evt_done3_st : R/WTC/SS; bitpos: [2]; default: 0; + * Represents REGDMA_evt_done3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_done3_st:1; + /** regdma_evt_err0_st : R/WTC/SS; bitpos: [3]; default: 0; + * Represents REGDMA_evt_err0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err0_st:1; + /** regdma_evt_err1_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents REGDMA_evt_err1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err1_st:1; + /** regdma_evt_err2_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents REGDMA_evt_err2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err2_st:1; + /** regdma_evt_err3_st : R/WTC/SS; bitpos: [6]; default: 0; + * Represents REGDMA_evt_err3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_evt_err3_st:1; /** tmpsnsr_evt_over_limit_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents TMPSNSR_EVT_OVER_LIMIT trigger status. + * Represents TMPSNSR_evt_over_limit trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_evt_over_limit_st:1; /** i2s0_evt_rx_done_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents I2S0_EVT_RX_DONE trigger status. + * Represents I2S0_evt_rx_done trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_rx_done_st:1; /** i2s0_evt_tx_done_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents I2S0_EVT_TX_DONE trigger status. + * Represents I2S0_evt_tx_done trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_tx_done_st:1; /** i2s0_evt_x_words_received_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents I2S0_EVT_X_WORDS_RECEIVED trigger status. + * Represents I2S0_evt_x_words_received trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_x_words_received_st:1; /** i2s0_evt_x_words_sent_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents I2S0_EVT_X_WORDS_SENT trigger status. + * Represents I2S0_evt_x_words_sent trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_evt_x_words_sent_st:1; - uint32_t reserved_12:7; + /** i2s1_evt_rx_done_st : R/WTC/SS; bitpos: [12]; default: 0; + * Represents I2S1_evt_rx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_rx_done_st:1; + /** i2s1_evt_tx_done_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents I2S1_evt_tx_done trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_tx_done_st:1; + /** i2s1_evt_x_words_received_st : R/WTC/SS; bitpos: [14]; default: 0; + * Represents I2S1_evt_x_words_received trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_x_words_received_st:1; + /** i2s1_evt_x_words_sent_st : R/WTC/SS; bitpos: [15]; default: 0; + * Represents I2S1_evt_x_words_sent trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_evt_x_words_sent_st:1; + /** ulp_evt_err_intr_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents ULP_evt_err_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_err_intr_st:1; + /** ulp_evt_halt_st : R/WTC/SS; bitpos: [17]; default: 0; + * Represents ULP_evt_halt trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_halt_st:1; + /** ulp_evt_start_intr_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents ULP_evt_start_intr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_evt_start_intr_st:1; /** rtc_evt_tick_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents RTC_EVT_TICK trigger status. + * Represents RTC_evt_tick trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_tick_st:1; /** rtc_evt_ovf_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents RTC_EVT_OVF trigger status. + * Represents RTC_evt_ovf trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_ovf_st:1; /** rtc_evt_cmp_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents RTC_EVT_CMP trigger status. + * Represents RTC_evt_cmp trigger status. * 0: Not triggered * 1: Triggered */ uint32_t rtc_evt_cmp_st:1; /** gdma_ahb_evt_in_done_ch0_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_in_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_done_ch0_st:1; /** gdma_ahb_evt_in_done_ch1_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GDMA_AHB_EVT_IN_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_in_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_done_ch1_st:1; - uint32_t reserved_24:1; + /** gdma_ahb_evt_in_done_ch2_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_done_ch2_st:1; /** gdma_ahb_evt_in_suc_eof_ch0_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_suc_eof_ch0_st:1; /** gdma_ahb_evt_in_suc_eof_ch1_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_in_suc_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_suc_eof_ch1_st:1; - uint32_t reserved_27:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st:1; /** gdma_ahb_evt_in_fifo_empty_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st:1; /** gdma_ahb_evt_in_fifo_empty_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st:1; - uint32_t reserved_30:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st:1; /** gdma_ahb_evt_in_fifo_full_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -821,84 +934,114 @@ typedef union { } soc_etm_evt_st2_reg_t; /** Type of evt_st3 register - * Event trigger status register + * Events trigger status register */ typedef union { struct { /** gdma_ahb_evt_in_fifo_full_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_in_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_in_fifo_full_ch1_st:1; - uint32_t reserved_1:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st:1; /** gdma_ahb_evt_out_done_ch0_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. + * Represents GDMA_AHB_evt_out_done_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_done_ch0_st:1; /** gdma_ahb_evt_out_done_ch1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. + * Represents GDMA_AHB_evt_out_done_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_done_ch1_st:1; - uint32_t reserved_4:1; + /** gdma_ahb_evt_out_done_ch2_st : R/WTC/SS; bitpos: [4]; default: 0; + * Represents GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_done_ch2_st:1; /** gdma_ahb_evt_out_eof_ch0_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_eof_ch0_st:1; /** gdma_ahb_evt_out_eof_ch1_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_eof_ch1_st:1; - uint32_t reserved_7:1; + /** gdma_ahb_evt_out_eof_ch2_st : R/WTC/SS; bitpos: [7]; default: 0; + * Represents GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st:1; /** gdma_ahb_evt_out_total_eof_ch0_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_total_eof_ch0_st:1; /** gdma_ahb_evt_out_total_eof_ch1_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. + * Represents GDMA_AHB_evt_out_total_eof_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_total_eof_ch1_st:1; - uint32_t reserved_10:1; + /** gdma_ahb_evt_out_total_eof_ch2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st:1; /** gdma_ahb_evt_out_fifo_empty_ch0_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st:1; /** gdma_ahb_evt_out_fifo_empty_ch1_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st:1; - uint32_t reserved_13:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st : R/WTC/SS; bitpos: [13]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st:1; /** gdma_ahb_evt_out_fifo_full_ch0_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_full_ch0_st:1; /** gdma_ahb_evt_out_fifo_full_ch1_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. + * Represents GDMA_AHB_evt_out_fifo_full_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_evt_out_fifo_full_ch1_st:1; - uint32_t reserved_16:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st : R/WTC/SS; bitpos: [16]; default: 0; + * Represents GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st:1; /** pmu_evt_sleep_weekup_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents PMU_EVT_SLEEP_WEEKUP trigger status. + * Represents PMU_evt_sleep_weekup trigger status. * 0: Not triggered * 1: Triggered */ @@ -909,198 +1052,198 @@ typedef union { } soc_etm_evt_st3_reg_t; /** Type of task_st0 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** gpio_task_ch0_set_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GPIO_TASK_CH0_SET trigger status. + * Represents GPIO_task_ch0_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_set_st:1; /** gpio_task_ch1_set_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents GPIO_TASK_CH1_SET trigger status. + * Represents GPIO_task_ch1_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_set_st:1; /** gpio_task_ch2_set_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents GPIO_TASK_CH2_SET trigger status. + * Represents GPIO_task_ch2_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_set_st:1; /** gpio_task_ch3_set_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents GPIO_TASK_CH3_SET trigger status. + * Represents GPIO_task_ch3_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_set_st:1; /** gpio_task_ch4_set_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents GPIO_TASK_CH4_SET trigger status. + * Represents GPIO_task_ch4_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_set_st:1; /** gpio_task_ch5_set_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents GPIO_TASK_CH5_SET trigger status. + * Represents GPIO_task_ch5_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_set_st:1; /** gpio_task_ch6_set_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents GPIO_TASK_CH6_SET trigger status. + * Represents GPIO_task_ch6_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_set_st:1; /** gpio_task_ch7_set_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents GPIO_TASK_CH7_SET trigger status. + * Represents GPIO_task_ch7_set trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_set_st:1; /** gpio_task_ch0_clear_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents GPIO_TASK_CH0_CLEAR trigger status. + * Represents GPIO_task_ch0_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_clear_st:1; /** gpio_task_ch1_clear_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents GPIO_TASK_CH1_CLEAR trigger status. + * Represents GPIO_task_ch1_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_clear_st:1; /** gpio_task_ch2_clear_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents GPIO_TASK_CH2_CLEAR trigger status. + * Represents GPIO_task_ch2_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_clear_st:1; /** gpio_task_ch3_clear_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents GPIO_TASK_CH3_CLEAR trigger status. + * Represents GPIO_task_ch3_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_clear_st:1; /** gpio_task_ch4_clear_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents GPIO_TASK_CH4_CLEAR trigger status. + * Represents GPIO_task_ch4_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_clear_st:1; /** gpio_task_ch5_clear_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents GPIO_TASK_CH5_CLEAR trigger status. + * Represents GPIO_task_ch5_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_clear_st:1; /** gpio_task_ch6_clear_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents GPIO_TASK_CH6_CLEAR trigger status. + * Represents GPIO_task_ch6_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_clear_st:1; /** gpio_task_ch7_clear_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents GPIO_TASK_CH7_CLEAR trigger status. + * Represents GPIO_task_ch7_clear trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_clear_st:1; /** gpio_task_ch0_toggle_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents GPIO_TASK_CH0_TOGGLE trigger status. + * Represents GPIO_task_ch0_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch0_toggle_st:1; /** gpio_task_ch1_toggle_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents GPIO_TASK_CH1_TOGGLE trigger status. + * Represents GPIO_task_ch1_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch1_toggle_st:1; /** gpio_task_ch2_toggle_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents GPIO_TASK_CH2_TOGGLE trigger status. + * Represents GPIO_task_ch2_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch2_toggle_st:1; /** gpio_task_ch3_toggle_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents GPIO_TASK_CH3_TOGGLE trigger status. + * Represents GPIO_task_ch3_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch3_toggle_st:1; /** gpio_task_ch4_toggle_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents GPIO_TASK_CH4_TOGGLE trigger status. + * Represents GPIO_task_ch4_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch4_toggle_st:1; /** gpio_task_ch5_toggle_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents GPIO_TASK_CH5_TOGGLE trigger status. + * Represents GPIO_task_ch5_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch5_toggle_st:1; /** gpio_task_ch6_toggle_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents GPIO_TASK_CH6_TOGGLE trigger status. + * Represents GPIO_task_ch6_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch6_toggle_st:1; /** gpio_task_ch7_toggle_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents GPIO_TASK_CH7_TOGGLE trigger status. + * Represents GPIO_task_ch7_toggle trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gpio_task_ch7_toggle_st:1; /** ledc_task_timer0_res_update_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER0_RES_UPDATE trigger status. + * Represents LEDC_task_timer0_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_res_update_st:1; /** ledc_task_timer1_res_update_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER1_RES_UPDATE trigger status. + * Represents LEDC_task_timer1_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_res_update_st:1; /** ledc_task_timer2_res_update_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER2_RES_UPDATE trigger status. + * Represents LEDC_task_timer2_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_res_update_st:1; /** ledc_task_timer3_res_update_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER3_RES_UPDATE trigger status. + * Represents LEDC_task_timer3_res_update trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_res_update_st:1; /** ledc_task_duty_scale_update_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. + * Represents LEDC_task_duty_scale_update_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch0_st:1; /** ledc_task_duty_scale_update_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. + * Represents LEDC_task_duty_scale_update_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch1_st:1; /** ledc_task_duty_scale_update_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. + * Represents LEDC_task_duty_scale_update_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch2_st:1; /** ledc_task_duty_scale_update_ch3_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. + * Represents LEDC_task_duty_scale_update_ch3 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1110,198 +1253,198 @@ typedef union { } soc_etm_task_st0_reg_t; /** Type of task_st1 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** ledc_task_duty_scale_update_ch4_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. + * Represents LEDC_task_duty_scale_update_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch4_st:1; /** ledc_task_duty_scale_update_ch5_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. + * Represents LEDC_task_duty_scale_update_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_duty_scale_update_ch5_st:1; /** ledc_task_timer0_cap_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_TIMER0_CAP trigger status. + * Represents LEDC_task_timer0_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_cap_st:1; /** ledc_task_timer1_cap_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_TIMER1_CAP trigger status. + * Represents LEDC_task_timer1_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_cap_st:1; /** ledc_task_timer2_cap_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_TIMER2_CAP trigger status. + * Represents LEDC_task_timer2_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_cap_st:1; /** ledc_task_timer3_cap_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_TIMER3_CAP trigger status. + * Represents LEDC_task_timer3_cap trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_cap_st:1; /** ledc_task_sig_out_dis_ch0_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. + * Represents LEDC_task_sig_out_dis_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch0_st:1; /** ledc_task_sig_out_dis_ch1_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. + * Represents LEDC_task_sig_out_dis_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch1_st:1; /** ledc_task_sig_out_dis_ch2_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. + * Represents LEDC_task_sig_out_dis_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch2_st:1; /** ledc_task_sig_out_dis_ch3_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. + * Represents LEDC_task_sig_out_dis_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch3_st:1; /** ledc_task_sig_out_dis_ch4_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. + * Represents LEDC_task_sig_out_dis_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch4_st:1; /** ledc_task_sig_out_dis_ch5_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. + * Represents LEDC_task_sig_out_dis_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_sig_out_dis_ch5_st:1; /** ledc_task_ovf_cnt_rst_ch0_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH0 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch0_st:1; /** ledc_task_ovf_cnt_rst_ch1_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH1 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch1_st:1; /** ledc_task_ovf_cnt_rst_ch2_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH2 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch2_st:1; /** ledc_task_ovf_cnt_rst_ch3_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH3 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch3_st:1; /** ledc_task_ovf_cnt_rst_ch4_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH4 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch4_st:1; /** ledc_task_ovf_cnt_rst_ch5_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents LEDC_TASK_OVF_CNT_RST_CH5 trigger status. + * Represents LEDC_task_ovf_cnt_rst_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_ovf_cnt_rst_ch5_st:1; /** ledc_task_timer0_rst_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents LEDC_TASK_TIMER0_RST trigger status. + * Represents LEDC_task_timer0_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_rst_st:1; /** ledc_task_timer1_rst_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents LEDC_TASK_TIMER1_RST trigger status. + * Represents LEDC_task_timer1_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_rst_st:1; /** ledc_task_timer2_rst_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents LEDC_TASK_TIMER2_RST trigger status. + * Represents LEDC_task_timer2_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_rst_st:1; /** ledc_task_timer3_rst_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents LEDC_TASK_TIMER3_RST trigger status. + * Represents LEDC_task_timer3_rst trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_rst_st:1; /** ledc_task_timer0_resume_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents LEDC_TASK_TIMER0_RESUME trigger status. + * Represents LEDC_task_timer0_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_resume_st:1; /** ledc_task_timer1_resume_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents LEDC_TASK_TIMER1_RESUME trigger status. + * Represents LEDC_task_timer1_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_resume_st:1; /** ledc_task_timer2_resume_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents LEDC_TASK_TIMER2_RESUME trigger status. + * Represents LEDC_task_timer2_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_resume_st:1; /** ledc_task_timer3_resume_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents LEDC_TASK_TIMER3_RESUME trigger status. + * Represents LEDC_task_timer3_resume trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_resume_st:1; /** ledc_task_timer0_pause_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents LEDC_TASK_TIMER0_PAUSE trigger status. + * Represents LEDC_task_timer0_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer0_pause_st:1; /** ledc_task_timer1_pause_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents LEDC_TASK_TIMER1_PAUSE trigger status. + * Represents LEDC_task_timer1_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer1_pause_st:1; /** ledc_task_timer2_pause_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents LEDC_TASK_TIMER2_PAUSE trigger status. + * Represents LEDC_task_timer2_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer2_pause_st:1; /** ledc_task_timer3_pause_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents LEDC_TASK_TIMER3_PAUSE trigger status. + * Represents LEDC_task_timer3_pause trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_timer3_pause_st:1; /** ledc_task_gamma_restart_ch0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH0 trigger status. + * Represents LEDC_task_gamma_restart_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch0_st:1; /** ledc_task_gamma_restart_ch1_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH1 trigger status. + * Represents LEDC_task_gamma_restart_ch1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1311,198 +1454,198 @@ typedef union { } soc_etm_task_st1_reg_t; /** Type of task_st2 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** ledc_task_gamma_restart_ch2_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH2 trigger status. + * Represents LEDC_task_gamma_restart_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch2_st:1; /** ledc_task_gamma_restart_ch3_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH3 trigger status. + * Represents LEDC_task_gamma_restart_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch3_st:1; /** ledc_task_gamma_restart_ch4_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH4 trigger status. + * Represents LEDC_task_gamma_restart_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch4_st:1; /** ledc_task_gamma_restart_ch5_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents LEDC_TASK_GAMMA_RESTART_CH5 trigger status. + * Represents LEDC_task_gamma_restart_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_restart_ch5_st:1; /** ledc_task_gamma_pause_ch0_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. + * Represents LEDC_task_gamma_pause_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch0_st:1; /** ledc_task_gamma_pause_ch1_st : R/WTC/SS; bitpos: [5]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. + * Represents LEDC_task_gamma_pause_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch1_st:1; /** ledc_task_gamma_pause_ch2_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. + * Represents LEDC_task_gamma_pause_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch2_st:1; /** ledc_task_gamma_pause_ch3_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. + * Represents LEDC_task_gamma_pause_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch3_st:1; /** ledc_task_gamma_pause_ch4_st : R/WTC/SS; bitpos: [8]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. + * Represents LEDC_task_gamma_pause_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch4_st:1; /** ledc_task_gamma_pause_ch5_st : R/WTC/SS; bitpos: [9]; default: 0; - * Represents LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. + * Represents LEDC_task_gamma_pause_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_pause_ch5_st:1; /** ledc_task_gamma_resume_ch0_st : R/WTC/SS; bitpos: [10]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH0 trigger status. + * Represents LEDC_task_gamma_resume_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch0_st:1; /** ledc_task_gamma_resume_ch1_st : R/WTC/SS; bitpos: [11]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH1 trigger status. + * Represents LEDC_task_gamma_resume_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch1_st:1; /** ledc_task_gamma_resume_ch2_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH2 trigger status. + * Represents LEDC_task_gamma_resume_ch2 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch2_st:1; /** ledc_task_gamma_resume_ch3_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH3 trigger status. + * Represents LEDC_task_gamma_resume_ch3 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch3_st:1; /** ledc_task_gamma_resume_ch4_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH4 trigger status. + * Represents LEDC_task_gamma_resume_ch4 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch4_st:1; /** ledc_task_gamma_resume_ch5_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents LEDC_TASK_GAMMA_RESUME_CH5 trigger status. + * Represents LEDC_task_gamma_resume_ch5 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t ledc_task_gamma_resume_ch5_st:1; /** tg0_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER0 trigger status. + * Represents TG0_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_start_timer0_st:1; /** tg0_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG0_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_alarm_start_timer0_st:1; /** tg0_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [18]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG0_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_stop_timer0_st:1; /** tg0_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [19]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG0_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_reload_timer0_st:1; /** tg0_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [20]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG0_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_cap_timer0_st:1; /** tg0_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [21]; default: 0; - * Represents TG0_TASK_CNT_START_TIMER1 trigger status. + * Represents TG0_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_start_timer1_st:1; /** tg0_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [22]; default: 0; - * Represents TG0_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG0_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_alarm_start_timer1_st:1; /** tg0_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [23]; default: 0; - * Represents TG0_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG0_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_stop_timer1_st:1; /** tg0_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [24]; default: 0; - * Represents TG0_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG0_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_reload_timer1_st:1; /** tg0_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [25]; default: 0; - * Represents TG0_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG0_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg0_task_cnt_cap_timer1_st:1; /** tg1_task_cnt_start_timer0_st : R/WTC/SS; bitpos: [26]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER0 trigger status. + * Represents TG1_task_cnt_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_start_timer0_st:1; /** tg1_task_alarm_start_timer0_st : R/WTC/SS; bitpos: [27]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER0 trigger status. + * Represents TG1_task_alarm_start_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_alarm_start_timer0_st:1; /** tg1_task_cnt_stop_timer0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER0 trigger status. + * Represents TG1_task_cnt_stop_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_stop_timer0_st:1; /** tg1_task_cnt_reload_timer0_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER0 trigger status. + * Represents TG1_task_cnt_reload_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_reload_timer0_st:1; /** tg1_task_cnt_cap_timer0_st : R/WTC/SS; bitpos: [30]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER0 trigger status. + * Represents TG1_task_cnt_cap_timer0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_cap_timer0_st:1; /** tg1_task_cnt_start_timer1_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents TG1_TASK_CNT_START_TIMER1 trigger status. + * Represents TG1_task_cnt_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1512,106 +1655,198 @@ typedef union { } soc_etm_task_st2_reg_t; /** Type of task_st3 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** tg1_task_alarm_start_timer1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents TG1_TASK_ALARM_START_TIMER1 trigger status. + * Represents TG1_task_alarm_start_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_alarm_start_timer1_st:1; /** tg1_task_cnt_stop_timer1_st : R/WTC/SS; bitpos: [1]; default: 0; - * Represents TG1_TASK_CNT_STOP_TIMER1 trigger status. + * Represents TG1_task_cnt_stop_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_stop_timer1_st:1; /** tg1_task_cnt_reload_timer1_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents TG1_TASK_CNT_RELOAD_TIMER1 trigger status. + * Represents TG1_task_cnt_reload_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_reload_timer1_st:1; /** tg1_task_cnt_cap_timer1_st : R/WTC/SS; bitpos: [3]; default: 0; - * Represents TG1_TASK_CNT_CAP_TIMER1 trigger status. + * Represents TG1_task_cnt_cap_timer1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tg1_task_cnt_cap_timer1_st:1; /** adc_task_sample0_st : R/WTC/SS; bitpos: [4]; default: 0; - * Represents ADC_TASK_SAMPLE0 trigger status. + * Represents ADC_task_sample0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_sample0_st:1; - uint32_t reserved_5:1; + /** adc_task_sample1_st : R/WTC/SS; bitpos: [5]; default: 0; + * Represents ADC_task_sample1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t adc_task_sample1_st:1; /** adc_task_start0_st : R/WTC/SS; bitpos: [6]; default: 0; - * Represents ADC_TASK_START0 trigger status. + * Represents ADC_task_start0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_start0_st:1; /** adc_task_stop0_st : R/WTC/SS; bitpos: [7]; default: 0; - * Represents ADC_TASK_STOP0 trigger status. + * Represents ADC_task_stop0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t adc_task_stop0_st:1; - uint32_t reserved_8:4; + /** regdma_task_start0_st : R/WTC/SS; bitpos: [8]; default: 0; + * Represents REGDMA_task_start0 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start0_st:1; + /** regdma_task_start1_st : R/WTC/SS; bitpos: [9]; default: 0; + * Represents REGDMA_task_start1 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start1_st:1; + /** regdma_task_start2_st : R/WTC/SS; bitpos: [10]; default: 0; + * Represents REGDMA_task_start2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start2_st:1; + /** regdma_task_start3_st : R/WTC/SS; bitpos: [11]; default: 0; + * Represents REGDMA_task_start3 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t regdma_task_start3_st:1; /** tmpsnsr_task_start_sample_st : R/WTC/SS; bitpos: [12]; default: 0; - * Represents TMPSNSR_TASK_START_SAMPLE trigger status. + * Represents TMPSNSR_task_start_sample trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_task_start_sample_st:1; /** tmpsnsr_task_stop_sample_st : R/WTC/SS; bitpos: [13]; default: 0; - * Represents TMPSNSR_TASK_STOP_SAMPLE trigger status. + * Represents TMPSNSR_task_stop_sample trigger status. * 0: Not triggered * 1: Triggered */ uint32_t tmpsnsr_task_stop_sample_st:1; /** i2s0_task_start_rx_st : R/WTC/SS; bitpos: [14]; default: 0; - * Represents I2S0_TASK_START_RX trigger status. + * Represents I2S0_task_start_rx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_start_rx_st:1; /** i2s0_task_start_tx_st : R/WTC/SS; bitpos: [15]; default: 0; - * Represents I2S0_TASK_START_TX trigger status. + * Represents I2S0_task_start_tx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_start_tx_st:1; /** i2s0_task_stop_rx_st : R/WTC/SS; bitpos: [16]; default: 0; - * Represents I2S0_TASK_STOP_RX trigger status. + * Represents I2S0_task_stop_rx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_stop_rx_st:1; /** i2s0_task_stop_tx_st : R/WTC/SS; bitpos: [17]; default: 0; - * Represents I2S0_TASK_STOP_TX trigger status. + * Represents I2S0_task_stop_tx trigger status. * 0: Not triggered * 1: Triggered */ uint32_t i2s0_task_stop_tx_st:1; - uint32_t reserved_18:10; + /** i2s1_task_start_rx_st : R/WTC/SS; bitpos: [18]; default: 0; + * Represents I2S1_task_start_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_start_rx_st:1; + /** i2s1_task_start_tx_st : R/WTC/SS; bitpos: [19]; default: 0; + * Represents I2S1_task_start_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_start_tx_st:1; + /** i2s1_task_stop_rx_st : R/WTC/SS; bitpos: [20]; default: 0; + * Represents I2S1_task_stop_rx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_stop_rx_st:1; + /** i2s1_task_stop_tx_st : R/WTC/SS; bitpos: [21]; default: 0; + * Represents I2S1_task_stop_tx trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t i2s1_task_stop_tx_st:1; + /** ulp_task_wakeup_cpu_st : R/WTC/SS; bitpos: [22]; default: 0; + * Represents ULP_task_wakeup_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_task_wakeup_cpu_st:1; + /** ulp_task_int_cpu_st : R/WTC/SS; bitpos: [23]; default: 0; + * Represents ULP_task_int_cpu trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t ulp_task_int_cpu_st:1; + /** rtc_task_start_st : R/WTC/SS; bitpos: [24]; default: 0; + * Represents RTC_task_start trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_start_st:1; + /** rtc_task_stop_st : R/WTC/SS; bitpos: [25]; default: 0; + * Represents RTC_task_stop trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_stop_st:1; + /** rtc_task_clr_st : R/WTC/SS; bitpos: [26]; default: 0; + * Represents RTC_task_clr trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_clr_st:1; + /** rtc_task_triggerflw_st : R/WTC/SS; bitpos: [27]; default: 0; + * Represents RTC_task_triggerflw trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t rtc_task_triggerflw_st:1; /** gdma_ahb_task_in_start_ch0_st : R/WTC/SS; bitpos: [28]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH0 trigger status. + * Represents GDMA_AHB_task_in_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_in_start_ch0_st:1; /** gdma_ahb_task_in_start_ch1_st : R/WTC/SS; bitpos: [29]; default: 0; - * Represents GDMA_AHB_TASK_IN_START_CH1 trigger status. + * Represents GDMA_AHB_task_in_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_in_start_ch1_st:1; - uint32_t reserved_30:1; + /** gdma_ahb_task_in_start_ch2_st : R/WTC/SS; bitpos: [30]; default: 0; + * Represents GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_task_in_start_ch2_st:1; /** gdma_ahb_task_out_start_ch0_st : R/WTC/SS; bitpos: [31]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH0 trigger status. + * Represents GDMA_AHB_task_out_start_ch0 trigger status. * 0: Not triggered * 1: Triggered */ @@ -1621,19 +1856,24 @@ typedef union { } soc_etm_task_st3_reg_t; /** Type of task_st4 register - * Task trigger status register + * Tasks trigger status register */ typedef union { struct { /** gdma_ahb_task_out_start_ch1_st : R/WTC/SS; bitpos: [0]; default: 0; - * Represents GDMA_AHB_TASK_OUT_START_CH1 trigger status. + * Represents GDMA_AHB_task_out_start_ch1 trigger status. * 0: Not triggered * 1: Triggered */ uint32_t gdma_ahb_task_out_start_ch1_st:1; - uint32_t reserved_1:1; + /** gdma_ahb_task_out_start_ch2_st : R/WTC/SS; bitpos: [1]; default: 0; + * Represents GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Not triggered + * 1: Triggered + */ + uint32_t gdma_ahb_task_out_start_ch2_st:1; /** pmu_task_sleep_req_st : R/WTC/SS; bitpos: [2]; default: 0; - * Represents PMU_TASK_SLEEP_REQ trigger status. + * Represents PMU_task_sleep_req trigger status. * 0: Not triggered * 1: Triggered */ @@ -1646,199 +1886,199 @@ typedef union { /** Group: Configuration Register */ /** Type of ch_ena_ad0_set register - * Channel enable register + * Channel enable set register */ typedef union { struct { /** ch_enable0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel0. - * 0: Invalid. No effect + * Configures whether or not to enable ch0. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable0:1; /** ch_enable1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel1. - * 0: Invalid. No effect + * Configures whether or not to enable ch1. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable1:1; /** ch_enable2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel2. - * 0: Invalid. No effect + * Configures whether or not to enable ch2. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable2:1; /** ch_enable3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel3. - * 0: Invalid. No effect + * Configures whether or not to enable ch3. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable3:1; /** ch_enable4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel4. - * 0: Invalid. No effect + * Configures whether or not to enable ch4. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable4:1; /** ch_enable5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel5. - * 0: Invalid. No effect + * Configures whether or not to enable ch5. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable5:1; /** ch_enable6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel6. - * 0: Invalid. No effect + * Configures whether or not to enable ch6. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable6:1; /** ch_enable7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel7. - * 0: Invalid. No effect + * Configures whether or not to enable ch7. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable7:1; /** ch_enable8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel8. - * 0: Invalid. No effect + * Configures whether or not to enable ch8. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable8:1; /** ch_enable9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel9. - * 0: Invalid. No effect + * Configures whether or not to enable ch9. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable9:1; /** ch_enable10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel10. - * 0: Invalid. No effect + * Configures whether or not to enable ch10. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable10:1; /** ch_enable11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel11. - * 0: Invalid. No effect + * Configures whether or not to enable ch11. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable11:1; /** ch_enable12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel12. - * 0: Invalid. No effect + * Configures whether or not to enable ch12. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable12:1; /** ch_enable13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel13. - * 0: Invalid. No effect + * Configures whether or not to enable ch13. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable13:1; /** ch_enable14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel14. - * 0: Invalid. No effect + * Configures whether or not to enable ch14. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable14:1; /** ch_enable15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel15. - * 0: Invalid. No effect + * Configures whether or not to enable ch15. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable15:1; /** ch_enable16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel16. - * 0: Invalid. No effect + * Configures whether or not to enable ch16. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable16:1; /** ch_enable17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel17. - * 0: Invalid. No effect + * Configures whether or not to enable ch17. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable17:1; /** ch_enable18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to enable channel18. - * 0: Invalid. No effect + * Configures whether or not to enable ch18. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable18:1; /** ch_enable19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to enable channel19. - * 0: Invalid. No effect + * Configures whether or not to enable ch19. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable19:1; /** ch_enable20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to enable channel20. - * 0: Invalid. No effect + * Configures whether or not to enable ch20. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable20:1; /** ch_enable21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to enable channel21. - * 0: Invalid. No effect + * Configures whether or not to enable ch21. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable21:1; /** ch_enable22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to enable channel22. - * 0: Invalid. No effect + * Configures whether or not to enable ch22. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable22:1; /** ch_enable23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to enable channel23. - * 0: Invalid. No effect + * Configures whether or not to enable ch23. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable23:1; /** ch_enable24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to enable channel24. - * 0: Invalid. No effect + * Configures whether or not to enable ch24. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable24:1; /** ch_enable25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to enable channel25. - * 0: Invalid. No effect + * Configures whether or not to enable ch25. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable25:1; /** ch_enable26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to enable channel26. - * 0: Invalid. No effect + * Configures whether or not to enable ch26. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable26:1; /** ch_enable27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to enable channel27. - * 0: Invalid. No effect + * Configures whether or not to enable ch27. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable27:1; /** ch_enable28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to enable channel28. - * 0: Invalid. No effect + * Configures whether or not to enable ch28. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable28:1; /** ch_enable29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to enable channel29. - * 0: Invalid. No effect + * Configures whether or not to enable ch29. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable29:1; /** ch_enable30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to enable channel30. - * 0: Invalid. No effect + * Configures whether or not to enable ch30. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable30:1; /** ch_enable31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to enable channel31. - * 0: Invalid. No effect + * Configures whether or not to enable ch31. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable31:1; @@ -1847,199 +2087,199 @@ typedef union { } soc_etm_ch_ena_ad0_set_reg_t; /** Type of ch_ena_ad0_clr register - * Channel disable register + * Channel enable clear register */ typedef union { struct { /** ch_disable0 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel0. - * 0: Invalid. No effect + * Configures whether or not to clear ch0 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable0:1; /** ch_disable1 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel1. - * 0: Invalid. No effect + * Configures whether or not to clear ch1 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable1:1; /** ch_disable2 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel2. - * 0: Invalid. No effect + * Configures whether or not to clear ch2 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable2:1; /** ch_disable3 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel3. - * 0: Invalid. No effect + * Configures whether or not to clear ch3 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable3:1; /** ch_disable4 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel4. - * 0: Invalid. No effect + * Configures whether or not to clear ch4 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable4:1; /** ch_disable5 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel5. - * 0: Invalid. No effect + * Configures whether or not to clear ch5 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable5:1; /** ch_disable6 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel6. - * 0: Invalid. No effect + * Configures whether or not to clear ch6 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable6:1; /** ch_disable7 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel7. - * 0: Invalid. No effect + * Configures whether or not to clear ch7 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable7:1; /** ch_disable8 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel8. - * 0: Invalid. No effect + * Configures whether or not to clear ch8 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable8:1; /** ch_disable9 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel9. - * 0: Invalid. No effect + * Configures whether or not to clear ch9 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable9:1; /** ch_disable10 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel10. - * 0: Invalid. No effect + * Configures whether or not to clear ch10 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable10:1; /** ch_disable11 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel11. - * 0: Invalid. No effect + * Configures whether or not to clear ch11 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable11:1; /** ch_disable12 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel12. - * 0: Invalid. No effect + * Configures whether or not to clear ch12 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable12:1; /** ch_disable13 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel13. - * 0: Invalid. No effect + * Configures whether or not to clear ch13 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable13:1; /** ch_disable14 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel14. - * 0: Invalid. No effect + * Configures whether or not to clear ch14 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable14:1; /** ch_disable15 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel15. - * 0: Invalid. No effect + * Configures whether or not to clear ch15 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable15:1; /** ch_disable16 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel16. - * 0: Invalid. No effect + * Configures whether or not to clear ch16 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable16:1; /** ch_disable17 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel17. - * 0: Invalid. No effect + * Configures whether or not to clear ch17 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable17:1; /** ch_disable18 : WT; bitpos: [18]; default: 0; - * Configures whether or not to disable channel18. - * 0: Invalid. No effect + * Configures whether or not to clear ch18 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable18:1; /** ch_disable19 : WT; bitpos: [19]; default: 0; - * Configures whether or not to disable channel19. - * 0: Invalid. No effect + * Configures whether or not to clear ch19 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable19:1; /** ch_disable20 : WT; bitpos: [20]; default: 0; - * Configures whether or not to disable channel20. - * 0: Invalid. No effect + * Configures whether or not to clear ch20 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable20:1; /** ch_disable21 : WT; bitpos: [21]; default: 0; - * Configures whether or not to disable channel21. - * 0: Invalid. No effect + * Configures whether or not to clear ch21 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable21:1; /** ch_disable22 : WT; bitpos: [22]; default: 0; - * Configures whether or not to disable channel22. - * 0: Invalid. No effect + * Configures whether or not to clear ch22 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable22:1; /** ch_disable23 : WT; bitpos: [23]; default: 0; - * Configures whether or not to disable channel23. - * 0: Invalid. No effect + * Configures whether or not to clear ch23 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable23:1; /** ch_disable24 : WT; bitpos: [24]; default: 0; - * Configures whether or not to disable channel24. - * 0: Invalid. No effect + * Configures whether or not to clear ch24 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable24:1; /** ch_disable25 : WT; bitpos: [25]; default: 0; - * Configures whether or not to disable channel25. - * 0: Invalid. No effect + * Configures whether or not to clear ch25 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable25:1; /** ch_disable26 : WT; bitpos: [26]; default: 0; - * Configures whether or not to disable channel26. - * 0: Invalid. No effect + * Configures whether or not to clear ch26 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable26:1; /** ch_disable27 : WT; bitpos: [27]; default: 0; - * Configures whether or not to disable channel27. - * 0: Invalid. No effect + * Configures whether or not to clear ch27 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable27:1; /** ch_disable28 : WT; bitpos: [28]; default: 0; - * Configures whether or not to disable channel28. - * 0: Invalid. No effect + * Configures whether or not to clear ch28 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable28:1; /** ch_disable29 : WT; bitpos: [29]; default: 0; - * Configures whether or not to disable channel29. - * 0: Invalid. No effect + * Configures whether or not to clear ch29 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable29:1; /** ch_disable30 : WT; bitpos: [30]; default: 0; - * Configures whether or not to disable channel30. - * 0: Invalid. No effect + * Configures whether or not to clear ch30 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable30:1; /** ch_disable31 : WT; bitpos: [31]; default: 0; - * Configures whether or not to disable channel31. - * 0: Invalid. No effect + * Configures whether or not to clear ch31 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable31:1; @@ -2048,115 +2288,115 @@ typedef union { } soc_etm_ch_ena_ad0_clr_reg_t; /** Type of ch_ena_ad1_set register - * Channel enable register + * Channel enable set register */ typedef union { struct { /** ch_enable32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to enable channel32. - * 0: Invalid. No effect + * Configures whether or not to enable ch32. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable32:1; /** ch_enable33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to enable channel33. - * 0: Invalid. No effect + * Configures whether or not to enable ch33. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable33:1; /** ch_enable34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to enable channel34. - * 0: Invalid. No effect + * Configures whether or not to enable ch34. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable34:1; /** ch_enable35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to enable channel35. - * 0: Invalid. No effect + * Configures whether or not to enable ch35. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable35:1; /** ch_enable36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to enable channel36. - * 0: Invalid. No effect + * Configures whether or not to enable ch36. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable36:1; /** ch_enable37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to enable channel37. - * 0: Invalid. No effect + * Configures whether or not to enable ch37. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable37:1; /** ch_enable38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to enable channel38. - * 0: Invalid. No effect + * Configures whether or not to enable ch38. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable38:1; /** ch_enable39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to enable channel39. - * 0: Invalid. No effect + * Configures whether or not to enable ch39. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable39:1; /** ch_enable40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to enable channel40. - * 0: Invalid. No effect + * Configures whether or not to enable ch40. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable40:1; /** ch_enable41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to enable channel41. - * 0: Invalid. No effect + * Configures whether or not to enable ch41. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable41:1; /** ch_enable42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to enable channel42. - * 0: Invalid. No effect + * Configures whether or not to enable ch42. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable42:1; /** ch_enable43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to enable channel43. - * 0: Invalid. No effect + * Configures whether or not to enable ch43. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable43:1; /** ch_enable44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to enable channel44. - * 0: Invalid. No effect + * Configures whether or not to enable ch44. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable44:1; /** ch_enable45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to enable channel45. - * 0: Invalid. No effect + * Configures whether or not to enable ch45. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable45:1; /** ch_enable46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to enable channel46. - * 0: Invalid. No effect + * Configures whether or not to enable ch46. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable46:1; /** ch_enable47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to enable channel47. - * 0: Invalid. No effect + * Configures whether or not to enable ch47. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable47:1; /** ch_enable48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to enable channel48. - * 0: Invalid. No effect + * Configures whether or not to enable ch48. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable48:1; /** ch_enable49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to enable channel49. - * 0: Invalid. No effect + * Configures whether or not to enable ch49. + * 0: Invalid, No effect * 1: Enable */ uint32_t ch_enable49:1; @@ -2166,115 +2406,115 @@ typedef union { } soc_etm_ch_ena_ad1_set_reg_t; /** Type of ch_ena_ad1_clr register - * Channel disable register + * Channel enable clear register */ typedef union { struct { /** ch_disable32 : WT; bitpos: [0]; default: 0; - * Configures whether or not to disable channel32. - * 0: Invalid. No effect + * Configures whether or not to clear ch32 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable32:1; /** ch_disable33 : WT; bitpos: [1]; default: 0; - * Configures whether or not to disable channel33. - * 0: Invalid. No effect + * Configures whether or not to clear ch33 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable33:1; /** ch_disable34 : WT; bitpos: [2]; default: 0; - * Configures whether or not to disable channel34. - * 0: Invalid. No effect + * Configures whether or not to clear ch34 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable34:1; /** ch_disable35 : WT; bitpos: [3]; default: 0; - * Configures whether or not to disable channel35. - * 0: Invalid. No effect + * Configures whether or not to clear ch35 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable35:1; /** ch_disable36 : WT; bitpos: [4]; default: 0; - * Configures whether or not to disable channel36. - * 0: Invalid. No effect + * Configures whether or not to clear ch36 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable36:1; /** ch_disable37 : WT; bitpos: [5]; default: 0; - * Configures whether or not to disable channel37. - * 0: Invalid. No effect + * Configures whether or not to clear ch37 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable37:1; /** ch_disable38 : WT; bitpos: [6]; default: 0; - * Configures whether or not to disable channel38. - * 0: Invalid. No effect + * Configures whether or not to clear ch38 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable38:1; /** ch_disable39 : WT; bitpos: [7]; default: 0; - * Configures whether or not to disable channel39. - * 0: Invalid. No effect + * Configures whether or not to clear ch39 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable39:1; /** ch_disable40 : WT; bitpos: [8]; default: 0; - * Configures whether or not to disable channel40. - * 0: Invalid. No effect + * Configures whether or not to clear ch40 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable40:1; /** ch_disable41 : WT; bitpos: [9]; default: 0; - * Configures whether or not to disable channel41. - * 0: Invalid. No effect + * Configures whether or not to clear ch41 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable41:1; /** ch_disable42 : WT; bitpos: [10]; default: 0; - * Configures whether or not to disable channel42. - * 0: Invalid. No effect + * Configures whether or not to clear ch42 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable42:1; /** ch_disable43 : WT; bitpos: [11]; default: 0; - * Configures whether or not to disable channel43. - * 0: Invalid. No effect + * Configures whether or not to clear ch43 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable43:1; /** ch_disable44 : WT; bitpos: [12]; default: 0; - * Configures whether or not to disable channel44. - * 0: Invalid. No effect + * Configures whether or not to clear ch44 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable44:1; /** ch_disable45 : WT; bitpos: [13]; default: 0; - * Configures whether or not to disable channel45. - * 0: Invalid. No effect + * Configures whether or not to clear ch45 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable45:1; /** ch_disable46 : WT; bitpos: [14]; default: 0; - * Configures whether or not to disable channel46. - * 0: Invalid. No effect + * Configures whether or not to clear ch46 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable46:1; /** ch_disable47 : WT; bitpos: [15]; default: 0; - * Configures whether or not to disable channel47. - * 0: Invalid. No effect + * Configures whether or not to clear ch47 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable47:1; /** ch_disable48 : WT; bitpos: [16]; default: 0; - * Configures whether or not to disable channel48. - * 0: Invalid. No effect + * Configures whether or not to clear ch48 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable48:1; /** ch_disable49 : WT; bitpos: [17]; default: 0; - * Configures whether or not to disable channel49. - * 0: Invalid. No effect + * Configures whether or not to clear ch49 enable. + * 0: Invalid, No effect * 1: Clear */ uint32_t ch_disable49:1; @@ -2283,13 +2523,13 @@ typedef union { uint32_t val; } soc_etm_ch_ena_ad1_clr_reg_t; -/** Type of chn_evt_id register - * Channeln event ID register +/** Type of ch_evt_id register + * Channel0 event id register */ typedef union { struct { - /** chn_evt_id : R/W; bitpos: [6:0]; default: 0; - * Configures channeln event ID. + /** ch_evt_id : R/W; bitpos: [6:0]; default: 0; + * Configures ch_evt_id */ uint32_t chn_evt_id:7; uint32_t reserved_7:25; @@ -2297,13 +2537,13 @@ typedef union { uint32_t val; } soc_etm_chn_evt_id_reg_t; -/** Type of chn_task_id register - * Channeln task ID register +/** Type of ch_task_id register + * Channel0 task id register */ typedef union { struct { - /** chn_task_id : R/W; bitpos: [7:0]; default: 0; - * Configures channeln task ID. + /** ch_task_id : R/W; bitpos: [7:0]; default: 0; + * Configures ch_task_id */ uint32_t chn_task_id:8; uint32_t reserved_8:24; @@ -2312,188 +2552,199 @@ typedef union { } soc_etm_chn_task_id_reg_t; /** Type of evt_st0_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** gpio_evt_ch0_rise_edge_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_rise_edge_st_clr:1; /** gpio_evt_ch1_rise_edge_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_rise_edge_st_clr:1; /** gpio_evt_ch2_rise_edge_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_rise_edge_st_clr:1; /** gpio_evt_ch3_rise_edge_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_rise_edge_st_clr:1; /** gpio_evt_ch4_rise_edge_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_rise_edge_st_clr:1; /** gpio_evt_ch5_rise_edge_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_rise_edge_st_clr:1; /** gpio_evt_ch6_rise_edge_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_rise_edge_st_clr:1; /** gpio_evt_ch7_rise_edge_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_RISE_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_rise_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_rise_edge_st_clr:1; /** gpio_evt_ch0_fall_edge_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_fall_edge_st_clr:1; /** gpio_evt_ch1_fall_edge_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_fall_edge_st_clr:1; /** gpio_evt_ch2_fall_edge_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_fall_edge_st_clr:1; /** gpio_evt_ch3_fall_edge_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_fall_edge_st_clr:1; /** gpio_evt_ch4_fall_edge_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_fall_edge_st_clr:1; /** gpio_evt_ch5_fall_edge_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_fall_edge_st_clr:1; /** gpio_evt_ch6_fall_edge_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_fall_edge_st_clr:1; /** gpio_evt_ch7_fall_edge_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_FALL_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_fall_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_fall_edge_st_clr:1; /** gpio_evt_ch0_any_edge_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH0_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch0_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch0_any_edge_st_clr:1; /** gpio_evt_ch1_any_edge_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH1_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch1_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch1_any_edge_st_clr:1; /** gpio_evt_ch2_any_edge_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH2_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch2_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch2_any_edge_st_clr:1; /** gpio_evt_ch3_any_edge_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH3_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch3_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch3_any_edge_st_clr:1; /** gpio_evt_ch4_any_edge_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH4_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch4_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch4_any_edge_st_clr:1; /** gpio_evt_ch5_any_edge_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH5_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch5_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch5_any_edge_st_clr:1; /** gpio_evt_ch6_any_edge_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH6_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch6_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch6_any_edge_st_clr:1; /** gpio_evt_ch7_any_edge_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_EVT_CH7_ANY_EDGE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_ch7_any_edge trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_ch7_any_edge_st_clr:1; /** gpio_evt_zero_det_pos0_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_POS0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_pos0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_zero_det_pos0_st_clr:1; /** gpio_evt_zero_det_neg0_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GPIO_EVT_ZERO_DET_NEG0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_evt_zero_det_neg0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_evt_zero_det_neg0_st_clr:1; - uint32_t reserved_26:2; + /** gpio_evt_zero_det_pos1_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_pos1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gpio_evt_zero_det_pos1_st_clr:1; + /** gpio_evt_zero_det_neg1_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GPIO_evt_zero_det_neg1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gpio_evt_zero_det_neg1_st_clr:1; /** ledc_evt_duty_chng_end_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch0_st_clr:1; /** ledc_evt_duty_chng_end_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch1_st_clr:1; /** ledc_evt_duty_chng_end_ch2_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch2_st_clr:1; /** ledc_evt_duty_chng_end_ch3_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch3_st_clr:1; @@ -2502,298 +2753,400 @@ typedef union { } soc_etm_evt_st0_clr_reg_t; /** Type of evt_st1_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** ledc_evt_duty_chng_end_ch4_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch4_st_clr:1; /** ledc_evt_duty_chng_end_ch5_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_EVT_DUTY_CHNG_END_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_duty_chng_end_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_duty_chng_end_ch5_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch0_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch0_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch1_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch2_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch2_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch3_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch3_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch4_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch4_st_clr:1; /** ledc_evt_ovf_cnt_pls_ch5_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_EVT_OVF_CNT_PLS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_ovf_cnt_pls_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_ovf_cnt_pls_ch5_st_clr:1; /** ledc_evt_time_ovf_timer0_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer0_st_clr:1; /** ledc_evt_time_ovf_timer1_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer1_st_clr:1; /** ledc_evt_time_ovf_timer2_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer2_st_clr:1; /** ledc_evt_time_ovf_timer3_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIME_OVF_TIMER3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_time_ovf_timer3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_time_ovf_timer3_st_clr:1; /** ledc_evt_timer0_cmp_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER0_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer0_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer0_cmp_st_clr:1; /** ledc_evt_timer1_cmp_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER1_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer1_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer1_cmp_st_clr:1; /** ledc_evt_timer2_cmp_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER2_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer2_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer2_cmp_st_clr:1; /** ledc_evt_timer3_cmp_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_EVT_TIMER3_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_evt_timer3_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_evt_timer3_cmp_st_clr:1; /** tg0_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_evt_cnt_cmp_timer0_st_clr:1; /** tg0_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_evt_cnt_cmp_timer1_st_clr:1; /** tg1_evt_cnt_cmp_timer0_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_evt_cnt_cmp_timer0_st_clr:1; /** tg1_evt_cnt_cmp_timer1_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG1_EVT_CNT_CMP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_evt_cnt_cmp_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_evt_cnt_cmp_timer1_st_clr:1; /** systimer_evt_cnt_cmp0_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp0_st_clr:1; /** systimer_evt_cnt_cmp1_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp1_st_clr:1; /** systimer_evt_cnt_cmp2_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear SYSTIMER_EVT_CNT_CMP2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear SYSTIMER_evt_cnt_cmp2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t systimer_evt_cnt_cmp2_st_clr:1; /** adc_evt_conv_cmplt0_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear ADC_EVT_CONV_CMPLT0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_conv_cmplt0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_conv_cmplt0_st_clr:1; /** adc_evt_eq_above_thresh0_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_above_thresh0_st_clr:1; /** adc_evt_eq_above_thresh1_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_ABOVE_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_above_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_above_thresh1_st_clr:1; /** adc_evt_eq_below_thresh0_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_below_thresh0_st_clr:1; /** adc_evt_eq_below_thresh1_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear ADC_EVT_EQ_BELOW_THRESH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_eq_below_thresh1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_eq_below_thresh1_st_clr:1; /** adc_evt_result_done0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear ADC_EVT_RESULT_DONE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_result_done0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_result_done0_st_clr:1; /** adc_evt_stopped0_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear ADC_EVT_STOPPED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_stopped0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_stopped0_st_clr:1; /** adc_evt_started0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear ADC_EVT_STARTED0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_evt_started0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_evt_started0_st_clr:1; - uint32_t reserved_31:1; + /** regdma_evt_done0_st_clr : WT; bitpos: [31]; default: 0; + * Configures whether or not to clear REGDMA_evt_done0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done0_st_clr:1; }; uint32_t val; } soc_etm_evt_st1_clr_reg_t; /** Type of evt_st2_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { - uint32_t reserved_0:7; + /** regdma_evt_done1_st_clr : WT; bitpos: [0]; default: 0; + * Configures whether or not to clear REGDMA_evt_done1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done1_st_clr:1; + /** regdma_evt_done2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear REGDMA_evt_done2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done2_st_clr:1; + /** regdma_evt_done3_st_clr : WT; bitpos: [2]; default: 0; + * Configures whether or not to clear REGDMA_evt_done3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_done3_st_clr:1; + /** regdma_evt_err0_st_clr : WT; bitpos: [3]; default: 0; + * Configures whether or not to clear REGDMA_evt_err0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err0_st_clr:1; + /** regdma_evt_err1_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear REGDMA_evt_err1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err1_st_clr:1; + /** regdma_evt_err2_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear REGDMA_evt_err2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err2_st_clr:1; + /** regdma_evt_err3_st_clr : WT; bitpos: [6]; default: 0; + * Configures whether or not to clear REGDMA_evt_err3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_evt_err3_st_clr:1; /** tmpsnsr_evt_over_limit_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear TMPSNSR_EVT_OVER_LIMIT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_evt_over_limit trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_evt_over_limit_st_clr:1; /** i2s0_evt_rx_done_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear I2S0_EVT_RX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_rx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_rx_done_st_clr:1; /** i2s0_evt_tx_done_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear I2S0_EVT_TX_DONE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_tx_done trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_tx_done_st_clr:1; /** i2s0_evt_x_words_received_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_RECEIVED trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_received trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_x_words_received_st_clr:1; /** i2s0_evt_x_words_sent_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear I2S0_EVT_X_WORDS_SENT trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_evt_x_words_sent trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_evt_x_words_sent_st_clr:1; - uint32_t reserved_12:7; + /** i2s1_evt_rx_done_st_clr : WT; bitpos: [12]; default: 0; + * Configures whether or not to clear I2S1_evt_rx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_rx_done_st_clr:1; + /** i2s1_evt_tx_done_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear I2S1_evt_tx_done trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_tx_done_st_clr:1; + /** i2s1_evt_x_words_received_st_clr : WT; bitpos: [14]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_received trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_x_words_received_st_clr:1; + /** i2s1_evt_x_words_sent_st_clr : WT; bitpos: [15]; default: 0; + * Configures whether or not to clear I2S1_evt_x_words_sent trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_evt_x_words_sent_st_clr:1; + /** ulp_evt_err_intr_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear ULP_evt_err_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_err_intr_st_clr:1; + /** ulp_evt_halt_st_clr : WT; bitpos: [17]; default: 0; + * Configures whether or not to clear ULP_evt_halt trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_halt_st_clr:1; + /** ulp_evt_start_intr_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear ULP_evt_start_intr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_evt_start_intr_st_clr:1; /** rtc_evt_tick_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear RTC_EVT_TICK trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_tick trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_tick_st_clr:1; /** rtc_evt_ovf_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear RTC_EVT_OVF trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_ovf trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_ovf_st_clr:1; /** rtc_evt_cmp_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear RTC_EVT_CMP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear RTC_evt_cmp trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t rtc_evt_cmp_st_clr:1; /** gdma_ahb_evt_in_done_ch0_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_done_ch0_st_clr:1; /** gdma_ahb_evt_in_done_ch1_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_done_ch1_st_clr:1; - uint32_t reserved_24:1; + /** gdma_ahb_evt_in_done_ch2_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_done_ch2_st_clr:1; /** gdma_ahb_evt_in_suc_eof_ch0_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_suc_eof_ch0_st_clr:1; /** gdma_ahb_evt_in_suc_eof_ch1_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_SUC_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_suc_eof_ch1_st_clr:1; - uint32_t reserved_27:1; + /** gdma_ahb_evt_in_suc_eof_ch2_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_suc_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_suc_eof_ch2_st_clr:1; /** gdma_ahb_evt_in_fifo_empty_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_empty_ch0_st_clr:1; /** gdma_ahb_evt_in_fifo_empty_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_empty_ch1_st_clr:1; - uint32_t reserved_30:1; + /** gdma_ahb_evt_in_fifo_empty_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_empty_ch2_st_clr:1; /** gdma_ahb_evt_in_fifo_full_ch0_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_full_ch0_st_clr:1; @@ -2802,85 +3155,115 @@ typedef union { } soc_etm_evt_st2_clr_reg_t; /** Type of evt_st3_clr register - * Event trigger status clear register + * Events trigger status clear register */ typedef union { struct { /** gdma_ahb_evt_in_fifo_full_ch1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_IN_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_in_fifo_full_ch1_st_clr:1; - uint32_t reserved_1:1; + /** gdma_ahb_evt_in_fifo_full_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_in_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_in_fifo_full_ch2_st_clr:1; /** gdma_ahb_evt_out_done_ch0_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_done_ch0_st_clr:1; /** gdma_ahb_evt_out_done_ch1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_DONE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_done_ch1_st_clr:1; - uint32_t reserved_4:1; + /** gdma_ahb_evt_out_done_ch2_st_clr : WT; bitpos: [4]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_done_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_done_ch2_st_clr:1; /** gdma_ahb_evt_out_eof_ch0_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_eof_ch0_st_clr:1; /** gdma_ahb_evt_out_eof_ch1_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_eof_ch1_st_clr:1; - uint32_t reserved_7:1; + /** gdma_ahb_evt_out_eof_ch2_st_clr : WT; bitpos: [7]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_eof_ch2_st_clr:1; /** gdma_ahb_evt_out_total_eof_ch0_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_total_eof_ch0_st_clr:1; /** gdma_ahb_evt_out_total_eof_ch1_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_TOTAL_EOF_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_total_eof_ch1_st_clr:1; - uint32_t reserved_10:1; + /** gdma_ahb_evt_out_total_eof_ch2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_total_eof_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_total_eof_ch2_st_clr:1; /** gdma_ahb_evt_out_fifo_empty_ch0_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_empty_ch0_st_clr:1; /** gdma_ahb_evt_out_fifo_empty_ch1_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_EMPTY_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_empty_ch1_st_clr:1; - uint32_t reserved_13:1; + /** gdma_ahb_evt_out_fifo_empty_ch2_st_clr : WT; bitpos: [13]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_empty_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_empty_ch2_st_clr:1; /** gdma_ahb_evt_out_fifo_full_ch0_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_full_ch0_st_clr:1; /** gdma_ahb_evt_out_fifo_full_ch1_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GDMA_AHB_EVT_OUT_FIFO_FULL_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_evt_out_fifo_full_ch1_st_clr:1; - uint32_t reserved_16:1; + /** gdma_ahb_evt_out_fifo_full_ch2_st_clr : WT; bitpos: [16]; default: 0; + * Configures whether or not to clear GDMA_AHB_evt_out_fifo_full_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_evt_out_fifo_full_ch2_st_clr:1; /** pmu_evt_sleep_weekup_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear PMU_EVT_SLEEP_WEEKUP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_evt_sleep_weekup trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t pmu_evt_sleep_weekup_st_clr:1; @@ -2890,199 +3273,199 @@ typedef union { } soc_etm_evt_st3_clr_reg_t; /** Type of task_st0_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** gpio_task_ch0_set_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_set_st_clr:1; /** gpio_task_ch1_set_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_set_st_clr:1; /** gpio_task_ch2_set_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_set_st_clr:1; /** gpio_task_ch3_set_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_set_st_clr:1; /** gpio_task_ch4_set_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_set_st_clr:1; /** gpio_task_ch5_set_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_set_st_clr:1; /** gpio_task_ch6_set_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_set_st_clr:1; /** gpio_task_ch7_set_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_SET trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_set trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_set_st_clr:1; /** gpio_task_ch0_clear_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_clear_st_clr:1; /** gpio_task_ch1_clear_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_clear_st_clr:1; /** gpio_task_ch2_clear_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_clear_st_clr:1; /** gpio_task_ch3_clear_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_clear_st_clr:1; /** gpio_task_ch4_clear_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_clear_st_clr:1; /** gpio_task_ch5_clear_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_clear_st_clr:1; /** gpio_task_ch6_clear_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_clear_st_clr:1; /** gpio_task_ch7_clear_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_CLEAR trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_clear trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_clear_st_clr:1; /** gpio_task_ch0_toggle_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH0_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch0_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch0_toggle_st_clr:1; /** gpio_task_ch1_toggle_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH1_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch1_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch1_toggle_st_clr:1; /** gpio_task_ch2_toggle_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH2_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch2_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch2_toggle_st_clr:1; /** gpio_task_ch3_toggle_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH3_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch3_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch3_toggle_st_clr:1; /** gpio_task_ch4_toggle_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH4_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch4_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch4_toggle_st_clr:1; /** gpio_task_ch5_toggle_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH5_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch5_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch5_toggle_st_clr:1; /** gpio_task_ch6_toggle_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH6_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch6_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch6_toggle_st_clr:1; /** gpio_task_ch7_toggle_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear GPIO_TASK_CH7_TOGGLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GPIO_task_ch7_toggle trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gpio_task_ch7_toggle_st_clr:1; /** ledc_task_timer0_res_update_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_res_update_st_clr:1; /** ledc_task_timer1_res_update_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_res_update_st_clr:1; /** ledc_task_timer2_res_update_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_res_update_st_clr:1; /** ledc_task_timer3_res_update_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RES_UPDATE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_res_update trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_res_update_st_clr:1; /** ledc_task_duty_scale_update_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch0_st_clr:1; /** ledc_task_duty_scale_update_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch1_st_clr:1; /** ledc_task_duty_scale_update_ch2_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch2_st_clr:1; /** ledc_task_duty_scale_update_ch3_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch3_st_clr:1; @@ -3091,199 +3474,199 @@ typedef union { } soc_etm_task_st0_clr_reg_t; /** Type of task_st1_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** ledc_task_duty_scale_update_ch4_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch4_st_clr:1; /** ledc_task_duty_scale_update_ch5_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_DUTY_SCALE_UPDATE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_duty_scale_update_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_duty_scale_update_ch5_st_clr:1; /** ledc_task_timer0_cap_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_cap_st_clr:1; /** ledc_task_timer1_cap_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_cap_st_clr:1; /** ledc_task_timer2_cap_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_cap_st_clr:1; /** ledc_task_timer3_cap_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_CAP trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_cap trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_cap_st_clr:1; /** ledc_task_sig_out_dis_ch0_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch0_st_clr:1; /** ledc_task_sig_out_dis_ch1_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch1_st_clr:1; /** ledc_task_sig_out_dis_ch2_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch2_st_clr:1; /** ledc_task_sig_out_dis_ch3_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch3_st_clr:1; /** ledc_task_sig_out_dis_ch4_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch4_st_clr:1; /** ledc_task_sig_out_dis_ch5_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_SIG_OUT_DIS_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_sig_out_dis_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_sig_out_dis_ch5_st_clr:1; /** ledc_task_ovf_cnt_rst_ch0_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch0_st_clr:1; /** ledc_task_ovf_cnt_rst_ch1_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch1_st_clr:1; /** ledc_task_ovf_cnt_rst_ch2_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch2_st_clr:1; /** ledc_task_ovf_cnt_rst_ch3_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch3_st_clr:1; /** ledc_task_ovf_cnt_rst_ch4_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch4_st_clr:1; /** ledc_task_ovf_cnt_rst_ch5_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear LEDC_TASK_OVF_CNT_RST_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_ovf_cnt_rst_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_ovf_cnt_rst_ch5_st_clr:1; /** ledc_task_timer0_rst_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_rst_st_clr:1; /** ledc_task_timer1_rst_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_rst_st_clr:1; /** ledc_task_timer2_rst_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_rst_st_clr:1; /** ledc_task_timer3_rst_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RST trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_rst trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_rst_st_clr:1; /** ledc_task_timer0_resume_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_resume_st_clr:1; /** ledc_task_timer1_resume_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_resume_st_clr:1; /** ledc_task_timer2_resume_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_resume_st_clr:1; /** ledc_task_timer3_resume_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_RESUME trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_resume trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_resume_st_clr:1; /** ledc_task_timer0_pause_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER0_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer0_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer0_pause_st_clr:1; /** ledc_task_timer1_pause_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER1_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer1_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer1_pause_st_clr:1; /** ledc_task_timer2_pause_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER2_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer2_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer2_pause_st_clr:1; /** ledc_task_timer3_pause_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear LEDC_TASK_TIMER3_PAUSE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_timer3_pause trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_timer3_pause_st_clr:1; /** ledc_task_gamma_restart_ch0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch0_st_clr:1; /** ledc_task_gamma_restart_ch1_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch1_st_clr:1; @@ -3292,199 +3675,199 @@ typedef union { } soc_etm_task_st1_clr_reg_t; /** Type of task_st2_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** ledc_task_gamma_restart_ch2_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch2_st_clr:1; /** ledc_task_gamma_restart_ch3_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch3_st_clr:1; /** ledc_task_gamma_restart_ch4_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch4_st_clr:1; /** ledc_task_gamma_restart_ch5_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESTART_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_restart_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_restart_ch5_st_clr:1; /** ledc_task_gamma_pause_ch0_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch0_st_clr:1; /** ledc_task_gamma_pause_ch1_st_clr : WT; bitpos: [5]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch1_st_clr:1; /** ledc_task_gamma_pause_ch2_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch2_st_clr:1; /** ledc_task_gamma_pause_ch3_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch3_st_clr:1; /** ledc_task_gamma_pause_ch4_st_clr : WT; bitpos: [8]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch4_st_clr:1; /** ledc_task_gamma_pause_ch5_st_clr : WT; bitpos: [9]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_PAUSE_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_pause_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_pause_ch5_st_clr:1; /** ledc_task_gamma_resume_ch0_st_clr : WT; bitpos: [10]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch0_st_clr:1; /** ledc_task_gamma_resume_ch1_st_clr : WT; bitpos: [11]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch1_st_clr:1; /** ledc_task_gamma_resume_ch2_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH2 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch2 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch2_st_clr:1; /** ledc_task_gamma_resume_ch3_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH3 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch3 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch3_st_clr:1; /** ledc_task_gamma_resume_ch4_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH4 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch4 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch4_st_clr:1; /** ledc_task_gamma_resume_ch5_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear LEDC_TASK_GAMMA_RESUME_CH5 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear LEDC_task_gamma_resume_ch5 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t ledc_task_gamma_resume_ch5_st_clr:1; /** tg0_task_cnt_start_timer0_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_start_timer0_st_clr:1; /** tg0_task_alarm_start_timer0_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_alarm_start_timer0_st_clr:1; /** tg0_task_cnt_stop_timer0_st_clr : WT; bitpos: [18]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_stop_timer0_st_clr:1; /** tg0_task_cnt_reload_timer0_st_clr : WT; bitpos: [19]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_reload_timer0_st_clr:1; /** tg0_task_cnt_cap_timer0_st_clr : WT; bitpos: [20]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_cap_timer0_st_clr:1; /** tg0_task_cnt_start_timer1_st_clr : WT; bitpos: [21]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_start_timer1_st_clr:1; /** tg0_task_alarm_start_timer1_st_clr : WT; bitpos: [22]; default: 0; - * Configures whether or not to clear TG0_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_alarm_start_timer1_st_clr:1; /** tg0_task_cnt_stop_timer1_st_clr : WT; bitpos: [23]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_stop_timer1_st_clr:1; /** tg0_task_cnt_reload_timer1_st_clr : WT; bitpos: [24]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_reload_timer1_st_clr:1; /** tg0_task_cnt_cap_timer1_st_clr : WT; bitpos: [25]; default: 0; - * Configures whether or not to clear TG0_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG0_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg0_task_cnt_cap_timer1_st_clr:1; /** tg1_task_cnt_start_timer0_st_clr : WT; bitpos: [26]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_start_timer0_st_clr:1; /** tg1_task_alarm_start_timer0_st_clr : WT; bitpos: [27]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_alarm_start_timer0_st_clr:1; /** tg1_task_cnt_stop_timer0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_stop_timer0_st_clr:1; /** tg1_task_cnt_reload_timer0_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_reload_timer0_st_clr:1; /** tg1_task_cnt_cap_timer0_st_clr : WT; bitpos: [30]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_cap_timer0_st_clr:1; /** tg1_task_cnt_start_timer1_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_start_timer1_st_clr:1; @@ -3493,107 +3876,199 @@ typedef union { } soc_etm_task_st2_clr_reg_t; /** Type of task_st3_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** tg1_task_alarm_start_timer1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear TG1_TASK_ALARM_START_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_alarm_start_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_alarm_start_timer1_st_clr:1; /** tg1_task_cnt_stop_timer1_st_clr : WT; bitpos: [1]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_STOP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_stop_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_stop_timer1_st_clr:1; /** tg1_task_cnt_reload_timer1_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_RELOAD_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_reload_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_reload_timer1_st_clr:1; /** tg1_task_cnt_cap_timer1_st_clr : WT; bitpos: [3]; default: 0; - * Configures whether or not to clear TG1_TASK_CNT_CAP_TIMER1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TG1_task_cnt_cap_timer1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tg1_task_cnt_cap_timer1_st_clr:1; /** adc_task_sample0_st_clr : WT; bitpos: [4]; default: 0; - * Configures whether or not to clear ADC_TASK_SAMPLE0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_sample0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_sample0_st_clr:1; - uint32_t reserved_5:1; + /** adc_task_sample1_st_clr : WT; bitpos: [5]; default: 0; + * Configures whether or not to clear ADC_task_sample1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t adc_task_sample1_st_clr:1; /** adc_task_start0_st_clr : WT; bitpos: [6]; default: 0; - * Configures whether or not to clear ADC_TASK_START0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_start0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_start0_st_clr:1; /** adc_task_stop0_st_clr : WT; bitpos: [7]; default: 0; - * Configures whether or not to clear ADC_TASK_STOP0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear ADC_task_stop0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t adc_task_stop0_st_clr:1; - uint32_t reserved_8:4; + /** regdma_task_start0_st_clr : WT; bitpos: [8]; default: 0; + * Configures whether or not to clear REGDMA_task_start0 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start0_st_clr:1; + /** regdma_task_start1_st_clr : WT; bitpos: [9]; default: 0; + * Configures whether or not to clear REGDMA_task_start1 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start1_st_clr:1; + /** regdma_task_start2_st_clr : WT; bitpos: [10]; default: 0; + * Configures whether or not to clear REGDMA_task_start2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start2_st_clr:1; + /** regdma_task_start3_st_clr : WT; bitpos: [11]; default: 0; + * Configures whether or not to clear REGDMA_task_start3 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t regdma_task_start3_st_clr:1; /** tmpsnsr_task_start_sample_st_clr : WT; bitpos: [12]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_START_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_start_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_task_start_sample_st_clr:1; /** tmpsnsr_task_stop_sample_st_clr : WT; bitpos: [13]; default: 0; - * Configures whether or not to clear TMPSNSR_TASK_STOP_SAMPLE trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear TMPSNSR_task_stop_sample trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t tmpsnsr_task_stop_sample_st_clr:1; /** i2s0_task_start_rx_st_clr : WT; bitpos: [14]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_start_rx_st_clr:1; /** i2s0_task_start_tx_st_clr : WT; bitpos: [15]; default: 0; - * Configures whether or not to clear I2S0_TASK_START_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_start_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_start_tx_st_clr:1; /** i2s0_task_stop_rx_st_clr : WT; bitpos: [16]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_RX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_rx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_stop_rx_st_clr:1; /** i2s0_task_stop_tx_st_clr : WT; bitpos: [17]; default: 0; - * Configures whether or not to clear I2S0_TASK_STOP_TX trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear I2S0_task_stop_tx trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t i2s0_task_stop_tx_st_clr:1; - uint32_t reserved_18:10; + /** i2s1_task_start_rx_st_clr : WT; bitpos: [18]; default: 0; + * Configures whether or not to clear I2S1_task_start_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_start_rx_st_clr:1; + /** i2s1_task_start_tx_st_clr : WT; bitpos: [19]; default: 0; + * Configures whether or not to clear I2S1_task_start_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_start_tx_st_clr:1; + /** i2s1_task_stop_rx_st_clr : WT; bitpos: [20]; default: 0; + * Configures whether or not to clear I2S1_task_stop_rx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_stop_rx_st_clr:1; + /** i2s1_task_stop_tx_st_clr : WT; bitpos: [21]; default: 0; + * Configures whether or not to clear I2S1_task_stop_tx trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t i2s1_task_stop_tx_st_clr:1; + /** ulp_task_wakeup_cpu_st_clr : WT; bitpos: [22]; default: 0; + * Configures whether or not to clear ULP_task_wakeup_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_task_wakeup_cpu_st_clr:1; + /** ulp_task_int_cpu_st_clr : WT; bitpos: [23]; default: 0; + * Configures whether or not to clear ULP_task_int_cpu trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t ulp_task_int_cpu_st_clr:1; + /** rtc_task_start_st_clr : WT; bitpos: [24]; default: 0; + * Configures whether or not to clear RTC_task_start trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_start_st_clr:1; + /** rtc_task_stop_st_clr : WT; bitpos: [25]; default: 0; + * Configures whether or not to clear RTC_task_stop trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_stop_st_clr:1; + /** rtc_task_clr_st_clr : WT; bitpos: [26]; default: 0; + * Configures whether or not to clear RTC_task_clr trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_clr_st_clr:1; + /** rtc_task_triggerflw_st_clr : WT; bitpos: [27]; default: 0; + * Configures whether or not to clear RTC_task_triggerflw trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t rtc_task_triggerflw_st_clr:1; /** gdma_ahb_task_in_start_ch0_st_clr : WT; bitpos: [28]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_in_start_ch0_st_clr:1; /** gdma_ahb_task_in_start_ch1_st_clr : WT; bitpos: [29]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_IN_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_in_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_in_start_ch1_st_clr:1; - uint32_t reserved_30:1; + /** gdma_ahb_task_in_start_ch2_st_clr : WT; bitpos: [30]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_in_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_task_in_start_ch2_st_clr:1; /** gdma_ahb_task_out_start_ch0_st_clr : WT; bitpos: [31]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH0 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch0 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_out_start_ch0_st_clr:1; @@ -3602,20 +4077,25 @@ typedef union { } soc_etm_task_st3_clr_reg_t; /** Type of task_st4_clr register - * Task trigger status clear register + * Tasks trigger status clear register */ typedef union { struct { /** gdma_ahb_task_out_start_ch1_st_clr : WT; bitpos: [0]; default: 0; - * Configures whether or not to clear GDMA_AHB_TASK_OUT_START_CH1 trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear GDMA_AHB_task_out_start_ch1 trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t gdma_ahb_task_out_start_ch1_st_clr:1; - uint32_t reserved_1:1; + /** gdma_ahb_task_out_start_ch2_st_clr : WT; bitpos: [1]; default: 0; + * Configures whether or not to clear GDMA_AHB_task_out_start_ch2 trigger status. + * 0: Invalid, No effect + * 1: Clear + */ + uint32_t gdma_ahb_task_out_start_ch2_st_clr:1; /** pmu_task_sleep_req_st_clr : WT; bitpos: [2]; default: 0; - * Configures whether or not to clear PMU_TASK_SLEEP_REQ trigger status. - * 0: Invalid. No effect + * Configures whether or not to clear PMU_task_sleep_req trigger status. + * 0: Invalid, No effect * 1: Clear */ uint32_t pmu_task_sleep_req_st_clr:1; @@ -3643,12 +4123,12 @@ typedef union { /** Group: Version Register */ /** Type of date register - * Version control register + * ETM date register */ typedef union { struct { /** date : R/W; bitpos: [27:0]; default: 36737361; - * Version control register. + * Configures the version. */ uint32_t date:28; uint32_t reserved_28:4; diff --git a/components/soc/esp32c61/register/soc/spi1_mem_reg.h b/components/soc/esp32c61/register/soc/spi1_mem_reg.h index 73d7b8f526..92bd65ae03 100644 --- a/components/soc/esp32c61/register/soc/spi1_mem_reg.h +++ b/components/soc/esp32c61/register/soc/spi1_mem_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -35,6 +35,7 @@ extern "C" { * In user mode, it is set to indicate that program/erase operation will be triggered. * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_PE (BIT(17)) #define SPI_MEM_FLASH_PE_M (SPI_MEM_FLASH_PE_V << SPI_MEM_FLASH_PE_S) @@ -51,6 +52,7 @@ extern "C" { /** SPI_MEM_FLASH_HPM : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_HPM (BIT(19)) #define SPI_MEM_FLASH_HPM_M (SPI_MEM_FLASH_HPM_V << SPI_MEM_FLASH_HPM_S) @@ -60,6 +62,7 @@ extern "C" { * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RES (BIT(20)) #define SPI_MEM_FLASH_RES_M (SPI_MEM_FLASH_RES_V << SPI_MEM_FLASH_RES_S) @@ -68,6 +71,7 @@ extern "C" { /** SPI_MEM_FLASH_DP : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_DP (BIT(21)) #define SPI_MEM_FLASH_DP_M (SPI_MEM_FLASH_DP_V << SPI_MEM_FLASH_DP_S) @@ -76,6 +80,7 @@ extern "C" { /** SPI_MEM_FLASH_CE : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_CE (BIT(22)) #define SPI_MEM_FLASH_CE_M (SPI_MEM_FLASH_CE_V << SPI_MEM_FLASH_CE_S) @@ -84,6 +89,7 @@ extern "C" { /** SPI_MEM_FLASH_BE : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_BE (BIT(23)) #define SPI_MEM_FLASH_BE_M (SPI_MEM_FLASH_BE_V << SPI_MEM_FLASH_BE_S) @@ -92,6 +98,7 @@ extern "C" { /** SPI_MEM_FLASH_SE : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_SE (BIT(24)) #define SPI_MEM_FLASH_SE_M (SPI_MEM_FLASH_SE_V << SPI_MEM_FLASH_SE_S) @@ -101,6 +108,7 @@ extern "C" { * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_PP (BIT(25)) #define SPI_MEM_FLASH_PP_M (SPI_MEM_FLASH_PP_V << SPI_MEM_FLASH_PP_S) @@ -109,6 +117,7 @@ extern "C" { /** SPI_MEM_FLASH_WRSR : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WRSR (BIT(26)) #define SPI_MEM_FLASH_WRSR_M (SPI_MEM_FLASH_WRSR_V << SPI_MEM_FLASH_WRSR_S) @@ -117,6 +126,7 @@ extern "C" { /** SPI_MEM_FLASH_RDSR : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RDSR (BIT(27)) #define SPI_MEM_FLASH_RDSR_M (SPI_MEM_FLASH_RDSR_V << SPI_MEM_FLASH_RDSR_S) @@ -125,6 +135,7 @@ extern "C" { /** SPI_MEM_FLASH_RDID : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_RDID (BIT(28)) #define SPI_MEM_FLASH_RDID_M (SPI_MEM_FLASH_RDID_V << SPI_MEM_FLASH_RDID_S) @@ -133,6 +144,7 @@ extern "C" { /** SPI_MEM_FLASH_WRDI : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WRDI (BIT(29)) #define SPI_MEM_FLASH_WRDI_M (SPI_MEM_FLASH_WRDI_V << SPI_MEM_FLASH_WRDI_S) @@ -141,6 +153,7 @@ extern "C" { /** SPI_MEM_FLASH_WREN : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_WREN (BIT(30)) #define SPI_MEM_FLASH_WREN_M (SPI_MEM_FLASH_WREN_V << SPI_MEM_FLASH_WREN_S) @@ -149,6 +162,7 @@ extern "C" { /** SPI_MEM_FLASH_READ : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FLASH_READ (BIT(31)) #define SPI_MEM_FLASH_READ_M (SPI_MEM_FLASH_READ_V << SPI_MEM_FLASH_READ_S) @@ -226,6 +240,7 @@ extern "C" { /** SPI_MEM_FCS_CRC_EN : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FCS_CRC_EN (BIT(10)) #define SPI_MEM_FCS_CRC_EN_M (SPI_MEM_FCS_CRC_EN_V << SPI_MEM_FCS_CRC_EN_S) @@ -233,6 +248,7 @@ extern "C" { #define SPI_MEM_FCS_CRC_EN_S 10 /** SPI_MEM_TX_CRC_EN : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_TX_CRC_EN (BIT(11)) #define SPI_MEM_TX_CRC_EN_M (SPI_MEM_TX_CRC_EN_V << SPI_MEM_TX_CRC_EN_S) @@ -256,6 +272,7 @@ extern "C" { /** SPI_MEM_RESANDRES : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_RESANDRES (BIT(15)) #define SPI_MEM_RESANDRES_M (SPI_MEM_RESANDRES_V << SPI_MEM_RESANDRES_S) @@ -292,6 +309,7 @@ extern "C" { /** SPI_MEM_WRSR_2B : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WRSR_2B (BIT(22)) #define SPI_MEM_WRSR_2B_M (SPI_MEM_WRSR_2B_V << SPI_MEM_WRSR_2B_S) @@ -328,13 +346,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 /** SPI_MEM_CS_HOLD_DLY_RES : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ #define SPI_MEM_CS_HOLD_DLY_RES 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_M (SPI_MEM_CS_HOLD_DLY_RES_V << SPI_MEM_CS_HOLD_DLY_RES_S) #define SPI_MEM_CS_HOLD_DLY_RES_V 0x000003FFU #define SPI_MEM_CS_HOLD_DLY_RES_S 2 +/** SPI_MEM_CS_HOLD_DLY_PER : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ +#define SPI_MEM_CS_HOLD_DLY_PER 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_M (SPI_MEM_CS_HOLD_DLY_PER_V << SPI_MEM_CS_HOLD_DLY_PER_S) +#define SPI_MEM_CS_HOLD_DLY_PER_V 0x000003FFU +#define SPI_MEM_CS_HOLD_DLY_PER_S 12 /** SPI_MEM_CTRL2_REG register * SPI1 control2 register. @@ -353,14 +379,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -368,7 +394,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -556,6 +582,7 @@ extern "C" { #define SPI_MEM_STATUS_S 0 /** SPI_MEM_WB_MODE : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE 0x000000FFU #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) @@ -563,6 +590,7 @@ extern "C" { #define SPI_MEM_WB_MODE_S 16 /** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_BITLEN 0x00000007U #define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) @@ -570,6 +598,7 @@ extern "C" { #define SPI_MEM_WB_MODE_BITLEN_S 24 /** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_WB_MODE_EN (BIT(27)) #define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) @@ -625,10 +654,13 @@ extern "C" { /** SPI_MEM_CACHE_FCTRL_REG register * SPI1 bit mode control register. + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3c) /** SPI_MEM_CACHE_USR_ADDR_4BYTE : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_CACHE_USR_ADDR_4BYTE (BIT(1)) #define SPI_MEM_CACHE_USR_ADDR_4BYTE_M (SPI_MEM_CACHE_USR_ADDR_4BYTE_V << SPI_MEM_CACHE_USR_ADDR_4BYTE_S) @@ -637,6 +669,7 @@ extern "C" { /** SPI_MEM_FDIN_DUAL : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDIN_DUAL (BIT(3)) #define SPI_MEM_FDIN_DUAL_M (SPI_MEM_FDIN_DUAL_V << SPI_MEM_FDIN_DUAL_S) @@ -645,6 +678,7 @@ extern "C" { /** SPI_MEM_FDOUT_DUAL : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDOUT_DUAL (BIT(4)) #define SPI_MEM_FDOUT_DUAL_M (SPI_MEM_FDOUT_DUAL_V << SPI_MEM_FDOUT_DUAL_S) @@ -653,6 +687,7 @@ extern "C" { /** SPI_MEM_FADDR_DUAL : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FADDR_DUAL (BIT(5)) #define SPI_MEM_FADDR_DUAL_M (SPI_MEM_FADDR_DUAL_V << SPI_MEM_FADDR_DUAL_S) @@ -661,6 +696,7 @@ extern "C" { /** SPI_MEM_FDIN_QUAD : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDIN_QUAD (BIT(6)) #define SPI_MEM_FDIN_QUAD_M (SPI_MEM_FDIN_QUAD_V << SPI_MEM_FDIN_QUAD_S) @@ -669,6 +705,7 @@ extern "C" { /** SPI_MEM_FDOUT_QUAD : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FDOUT_QUAD (BIT(7)) #define SPI_MEM_FDOUT_QUAD_M (SPI_MEM_FDOUT_QUAD_V << SPI_MEM_FDOUT_QUAD_S) @@ -677,6 +714,7 @@ extern "C" { /** SPI_MEM_FADDR_QUAD : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_FADDR_QUAD (BIT(8)) #define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) @@ -999,14 +1037,14 @@ extern "C" { #define SPI_MEM_PESR_END_MSK_M (SPI_MEM_PESR_END_MSK_V << SPI_MEM_PESR_END_MSK_S) #define SPI_MEM_PESR_END_MSK_V 0x0000FFFFU #define SPI_MEM_PESR_END_MSK_S 6 -/** SPI_MEM_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; +/** SPI_FMEM_RD_SUS_2B : R/W; bitpos: [22]; default: 0; * 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when * check flash SUS/SUS1/SUS2 status bit */ -#define SPI_MEM_FMEM_RD_SUS_2B (BIT(22)) -#define SPI_MEM_FMEM_RD_SUS_2B_M (SPI_MEM_FMEM_RD_SUS_2B_V << SPI_MEM_FMEM_RD_SUS_2B_S) -#define SPI_MEM_FMEM_RD_SUS_2B_V 0x00000001U -#define SPI_MEM_FMEM_RD_SUS_2B_S 22 +#define SPI_FMEM_RD_SUS_2B (BIT(22)) +#define SPI_FMEM_RD_SUS_2B_M (SPI_FMEM_RD_SUS_2B_V << SPI_FMEM_RD_SUS_2B_S) +#define SPI_FMEM_RD_SUS_2B_V 0x00000001U +#define SPI_FMEM_RD_SUS_2B_S 22 /** SPI_MEM_PER_END_EN : R/W; bitpos: [23]; default: 0; * 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of * flash. 0: Only need to check WIP is 0. @@ -1361,110 +1399,110 @@ extern "C" { * SPI1 DDR control register */ #define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) -/** SPI_MEM_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in ddr mode, 0 in sdr mode */ -#define SPI_MEM_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_FMEM_DDR_EN_M (SPI_MEM_FMEM_DDR_EN_V << SPI_MEM_FMEM_DDR_EN_S) -#define SPI_MEM_FMEM_DDR_EN_V 0x00000001U -#define SPI_MEM_FMEM_DDR_EN_S 0 -/** SPI_MEM_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; +#define SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) +#define SPI_FMEM_DDR_EN_V 0x00000001U +#define SPI_FMEM_DDR_EN_S 0 +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi ddr mode. */ -#define SPI_MEM_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_FMEM_VAR_DUMMY_M (SPI_MEM_FMEM_VAR_DUMMY_V << SPI_MEM_FMEM_VAR_DUMMY_S) -#define SPI_MEM_FMEM_VAR_DUMMY_V 0x00000001U -#define SPI_MEM_FMEM_VAR_DUMMY_S 1 -/** SPI_MEM_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; +#define SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) +#define SPI_FMEM_VAR_DUMMY_V 0x00000001U +#define SPI_FMEM_VAR_DUMMY_S 1 +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi ddr mode. */ -#define SPI_MEM_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_FMEM_DDR_RDAT_SWP_M (SPI_MEM_FMEM_DDR_RDAT_SWP_V << SPI_MEM_FMEM_DDR_RDAT_SWP_S) -#define SPI_MEM_FMEM_DDR_RDAT_SWP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_MEM_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; +#define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) +#define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_RDAT_SWP_S 2 +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi ddr mode. */ -#define SPI_MEM_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_FMEM_DDR_WDAT_SWP_M (SPI_MEM_FMEM_DDR_WDAT_SWP_V << SPI_MEM_FMEM_DDR_WDAT_SWP_S) -#define SPI_MEM_FMEM_DDR_WDAT_SWP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_MEM_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; +#define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) +#define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U +#define SPI_FMEM_DDR_WDAT_SWP_S 3 +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when ddr mode. */ -#define SPI_MEM_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_FMEM_DDR_CMD_DIS_M (SPI_MEM_FMEM_DDR_CMD_DIS_V << SPI_MEM_FMEM_DDR_CMD_DIS_S) -#define SPI_MEM_FMEM_DDR_CMD_DIS_V 0x00000001U -#define SPI_MEM_FMEM_DDR_CMD_DIS_S 4 -/** SPI_MEM_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; +#define SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) +#define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U +#define SPI_FMEM_DDR_CMD_DIS_S 4 +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ -#define SPI_MEM_FMEM_OUTMINBYTELEN 0x0000007FU -#define SPI_MEM_FMEM_OUTMINBYTELEN_M (SPI_MEM_FMEM_OUTMINBYTELEN_V << SPI_MEM_FMEM_OUTMINBYTELEN_S) -#define SPI_MEM_FMEM_OUTMINBYTELEN_V 0x0000007FU -#define SPI_MEM_FMEM_OUTMINBYTELEN_S 5 -/** SPI_MEM_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; +#define SPI_FMEM_OUTMINBYTELEN 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) +#define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU +#define SPI_FMEM_OUTMINBYTELEN_S 5 +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ -#define SPI_MEM_FMEM_USR_DDR_DQS_THD 0x0000007FU -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_M (SPI_MEM_FMEM_USR_DDR_DQS_THD_V << SPI_MEM_FMEM_USR_DDR_DQS_THD_S) -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_V 0x0000007FU -#define SPI_MEM_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_MEM_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; +#define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) +#define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU +#define SPI_FMEM_USR_DDR_DQS_THD_S 14 +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ -#define SPI_MEM_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_FMEM_DDR_DQS_LOOP_M (SPI_MEM_FMEM_DDR_DQS_LOOP_V << SPI_MEM_FMEM_DDR_DQS_LOOP_S) -#define SPI_MEM_FMEM_DDR_DQS_LOOP_V 0x00000001U -#define SPI_MEM_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_MEM_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; +#define SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) +#define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U +#define SPI_FMEM_DDR_DQS_LOOP_S 21 +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ -#define SPI_MEM_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_FMEM_CLK_DIFF_EN_M (SPI_MEM_FMEM_CLK_DIFF_EN_V << SPI_MEM_FMEM_CLK_DIFF_EN_S) -#define SPI_MEM_FMEM_CLK_DIFF_EN_V 0x00000001U -#define SPI_MEM_FMEM_CLK_DIFF_EN_S 24 -/** SPI_MEM_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; +#define SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) +#define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_EN_S 24 +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ -#define SPI_MEM_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_FMEM_DQS_CA_IN_M (SPI_MEM_FMEM_DQS_CA_IN_V << SPI_MEM_FMEM_DQS_CA_IN_S) -#define SPI_MEM_FMEM_DQS_CA_IN_V 0x00000001U -#define SPI_MEM_FMEM_DQS_CA_IN_S 26 -/** SPI_MEM_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; +#define SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) +#define SPI_FMEM_DQS_CA_IN_V 0x00000001U +#define SPI_FMEM_DQS_CA_IN_S 26 +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_M (SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V << SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S) -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U -#define SPI_MEM_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_MEM_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; +#define SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) +#define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U +#define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ -#define SPI_MEM_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_FMEM_CLK_DIFF_INV_M (SPI_MEM_FMEM_CLK_DIFF_INV_V << SPI_MEM_FMEM_CLK_DIFF_INV_S) -#define SPI_MEM_FMEM_CLK_DIFF_INV_V 0x00000001U -#define SPI_MEM_FMEM_CLK_DIFF_INV_S 28 -/** SPI_MEM_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; +#define SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) +#define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U +#define SPI_FMEM_CLK_DIFF_INV_S 28 +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ -#define SPI_MEM_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_M (SPI_MEM_FMEM_OCTA_RAM_ADDR_V << SPI_MEM_FMEM_OCTA_RAM_ADDR_S) -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_V 0x00000001U -#define SPI_MEM_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_MEM_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; +#define SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) +#define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U +#define SPI_FMEM_OCTA_RAM_ADDR_S 29 +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ -#define SPI_MEM_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_FMEM_HYPERBUS_CA_M (SPI_MEM_FMEM_HYPERBUS_CA_V << SPI_MEM_FMEM_HYPERBUS_CA_S) -#define SPI_MEM_FMEM_HYPERBUS_CA_V 0x00000001U -#define SPI_MEM_FMEM_HYPERBUS_CA_S 30 +#define SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_FMEM_HYPERBUS_CA_M (SPI_FMEM_HYPERBUS_CA_V << SPI_FMEM_HYPERBUS_CA_S) +#define SPI_FMEM_HYPERBUS_CA_V 0x00000001U +#define SPI_FMEM_HYPERBUS_CA_S 30 /** SPI_MEM_TIMING_CALI_REG register * SPI1 timing control register @@ -1501,7 +1539,7 @@ extern "C" { * Version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36774400; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37823232; * Version control register */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi1_mem_struct.h b/components/soc/esp32c61/register/soc/spi1_mem_struct.h index 9ff190d0d5..f89e1d3d17 100644 --- a/components/soc/esp32c61/register/soc/spi1_mem_struct.h +++ b/components/soc/esp32c61/register/soc/spi1_mem_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,6 +31,7 @@ typedef union { * In user mode, it is set to indicate that program/erase operation will be triggered. * The bit is combined with spi_mem_usr bit. The bit will be cleared once the * operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pe:1; /** usr : R/W/SC; bitpos: [18]; default: 0; @@ -41,68 +42,81 @@ typedef union { /** flash_hpm : R/W/SC; bitpos: [19]; default: 0; * Drive Flash into high performance mode. The bit will be cleared once the operation * done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_hpm:1; /** flash_res : R/W/SC; bitpos: [20]; default: 0; * This bit combined with reg_resandres bit releases Flash from the power-down state * or high performance mode and obtains the devices ID. The bit will be cleared once * the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_res:1; /** flash_dp : R/W/SC; bitpos: [21]; default: 0; * Drive Flash into power down. An operation will be triggered when the bit is set. * The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_dp:1; /** flash_ce : R/W/SC; bitpos: [22]; default: 0; * Chip erase enable. Chip erase operation will be triggered when the bit is set. The * bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_ce:1; /** flash_be : R/W/SC; bitpos: [23]; default: 0; * Block erase enable(32KB) . Block erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_be:1; /** flash_se : R/W/SC; bitpos: [24]; default: 0; * Sector erase enable(4KB). Sector erase operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_se:1; /** flash_pp : R/W/SC; bitpos: [25]; default: 0; * Page program enable(1 byte ~256 bytes data to be programmed). Page program * operation will be triggered when the bit is set. The bit will be cleared once the * operation done .1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_pp:1; /** flash_wrsr : R/W/SC; bitpos: [26]; default: 0; * Write status register enable. Write status operation will be triggered when the * bit is set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrsr:1; /** flash_rdsr : R/W/SC; bitpos: [27]; default: 0; * Read status register-1. Read status operation will be triggered when the bit is * set. The bit will be cleared once the operation done.1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdsr:1; /** flash_rdid : R/W/SC; bitpos: [28]; default: 0; * Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be * cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_rdid:1; /** flash_wrdi : R/W/SC; bitpos: [29]; default: 0; * Write flash disable. Write disable command will be sent when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wrdi:1; /** flash_wren : R/W/SC; bitpos: [30]; default: 0; * Write flash enable. Write enable command will be sent when the bit is set. The bit * will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_wren:1; /** flash_read : R/W/SC; bitpos: [31]; default: 0; * Read flash enable. Read flash operation will be triggered when the bit is set. The * bit will be cleared once the operation done. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t flash_read:1; }; @@ -268,10 +282,12 @@ typedef union { /** fcs_crc_en : R/W; bitpos: [10]; default: 0; * For SPI1, initialize crc32 module before writing encrypted data to flash. Active * low. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fcs_crc_en:1; /** tx_crc_en : R/W; bitpos: [11]; default: 0; * For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t tx_crc_en:1; uint32_t reserved_12:1; @@ -287,6 +303,7 @@ typedef union { /** resandres : R/W; bitpos: [15]; default: 1; * The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with * spi_mem_flash_res bit. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t resandres:1; uint32_t reserved_16:2; @@ -309,6 +326,7 @@ typedef union { /** wrsr_2b : R/W; bitpos: [22]; default: 0; * two bytes data will be written to status register when it is set. 1: enable 0: * disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wrsr_2b:1; /** fread_dio : R/W; bitpos: [23]; default: 0; @@ -338,11 +356,16 @@ typedef union { */ uint32_t clk_mode:2; /** cs_hold_dly_res : R/W; bitpos: [11:2]; default: 1023; - * After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) - * SPI_CLK cycles. + * After RES/DP/HPM/PES command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * + * 128) SPI_CLK cycles. */ uint32_t cs_hold_dly_res:10; - uint32_t reserved_12:20; + /** cs_hold_dly_per : R/W; bitpos: [21:12]; default: 1023; + * After PER command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DLY_PER[9:0] * 128) SPI_CLK + * cycles. + */ + uint32_t cs_hold_dly_per:10; + uint32_t reserved_22:10; }; uint32_t val; } spi_mem_ctrl1_reg_t; @@ -367,16 +390,16 @@ typedef union { typedef union { struct { /** clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t clkcnt_l:8; /** clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t clkcnt_h:8; /** clkcnt_n : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t clkcnt_n:8; uint32_t reserved_24:7; @@ -427,14 +450,17 @@ typedef union { uint32_t status:16; /** wb_mode : R/W; bitpos: [23:16]; default: 0; * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode:8; /** wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode_bitlen:3; /** wb_mode_en : R/W; bitpos: [27]; default: 0; * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t wb_mode_en:1; uint32_t reserved_28:4; @@ -479,37 +505,44 @@ typedef union { uint32_t reserved_0:1; /** cache_usr_addr_4byte : R/W; bitpos: [1]; default: 0; * For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t cache_usr_addr_4byte:1; uint32_t reserved_2:1; /** fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with * spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_dual:1; /** fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_dual:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_dio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_dual:1; /** fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdin_quad:1; /** fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t fdout_quad:1; /** faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same * with spi_mem_fread_qio. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t faddr_quad:1; uint32_t reserved_9:23; @@ -834,216 +867,6 @@ typedef union { } spi_mem_tx_crc_reg_t; -/** Group: Memory data buffer register */ -/** Type of word buffer register - * SPI1 memory data buffer_n - */ -typedef union { - struct { - /** buf0 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf0:32; - }; - uint32_t val; -} spi_mem_buffer_reg_t; - -/** Type of w1 register - * SPI1 memory data buffer1 - */ -typedef union { - struct { - /** buf1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf1:32; - }; - uint32_t val; -} spi_mem_w1_reg_t; - -/** Type of w2 register - * SPI1 memory data buffer2 - */ -typedef union { - struct { - /** buf2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf2:32; - }; - uint32_t val; -} spi_mem_w2_reg_t; - -/** Type of w3 register - * SPI1 memory data buffer3 - */ -typedef union { - struct { - /** buf3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf3:32; - }; - uint32_t val; -} spi_mem_w3_reg_t; - -/** Type of w4 register - * SPI1 memory data buffer4 - */ -typedef union { - struct { - /** buf4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf4:32; - }; - uint32_t val; -} spi_mem_w4_reg_t; - -/** Type of w5 register - * SPI1 memory data buffer5 - */ -typedef union { - struct { - /** buf5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf5:32; - }; - uint32_t val; -} spi_mem_w5_reg_t; - -/** Type of w6 register - * SPI1 memory data buffer6 - */ -typedef union { - struct { - /** buf6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf6:32; - }; - uint32_t val; -} spi_mem_w6_reg_t; - -/** Type of w7 register - * SPI1 memory data buffer7 - */ -typedef union { - struct { - /** buf7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf7:32; - }; - uint32_t val; -} spi_mem_w7_reg_t; - -/** Type of w8 register - * SPI1 memory data buffer8 - */ -typedef union { - struct { - /** buf8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf8:32; - }; - uint32_t val; -} spi_mem_w8_reg_t; - -/** Type of w9 register - * SPI1 memory data buffer9 - */ -typedef union { - struct { - /** buf9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf9:32; - }; - uint32_t val; -} spi_mem_w9_reg_t; - -/** Type of w10 register - * SPI1 memory data buffer10 - */ -typedef union { - struct { - /** buf10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf10:32; - }; - uint32_t val; -} spi_mem_w10_reg_t; - -/** Type of w11 register - * SPI1 memory data buffer11 - */ -typedef union { - struct { - /** buf11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf11:32; - }; - uint32_t val; -} spi_mem_w11_reg_t; - -/** Type of w12 register - * SPI1 memory data buffer12 - */ -typedef union { - struct { - /** buf12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf12:32; - }; - uint32_t val; -} spi_mem_w12_reg_t; - -/** Type of w13 register - * SPI1 memory data buffer13 - */ -typedef union { - struct { - /** buf13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf13:32; - }; - uint32_t val; -} spi_mem_w13_reg_t; - -/** Type of w14 register - * SPI1 memory data buffer14 - */ -typedef union { - struct { - /** buf14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf14:32; - }; - uint32_t val; -} spi_mem_w14_reg_t; - -/** Type of w15 register - * SPI1 memory data buffer15 - */ -typedef union { - struct { - /** buf15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - uint32_t buf15:32; - }; - uint32_t val; -} spi_mem_w15_reg_t; - - /** Group: Interrupt registers */ /** Type of int_ena register * SPI1 interrupt enable register @@ -1222,7 +1045,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36774400; + /** date : R/W; bitpos: [27:0]; default: 37823232; * Version control register */ uint32_t date:28; diff --git a/components/soc/esp32c61/register/soc/spi_mem_c_reg.h b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h index 6bde89aefd..7d3370c582 100644 --- a/components/soc/esp32c61/register/soc/spi_mem_c_reg.h +++ b/components/soc/esp32c61/register/soc/spi_mem_c_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -47,7 +47,7 @@ extern "C" { * SPI0 control register. */ #define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) -/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ @@ -81,21 +81,21 @@ extern "C" { #define SPI_MEM_FDUMMY_WOUT_M (SPI_MEM_FDUMMY_WOUT_V << SPI_MEM_FDUMMY_WOUT_S) #define SPI_MEM_FDUMMY_WOUT_V 0x00000001U #define SPI_MEM_FDUMMY_WOUT_S 3 -/** SPI_MEM_FDOUT_OCT : HRO; bitpos: [4]; default: 0; +/** SPI_MEM_FDOUT_OCT : R/W; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ #define SPI_MEM_FDOUT_OCT (BIT(4)) #define SPI_MEM_FDOUT_OCT_M (SPI_MEM_FDOUT_OCT_V << SPI_MEM_FDOUT_OCT_S) #define SPI_MEM_FDOUT_OCT_V 0x00000001U #define SPI_MEM_FDOUT_OCT_S 4 -/** SPI_MEM_FDIN_OCT : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_FDIN_OCT : R/W; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ #define SPI_MEM_FDIN_OCT (BIT(5)) #define SPI_MEM_FDIN_OCT_M (SPI_MEM_FDIN_OCT_V << SPI_MEM_FDIN_OCT_S) #define SPI_MEM_FDIN_OCT_V 0x00000001U #define SPI_MEM_FDIN_OCT_S 5 -/** SPI_MEM_FADDR_OCT : HRO; bitpos: [6]; default: 0; +/** SPI_MEM_FADDR_OCT : R/W; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ #define SPI_MEM_FADDR_OCT (BIT(6)) @@ -109,7 +109,7 @@ extern "C" { #define SPI_MEM_FCMD_QUAD_M (SPI_MEM_FCMD_QUAD_V << SPI_MEM_FCMD_QUAD_S) #define SPI_MEM_FCMD_QUAD_V 0x00000001U #define SPI_MEM_FCMD_QUAD_S 8 -/** SPI_MEM_FCMD_OCT : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_FCMD_OCT : R/W; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ #define SPI_MEM_FCMD_OCT (BIT(9)) @@ -175,7 +175,7 @@ extern "C" { #define SPI_MEM_FREAD_QIO_M (SPI_MEM_FREAD_QIO_V << SPI_MEM_FREAD_QIO_S) #define SPI_MEM_FREAD_QIO_V 0x00000001U #define SPI_MEM_FREAD_QIO_S 24 -/** SPI_MEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 0; +/** SPI_MEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ @@ -205,29 +205,21 @@ extern "C" { #define SPI_MEM_CLK_MODE_M (SPI_MEM_CLK_MODE_V << SPI_MEM_CLK_MODE_S) #define SPI_MEM_CLK_MODE_V 0x00000003U #define SPI_MEM_CLK_MODE_S 0 -/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [21]; default: 1; +/** SPI_AR_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(21)) +#define SPI_AR_SIZE0_1_SUPPORT_EN (BIT(22)) #define SPI_AR_SIZE0_1_SUPPORT_EN_M (SPI_AR_SIZE0_1_SUPPORT_EN_V << SPI_AR_SIZE0_1_SUPPORT_EN_S) #define SPI_AR_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AR_SIZE0_1_SUPPORT_EN_S 21 -/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [22]; default: 1; +#define SPI_AR_SIZE0_1_SUPPORT_EN_S 22 +/** SPI_AW_SIZE0_1_SUPPORT_EN : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ -#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(22)) +#define SPI_AW_SIZE0_1_SUPPORT_EN (BIT(23)) #define SPI_AW_SIZE0_1_SUPPORT_EN_M (SPI_AW_SIZE0_1_SUPPORT_EN_V << SPI_AW_SIZE0_1_SUPPORT_EN_S) #define SPI_AW_SIZE0_1_SUPPORT_EN_V 0x00000001U -#define SPI_AW_SIZE0_1_SUPPORT_EN_S 22 -/** SPI_AXI_RDATA_BACK_FAST : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ -#define SPI_AXI_RDATA_BACK_FAST (BIT(23)) -#define SPI_AXI_RDATA_BACK_FAST_M (SPI_AXI_RDATA_BACK_FAST_V << SPI_AXI_RDATA_BACK_FAST_S) -#define SPI_AXI_RDATA_BACK_FAST_V 0x00000001U -#define SPI_AXI_RDATA_BACK_FAST_S 23 +#define SPI_AW_SIZE0_1_SUPPORT_EN_S 23 /** SPI_MEM_RRESP_ECC_ERR_EN : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded @@ -237,14 +229,14 @@ extern "C" { #define SPI_MEM_RRESP_ECC_ERR_EN_M (SPI_MEM_RRESP_ECC_ERR_EN_V << SPI_MEM_RRESP_ECC_ERR_EN_S) #define SPI_MEM_RRESP_ECC_ERR_EN_V 0x00000001U #define SPI_MEM_RRESP_ECC_ERR_EN_S 24 -/** SPI_MEM_AR_SPLICE_EN : HRO; bitpos: [25]; default: 0; +/** SPI_MEM_AR_SPLICE_EN : R/W; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ #define SPI_MEM_AR_SPLICE_EN (BIT(25)) #define SPI_MEM_AR_SPLICE_EN_M (SPI_MEM_AR_SPLICE_EN_V << SPI_MEM_AR_SPLICE_EN_S) #define SPI_MEM_AR_SPLICE_EN_V 0x00000001U #define SPI_MEM_AR_SPLICE_EN_S 25 -/** SPI_MEM_AW_SPLICE_EN : HRO; bitpos: [26]; default: 0; +/** SPI_MEM_AW_SPLICE_EN : R/W; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ #define SPI_MEM_AW_SPLICE_EN (BIT(26)) @@ -315,7 +307,7 @@ extern "C" { #define SPI_MEM_CS_HOLD_TIME_M (SPI_MEM_CS_HOLD_TIME_V << SPI_MEM_CS_HOLD_TIME_S) #define SPI_MEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_MEM_CS_HOLD_TIME_S 5 -/** SPI_MEM_ECC_CS_HOLD_TIME : HRO; bitpos: [12:10]; default: 3; +/** SPI_MEM_ECC_CS_HOLD_TIME : R/W; bitpos: [12:10]; default: 3; * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ @@ -323,7 +315,7 @@ extern "C" { #define SPI_MEM_ECC_CS_HOLD_TIME_M (SPI_MEM_ECC_CS_HOLD_TIME_V << SPI_MEM_ECC_CS_HOLD_TIME_S) #define SPI_MEM_ECC_CS_HOLD_TIME_V 0x00000007U #define SPI_MEM_ECC_CS_HOLD_TIME_S 10 -/** SPI_MEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [13]; default: 1; +/** SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ @@ -331,7 +323,7 @@ extern "C" { #define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (SPI_MEM_ECC_SKIP_PAGE_CORNER_V << SPI_MEM_ECC_SKIP_PAGE_CORNER_S) #define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U #define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 -/** SPI_MEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [14]; default: 0; +/** SPI_MEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ @@ -370,14 +362,14 @@ extern "C" { */ #define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) /** SPI_MEM_CLKCNT_L : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ #define SPI_MEM_CLKCNT_L 0x000000FFU #define SPI_MEM_CLKCNT_L_M (SPI_MEM_CLKCNT_L_V << SPI_MEM_CLKCNT_L_S) #define SPI_MEM_CLKCNT_L_V 0x000000FFU #define SPI_MEM_CLKCNT_L_S 0 /** SPI_MEM_CLKCNT_H : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ #define SPI_MEM_CLKCNT_H 0x000000FFU #define SPI_MEM_CLKCNT_H_M (SPI_MEM_CLKCNT_H_V << SPI_MEM_CLKCNT_H_S) @@ -385,7 +377,7 @@ extern "C" { #define SPI_MEM_CLKCNT_H_S 8 /** SPI_MEM_CLKCNT_N : R/W; bitpos: [23:16]; default: 3; * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is - * system/(spi_mem_clkcnt_N+1) + * system/(SPI_MEM_CLKCNT_N+1) */ #define SPI_MEM_CLKCNT_N 0x000000FFU #define SPI_MEM_CLKCNT_N_M (SPI_MEM_CLKCNT_N_V << SPI_MEM_CLKCNT_N_S) @@ -452,12 +444,12 @@ extern "C" { #define SPI_MEM_USR_DUMMY_CYCLELEN_M (SPI_MEM_USR_DUMMY_CYCLELEN_V << SPI_MEM_USR_DUMMY_CYCLELEN_S) #define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x0000003FU #define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 -/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [8:6]; default: 1; +/** SPI_MEM_USR_DBYTELEN : HRO; bitpos: [11:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ -#define SPI_MEM_USR_DBYTELEN 0x00000007U +#define SPI_MEM_USR_DBYTELEN 0x0000003FU #define SPI_MEM_USR_DBYTELEN_M (SPI_MEM_USR_DBYTELEN_V << SPI_MEM_USR_DBYTELEN_S) -#define SPI_MEM_USR_DBYTELEN_V 0x00000007U +#define SPI_MEM_USR_DBYTELEN_V 0x0000003FU #define SPI_MEM_USR_DBYTELEN_S 6 /** SPI_MEM_USR_ADDR_BITLEN : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). @@ -500,6 +492,22 @@ extern "C" { #define SPI_MEM_WB_MODE_M (SPI_MEM_WB_MODE_V << SPI_MEM_WB_MODE_S) #define SPI_MEM_WB_MODE_V 0x000000FFU #define SPI_MEM_WB_MODE_S 16 +/** SPI_MEM_WB_MODE_BITLEN : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_BITLEN 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_M (SPI_MEM_WB_MODE_BITLEN_V << SPI_MEM_WB_MODE_BITLEN_S) +#define SPI_MEM_WB_MODE_BITLEN_V 0x00000007U +#define SPI_MEM_WB_MODE_BITLEN_S 24 +/** SPI_MEM_WB_MODE_EN : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define SPI_MEM_WB_MODE_EN (BIT(27)) +#define SPI_MEM_WB_MODE_EN_M (SPI_MEM_WB_MODE_EN_V << SPI_MEM_WB_MODE_EN_S) +#define SPI_MEM_WB_MODE_EN_V 0x00000001U +#define SPI_MEM_WB_MODE_EN_S 27 /** SPI_MEM_MISC_REG register * SPI0 misc register @@ -616,7 +624,7 @@ extern "C" { #define SPI_MEM_FADDR_QUAD_M (SPI_MEM_FADDR_QUAD_V << SPI_MEM_FADDR_QUAD_S) #define SPI_MEM_FADDR_QUAD_V 0x00000001U #define SPI_MEM_FADDR_QUAD_S 8 -/** SPI_SAME_AW_AR_ADDR_CHK_EN : HRO; bitpos: [30]; default: 1; +/** SPI_SAME_AW_AR_ADDR_CHK_EN : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ #define SPI_SAME_AW_AR_ADDR_CHK_EN (BIT(30)) @@ -638,7 +646,7 @@ extern "C" { * applications. */ #define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) -/** SPI_MEM_CACHE_USR_SADDR_4BYTE : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_CACHE_USR_SADDR_4BYTE : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. @@ -647,7 +655,7 @@ extern "C" { #define SPI_MEM_CACHE_USR_SADDR_4BYTE_M (SPI_MEM_CACHE_USR_SADDR_4BYTE_V << SPI_MEM_CACHE_USR_SADDR_4BYTE_S) #define SPI_MEM_CACHE_USR_SADDR_4BYTE_V 0x00000001U #define SPI_MEM_CACHE_USR_SADDR_4BYTE_S 0 -/** SPI_MEM_USR_SRAM_DIO : HRO; bitpos: [1]; default: 0; +/** SPI_MEM_USR_SRAM_DIO : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -655,7 +663,7 @@ extern "C" { #define SPI_MEM_USR_SRAM_DIO_M (SPI_MEM_USR_SRAM_DIO_V << SPI_MEM_USR_SRAM_DIO_S) #define SPI_MEM_USR_SRAM_DIO_V 0x00000001U #define SPI_MEM_USR_SRAM_DIO_S 1 -/** SPI_MEM_USR_SRAM_QIO : HRO; bitpos: [2]; default: 0; +/** SPI_MEM_USR_SRAM_QIO : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -663,7 +671,7 @@ extern "C" { #define SPI_MEM_USR_SRAM_QIO_M (SPI_MEM_USR_SRAM_QIO_V << SPI_MEM_USR_SRAM_QIO_S) #define SPI_MEM_USR_SRAM_QIO_V 0x00000001U #define SPI_MEM_USR_SRAM_QIO_S 2 -/** SPI_MEM_USR_WR_SRAM_DUMMY : HRO; bitpos: [3]; default: 0; +/** SPI_MEM_USR_WR_SRAM_DUMMY : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. * This field is only for internal debugging purposes. Do not use it in applications. @@ -672,7 +680,7 @@ extern "C" { #define SPI_MEM_USR_WR_SRAM_DUMMY_M (SPI_MEM_USR_WR_SRAM_DUMMY_V << SPI_MEM_USR_WR_SRAM_DUMMY_S) #define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x00000001U #define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 -/** SPI_MEM_USR_RD_SRAM_DUMMY : HRO; bitpos: [4]; default: 1; +/** SPI_MEM_USR_RD_SRAM_DUMMY : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. * This field is only for internal debugging purposes. Do not use it in applications. @@ -681,7 +689,7 @@ extern "C" { #define SPI_MEM_USR_RD_SRAM_DUMMY_M (SPI_MEM_USR_RD_SRAM_DUMMY_V << SPI_MEM_USR_RD_SRAM_DUMMY_S) #define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x00000001U #define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 -/** SPI_MEM_CACHE_SRAM_USR_RCMD : HRO; bitpos: [5]; default: 1; +/** SPI_MEM_CACHE_SRAM_USR_RCMD : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -689,7 +697,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_RCMD_M (SPI_MEM_CACHE_SRAM_USR_RCMD_V << SPI_MEM_CACHE_SRAM_USR_RCMD_S) #define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x00000001U #define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 -/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : HRO; bitpos: [11:6]; default: 1; +/** SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -698,7 +706,7 @@ extern "C" { #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M (SPI_MEM_SRAM_RDUMMY_CYCLELEN_V << SPI_MEM_SRAM_RDUMMY_CYCLELEN_S) #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x0000003FU #define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 -/** SPI_MEM_SRAM_ADDR_BITLEN : HRO; bitpos: [19:14]; default: 23; +/** SPI_MEM_SRAM_ADDR_BITLEN : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -707,7 +715,7 @@ extern "C" { #define SPI_MEM_SRAM_ADDR_BITLEN_M (SPI_MEM_SRAM_ADDR_BITLEN_V << SPI_MEM_SRAM_ADDR_BITLEN_S) #define SPI_MEM_SRAM_ADDR_BITLEN_V 0x0000003FU #define SPI_MEM_SRAM_ADDR_BITLEN_S 14 -/** SPI_MEM_CACHE_SRAM_USR_WCMD : HRO; bitpos: [20]; default: 1; +/** SPI_MEM_CACHE_SRAM_USR_WCMD : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -715,7 +723,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_WCMD_M (SPI_MEM_CACHE_SRAM_USR_WCMD_V << SPI_MEM_CACHE_SRAM_USR_WCMD_S) #define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x00000001U #define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 -/** SPI_MEM_SRAM_OCT : HRO; bitpos: [21]; default: 0; +/** SPI_MEM_SRAM_OCT : R/W; bitpos: [21]; default: 0; * reserved * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -723,7 +731,7 @@ extern "C" { #define SPI_MEM_SRAM_OCT_M (SPI_MEM_SRAM_OCT_V << SPI_MEM_SRAM_OCT_S) #define SPI_MEM_SRAM_OCT_V 0x00000001U #define SPI_MEM_SRAM_OCT_S 21 -/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : HRO; bitpos: [27:22]; default: 1; +/** SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -737,7 +745,7 @@ extern "C" { * SPI0 external RAM mode control register */ #define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) -/** SPI_MEM_SCLK_MODE : HRO; bitpos: [1:0]; default: 0; +/** SPI_MEM_SCLK_MODE : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. @@ -747,7 +755,7 @@ extern "C" { #define SPI_MEM_SCLK_MODE_M (SPI_MEM_SCLK_MODE_V << SPI_MEM_SCLK_MODE_S) #define SPI_MEM_SCLK_MODE_V 0x00000003U #define SPI_MEM_SCLK_MODE_S 0 -/** SPI_MEM_SWB_MODE : HRO; bitpos: [9:2]; default: 0; +/** SPI_MEM_SWB_MODE : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with * spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. @@ -756,7 +764,7 @@ extern "C" { #define SPI_MEM_SWB_MODE_M (SPI_MEM_SWB_MODE_V << SPI_MEM_SWB_MODE_S) #define SPI_MEM_SWB_MODE_V 0x000000FFU #define SPI_MEM_SWB_MODE_S 2 -/** SPI_MEM_SDIN_DUAL : HRO; bitpos: [10]; default: 0; +/** SPI_MEM_SDIN_DUAL : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -765,7 +773,7 @@ extern "C" { #define SPI_MEM_SDIN_DUAL_M (SPI_MEM_SDIN_DUAL_V << SPI_MEM_SDIN_DUAL_S) #define SPI_MEM_SDIN_DUAL_V 0x00000001U #define SPI_MEM_SDIN_DUAL_S 10 -/** SPI_MEM_SDOUT_DUAL : HRO; bitpos: [11]; default: 0; +/** SPI_MEM_SDOUT_DUAL : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -774,7 +782,7 @@ extern "C" { #define SPI_MEM_SDOUT_DUAL_M (SPI_MEM_SDOUT_DUAL_V << SPI_MEM_SDOUT_DUAL_S) #define SPI_MEM_SDOUT_DUAL_V 0x00000001U #define SPI_MEM_SDOUT_DUAL_S 11 -/** SPI_MEM_SADDR_DUAL : HRO; bitpos: [12]; default: 0; +/** SPI_MEM_SADDR_DUAL : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -783,7 +791,7 @@ extern "C" { #define SPI_MEM_SADDR_DUAL_M (SPI_MEM_SADDR_DUAL_V << SPI_MEM_SADDR_DUAL_S) #define SPI_MEM_SADDR_DUAL_V 0x00000001U #define SPI_MEM_SADDR_DUAL_S 12 -/** SPI_MEM_SDIN_QUAD : HRO; bitpos: [14]; default: 0; +/** SPI_MEM_SDIN_QUAD : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -792,7 +800,7 @@ extern "C" { #define SPI_MEM_SDIN_QUAD_M (SPI_MEM_SDIN_QUAD_V << SPI_MEM_SDIN_QUAD_S) #define SPI_MEM_SDIN_QUAD_V 0x00000001U #define SPI_MEM_SDIN_QUAD_S 14 -/** SPI_MEM_SDOUT_QUAD : HRO; bitpos: [15]; default: 0; +/** SPI_MEM_SDOUT_QUAD : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit * is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -801,7 +809,7 @@ extern "C" { #define SPI_MEM_SDOUT_QUAD_M (SPI_MEM_SDOUT_QUAD_V << SPI_MEM_SDOUT_QUAD_S) #define SPI_MEM_SDOUT_QUAD_V 0x00000001U #define SPI_MEM_SDOUT_QUAD_S 15 -/** SPI_MEM_SADDR_QUAD : HRO; bitpos: [16]; default: 0; +/** SPI_MEM_SADDR_QUAD : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The * bit is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -810,7 +818,7 @@ extern "C" { #define SPI_MEM_SADDR_QUAD_M (SPI_MEM_SADDR_QUAD_V << SPI_MEM_SADDR_QUAD_S) #define SPI_MEM_SADDR_QUAD_V 0x00000001U #define SPI_MEM_SADDR_QUAD_S 16 -/** SPI_MEM_SCMD_QUAD : HRO; bitpos: [17]; default: 0; +/** SPI_MEM_SCMD_QUAD : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. @@ -819,7 +827,7 @@ extern "C" { #define SPI_MEM_SCMD_QUAD_M (SPI_MEM_SCMD_QUAD_V << SPI_MEM_SCMD_QUAD_S) #define SPI_MEM_SCMD_QUAD_V 0x00000001U #define SPI_MEM_SCMD_QUAD_S 17 -/** SPI_MEM_SDIN_OCT : HRO; bitpos: [18]; default: 0; +/** SPI_MEM_SDIN_OCT : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -827,7 +835,7 @@ extern "C" { #define SPI_MEM_SDIN_OCT_M (SPI_MEM_SDIN_OCT_V << SPI_MEM_SDIN_OCT_S) #define SPI_MEM_SDIN_OCT_V 0x00000001U #define SPI_MEM_SDIN_OCT_S 18 -/** SPI_MEM_SDOUT_OCT : HRO; bitpos: [19]; default: 0; +/** SPI_MEM_SDOUT_OCT : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -835,7 +843,7 @@ extern "C" { #define SPI_MEM_SDOUT_OCT_M (SPI_MEM_SDOUT_OCT_V << SPI_MEM_SDOUT_OCT_S) #define SPI_MEM_SDOUT_OCT_V 0x00000001U #define SPI_MEM_SDOUT_OCT_S 19 -/** SPI_MEM_SADDR_OCT : HRO; bitpos: [20]; default: 0; +/** SPI_MEM_SADDR_OCT : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -843,7 +851,7 @@ extern "C" { #define SPI_MEM_SADDR_OCT_M (SPI_MEM_SADDR_OCT_V << SPI_MEM_SADDR_OCT_S) #define SPI_MEM_SADDR_OCT_V 0x00000001U #define SPI_MEM_SADDR_OCT_S 20 -/** SPI_MEM_SCMD_OCT : HRO; bitpos: [21]; default: 0; +/** SPI_MEM_SCMD_OCT : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -860,7 +868,7 @@ extern "C" { #define SPI_MEM_SDUMMY_RIN_M (SPI_MEM_SDUMMY_RIN_V << SPI_MEM_SDUMMY_RIN_S) #define SPI_MEM_SDUMMY_RIN_V 0x00000001U #define SPI_MEM_SDUMMY_RIN_S 22 -/** SPI_MEM_SDUMMY_WOUT : HRO; bitpos: [23]; default: 0; +/** SPI_MEM_SDUMMY_WOUT : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. * This field is only for internal debugging purposes. Do not use it in applications. @@ -869,7 +877,7 @@ extern "C" { #define SPI_MEM_SDUMMY_WOUT_M (SPI_MEM_SDUMMY_WOUT_V << SPI_MEM_SDUMMY_WOUT_S) #define SPI_MEM_SDUMMY_WOUT_V 0x00000001U #define SPI_MEM_SDUMMY_WOUT_S 23 -/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : HRO; bitpos: [24]; default: 0; +/** SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. */ @@ -877,7 +885,7 @@ extern "C" { #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S) #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_V 0x00000001U #define SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_S 24 -/** SPI_SMEM_WDUMMY_ALWAYS_OUT : HRO; bitpos: [25]; default: 0; +/** SPI_SMEM_WDUMMY_ALWAYS_OUT : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_IO[7:0] is output by the MSPI controller. */ @@ -885,7 +893,7 @@ extern "C" { #define SPI_SMEM_WDUMMY_ALWAYS_OUT_M (SPI_SMEM_WDUMMY_ALWAYS_OUT_V << SPI_SMEM_WDUMMY_ALWAYS_OUT_S) #define SPI_SMEM_WDUMMY_ALWAYS_OUT_V 0x00000001U #define SPI_SMEM_WDUMMY_ALWAYS_OUT_S 25 -/** SPI_SMEM_DQS_IE_ALWAYS_ON : HRO; bitpos: [30]; default: 1; +/** SPI_SMEM_DQS_IE_ALWAYS_ON : R/W; bitpos: [30]; default: 0; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ @@ -893,7 +901,7 @@ extern "C" { #define SPI_SMEM_DQS_IE_ALWAYS_ON_M (SPI_SMEM_DQS_IE_ALWAYS_ON_V << SPI_SMEM_DQS_IE_ALWAYS_ON_S) #define SPI_SMEM_DQS_IE_ALWAYS_ON_V 0x00000001U #define SPI_SMEM_DQS_IE_ALWAYS_ON_S 30 -/** SPI_SMEM_DATA_IE_ALWAYS_ON : HRO; bitpos: [31]; default: 1; +/** SPI_SMEM_DATA_IE_ALWAYS_ON : R/W; bitpos: [31]; default: 1; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ @@ -908,7 +916,7 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. @@ -917,7 +925,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S) #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0x0000FFFFU #define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -933,7 +941,7 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4c) -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : HRO; bitpos: [15:0]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. @@ -942,7 +950,7 @@ extern "C" { #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V << SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S) #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0x0000FFFFU #define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 -/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : HRO; bitpos: [31:28]; default: 0; +/** SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -958,32 +966,32 @@ extern "C" { * applications. */ #define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) -/** SPI_MEM_SCLKCNT_L : HRO; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N. +/** SPI_MEM_SCLKCNT_L : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_L 0x000000FFU #define SPI_MEM_SCLKCNT_L_M (SPI_MEM_SCLKCNT_L_V << SPI_MEM_SCLKCNT_L_S) #define SPI_MEM_SCLKCNT_L_V 0x000000FFU #define SPI_MEM_SCLKCNT_L_S 0 -/** SPI_MEM_SCLKCNT_H : HRO; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1). +/** SPI_MEM_SCLKCNT_H : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_H 0x000000FFU #define SPI_MEM_SCLKCNT_H_M (SPI_MEM_SCLKCNT_H_V << SPI_MEM_SCLKCNT_H_S) #define SPI_MEM_SCLKCNT_H_V 0x000000FFU #define SPI_MEM_SCLKCNT_H_S 8 -/** SPI_MEM_SCLKCNT_N : HRO; bitpos: [23:16]; default: 3; +/** SPI_MEM_SCLKCNT_N : R/W; bitpos: [23:16]; default: 3; * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk - * frequency is system/(spi_mem_clkcnt_N+1) + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ #define SPI_MEM_SCLKCNT_N 0x000000FFU #define SPI_MEM_SCLKCNT_N_M (SPI_MEM_SCLKCNT_N_V << SPI_MEM_SCLKCNT_N_S) #define SPI_MEM_SCLKCNT_N_V 0x000000FFU #define SPI_MEM_SCLKCNT_N_S 16 -/** SPI_MEM_SCLK_EQU_SYSCLK : HRO; bitpos: [31]; default: 0; +/** SPI_MEM_SCLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 0; * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. * This field is only for internal debugging purposes. Do not use it in applications. @@ -997,13 +1005,27 @@ extern "C" { * SPI0 FSM status register */ #define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) -/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [11:7]; default: 4; +/** SPI_MEM_LOCK_DELAY_TIME : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ -#define SPI_MEM_LOCK_DELAY_TIME 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_M (SPI_MEM_LOCK_DELAY_TIME_V << SPI_MEM_LOCK_DELAY_TIME_S) -#define SPI_MEM_LOCK_DELAY_TIME_V 0x0000001FU +#define SPI_MEM_LOCK_DELAY_TIME_V 0x00000FFFU #define SPI_MEM_LOCK_DELAY_TIME_S 7 +/** SPI_MEM_FLASH_LOCK_EN : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_FLASH_LOCK_EN (BIT(19)) +#define SPI_MEM_FLASH_LOCK_EN_M (SPI_MEM_FLASH_LOCK_EN_V << SPI_MEM_FLASH_LOCK_EN_S) +#define SPI_MEM_FLASH_LOCK_EN_V 0x00000001U +#define SPI_MEM_FLASH_LOCK_EN_S 19 +/** SPI_MEM_SRAM_LOCK_EN : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ +#define SPI_MEM_SRAM_LOCK_EN (BIT(20)) +#define SPI_MEM_SRAM_LOCK_EN_M (SPI_MEM_SRAM_LOCK_EN_V << SPI_MEM_SRAM_LOCK_EN_S) +#define SPI_MEM_SRAM_LOCK_EN_V 0x00000001U +#define SPI_MEM_SRAM_LOCK_EN_S 20 /** SPI_MEM_INT_ENA_REG register * SPI0 interrupt enable register @@ -1023,7 +1045,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_ENA_M (SPI_MEM_MST_ST_END_INT_ENA_V << SPI_MEM_MST_ST_END_INT_ENA_S) #define SPI_MEM_MST_ST_END_INT_ENA_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_ENA_S 4 -/** SPI_MEM_ECC_ERR_INT_ENA : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_ENA (BIT(5)) @@ -1044,20 +1066,48 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_M (SPI_MEM_AXI_RADDR_ERR_INT_ENA_V << SPI_MEM_AXI_RADDR_ERR_INT_ENA_S) #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_ENA_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA : R/W; bitpos: [8]; default: 0; * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ENA_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT__ENA : R/W; bitpos: [9]; default: 0; * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT__ENA (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_M (SPI_MEM_AXI_WADDR_ERR_INT__ENA_V << SPI_MEM_AXI_WADDR_ERR_INT__ENA_S) #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT__ENA_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ENA : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ENA_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ENA : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ENA_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ENA : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ENA_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ENA : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_M (SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V << SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ENA_S 31 /** SPI_MEM_INT_CLR_REG register * SPI0 interrupt clear register @@ -1077,7 +1127,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_CLR_M (SPI_MEM_MST_ST_END_INT_CLR_V << SPI_MEM_MST_ST_END_INT_CLR_S) #define SPI_MEM_MST_ST_END_INT_CLR_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_CLR_S 4 -/** SPI_MEM_ECC_ERR_INT_CLR : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_CLR : WT; bitpos: [5]; default: 0; * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_CLR (BIT(5)) @@ -1098,20 +1148,48 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_M (SPI_MEM_AXI_RADDR_ERR_INT_CLR_V << SPI_MEM_AXI_RADDR_ERR_INT_CLR_S) #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_CLR_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR : WT; bitpos: [8]; default: 0; * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_CLR_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_CLR : WT; bitpos: [9]; default: 0; * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT_CLR (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_M (SPI_MEM_AXI_WADDR_ERR_INT_CLR_V << SPI_MEM_AXI_WADDR_ERR_INT_CLR_S) #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_CLR_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_CLR : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_CLR_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_CLR : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_M (SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V << SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_CLR_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_CLR : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_CLR_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_CLR : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_M (SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V << SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_CLR_S 31 /** SPI_MEM_INT_RAW_REG register * SPI0 interrupt raw register @@ -1134,7 +1212,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_RAW_M (SPI_MEM_MST_ST_END_INT_RAW_V << SPI_MEM_MST_ST_END_INT_RAW_S) #define SPI_MEM_MST_ST_END_INT_RAW_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_RAW_S 4 -/** SPI_MEM_ECC_ERR_INT_RAW : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When @@ -1166,7 +1244,7 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_M (SPI_MEM_AXI_RADDR_ERR_INT_RAW_V << SPI_MEM_AXI_RADDR_ERR_INT_RAW_S) #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_RAW_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ @@ -1174,7 +1252,7 @@ extern "C" { #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_RAW_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ @@ -1182,6 +1260,38 @@ extern "C" { #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_M (SPI_MEM_AXI_WADDR_ERR_INT_RAW_V << SPI_MEM_AXI_WADDR_ERR_INT_RAW_S) #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_RAW_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_RAW_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_M (SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V << SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_RAW_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_RAW_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_M (SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V << SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_RAW_S 31 /** SPI_MEM_INT_ST_REG register * SPI0 interrupt status register @@ -1201,7 +1311,7 @@ extern "C" { #define SPI_MEM_MST_ST_END_INT_ST_M (SPI_MEM_MST_ST_END_INT_ST_V << SPI_MEM_MST_ST_END_INT_ST_S) #define SPI_MEM_MST_ST_END_INT_ST_V 0x00000001U #define SPI_MEM_MST_ST_END_INT_ST_S 4 -/** SPI_MEM_ECC_ERR_INT_ST : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_ECC_ERR_INT_ST : RO; bitpos: [5]; default: 0; * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_MEM_ECC_ERR_INT_ST (BIT(5)) @@ -1222,68 +1332,96 @@ extern "C" { #define SPI_MEM_AXI_RADDR_ERR_INT_ST_M (SPI_MEM_AXI_RADDR_ERR_INT_ST_V << SPI_MEM_AXI_RADDR_ERR_INT_ST_S) #define SPI_MEM_AXI_RADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_RADDR_ERR_INT_ST_S 7 -/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : HRO; bitpos: [8]; default: 0; +/** SPI_MEM_AXI_WR_FLASH_ERR_INT_ST : RO; bitpos: [8]; default: 0; * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST (BIT(8)) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_M (SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V << SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S) #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_WR_FLASH_ERR_INT_ST_S 8 -/** SPI_MEM_AXI_WADDR_ERR_INT_ST : HRO; bitpos: [9]; default: 0; +/** SPI_MEM_AXI_WADDR_ERR_INT_ST : RO; bitpos: [9]; default: 0; * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ #define SPI_MEM_AXI_WADDR_ERR_INT_ST (BIT(9)) #define SPI_MEM_AXI_WADDR_ERR_INT_ST_M (SPI_MEM_AXI_WADDR_ERR_INT_ST_V << SPI_MEM_AXI_WADDR_ERR_INT_ST_S) #define SPI_MEM_AXI_WADDR_ERR_INT_ST_V 0x00000001U #define SPI_MEM_AXI_WADDR_ERR_INT_ST_S 9 +/** SPI_MEM_DQS0_AFIFO_OVF_INT_ST : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST (BIT(28)) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS0_AFIFO_OVF_INT_ST_S 28 +/** SPI_MEM_DQS1_AFIFO_OVF_INT_ST : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST (BIT(29)) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_M (SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V << SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S) +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_V 0x00000001U +#define SPI_MEM_DQS1_AFIFO_OVF_INT_ST_S 29 +/** SPI_MEM_BUS_FIFO1_UDF_INT_ST : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST (BIT(30)) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_M (SPI_MEM_BUS_FIFO1_UDF_INT_ST_V << SPI_MEM_BUS_FIFO1_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO1_UDF_INT_ST_S 30 +/** SPI_MEM_BUS_FIFO0_UDF_INT_ST : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST (BIT(31)) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_M (SPI_MEM_BUS_FIFO0_UDF_INT_ST_V << SPI_MEM_BUS_FIFO0_UDF_INT_ST_S) +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_V 0x00000001U +#define SPI_MEM_BUS_FIFO0_UDF_INT_ST_S 31 /** SPI_MEM_DDR_REG register * SPI0 flash DDR mode control register */ #define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd4) -/** SPI_FMEM_DDR_EN : HRO; bitpos: [0]; default: 0; +/** SPI_FMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ #define SPI_FMEM_DDR_EN (BIT(0)) #define SPI_FMEM_DDR_EN_M (SPI_FMEM_DDR_EN_V << SPI_FMEM_DDR_EN_S) #define SPI_FMEM_DDR_EN_V 0x00000001U #define SPI_FMEM_DDR_EN_S 0 -/** SPI_FMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; +/** SPI_FMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ #define SPI_FMEM_VAR_DUMMY (BIT(1)) #define SPI_FMEM_VAR_DUMMY_M (SPI_FMEM_VAR_DUMMY_V << SPI_FMEM_VAR_DUMMY_S) #define SPI_FMEM_VAR_DUMMY_V 0x00000001U #define SPI_FMEM_VAR_DUMMY_S 1 -/** SPI_FMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; +/** SPI_FMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ #define SPI_FMEM_DDR_RDAT_SWP (BIT(2)) #define SPI_FMEM_DDR_RDAT_SWP_M (SPI_FMEM_DDR_RDAT_SWP_V << SPI_FMEM_DDR_RDAT_SWP_S) #define SPI_FMEM_DDR_RDAT_SWP_V 0x00000001U #define SPI_FMEM_DDR_RDAT_SWP_S 2 -/** SPI_FMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; +/** SPI_FMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ #define SPI_FMEM_DDR_WDAT_SWP (BIT(3)) #define SPI_FMEM_DDR_WDAT_SWP_M (SPI_FMEM_DDR_WDAT_SWP_V << SPI_FMEM_DDR_WDAT_SWP_S) #define SPI_FMEM_DDR_WDAT_SWP_V 0x00000001U #define SPI_FMEM_DDR_WDAT_SWP_S 3 -/** SPI_FMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; +/** SPI_FMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ #define SPI_FMEM_DDR_CMD_DIS (BIT(4)) #define SPI_FMEM_DDR_CMD_DIS_M (SPI_FMEM_DDR_CMD_DIS_V << SPI_FMEM_DDR_CMD_DIS_S) #define SPI_FMEM_DDR_CMD_DIS_V 0x00000001U #define SPI_FMEM_DDR_CMD_DIS_S 4 -/** SPI_FMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; +/** SPI_FMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ #define SPI_FMEM_OUTMINBYTELEN 0x0000007FU #define SPI_FMEM_OUTMINBYTELEN_M (SPI_FMEM_OUTMINBYTELEN_V << SPI_FMEM_OUTMINBYTELEN_S) #define SPI_FMEM_OUTMINBYTELEN_V 0x0000007FU #define SPI_FMEM_OUTMINBYTELEN_S 5 -/** SPI_FMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; +/** SPI_FMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to flash. */ @@ -1291,7 +1429,7 @@ extern "C" { #define SPI_FMEM_TX_DDR_MSK_EN_M (SPI_FMEM_TX_DDR_MSK_EN_V << SPI_FMEM_TX_DDR_MSK_EN_S) #define SPI_FMEM_TX_DDR_MSK_EN_V 0x00000001U #define SPI_FMEM_TX_DDR_MSK_EN_S 12 -/** SPI_FMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; +/** SPI_FMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to flash. */ @@ -1299,14 +1437,14 @@ extern "C" { #define SPI_FMEM_RX_DDR_MSK_EN_M (SPI_FMEM_RX_DDR_MSK_EN_V << SPI_FMEM_RX_DDR_MSK_EN_S) #define SPI_FMEM_RX_DDR_MSK_EN_V 0x00000001U #define SPI_FMEM_RX_DDR_MSK_EN_S 13 -/** SPI_FMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; +/** SPI_FMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ #define SPI_FMEM_USR_DDR_DQS_THD 0x0000007FU #define SPI_FMEM_USR_DDR_DQS_THD_M (SPI_FMEM_USR_DDR_DQS_THD_V << SPI_FMEM_USR_DDR_DQS_THD_S) #define SPI_FMEM_USR_DDR_DQS_THD_V 0x0000007FU #define SPI_FMEM_USR_DDR_DQS_THD_S 14 -/** SPI_FMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; +/** SPI_FMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and @@ -1316,21 +1454,21 @@ extern "C" { #define SPI_FMEM_DDR_DQS_LOOP_M (SPI_FMEM_DDR_DQS_LOOP_V << SPI_FMEM_DDR_DQS_LOOP_S) #define SPI_FMEM_DDR_DQS_LOOP_V 0x00000001U #define SPI_FMEM_DDR_DQS_LOOP_S 21 -/** SPI_FMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; +/** SPI_FMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ #define SPI_FMEM_CLK_DIFF_EN (BIT(24)) #define SPI_FMEM_CLK_DIFF_EN_M (SPI_FMEM_CLK_DIFF_EN_V << SPI_FMEM_CLK_DIFF_EN_S) #define SPI_FMEM_CLK_DIFF_EN_V 0x00000001U #define SPI_FMEM_CLK_DIFF_EN_S 24 -/** SPI_FMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; +/** SPI_FMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ #define SPI_FMEM_DQS_CA_IN (BIT(26)) #define SPI_FMEM_DQS_CA_IN_M (SPI_FMEM_DQS_CA_IN_V << SPI_FMEM_DQS_CA_IN_S) #define SPI_FMEM_DQS_CA_IN_V 0x00000001U #define SPI_FMEM_DQS_CA_IN_S 26 -/** SPI_FMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; +/** SPI_FMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ @@ -1338,14 +1476,14 @@ extern "C" { #define SPI_FMEM_HYPERBUS_DUMMY_2X_M (SPI_FMEM_HYPERBUS_DUMMY_2X_V << SPI_FMEM_HYPERBUS_DUMMY_2X_S) #define SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x00000001U #define SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_FMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; +/** SPI_FMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ #define SPI_FMEM_CLK_DIFF_INV (BIT(28)) #define SPI_FMEM_CLK_DIFF_INV_M (SPI_FMEM_CLK_DIFF_INV_V << SPI_FMEM_CLK_DIFF_INV_S) #define SPI_FMEM_CLK_DIFF_INV_V 0x00000001U #define SPI_FMEM_CLK_DIFF_INV_S 28 -/** SPI_FMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; +/** SPI_FMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ @@ -1353,7 +1491,7 @@ extern "C" { #define SPI_FMEM_OCTA_RAM_ADDR_M (SPI_FMEM_OCTA_RAM_ADDR_V << SPI_FMEM_OCTA_RAM_ADDR_S) #define SPI_FMEM_OCTA_RAM_ADDR_V 0x00000001U #define SPI_FMEM_OCTA_RAM_ADDR_S 29 -/** SPI_FMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; +/** SPI_FMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -1366,49 +1504,49 @@ extern "C" { * SPI0 external RAM DDR mode control register */ #define SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xd8) -/** SPI_SMEM_DDR_EN : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_DDR_EN : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ #define SPI_SMEM_DDR_EN (BIT(0)) #define SPI_SMEM_DDR_EN_M (SPI_SMEM_DDR_EN_V << SPI_SMEM_DDR_EN_S) #define SPI_SMEM_DDR_EN_V 0x00000001U #define SPI_SMEM_DDR_EN_S 0 -/** SPI_SMEM_VAR_DUMMY : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_VAR_DUMMY : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ #define SPI_SMEM_VAR_DUMMY (BIT(1)) #define SPI_SMEM_VAR_DUMMY_M (SPI_SMEM_VAR_DUMMY_V << SPI_SMEM_VAR_DUMMY_S) #define SPI_SMEM_VAR_DUMMY_V 0x00000001U #define SPI_SMEM_VAR_DUMMY_S 1 -/** SPI_SMEM_DDR_RDAT_SWP : HRO; bitpos: [2]; default: 0; +/** SPI_SMEM_DDR_RDAT_SWP : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ #define SPI_SMEM_DDR_RDAT_SWP (BIT(2)) #define SPI_SMEM_DDR_RDAT_SWP_M (SPI_SMEM_DDR_RDAT_SWP_V << SPI_SMEM_DDR_RDAT_SWP_S) #define SPI_SMEM_DDR_RDAT_SWP_V 0x00000001U #define SPI_SMEM_DDR_RDAT_SWP_S 2 -/** SPI_SMEM_DDR_WDAT_SWP : HRO; bitpos: [3]; default: 0; +/** SPI_SMEM_DDR_WDAT_SWP : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ #define SPI_SMEM_DDR_WDAT_SWP (BIT(3)) #define SPI_SMEM_DDR_WDAT_SWP_M (SPI_SMEM_DDR_WDAT_SWP_V << SPI_SMEM_DDR_WDAT_SWP_S) #define SPI_SMEM_DDR_WDAT_SWP_V 0x00000001U #define SPI_SMEM_DDR_WDAT_SWP_S 3 -/** SPI_SMEM_DDR_CMD_DIS : HRO; bitpos: [4]; default: 0; +/** SPI_SMEM_DDR_CMD_DIS : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ #define SPI_SMEM_DDR_CMD_DIS (BIT(4)) #define SPI_SMEM_DDR_CMD_DIS_M (SPI_SMEM_DDR_CMD_DIS_V << SPI_SMEM_DDR_CMD_DIS_S) #define SPI_SMEM_DDR_CMD_DIS_V 0x00000001U #define SPI_SMEM_DDR_CMD_DIS_S 4 -/** SPI_SMEM_OUTMINBYTELEN : HRO; bitpos: [11:5]; default: 1; +/** SPI_SMEM_OUTMINBYTELEN : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the DDR psram. */ #define SPI_SMEM_OUTMINBYTELEN 0x0000007FU #define SPI_SMEM_OUTMINBYTELEN_M (SPI_SMEM_OUTMINBYTELEN_V << SPI_SMEM_OUTMINBYTELEN_S) #define SPI_SMEM_OUTMINBYTELEN_V 0x0000007FU #define SPI_SMEM_OUTMINBYTELEN_S 5 -/** SPI_SMEM_TX_DDR_MSK_EN : HRO; bitpos: [12]; default: 1; +/** SPI_SMEM_TX_DDR_MSK_EN : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to external RAM. */ @@ -1416,7 +1554,7 @@ extern "C" { #define SPI_SMEM_TX_DDR_MSK_EN_M (SPI_SMEM_TX_DDR_MSK_EN_V << SPI_SMEM_TX_DDR_MSK_EN_S) #define SPI_SMEM_TX_DDR_MSK_EN_V 0x00000001U #define SPI_SMEM_TX_DDR_MSK_EN_S 12 -/** SPI_SMEM_RX_DDR_MSK_EN : HRO; bitpos: [13]; default: 1; +/** SPI_SMEM_RX_DDR_MSK_EN : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to external RAM. */ @@ -1424,14 +1562,14 @@ extern "C" { #define SPI_SMEM_RX_DDR_MSK_EN_M (SPI_SMEM_RX_DDR_MSK_EN_V << SPI_SMEM_RX_DDR_MSK_EN_S) #define SPI_SMEM_RX_DDR_MSK_EN_V 0x00000001U #define SPI_SMEM_RX_DDR_MSK_EN_S 13 -/** SPI_SMEM_USR_DDR_DQS_THD : HRO; bitpos: [20:14]; default: 0; +/** SPI_SMEM_USR_DDR_DQS_THD : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ #define SPI_SMEM_USR_DDR_DQS_THD 0x0000007FU #define SPI_SMEM_USR_DDR_DQS_THD_M (SPI_SMEM_USR_DDR_DQS_THD_V << SPI_SMEM_USR_DDR_DQS_THD_S) #define SPI_SMEM_USR_DDR_DQS_THD_V 0x0000007FU #define SPI_SMEM_USR_DDR_DQS_THD_S 14 -/** SPI_SMEM_DDR_DQS_LOOP : HRO; bitpos: [21]; default: 0; +/** SPI_SMEM_DDR_DQS_LOOP : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and @@ -1441,21 +1579,21 @@ extern "C" { #define SPI_SMEM_DDR_DQS_LOOP_M (SPI_SMEM_DDR_DQS_LOOP_V << SPI_SMEM_DDR_DQS_LOOP_S) #define SPI_SMEM_DDR_DQS_LOOP_V 0x00000001U #define SPI_SMEM_DDR_DQS_LOOP_S 21 -/** SPI_SMEM_CLK_DIFF_EN : HRO; bitpos: [24]; default: 0; +/** SPI_SMEM_CLK_DIFF_EN : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ #define SPI_SMEM_CLK_DIFF_EN (BIT(24)) #define SPI_SMEM_CLK_DIFF_EN_M (SPI_SMEM_CLK_DIFF_EN_V << SPI_SMEM_CLK_DIFF_EN_S) #define SPI_SMEM_CLK_DIFF_EN_V 0x00000001U #define SPI_SMEM_CLK_DIFF_EN_S 24 -/** SPI_SMEM_DQS_CA_IN : HRO; bitpos: [26]; default: 0; +/** SPI_SMEM_DQS_CA_IN : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ #define SPI_SMEM_DQS_CA_IN (BIT(26)) #define SPI_SMEM_DQS_CA_IN_M (SPI_SMEM_DQS_CA_IN_V << SPI_SMEM_DQS_CA_IN_S) #define SPI_SMEM_DQS_CA_IN_V 0x00000001U #define SPI_SMEM_DQS_CA_IN_S 26 -/** SPI_SMEM_HYPERBUS_DUMMY_2X : HRO; bitpos: [27]; default: 0; +/** SPI_SMEM_HYPERBUS_DUMMY_2X : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ @@ -1463,14 +1601,14 @@ extern "C" { #define SPI_SMEM_HYPERBUS_DUMMY_2X_M (SPI_SMEM_HYPERBUS_DUMMY_2X_V << SPI_SMEM_HYPERBUS_DUMMY_2X_S) #define SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x00000001U #define SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 -/** SPI_SMEM_CLK_DIFF_INV : HRO; bitpos: [28]; default: 0; +/** SPI_SMEM_CLK_DIFF_INV : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to external RAM. . */ #define SPI_SMEM_CLK_DIFF_INV (BIT(28)) #define SPI_SMEM_CLK_DIFF_INV_M (SPI_SMEM_CLK_DIFF_INV_V << SPI_SMEM_CLK_DIFF_INV_S) #define SPI_SMEM_CLK_DIFF_INV_V 0x00000001U #define SPI_SMEM_CLK_DIFF_INV_S 28 -/** SPI_SMEM_OCTA_RAM_ADDR : HRO; bitpos: [29]; default: 0; +/** SPI_SMEM_OCTA_RAM_ADDR : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], * 1'b0}. @@ -1479,7 +1617,7 @@ extern "C" { #define SPI_SMEM_OCTA_RAM_ADDR_M (SPI_SMEM_OCTA_RAM_ADDR_V << SPI_SMEM_OCTA_RAM_ADDR_S) #define SPI_SMEM_OCTA_RAM_ADDR_V 0x00000001U #define SPI_SMEM_OCTA_RAM_ADDR_S 29 -/** SPI_SMEM_HYPERBUS_CA : HRO; bitpos: [30]; default: 0; +/** SPI_SMEM_HYPERBUS_CA : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -1604,100 +1742,100 @@ extern "C" { * SPI1 flash PMS section 0 start address register */ #define SPI_FMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x110) -/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 0 start address value */ -#define SPI_FMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS0_ADDR_S_M (SPI_FMEM_PMS0_ADDR_S_V << SPI_FMEM_PMS0_ADDR_S_S) -#define SPI_FMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS0_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS0_ADDR_S_S 0 /** SPI_FMEM_PMS1_ADDR_REG register * SPI1 flash PMS section 1 start address register */ #define SPI_FMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x114) -/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 1 start address value */ -#define SPI_FMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS1_ADDR_S_M (SPI_FMEM_PMS1_ADDR_S_V << SPI_FMEM_PMS1_ADDR_S_S) -#define SPI_FMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS1_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS1_ADDR_S_S 0 /** SPI_FMEM_PMS2_ADDR_REG register * SPI1 flash PMS section 2 start address register */ #define SPI_FMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x118) -/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 2 start address value */ -#define SPI_FMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS2_ADDR_S_M (SPI_FMEM_PMS2_ADDR_S_V << SPI_FMEM_PMS2_ADDR_S_S) -#define SPI_FMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS2_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS2_ADDR_S_S 0 /** SPI_FMEM_PMS3_ADDR_REG register * SPI1 flash PMS section 3 start address register */ #define SPI_FMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x11c) -/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_FMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section 3 start address value */ -#define SPI_FMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S 0x1FFFFFFFU #define SPI_FMEM_PMS3_ADDR_S_M (SPI_FMEM_PMS3_ADDR_S_V << SPI_FMEM_PMS3_ADDR_S_S) -#define SPI_FMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_FMEM_PMS3_ADDR_S_V 0x1FFFFFFFU #define SPI_FMEM_PMS3_ADDR_S_S 0 /** SPI_FMEM_PMS0_SIZE_REG register * SPI1 flash PMS section 0 start address register */ #define SPI_FMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x120) -/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 0 address region is (SPI_FMEM_PMS0_ADDR_S, * SPI_FMEM_PMS0_ADDR_S + SPI_FMEM_PMS0_SIZE) */ -#define SPI_FMEM_PMS0_SIZE 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE 0x0001FFFFU #define SPI_FMEM_PMS0_SIZE_M (SPI_FMEM_PMS0_SIZE_V << SPI_FMEM_PMS0_SIZE_S) -#define SPI_FMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS0_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS0_SIZE_S 0 /** SPI_FMEM_PMS1_SIZE_REG register * SPI1 flash PMS section 1 start address register */ #define SPI_FMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x124) -/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 1 address region is (SPI_FMEM_PMS1_ADDR_S, * SPI_FMEM_PMS1_ADDR_S + SPI_FMEM_PMS1_SIZE) */ -#define SPI_FMEM_PMS1_SIZE 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE 0x0001FFFFU #define SPI_FMEM_PMS1_SIZE_M (SPI_FMEM_PMS1_SIZE_V << SPI_FMEM_PMS1_SIZE_S) -#define SPI_FMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS1_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS1_SIZE_S 0 /** SPI_FMEM_PMS2_SIZE_REG register * SPI1 flash PMS section 2 start address register */ #define SPI_FMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x128) -/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 2 address region is (SPI_FMEM_PMS2_ADDR_S, * SPI_FMEM_PMS2_ADDR_S + SPI_FMEM_PMS2_SIZE) */ -#define SPI_FMEM_PMS2_SIZE 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE 0x0001FFFFU #define SPI_FMEM_PMS2_SIZE_M (SPI_FMEM_PMS2_SIZE_V << SPI_FMEM_PMS2_SIZE_S) -#define SPI_FMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS2_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS2_SIZE_S 0 /** SPI_FMEM_PMS3_SIZE_REG register * SPI1 flash PMS section 3 start address register */ #define SPI_FMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x12c) -/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_FMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section 3 address region is (SPI_FMEM_PMS3_ADDR_S, * SPI_FMEM_PMS3_ADDR_S + SPI_FMEM_PMS3_SIZE) */ -#define SPI_FMEM_PMS3_SIZE 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE 0x0001FFFFU #define SPI_FMEM_PMS3_SIZE_M (SPI_FMEM_PMS3_SIZE_V << SPI_FMEM_PMS3_SIZE_S) -#define SPI_FMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_FMEM_PMS3_SIZE_V 0x0001FFFFU #define SPI_FMEM_PMS3_SIZE_S 0 /** SPI_SMEM_PMS0_ATTR_REG register @@ -1816,114 +1954,106 @@ extern "C" { * SPI1 external RAM PMS section 0 start address register */ #define SPI_SMEM_PMS0_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x140) -/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS0_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 0 start address value */ -#define SPI_SMEM_PMS0_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS0_ADDR_S_M (SPI_SMEM_PMS0_ADDR_S_V << SPI_SMEM_PMS0_ADDR_S_S) -#define SPI_SMEM_PMS0_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS0_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS0_ADDR_S_S 0 /** SPI_SMEM_PMS1_ADDR_REG register * SPI1 external RAM PMS section 1 start address register */ #define SPI_SMEM_PMS1_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x144) -/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS1_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 1 start address value */ -#define SPI_SMEM_PMS1_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS1_ADDR_S_M (SPI_SMEM_PMS1_ADDR_S_V << SPI_SMEM_PMS1_ADDR_S_S) -#define SPI_SMEM_PMS1_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS1_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS1_ADDR_S_S 0 /** SPI_SMEM_PMS2_ADDR_REG register * SPI1 external RAM PMS section 2 start address register */ #define SPI_SMEM_PMS2_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x148) -/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS2_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 2 start address value */ -#define SPI_SMEM_PMS2_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS2_ADDR_S_M (SPI_SMEM_PMS2_ADDR_S_V << SPI_SMEM_PMS2_ADDR_S_S) -#define SPI_SMEM_PMS2_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS2_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS2_ADDR_S_S 0 /** SPI_SMEM_PMS3_ADDR_REG register * SPI1 external RAM PMS section 3 start address register */ #define SPI_SMEM_PMS3_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x14c) -/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [26:0]; default: 0; +/** SPI_SMEM_PMS3_ADDR_S : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section 3 start address value */ -#define SPI_SMEM_PMS3_ADDR_S 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S 0x1FFFFFFFU #define SPI_SMEM_PMS3_ADDR_S_M (SPI_SMEM_PMS3_ADDR_S_V << SPI_SMEM_PMS3_ADDR_S_S) -#define SPI_SMEM_PMS3_ADDR_S_V 0x07FFFFFFU +#define SPI_SMEM_PMS3_ADDR_S_V 0x1FFFFFFFU #define SPI_SMEM_PMS3_ADDR_S_S 0 /** SPI_SMEM_PMS0_SIZE_REG register * SPI1 external RAM PMS section 0 start address register */ #define SPI_SMEM_PMS0_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x150) -/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS0_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 0 address region is (SPI_SMEM_PMS0_ADDR_S, * SPI_SMEM_PMS0_ADDR_S + SPI_SMEM_PMS0_SIZE) */ -#define SPI_SMEM_PMS0_SIZE 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE 0x0001FFFFU #define SPI_SMEM_PMS0_SIZE_M (SPI_SMEM_PMS0_SIZE_V << SPI_SMEM_PMS0_SIZE_S) -#define SPI_SMEM_PMS0_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS0_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS0_SIZE_S 0 /** SPI_SMEM_PMS1_SIZE_REG register * SPI1 external RAM PMS section 1 start address register */ #define SPI_SMEM_PMS1_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x154) -/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS1_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 1 address region is (SPI_SMEM_PMS1_ADDR_S, * SPI_SMEM_PMS1_ADDR_S + SPI_SMEM_PMS1_SIZE) */ -#define SPI_SMEM_PMS1_SIZE 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE 0x0001FFFFU #define SPI_SMEM_PMS1_SIZE_M (SPI_SMEM_PMS1_SIZE_V << SPI_SMEM_PMS1_SIZE_S) -#define SPI_SMEM_PMS1_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS1_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS1_SIZE_S 0 /** SPI_SMEM_PMS2_SIZE_REG register * SPI1 external RAM PMS section 2 start address register */ #define SPI_SMEM_PMS2_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x158) -/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS2_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 2 address region is (SPI_SMEM_PMS2_ADDR_S, * SPI_SMEM_PMS2_ADDR_S + SPI_SMEM_PMS2_SIZE) */ -#define SPI_SMEM_PMS2_SIZE 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE 0x0001FFFFU #define SPI_SMEM_PMS2_SIZE_M (SPI_SMEM_PMS2_SIZE_V << SPI_SMEM_PMS2_SIZE_S) -#define SPI_SMEM_PMS2_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS2_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS2_SIZE_S 0 /** SPI_SMEM_PMS3_SIZE_REG register * SPI1 external RAM PMS section 3 start address register */ #define SPI_SMEM_PMS3_SIZE_REG(i) (REG_SPI_MEM_BASE(i) + 0x15c) -/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [14:0]; default: 4096; +/** SPI_SMEM_PMS3_SIZE : R/W; bitpos: [16:0]; default: 4096; * SPI1 external RAM PMS section 3 address region is (SPI_SMEM_PMS3_ADDR_S, * SPI_SMEM_PMS3_ADDR_S + SPI_SMEM_PMS3_SIZE) */ -#define SPI_SMEM_PMS3_SIZE 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE 0x0001FFFFU #define SPI_SMEM_PMS3_SIZE_M (SPI_SMEM_PMS3_SIZE_V << SPI_SMEM_PMS3_SIZE_S) -#define SPI_SMEM_PMS3_SIZE_V 0x00007FFFU +#define SPI_SMEM_PMS3_SIZE_V 0x0001FFFFU #define SPI_SMEM_PMS3_SIZE_S 0 /** SPI_MEM_PMS_REJECT_REG register * SPI1 access reject register */ -#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) -/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * SPI_MEM_PMS_REJECT_INT_CLR bit is set. - */ -#define SPI_MEM_REJECT_ADDR 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) -#define SPI_MEM_REJECT_ADDR_V 0x07FFFFFFU -#define SPI_MEM_REJECT_ADDR_S 0 +#define SPI_MEM_PMS_REJECT_REG(i) (REG_SPI_MEM_BASE(i) + 0x160) /** SPI_MEM_PM_EN : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ @@ -1964,11 +2094,24 @@ extern "C" { #define SPI_MEM_PMS_IVD_V 0x00000001U #define SPI_MEM_PMS_IVD_S 31 +/** SPI_MEM_PMS_REJECT_ADDR_REG register + * SPI1 access reject addr register + */ +#define SPI_MEM_PMS_REJECT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x164) +/** SPI_MEM_REJECT_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ +#define SPI_MEM_REJECT_ADDR 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_M (SPI_MEM_REJECT_ADDR_V << SPI_MEM_REJECT_ADDR_S) +#define SPI_MEM_REJECT_ADDR_V 0x1FFFFFFFU +#define SPI_MEM_REJECT_ADDR_S 0 + /** SPI_MEM_ECC_CTRL_REG register * MSPI ECC control register */ #define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x168) -/** SPI_MEM_ECC_ERR_CNT : HRO; bitpos: [10:5]; default: 0; +/** SPI_MEM_ECC_ERR_CNT : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ @@ -1976,14 +2119,14 @@ extern "C" { #define SPI_MEM_ECC_ERR_CNT_M (SPI_MEM_ECC_ERR_CNT_V << SPI_MEM_ECC_ERR_CNT_S) #define SPI_MEM_ECC_ERR_CNT_V 0x0000003FU #define SPI_MEM_ECC_ERR_CNT_S 5 -/** SPI_FMEM_ECC_ERR_INT_NUM : HRO; bitpos: [16:11]; default: 10; +/** SPI_FMEM_ECC_ERR_INT_NUM : R/W; bitpos: [16:11]; default: 10; * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ #define SPI_FMEM_ECC_ERR_INT_NUM 0x0000003FU #define SPI_FMEM_ECC_ERR_INT_NUM_M (SPI_FMEM_ECC_ERR_INT_NUM_V << SPI_FMEM_ECC_ERR_INT_NUM_S) #define SPI_FMEM_ECC_ERR_INT_NUM_V 0x0000003FU #define SPI_FMEM_ECC_ERR_INT_NUM_S 11 -/** SPI_FMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; +/** SPI_FMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. */ #define SPI_FMEM_ECC_ERR_INT_EN (BIT(17)) @@ -1998,23 +2141,23 @@ extern "C" { #define SPI_FMEM_PAGE_SIZE_M (SPI_FMEM_PAGE_SIZE_V << SPI_FMEM_PAGE_SIZE_S) #define SPI_FMEM_PAGE_SIZE_V 0x00000003U #define SPI_FMEM_PAGE_SIZE_S 18 -/** SPI_FMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; +/** SPI_FMEM_ECC_ADDR_EN : R/W; bitpos: [21]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit * should be 0. Otherwise, this bit should be 1. */ -#define SPI_FMEM_ECC_ADDR_EN (BIT(20)) +#define SPI_FMEM_ECC_ADDR_EN (BIT(21)) #define SPI_FMEM_ECC_ADDR_EN_M (SPI_FMEM_ECC_ADDR_EN_V << SPI_FMEM_ECC_ADDR_EN_S) #define SPI_FMEM_ECC_ADDR_EN_V 0x00000001U -#define SPI_FMEM_ECC_ADDR_EN_S 20 -/** SPI_MEM_USR_ECC_ADDR_EN : HRO; bitpos: [21]; default: 0; +#define SPI_FMEM_ECC_ADDR_EN_S 21 +/** SPI_MEM_USR_ECC_ADDR_EN : R/W; bitpos: [22]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ -#define SPI_MEM_USR_ECC_ADDR_EN (BIT(21)) +#define SPI_MEM_USR_ECC_ADDR_EN (BIT(22)) #define SPI_MEM_USR_ECC_ADDR_EN_M (SPI_MEM_USR_ECC_ADDR_EN_V << SPI_MEM_USR_ECC_ADDR_EN_S) #define SPI_MEM_USR_ECC_ADDR_EN_V 0x00000001U -#define SPI_MEM_USR_ECC_ADDR_EN_S 21 -/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : HRO; bitpos: [24]; default: 1; +#define SPI_MEM_USR_ECC_ADDR_EN_S 22 +/** SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN : R/W; bitpos: [24]; default: 1; * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. @@ -2023,7 +2166,7 @@ extern "C" { #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_M (SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V << SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S) #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_V 0x00000001U #define SPI_MEM_ECC_CONTINUE_RECORD_ERR_EN_S 24 -/** SPI_MEM_ECC_ERR_BITS : HRO; bitpos: [31:25]; default: 0; +/** SPI_MEM_ECC_ERR_BITS : R/SS/WTC; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ @@ -2036,34 +2179,34 @@ extern "C" { * MSPI ECC error address register */ #define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x16c) -/** SPI_MEM_ECC_ERR_ADDR : HRO; bitpos: [26:0]; default: 0; +/** SPI_MEM_ECC_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ -#define SPI_MEM_ECC_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR 0x1FFFFFFFU #define SPI_MEM_ECC_ERR_ADDR_M (SPI_MEM_ECC_ERR_ADDR_V << SPI_MEM_ECC_ERR_ADDR_S) -#define SPI_MEM_ECC_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_ECC_ERR_ADDR_V 0x1FFFFFFFU #define SPI_MEM_ECC_ERR_ADDR_S 0 /** SPI_MEM_AXI_ERR_ADDR_REG register * SPI0 AXI request error address. */ #define SPI_MEM_AXI_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x170) -/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [26:0]; default: 0; +/** SPI_MEM_AXI_ERR_ADDR : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ -#define SPI_MEM_AXI_ERR_ADDR 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR 0x1FFFFFFFU #define SPI_MEM_AXI_ERR_ADDR_M (SPI_MEM_AXI_ERR_ADDR_V << SPI_MEM_AXI_ERR_ADDR_S) -#define SPI_MEM_AXI_ERR_ADDR_V 0x07FFFFFFU +#define SPI_MEM_AXI_ERR_ADDR_V 0x1FFFFFFFU #define SPI_MEM_AXI_ERR_ADDR_S 0 /** SPI_SMEM_ECC_CTRL_REG register * MSPI ECC control register */ #define SPI_SMEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x174) -/** SPI_SMEM_ECC_ERR_INT_EN : HRO; bitpos: [17]; default: 0; +/** SPI_SMEM_ECC_ERR_INT_EN : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. */ @@ -2071,7 +2214,7 @@ extern "C" { #define SPI_SMEM_ECC_ERR_INT_EN_M (SPI_SMEM_ECC_ERR_INT_EN_V << SPI_SMEM_ECC_ERR_INT_EN_S) #define SPI_SMEM_ECC_ERR_INT_EN_V 0x00000001U #define SPI_SMEM_ECC_ERR_INT_EN_S 17 -/** SPI_SMEM_PAGE_SIZE : HRO; bitpos: [19:18]; default: 2; +/** SPI_SMEM_PAGE_SIZE : R/W; bitpos: [19:18]; default: 2; * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. * 2: 1024 bytes. 3: 2048 bytes. */ @@ -2079,7 +2222,7 @@ extern "C" { #define SPI_SMEM_PAGE_SIZE_M (SPI_SMEM_PAGE_SIZE_V << SPI_SMEM_PAGE_SIZE_S) #define SPI_SMEM_PAGE_SIZE_V 0x00000003U #define SPI_SMEM_PAGE_SIZE_S 18 -/** SPI_SMEM_ECC_ADDR_EN : HRO; bitpos: [20]; default: 0; +/** SPI_SMEM_ECC_ADDR_EN : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of external RAM. If there is no ECC region in external * RAM, this bit should be 0. Otherwise, this bit should be 1. @@ -2142,49 +2285,49 @@ extern "C" { * SPI0 AXI error response enable register */ #define SPI_MEM_AXI_ERR_RESP_EN_REG(i) (REG_SPI_MEM_BASE(i) + 0x17c) -/** SPI_MEM_AW_RESP_EN_MMU_VLD : HRO; bitpos: [0]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_VLD : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_VLD (BIT(0)) #define SPI_MEM_AW_RESP_EN_MMU_VLD_M (SPI_MEM_AW_RESP_EN_MMU_VLD_V << SPI_MEM_AW_RESP_EN_MMU_VLD_S) #define SPI_MEM_AW_RESP_EN_MMU_VLD_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_VLD_S 0 -/** SPI_MEM_AW_RESP_EN_MMU_GID : HRO; bitpos: [1]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_GID : R/W; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_GID (BIT(1)) #define SPI_MEM_AW_RESP_EN_MMU_GID_M (SPI_MEM_AW_RESP_EN_MMU_GID_V << SPI_MEM_AW_RESP_EN_MMU_GID_S) #define SPI_MEM_AW_RESP_EN_MMU_GID_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_GID_S 1 -/** SPI_MEM_AW_RESP_EN_AXI_SIZE : HRO; bitpos: [2]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_SIZE : R/W; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_SIZE (BIT(2)) #define SPI_MEM_AW_RESP_EN_AXI_SIZE_M (SPI_MEM_AW_RESP_EN_AXI_SIZE_V << SPI_MEM_AW_RESP_EN_AXI_SIZE_S) #define SPI_MEM_AW_RESP_EN_AXI_SIZE_V 0x00000001U #define SPI_MEM_AW_RESP_EN_AXI_SIZE_S 2 -/** SPI_MEM_AW_RESP_EN_AXI_FLASH : HRO; bitpos: [3]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_FLASH : R/W; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_FLASH (BIT(3)) #define SPI_MEM_AW_RESP_EN_AXI_FLASH_M (SPI_MEM_AW_RESP_EN_AXI_FLASH_V << SPI_MEM_AW_RESP_EN_AXI_FLASH_S) #define SPI_MEM_AW_RESP_EN_AXI_FLASH_V 0x00000001U #define SPI_MEM_AW_RESP_EN_AXI_FLASH_S 3 -/** SPI_MEM_AW_RESP_EN_MMU_ECC : HRO; bitpos: [4]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_ECC : R/W; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_ECC (BIT(4)) #define SPI_MEM_AW_RESP_EN_MMU_ECC_M (SPI_MEM_AW_RESP_EN_MMU_ECC_V << SPI_MEM_AW_RESP_EN_MMU_ECC_S) #define SPI_MEM_AW_RESP_EN_MMU_ECC_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_ECC_S 4 -/** SPI_MEM_AW_RESP_EN_MMU_SENS : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_AW_RESP_EN_MMU_SENS : R/W; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ #define SPI_MEM_AW_RESP_EN_MMU_SENS (BIT(5)) #define SPI_MEM_AW_RESP_EN_MMU_SENS_M (SPI_MEM_AW_RESP_EN_MMU_SENS_V << SPI_MEM_AW_RESP_EN_MMU_SENS_S) #define SPI_MEM_AW_RESP_EN_MMU_SENS_V 0x00000001U #define SPI_MEM_AW_RESP_EN_MMU_SENS_S 5 -/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : HRO; bitpos: [6]; default: 0; +/** SPI_MEM_AW_RESP_EN_AXI_WSTRB : R/W; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ #define SPI_MEM_AW_RESP_EN_AXI_WSTRB (BIT(6)) @@ -2253,7 +2396,7 @@ extern "C" { #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M (SPI_MEM_EXTRA_DUMMY_CYCLELEN_V << SPI_MEM_EXTRA_DUMMY_CYCLELEN_S) #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U #define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_MEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; +/** SPI_MEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ @@ -2530,14 +2673,14 @@ extern "C" { * MSPI external RAM timing calibration register */ #define SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x190) -/** SPI_SMEM_TIMING_CLK_ENA : HRO; bitpos: [0]; default: 1; +/** SPI_SMEM_TIMING_CLK_ENA : R/W; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ #define SPI_SMEM_TIMING_CLK_ENA (BIT(0)) #define SPI_SMEM_TIMING_CLK_ENA_M (SPI_SMEM_TIMING_CLK_ENA_V << SPI_SMEM_TIMING_CLK_ENA_S) #define SPI_SMEM_TIMING_CLK_ENA_V 0x00000001U #define SPI_SMEM_TIMING_CLK_ENA_S 0 -/** SPI_SMEM_TIMING_CALI : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_TIMING_CALI : R/W; bitpos: [1]; default: 0; * For sram, the bit is used to enable timing auto-calibration for all reading * operations. */ @@ -2545,14 +2688,14 @@ extern "C" { #define SPI_SMEM_TIMING_CALI_M (SPI_SMEM_TIMING_CALI_V << SPI_SMEM_TIMING_CALI_S) #define SPI_SMEM_TIMING_CALI_V 0x00000001U #define SPI_SMEM_TIMING_CALI_S 1 -/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : HRO; bitpos: [4:2]; default: 0; +/** SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W; bitpos: [4:2]; default: 0; * For sram, add extra dummy spi clock cycle length for spi clock calibration. */ #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007U #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M (SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V << SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S) #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x00000007U #define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 -/** SPI_SMEM_DLL_TIMING_CALI : HRO; bitpos: [5]; default: 0; +/** SPI_SMEM_DLL_TIMING_CALI : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * EXT_RAM. */ @@ -2560,12 +2703,28 @@ extern "C" { #define SPI_SMEM_DLL_TIMING_CALI_M (SPI_SMEM_DLL_TIMING_CALI_V << SPI_SMEM_DLL_TIMING_CALI_S) #define SPI_SMEM_DLL_TIMING_CALI_V 0x00000001U #define SPI_SMEM_DLL_TIMING_CALI_S 5 +/** SPI_SMEM_DQS0_270_SEL : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_270_SEL 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_M (SPI_SMEM_DQS0_270_SEL_V << SPI_SMEM_DQS0_270_SEL_S) +#define SPI_SMEM_DQS0_270_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_270_SEL_S 7 +/** SPI_SMEM_DQS0_90_SEL : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ +#define SPI_SMEM_DQS0_90_SEL 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_M (SPI_SMEM_DQS0_90_SEL_V << SPI_SMEM_DQS0_90_SEL_S) +#define SPI_SMEM_DQS0_90_SEL_V 0x00000003U +#define SPI_SMEM_DQS0_90_SEL_S 9 /** SPI_SMEM_DIN_MODE_REG register * MSPI external RAM input timing delay mode control register */ #define SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x194) -/** SPI_SMEM_DIN0_MODE : HRO; bitpos: [2:0]; default: 0; +/** SPI_SMEM_DIN0_MODE : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2575,7 +2734,7 @@ extern "C" { #define SPI_SMEM_DIN0_MODE_M (SPI_SMEM_DIN0_MODE_V << SPI_SMEM_DIN0_MODE_S) #define SPI_SMEM_DIN0_MODE_V 0x00000007U #define SPI_SMEM_DIN0_MODE_S 0 -/** SPI_SMEM_DIN1_MODE : HRO; bitpos: [5:3]; default: 0; +/** SPI_SMEM_DIN1_MODE : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2585,7 +2744,7 @@ extern "C" { #define SPI_SMEM_DIN1_MODE_M (SPI_SMEM_DIN1_MODE_V << SPI_SMEM_DIN1_MODE_S) #define SPI_SMEM_DIN1_MODE_V 0x00000007U #define SPI_SMEM_DIN1_MODE_S 3 -/** SPI_SMEM_DIN2_MODE : HRO; bitpos: [8:6]; default: 0; +/** SPI_SMEM_DIN2_MODE : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2595,7 +2754,7 @@ extern "C" { #define SPI_SMEM_DIN2_MODE_M (SPI_SMEM_DIN2_MODE_V << SPI_SMEM_DIN2_MODE_S) #define SPI_SMEM_DIN2_MODE_V 0x00000007U #define SPI_SMEM_DIN2_MODE_S 6 -/** SPI_SMEM_DIN3_MODE : HRO; bitpos: [11:9]; default: 0; +/** SPI_SMEM_DIN3_MODE : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2605,7 +2764,7 @@ extern "C" { #define SPI_SMEM_DIN3_MODE_M (SPI_SMEM_DIN3_MODE_V << SPI_SMEM_DIN3_MODE_S) #define SPI_SMEM_DIN3_MODE_V 0x00000007U #define SPI_SMEM_DIN3_MODE_S 9 -/** SPI_SMEM_DIN4_MODE : HRO; bitpos: [14:12]; default: 0; +/** SPI_SMEM_DIN4_MODE : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2615,7 +2774,7 @@ extern "C" { #define SPI_SMEM_DIN4_MODE_M (SPI_SMEM_DIN4_MODE_V << SPI_SMEM_DIN4_MODE_S) #define SPI_SMEM_DIN4_MODE_V 0x00000007U #define SPI_SMEM_DIN4_MODE_S 12 -/** SPI_SMEM_DIN5_MODE : HRO; bitpos: [17:15]; default: 0; +/** SPI_SMEM_DIN5_MODE : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2625,7 +2784,7 @@ extern "C" { #define SPI_SMEM_DIN5_MODE_M (SPI_SMEM_DIN5_MODE_V << SPI_SMEM_DIN5_MODE_S) #define SPI_SMEM_DIN5_MODE_V 0x00000007U #define SPI_SMEM_DIN5_MODE_S 15 -/** SPI_SMEM_DIN6_MODE : HRO; bitpos: [20:18]; default: 0; +/** SPI_SMEM_DIN6_MODE : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2635,7 +2794,7 @@ extern "C" { #define SPI_SMEM_DIN6_MODE_M (SPI_SMEM_DIN6_MODE_V << SPI_SMEM_DIN6_MODE_S) #define SPI_SMEM_DIN6_MODE_V 0x00000007U #define SPI_SMEM_DIN6_MODE_S 18 -/** SPI_SMEM_DIN7_MODE : HRO; bitpos: [23:21]; default: 0; +/** SPI_SMEM_DIN7_MODE : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2645,7 +2804,7 @@ extern "C" { #define SPI_SMEM_DIN7_MODE_M (SPI_SMEM_DIN7_MODE_V << SPI_SMEM_DIN7_MODE_S) #define SPI_SMEM_DIN7_MODE_V 0x00000007U #define SPI_SMEM_DIN7_MODE_S 21 -/** SPI_SMEM_DINS_MODE : HRO; bitpos: [26:24]; default: 0; +/** SPI_SMEM_DINS_MODE : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -2660,7 +2819,7 @@ extern "C" { * MSPI external RAM input timing delay number control register */ #define SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x198) -/** SPI_SMEM_DIN0_NUM : HRO; bitpos: [1:0]; default: 0; +/** SPI_SMEM_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2668,7 +2827,7 @@ extern "C" { #define SPI_SMEM_DIN0_NUM_M (SPI_SMEM_DIN0_NUM_V << SPI_SMEM_DIN0_NUM_S) #define SPI_SMEM_DIN0_NUM_V 0x00000003U #define SPI_SMEM_DIN0_NUM_S 0 -/** SPI_SMEM_DIN1_NUM : HRO; bitpos: [3:2]; default: 0; +/** SPI_SMEM_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2676,7 +2835,7 @@ extern "C" { #define SPI_SMEM_DIN1_NUM_M (SPI_SMEM_DIN1_NUM_V << SPI_SMEM_DIN1_NUM_S) #define SPI_SMEM_DIN1_NUM_V 0x00000003U #define SPI_SMEM_DIN1_NUM_S 2 -/** SPI_SMEM_DIN2_NUM : HRO; bitpos: [5:4]; default: 0; +/** SPI_SMEM_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2684,7 +2843,7 @@ extern "C" { #define SPI_SMEM_DIN2_NUM_M (SPI_SMEM_DIN2_NUM_V << SPI_SMEM_DIN2_NUM_S) #define SPI_SMEM_DIN2_NUM_V 0x00000003U #define SPI_SMEM_DIN2_NUM_S 4 -/** SPI_SMEM_DIN3_NUM : HRO; bitpos: [7:6]; default: 0; +/** SPI_SMEM_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2692,7 +2851,7 @@ extern "C" { #define SPI_SMEM_DIN3_NUM_M (SPI_SMEM_DIN3_NUM_V << SPI_SMEM_DIN3_NUM_S) #define SPI_SMEM_DIN3_NUM_V 0x00000003U #define SPI_SMEM_DIN3_NUM_S 6 -/** SPI_SMEM_DIN4_NUM : HRO; bitpos: [9:8]; default: 0; +/** SPI_SMEM_DIN4_NUM : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2700,7 +2859,7 @@ extern "C" { #define SPI_SMEM_DIN4_NUM_M (SPI_SMEM_DIN4_NUM_V << SPI_SMEM_DIN4_NUM_S) #define SPI_SMEM_DIN4_NUM_V 0x00000003U #define SPI_SMEM_DIN4_NUM_S 8 -/** SPI_SMEM_DIN5_NUM : HRO; bitpos: [11:10]; default: 0; +/** SPI_SMEM_DIN5_NUM : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2708,7 +2867,7 @@ extern "C" { #define SPI_SMEM_DIN5_NUM_M (SPI_SMEM_DIN5_NUM_V << SPI_SMEM_DIN5_NUM_S) #define SPI_SMEM_DIN5_NUM_V 0x00000003U #define SPI_SMEM_DIN5_NUM_S 10 -/** SPI_SMEM_DIN6_NUM : HRO; bitpos: [13:12]; default: 0; +/** SPI_SMEM_DIN6_NUM : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2716,7 +2875,7 @@ extern "C" { #define SPI_SMEM_DIN6_NUM_M (SPI_SMEM_DIN6_NUM_V << SPI_SMEM_DIN6_NUM_S) #define SPI_SMEM_DIN6_NUM_V 0x00000003U #define SPI_SMEM_DIN6_NUM_S 12 -/** SPI_SMEM_DIN7_NUM : HRO; bitpos: [15:14]; default: 0; +/** SPI_SMEM_DIN7_NUM : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2724,7 +2883,7 @@ extern "C" { #define SPI_SMEM_DIN7_NUM_M (SPI_SMEM_DIN7_NUM_V << SPI_SMEM_DIN7_NUM_S) #define SPI_SMEM_DIN7_NUM_V 0x00000003U #define SPI_SMEM_DIN7_NUM_S 14 -/** SPI_SMEM_DINS_NUM : HRO; bitpos: [17:16]; default: 0; +/** SPI_SMEM_DINS_NUM : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -2737,7 +2896,7 @@ extern "C" { * MSPI external RAM output timing adjustment control register */ #define SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x19c) -/** SPI_SMEM_DOUT0_MODE : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_DOUT0_MODE : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2747,7 +2906,7 @@ extern "C" { #define SPI_SMEM_DOUT0_MODE_M (SPI_SMEM_DOUT0_MODE_V << SPI_SMEM_DOUT0_MODE_S) #define SPI_SMEM_DOUT0_MODE_V 0x00000001U #define SPI_SMEM_DOUT0_MODE_S 0 -/** SPI_SMEM_DOUT1_MODE : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_DOUT1_MODE : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2757,7 +2916,7 @@ extern "C" { #define SPI_SMEM_DOUT1_MODE_M (SPI_SMEM_DOUT1_MODE_V << SPI_SMEM_DOUT1_MODE_S) #define SPI_SMEM_DOUT1_MODE_V 0x00000001U #define SPI_SMEM_DOUT1_MODE_S 1 -/** SPI_SMEM_DOUT2_MODE : HRO; bitpos: [2]; default: 0; +/** SPI_SMEM_DOUT2_MODE : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2767,7 +2926,7 @@ extern "C" { #define SPI_SMEM_DOUT2_MODE_M (SPI_SMEM_DOUT2_MODE_V << SPI_SMEM_DOUT2_MODE_S) #define SPI_SMEM_DOUT2_MODE_V 0x00000001U #define SPI_SMEM_DOUT2_MODE_S 2 -/** SPI_SMEM_DOUT3_MODE : HRO; bitpos: [3]; default: 0; +/** SPI_SMEM_DOUT3_MODE : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2777,7 +2936,7 @@ extern "C" { #define SPI_SMEM_DOUT3_MODE_M (SPI_SMEM_DOUT3_MODE_V << SPI_SMEM_DOUT3_MODE_S) #define SPI_SMEM_DOUT3_MODE_V 0x00000001U #define SPI_SMEM_DOUT3_MODE_S 3 -/** SPI_SMEM_DOUT4_MODE : HRO; bitpos: [4]; default: 0; +/** SPI_SMEM_DOUT4_MODE : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2787,7 +2946,7 @@ extern "C" { #define SPI_SMEM_DOUT4_MODE_M (SPI_SMEM_DOUT4_MODE_V << SPI_SMEM_DOUT4_MODE_S) #define SPI_SMEM_DOUT4_MODE_V 0x00000001U #define SPI_SMEM_DOUT4_MODE_S 4 -/** SPI_SMEM_DOUT5_MODE : HRO; bitpos: [5]; default: 0; +/** SPI_SMEM_DOUT5_MODE : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2797,7 +2956,7 @@ extern "C" { #define SPI_SMEM_DOUT5_MODE_M (SPI_SMEM_DOUT5_MODE_V << SPI_SMEM_DOUT5_MODE_S) #define SPI_SMEM_DOUT5_MODE_V 0x00000001U #define SPI_SMEM_DOUT5_MODE_S 5 -/** SPI_SMEM_DOUT6_MODE : HRO; bitpos: [6]; default: 0; +/** SPI_SMEM_DOUT6_MODE : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2807,7 +2966,7 @@ extern "C" { #define SPI_SMEM_DOUT6_MODE_M (SPI_SMEM_DOUT6_MODE_V << SPI_SMEM_DOUT6_MODE_S) #define SPI_SMEM_DOUT6_MODE_V 0x00000001U #define SPI_SMEM_DOUT6_MODE_S 6 -/** SPI_SMEM_DOUT7_MODE : HRO; bitpos: [7]; default: 0; +/** SPI_SMEM_DOUT7_MODE : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2817,7 +2976,7 @@ extern "C" { #define SPI_SMEM_DOUT7_MODE_M (SPI_SMEM_DOUT7_MODE_V << SPI_SMEM_DOUT7_MODE_S) #define SPI_SMEM_DOUT7_MODE_V 0x00000001U #define SPI_SMEM_DOUT7_MODE_S 7 -/** SPI_SMEM_DOUTS_MODE : HRO; bitpos: [8]; default: 0; +/** SPI_SMEM_DOUTS_MODE : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -2832,7 +2991,7 @@ extern "C" { * MSPI external RAM ECC and SPI CS timing control register */ #define SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x1a0) -/** SPI_SMEM_CS_SETUP : HRO; bitpos: [0]; default: 0; +/** SPI_SMEM_CS_SETUP : R/W; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. */ @@ -2840,14 +2999,14 @@ extern "C" { #define SPI_SMEM_CS_SETUP_M (SPI_SMEM_CS_SETUP_V << SPI_SMEM_CS_SETUP_S) #define SPI_SMEM_CS_SETUP_V 0x00000001U #define SPI_SMEM_CS_SETUP_S 0 -/** SPI_SMEM_CS_HOLD : HRO; bitpos: [1]; default: 0; +/** SPI_SMEM_CS_HOLD : R/W; bitpos: [1]; default: 0; * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ #define SPI_SMEM_CS_HOLD (BIT(1)) #define SPI_SMEM_CS_HOLD_M (SPI_SMEM_CS_HOLD_V << SPI_SMEM_CS_HOLD_S) #define SPI_SMEM_CS_HOLD_V 0x00000001U #define SPI_SMEM_CS_HOLD_S 1 -/** SPI_SMEM_CS_SETUP_TIME : HRO; bitpos: [6:2]; default: 1; +/** SPI_SMEM_CS_SETUP_TIME : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with * spi_mem_cs_setup bit. */ @@ -2855,7 +3014,7 @@ extern "C" { #define SPI_SMEM_CS_SETUP_TIME_M (SPI_SMEM_CS_SETUP_TIME_V << SPI_SMEM_CS_SETUP_TIME_S) #define SPI_SMEM_CS_SETUP_TIME_V 0x0000001FU #define SPI_SMEM_CS_SETUP_TIME_S 2 -/** SPI_SMEM_CS_HOLD_TIME : HRO; bitpos: [11:7]; default: 1; +/** SPI_SMEM_CS_HOLD_TIME : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are * combined with spi_mem_cs_hold bit. */ @@ -2863,7 +3022,7 @@ extern "C" { #define SPI_SMEM_CS_HOLD_TIME_M (SPI_SMEM_CS_HOLD_TIME_V << SPI_SMEM_CS_HOLD_TIME_S) #define SPI_SMEM_CS_HOLD_TIME_V 0x0000001FU #define SPI_SMEM_CS_HOLD_TIME_S 7 -/** SPI_SMEM_ECC_CS_HOLD_TIME : HRO; bitpos: [14:12]; default: 3; +/** SPI_SMEM_ECC_CS_HOLD_TIME : R/W; bitpos: [14:12]; default: 3; * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ @@ -2871,7 +3030,7 @@ extern "C" { #define SPI_SMEM_ECC_CS_HOLD_TIME_M (SPI_SMEM_ECC_CS_HOLD_TIME_V << SPI_SMEM_ECC_CS_HOLD_TIME_S) #define SPI_SMEM_ECC_CS_HOLD_TIME_V 0x00000007U #define SPI_SMEM_ECC_CS_HOLD_TIME_S 12 -/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : HRO; bitpos: [15]; default: 1; +/** SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W; bitpos: [15]; default: 1; * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when * accesses external RAM. */ @@ -2879,7 +3038,7 @@ extern "C" { #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (SPI_SMEM_ECC_SKIP_PAGE_CORNER_V << SPI_SMEM_ECC_SKIP_PAGE_CORNER_S) #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x00000001U #define SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 -/** SPI_SMEM_ECC_16TO18_BYTE_EN : HRO; bitpos: [16]; default: 0; +/** SPI_SMEM_ECC_16TO18_BYTE_EN : R/W; bitpos: [16]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses external RAM. */ @@ -2887,7 +3046,7 @@ extern "C" { #define SPI_SMEM_ECC_16TO18_BYTE_EN_M (SPI_SMEM_ECC_16TO18_BYTE_EN_V << SPI_SMEM_ECC_16TO18_BYTE_EN_S) #define SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x00000001U #define SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 -/** SPI_SMEM_CS_HOLD_DELAY : HRO; bitpos: [30:25]; default: 0; +/** SPI_SMEM_CS_HOLD_DELAY : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. @@ -2896,7 +3055,7 @@ extern "C" { #define SPI_SMEM_CS_HOLD_DELAY_M (SPI_SMEM_CS_HOLD_DELAY_V << SPI_SMEM_CS_HOLD_DELAY_S) #define SPI_SMEM_CS_HOLD_DELAY_V 0x0000003FU #define SPI_SMEM_CS_HOLD_DELAY_S 25 -/** SPI_SMEM_SPLIT_TRANS_EN : HRO; bitpos: [31]; default: 0; +/** SPI_SMEM_SPLIT_TRANS_EN : R/W; bitpos: [31]; default: 0; * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter * whether there is an ECC region or not. @@ -3098,14 +3257,14 @@ extern "C" { #define SPI_MMU_PAGE_SIZE_M (SPI_MMU_PAGE_SIZE_V << SPI_MMU_PAGE_SIZE_S) #define SPI_MMU_PAGE_SIZE_V 0x00000003U #define SPI_MMU_PAGE_SIZE_S 3 -/** SPI_MEM_AUX_CTRL : HRO; bitpos: [29:16]; default: 4896; +/** SPI_MEM_AUX_CTRL : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ #define SPI_MEM_AUX_CTRL 0x00003FFFU #define SPI_MEM_AUX_CTRL_M (SPI_MEM_AUX_CTRL_V << SPI_MEM_AUX_CTRL_S) #define SPI_MEM_AUX_CTRL_V 0x00003FFFU #define SPI_MEM_AUX_CTRL_S 16 -/** SPI_MEM_RDN_ENA : HRO; bitpos: [30]; default: 0; +/** SPI_MEM_RDN_ENA : R/W; bitpos: [30]; default: 0; * ECO register enable bit * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3166,21 +3325,28 @@ extern "C" { #define SPI_MEM_MODE_PSEUDO_M (SPI_MEM_MODE_PSEUDO_V << SPI_MEM_MODE_PSEUDO_S) #define SPI_MEM_MODE_PSEUDO_V 0x00000003U #define SPI_MEM_MODE_PSEUDO_S 0 -/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [5:2]; default: 2; +/** SPI_MEM_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ +#define SPI_MEM_PSEUDO_RNG_CNT 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_M (SPI_MEM_PSEUDO_RNG_CNT_V << SPI_MEM_PSEUDO_RNG_CNT_S) +#define SPI_MEM_PSEUDO_RNG_CNT_V 0x00000007U +#define SPI_MEM_PSEUDO_RNG_CNT_S 2 +/** SPI_MEM_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2; * xts aes peseudo function base round that must be performed. */ #define SPI_MEM_PSEUDO_BASE 0x0000000FU #define SPI_MEM_PSEUDO_BASE_M (SPI_MEM_PSEUDO_BASE_V << SPI_MEM_PSEUDO_BASE_S) #define SPI_MEM_PSEUDO_BASE_V 0x0000000FU -#define SPI_MEM_PSEUDO_BASE_S 2 -/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [7:6]; default: 2; +#define SPI_MEM_PSEUDO_BASE_S 5 +/** SPI_MEM_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2; * xts aes peseudo function increment round that will be performed randomly between 0 & * 2**(inc+1). */ #define SPI_MEM_PSEUDO_INC 0x00000003U #define SPI_MEM_PSEUDO_INC_M (SPI_MEM_PSEUDO_INC_V << SPI_MEM_PSEUDO_INC_S) #define SPI_MEM_PSEUDO_INC_V 0x00000003U -#define SPI_MEM_PSEUDO_INC_S 6 +#define SPI_MEM_PSEUDO_INC_S 9 /** SPI_MEM_REGISTERRND_ECO_HIGH_REG register * MSPI ECO high register @@ -3188,7 +3354,7 @@ extern "C" { * applications. */ #define SPI_MEM_REGISTERRND_ECO_HIGH_REG(i) (REG_SPI_MEM_BASE(i) + 0x3f0) -/** SPI_MEM_REGISTERRND_ECO_HIGH : RO; bitpos: [31:0]; default: 892; +/** SPI_MEM_REGISTERRND_ECO_HIGH : R/W; bitpos: [31:0]; default: 892; * ECO high register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3203,7 +3369,7 @@ extern "C" { * applications. */ #define SPI_MEM_REGISTERRND_ECO_LOW_REG(i) (REG_SPI_MEM_BASE(i) + 0x3f4) -/** SPI_MEM_REGISTERRND_ECO_LOW : RO; bitpos: [31:0]; default: 892; +/** SPI_MEM_REGISTERRND_ECO_LOW : R/W; bitpos: [31:0]; default: 892; * ECO low register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -3216,7 +3382,7 @@ extern "C" { * SPI0 version control register */ #define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3fc) -/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 36770128; +/** SPI_MEM_DATE : R/W; bitpos: [27:0]; default: 37823232; * SPI0 register version. */ #define SPI_MEM_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi_mem_c_struct.h b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h index 8fef2bcb1c..7231833aef 100644 --- a/components/soc/esp32c61/register/soc/spi_mem_c_struct.h +++ b/components/soc/esp32c61/register/soc/spi_mem_c_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -30,7 +30,7 @@ typedef union { uint32_t mem_slv_st:4; uint32_t reserved_8:10; /** mem_usr : HRO; bitpos: [18]; default: 0; - * SPI0 USR_CMD start bit, only used when spi_mem_c_AXI_REQ_EN is cleared. An operation + * SPI0 USR_CMD start bit, only used when SPI_MEM_AXI_REQ_EN is cleared. An operation * will be triggered when the bit is set. The bit will be cleared once the operation * done.1: enable 0: disable. */ @@ -45,13 +45,13 @@ typedef union { */ typedef union { struct { - /** mem_axi_err_addr : R/SS/WTC; bitpos: [26:0]; default: 0; + /** mem_axi_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first AXI write/read invalid error or AXI write flash error - * address. It is cleared by when spi_mem_c_AXI_WADDR_ERR_INT_CLR, - * spi_mem_c_AXI_WR_FLASH_ERR_IN_CLR or spi_mem_c_AXI_RADDR_ERR_IN_CLR bit is set. + * address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, + * SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set. */ - uint32_t mem_axi_err_addr:27; - uint32_t reserved_27:5; + uint32_t mem_axi_err_addr:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_mem_c_axi_err_addr_reg_t; @@ -63,7 +63,7 @@ typedef union { */ typedef union { struct { - /** mem_wdummy_dqs_always_out : HRO; bitpos: [0]; default: 0; + /** mem_wdummy_dqs_always_out : R/W; bitpos: [0]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to flash, the level * of SPI_DQS is output by the MSPI controller. */ @@ -85,15 +85,15 @@ typedef union { * pre-drive flash. */ uint32_t mem_fdummy_wout:1; - /** mem_fdout_oct : HRO; bitpos: [4]; default: 0; + /** mem_fdout_oct : R/W; bitpos: [4]; default: 0; * Apply 8 signals during write-data phase 1:enable 0: disable */ uint32_t mem_fdout_oct:1; - /** mem_fdin_oct : HRO; bitpos: [5]; default: 0; + /** mem_fdin_oct : R/W; bitpos: [5]; default: 0; * Apply 8 signals during read-data phase 1:enable 0: disable */ uint32_t mem_fdin_oct:1; - /** mem_faddr_oct : HRO; bitpos: [6]; default: 0; + /** mem_faddr_oct : R/W; bitpos: [6]; default: 0; * Apply 8 signals during address phase 1:enable 0: disable */ uint32_t mem_faddr_oct:1; @@ -102,14 +102,14 @@ typedef union { * Apply 4 signals during command phase 1:enable 0: disable */ uint32_t mem_fcmd_quad:1; - /** mem_fcmd_oct : HRO; bitpos: [9]; default: 0; + /** mem_fcmd_oct : R/W; bitpos: [9]; default: 0; * Apply 8 signals during command phase 1:enable 0: disable */ uint32_t mem_fcmd_oct:1; uint32_t reserved_10:3; /** mem_fastrd_mode : R/W; bitpos: [13]; default: 1; - * This bit enable the bits: spi_mem_c_FREAD_QIO, spi_mem_c_FREAD_DIO, spi_mem_c_FREAD_QOUT - * and spi_mem_c_FREAD_DOUT. 1: enable 0: disable. + * This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT + * and SPI_MEM_FREAD_DOUT. 1: enable 0: disable. */ uint32_t mem_fastrd_mode:1; /** mem_fread_dual : R/W; bitpos: [14]; default: 0; @@ -145,7 +145,7 @@ typedef union { */ uint32_t mem_fread_qio:1; uint32_t reserved_25:5; - /** mem_dqs_ie_always_on : HRO; bitpos: [30]; default: 0; + /** mem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; * When accesses to flash, 1: the IE signals of pads connected to SPI_DQS are always * 1. 0: Others. */ @@ -170,39 +170,34 @@ typedef union { * SPI clock is always on. */ uint32_t mem_clk_mode:2; - uint32_t reserved_2:19; - /** ar_size0_1_support_en : R/W; bitpos: [21]; default: 1; + uint32_t reserved_2:20; + /** ar_size0_1_support_en : R/W; bitpos: [22]; default: 1; * 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply * the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t ar_size0_1_support_en:1; - /** aw_size0_1_support_en : R/W; bitpos: [22]; default: 1; + /** aw_size0_1_support_en : R/W; bitpos: [23]; default: 1; * 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR. */ uint32_t aw_size0_1_support_en:1; - /** axi_rdata_back_fast : HRO; bitpos: [23]; default: 1; - * 1: Reply AXI read data to AXI bus when one AXI read beat data is available. 0: - * Reply AXI read data to AXI bus when all the read data is available. - */ - uint32_t axi_rdata_back_fast:1; /** mem_rresp_ecc_err_en : R/W; bitpos: [24]; default: 0; * 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY * when there is a ECC error in AXI read data. The ECC error information is recorded - * in spi_mem_c_ECC_ERR_ADDR_REG. + * in SPI_MEM_ECC_ERR_ADDR_REG. */ uint32_t mem_rresp_ecc_err_en:1; - /** mem_ar_splice_en : HRO; bitpos: [25]; default: 0; + /** mem_ar_splice_en : R/W; bitpos: [25]; default: 0; * Set this bit to enable AXI Read Splice-transfer. */ uint32_t mem_ar_splice_en:1; - /** mem_aw_splice_en : HRO; bitpos: [26]; default: 0; + /** mem_aw_splice_en : R/W; bitpos: [26]; default: 0; * Set this bit to enable AXI Write Splice-transfer. */ uint32_t mem_aw_splice_en:1; /** mem_ram0_en : HRO; bitpos: [27]; default: 1; - * When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 1, only EXT_RAM0 will be - * accessed. When spi_mem_c_DUAL_RAM_EN is 0 and spi_mem_c_RAM0_EN is 0, only EXT_RAM1 - * will be accessed. When spi_mem_c_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be + * When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 1, only EXT_RAM0 will be + * accessed. When SPI_MEM_DUAL_RAM_EN is 0 and SPI_MEM_RAM0_EN is 0, only EXT_RAM1 + * will be accessed. When SPI_MEM_DUAL_RAM_EN is 1, EXT_RAM0 and EXT_RAM1 will be * accessed at the same time. */ uint32_t mem_ram0_en:1; @@ -238,25 +233,25 @@ typedef union { struct { /** mem_cs_setup_time : R/W; bitpos: [4:0]; default: 1; * (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with - * spi_mem_c_CS_SETUP bit. + * SPI_MEM_CS_SETUP bit. */ uint32_t mem_cs_setup_time:5; /** mem_cs_hold_time : R/W; bitpos: [9:5]; default: 1; * SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with - * spi_mem_c_CS_HOLD bit. + * SPI_MEM_CS_HOLD bit. */ uint32_t mem_cs_hold_time:5; - /** mem_ecc_cs_hold_time : HRO; bitpos: [12:10]; default: 3; - * spi_mem_c_CS_HOLD_TIME + spi_mem_c_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC + /** mem_ecc_cs_hold_time : R/W; bitpos: [12:10]; default: 3; + * SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC * mode when accessed flash. */ uint32_t mem_ecc_cs_hold_time:3; - /** mem_ecc_skip_page_corner : HRO; bitpos: [13]; default: 1; + /** mem_ecc_skip_page_corner : R/W; bitpos: [13]; default: 1; * 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when * accesses flash. */ uint32_t mem_ecc_skip_page_corner:1; - /** mem_ecc_16to18_byte_en : HRO; bitpos: [14]; default: 0; + /** mem_ecc_16to18_byte_en : R/W; bitpos: [14]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses flash. */ @@ -270,7 +265,7 @@ typedef union { uint32_t mem_split_trans_en:1; /** mem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to flash. tSHSL is (spi_mem_c_CS_HOLD_DELAY[5:0] + 1) MSPI + * transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI * core clock cycles. */ uint32_t mem_cs_hold_delay:6; @@ -331,42 +326,42 @@ typedef union { uint32_t mem_cache_flash_usr_cmd:1; /** mem_fdin_dual : R/W; bitpos: [3]; default: 0; * For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_dio. + * same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_dual:1; /** mem_fdout_dual : R/W; bitpos: [4]; default: 0; * For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_dio. + * same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_dual:1; /** mem_faddr_dual : R/W; bitpos: [5]; default: 0; * For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_fread_dio. + * the same with spi_mem_fread_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_dual:1; /** mem_fdin_quad : R/W; bitpos: [6]; default: 0; * For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_qio. + * same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdin_quad:1; /** mem_fdout_quad : R/W; bitpos: [7]; default: 0; * For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the - * same with spi_mem_c_fread_qio. + * same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_fdout_quad:1; /** mem_faddr_quad : R/W; bitpos: [8]; default: 0; * For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_fread_qio. + * the same with spi_mem_fread_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_faddr_quad:1; uint32_t reserved_9:21; - /** same_aw_ar_addr_chk_en : HRO; bitpos: [30]; default: 1; + /** same_aw_ar_addr_chk_en : R/W; bitpos: [30]; default: 1; * Set this bit to check AXI read/write the same address region. */ uint32_t same_aw_ar_addr_chk_en:1; @@ -384,76 +379,76 @@ typedef union { */ typedef union { struct { - /** fmem_ddr_en : HRO; bitpos: [0]; default: 0; + /** fmem_ddr_en : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ uint32_t fmem_ddr_en:1; - /** fmem_var_dummy : HRO; bitpos: [1]; default: 0; + /** fmem_var_dummy : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ uint32_t fmem_var_dummy:1; - /** fmem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + /** fmem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ uint32_t fmem_ddr_rdat_swp:1; - /** fmem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + /** fmem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ uint32_t fmem_ddr_wdat_swp:1; - /** fmem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + /** fmem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ uint32_t fmem_ddr_cmd_dis:1; - /** fmem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + /** fmem_outminbytelen : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the panda device. */ uint32_t fmem_outminbytelen:7; - /** fmem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + /** fmem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to flash. */ uint32_t fmem_tx_ddr_msk_en:1; - /** fmem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + /** fmem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to flash. */ uint32_t fmem_rx_ddr_msk_en:1; - /** fmem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + /** fmem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ uint32_t fmem_usr_ddr_dqs_thd:7; - /** fmem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + /** fmem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t fmem_ddr_dqs_loop:1; uint32_t reserved_22:2; - /** fmem_clk_diff_en : HRO; bitpos: [24]; default: 0; + /** fmem_clk_diff_en : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ uint32_t fmem_clk_diff_en:1; uint32_t reserved_25:1; - /** fmem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + /** fmem_dqs_ca_in : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ uint32_t fmem_dqs_ca_in:1; - /** fmem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + /** fmem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ uint32_t fmem_hyperbus_dummy_2x:1; - /** fmem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + /** fmem_clk_diff_inv : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to flash. . */ uint32_t fmem_clk_diff_inv:1; - /** fmem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + /** fmem_octa_ram_addr : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}. */ uint32_t fmem_octa_ram_addr:1; - /** fmem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + /** fmem_hyperbus_ca : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to flash, which means * ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -471,16 +466,16 @@ typedef union { typedef union { struct { /** mem_clkcnt_l : R/W; bitpos: [7:0]; default: 3; - * In the master mode it must be equal to spi_mem_c_clkcnt_N. + * In the master mode it must be equal to SPI_MEM_CLKCNT_N. */ uint32_t mem_clkcnt_l:8; /** mem_clkcnt_h : R/W; bitpos: [15:8]; default: 1; - * In the master mode it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + * In the master mode it must be floor((SPI_MEM_CLKCNT_N+1)/2-1). */ uint32_t mem_clkcnt_h:8; /** mem_clkcnt_n : R/W; bitpos: [23:16]; default: 3; - * In the master mode it is the divider of spi_mem_c_clk. So spi_mem_c_clk frequency is - * system/(spi_mem_c_clkcnt_N+1) + * In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is + * system/(SPI_MEM_CLKCNT_N+1) */ uint32_t mem_clkcnt_n:8; uint32_t reserved_24:7; @@ -498,25 +493,25 @@ typedef union { */ typedef union { struct { - /** mem_sclkcnt_l : HRO; bitpos: [7:0]; default: 3; - * For SPI0 external RAM interface, it must be equal to spi_mem_c_clkcnt_N. + /** mem_sclkcnt_l : R/W; bitpos: [7:0]; default: 3; + * For SPI0 external RAM interface, it must be equal to SPI_MEM_SCLKCNT_N. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_l:8; - /** mem_sclkcnt_h : HRO; bitpos: [15:8]; default: 1; - * For SPI0 external RAM interface, it must be floor((spi_mem_c_clkcnt_N+1)/2-1). + /** mem_sclkcnt_h : R/W; bitpos: [15:8]; default: 1; + * For SPI0 external RAM interface, it must be floor((SPI_MEM_SCLKCNT_N+1)/2-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_h:8; - /** mem_sclkcnt_n : HRO; bitpos: [23:16]; default: 3; - * For SPI0 external RAM interface, it is the divider of spi_mem_c_clk. So spi_mem_c_clk - * frequency is system/(spi_mem_c_clkcnt_N+1) + /** mem_sclkcnt_n : R/W; bitpos: [23:16]; default: 3; + * For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk + * frequency is system/(SPI_MEM_SCLKCNT_N+1) * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclkcnt_n:8; uint32_t reserved_24:7; - /** mem_sclk_equ_sysclk : HRO; bitpos: [31]; default: 0; - * For SPI0 external RAM interface, 1: spi_mem_c_clk is equal to system 0: spi_mem_c_clk + /** mem_sclk_equ_sysclk : R/W; bitpos: [31]; default: 0; + * For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk * is divided from system clock. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -557,7 +552,7 @@ typedef union { uint32_t mem_cs_setup:1; uint32_t reserved_8:1; /** mem_ck_out_edge : R/W; bitpos: [9]; default: 0; - * The bit combined with spi_mem_c_CK_IDLE_EDGE bit to control SPI clock mode 0~3. + * The bit combined with SPI_MEM_CK_IDLE_EDGE bit to control SPI clock mode 0~3. */ uint32_t mem_ck_out_edge:1; uint32_t reserved_10:16; @@ -581,15 +576,15 @@ typedef union { typedef union { struct { /** mem_usr_dummy_cyclelen : R/W; bitpos: [5:0]; default: 7; - * The length in spi_mem_c_clk cycles of dummy phase. The register value shall be + * The length in spi_mem_clk cycles of dummy phase. The register value shall be * (cycle_num-1). */ uint32_t mem_usr_dummy_cyclelen:6; - /** mem_usr_dbytelen : HRO; bitpos: [8:6]; default: 1; + /** mem_usr_dbytelen : HRO; bitpos: [11:6]; default: 1; * SPI0 USR_CMD read or write data byte length -1 */ - uint32_t mem_usr_dbytelen:3; - uint32_t reserved_9:17; + uint32_t mem_usr_dbytelen:6; + uint32_t reserved_12:14; /** mem_usr_addr_bitlen : R/W; bitpos: [31:26]; default: 23; * The length in bits of address phase. The register value shall be (bit_num-1). */ @@ -623,11 +618,21 @@ typedef union { struct { uint32_t reserved_0:16; /** mem_wb_mode : R/W; bitpos: [23:16]; default: 0; - * Mode bits in the flash fast read mode it is combined with spi_mem_c_fastrd_mode bit. + * Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_wb_mode:8; - uint32_t reserved_24:8; + /** mem_wb_mode_bitlen : R/W; bitpos: [26:24]; default: 0; + * Mode bits length for flash fast read mode. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_bitlen:3; + /** mem_wb_mode_en : R/W; bitpos: [27]; default: 0; + * Mode bits is valid while this bit is enable. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_wb_mode_en:1; + uint32_t reserved_28:4; }; uint32_t val; } spi_mem_c_rd_status_reg_t; @@ -639,63 +644,63 @@ typedef union { */ typedef union { struct { - /** mem_cache_usr_saddr_4byte : HRO; bitpos: [0]; default: 0; + /** mem_cache_usr_saddr_4byte : R/W; bitpos: [0]; default: 0; * For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: * enable, 0:disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_usr_saddr_4byte:1; - /** mem_usr_sram_dio : HRO; bitpos: [1]; default: 0; + /** mem_usr_sram_dio : R/W; bitpos: [1]; default: 0; * For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_dio:1; - /** mem_usr_sram_qio : HRO; bitpos: [2]; default: 0; + /** mem_usr_sram_qio : R/W; bitpos: [2]; default: 0; * For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_sram_qio:1; - /** mem_usr_wr_sram_dummy : HRO; bitpos: [3]; default: 0; + /** mem_usr_wr_sram_dummy : R/W; bitpos: [3]; default: 0; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write * operations. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_wr_sram_dummy:1; - /** mem_usr_rd_sram_dummy : HRO; bitpos: [4]; default: 1; + /** mem_usr_rd_sram_dummy : R/W; bitpos: [4]; default: 1; * For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read * operations. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_usr_rd_sram_dummy:1; - /** mem_cache_sram_usr_rcmd : HRO; bitpos: [5]; default: 1; + /** mem_cache_sram_usr_rcmd : R/W; bitpos: [5]; default: 1; * For SPI0, In the external RAM mode cache read external RAM for user define command. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rcmd:1; - /** mem_sram_rdummy_cyclelen : HRO; bitpos: [11:6]; default: 1; + /** mem_sram_rdummy_cyclelen : R/W; bitpos: [11:6]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_rdummy_cyclelen:6; uint32_t reserved_12:2; - /** mem_sram_addr_bitlen : HRO; bitpos: [19:14]; default: 23; + /** mem_sram_addr_bitlen : R/W; bitpos: [19:14]; default: 23; * For SPI0, In the external RAM mode, it is the length in bits of address phase. The * register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_addr_bitlen:6; - /** mem_cache_sram_usr_wcmd : HRO; bitpos: [20]; default: 1; + /** mem_cache_sram_usr_wcmd : R/W; bitpos: [20]; default: 1; * For SPI0, In the external RAM mode cache write sram for user define command * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wcmd:1; - /** mem_sram_oct : HRO; bitpos: [21]; default: 0; + /** mem_sram_oct : R/W; bitpos: [21]; default: 0; * reserved * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sram_oct:1; - /** mem_sram_wdummy_cyclelen : HRO; bitpos: [27:22]; default: 1; + /** mem_sram_wdummy_cyclelen : R/W; bitpos: [27:22]; default: 1; * For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -711,78 +716,78 @@ typedef union { */ typedef union { struct { - /** mem_sclk_mode : HRO; bitpos: [1:0]; default: 0; + /** mem_sclk_mode : R/W; bitpos: [1:0]; default: 0; * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed * one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: * SPI clock is always on. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sclk_mode:2; - /** mem_swb_mode : HRO; bitpos: [9:2]; default: 0; + /** mem_swb_mode : R/W; bitpos: [9:2]; default: 0; * Mode bits in the external RAM fast read mode it is combined with - * spi_mem_c_fastrd_mode bit. + * spi_mem_fastrd_mode bit. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_swb_mode:8; - /** mem_sdin_dual : HRO; bitpos: [10]; default: 0; + /** mem_sdin_dual : R/W; bitpos: [10]; default: 0; * For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_dio. + * the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_dual:1; - /** mem_sdout_dual : HRO; bitpos: [11]; default: 0; + /** mem_sdout_dual : R/W; bitpos: [11]; default: 0; * For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_c_usr_sram_dio. + * is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_dual:1; - /** mem_saddr_dual : HRO; bitpos: [12]; default: 0; + /** mem_saddr_dual : R/W; bitpos: [12]; default: 0; * For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_c_usr_sram_dio. + * bit is the same with spi_mem_usr_sram_dio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_dual:1; uint32_t reserved_13:1; - /** mem_sdin_quad : HRO; bitpos: [14]; default: 0; + /** mem_sdin_quad : R/W; bitpos: [14]; default: 0; * For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_qio. + * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_quad:1; - /** mem_sdout_quad : HRO; bitpos: [15]; default: 0; + /** mem_sdout_quad : R/W; bitpos: [15]; default: 0; * For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit - * is the same with spi_mem_c_usr_sram_qio. + * is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_quad:1; - /** mem_saddr_quad : HRO; bitpos: [16]; default: 0; + /** mem_saddr_quad : R/W; bitpos: [16]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The - * bit is the same with spi_mem_c_usr_sram_qio. + * bit is the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_quad:1; - /** mem_scmd_quad : HRO; bitpos: [17]; default: 0; + /** mem_scmd_quad : R/W; bitpos: [17]; default: 0; * For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is - * the same with spi_mem_c_usr_sram_qio. + * the same with spi_mem_usr_sram_qio. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_scmd_quad:1; - /** mem_sdin_oct : HRO; bitpos: [18]; default: 0; + /** mem_sdin_oct : R/W; bitpos: [18]; default: 0; * For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdin_oct:1; - /** mem_sdout_oct : HRO; bitpos: [19]; default: 0; + /** mem_sdout_oct : R/W; bitpos: [19]; default: 0; * For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdout_oct:1; - /** mem_saddr_oct : HRO; bitpos: [20]; default: 0; + /** mem_saddr_oct : R/W; bitpos: [20]; default: 0; * For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_saddr_oct:1; - /** mem_scmd_oct : HRO; bitpos: [21]; default: 0; + /** mem_scmd_oct : R/W; bitpos: [21]; default: 0; * For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable. * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -793,29 +798,39 @@ typedef union { * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_rin:1; - /** mem_sdummy_wout : HRO; bitpos: [23]; default: 0; + /** mem_sdummy_wout : R/W; bitpos: [23]; default: 1; * In the dummy phase of a MSPI write data transfer when accesses to external RAM, the * signal level of SPI bus is output by the MSPI controller. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_sdummy_wout:1; - /** smem_wdummy_dqs_always_out : HRO; bitpos: [24]; default: 0; + /** smem_wdummy_dqs_always_out : R/W; bitpos: [24]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_DQS is output by the MSPI controller. */ uint32_t smem_wdummy_dqs_always_out:1; - /** smem_wdummy_always_out : HRO; bitpos: [25]; default: 0; + /** smem_wdummy_always_out : R/W; bitpos: [25]; default: 0; * In the dummy phase of an MSPI write data transfer when accesses to external RAM, * the level of SPI_IO[7:0] is output by the MSPI controller. */ uint32_t smem_wdummy_always_out:1; - uint32_t reserved_26:4; - /** smem_dqs_ie_always_on : HRO; bitpos: [30]; default: 1; + /** mem_sdin_hex : HRO; bitpos: [26]; default: 0; + * For SPI0 external RAM , din phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdin_hex:1; + /** mem_sdout_hex : HRO; bitpos: [27]; default: 0; + * For SPI0 external RAM , dout phase apply 16 signals. 1: enable 0: disable. + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t mem_sdout_hex:1; + uint32_t reserved_28:2; + /** smem_dqs_ie_always_on : R/W; bitpos: [30]; default: 0; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are * always 1. 0: Others. */ uint32_t smem_dqs_ie_always_on:1; - /** smem_data_ie_always_on : HRO; bitpos: [31]; default: 1; + /** smem_data_ie_always_on : R/W; bitpos: [31]; default: 1; * When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] * are always 1. 0: Others. */ @@ -829,14 +844,14 @@ typedef union { */ typedef union { struct { - /** mem_cache_sram_usr_rd_cmd_value : HRO; bitpos: [15:0]; default: 0; + /** mem_cache_sram_usr_rd_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the read command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_rd_cmd_value:16; uint32_t reserved_16:12; - /** mem_cache_sram_usr_rd_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + /** mem_cache_sram_usr_rd_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the length in bits of command phase for * sram. The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -851,14 +866,14 @@ typedef union { */ typedef union { struct { - /** mem_cache_sram_usr_wr_cmd_value : HRO; bitpos: [15:0]; default: 0; + /** mem_cache_sram_usr_wr_cmd_value : R/W; bitpos: [15:0]; default: 0; * For SPI0,When cache mode is enable it is the write command value of command phase * for sram. * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mem_cache_sram_usr_wr_cmd_value:16; uint32_t reserved_16:12; - /** mem_cache_sram_usr_wr_cmd_bitlen : HRO; bitpos: [31:28]; default: 0; + /** mem_cache_sram_usr_wr_cmd_bitlen : R/W; bitpos: [31:28]; default: 0; * For SPI0,When cache mode is enable it is the in bits of command phase for sram. * The register value shall be (bit_num-1). * This field is only for internal debugging purposes. Do not use it in applications. @@ -873,77 +888,77 @@ typedef union { */ typedef union { struct { - /** smem_ddr_en : HRO; bitpos: [0]; default: 0; + /** smem_ddr_en : R/W; bitpos: [0]; default: 0; * 1: in DDR mode, 0 in SDR mode */ uint32_t smem_ddr_en:1; - /** smem_var_dummy : HRO; bitpos: [1]; default: 0; + /** smem_var_dummy : R/W; bitpos: [1]; default: 0; * Set the bit to enable variable dummy cycle in spi DDR mode. */ uint32_t smem_var_dummy:1; - /** smem_ddr_rdat_swp : HRO; bitpos: [2]; default: 0; + /** smem_ddr_rdat_swp : R/W; bitpos: [2]; default: 0; * Set the bit to reorder rx data of the word in spi DDR mode. */ uint32_t smem_ddr_rdat_swp:1; - /** smem_ddr_wdat_swp : HRO; bitpos: [3]; default: 0; + /** smem_ddr_wdat_swp : R/W; bitpos: [3]; default: 0; * Set the bit to reorder tx data of the word in spi DDR mode. */ uint32_t smem_ddr_wdat_swp:1; - /** smem_ddr_cmd_dis : HRO; bitpos: [4]; default: 0; + /** smem_ddr_cmd_dis : R/W; bitpos: [4]; default: 0; * the bit is used to disable dual edge in command phase when DDR mode. */ uint32_t smem_ddr_cmd_dis:1; - /** smem_outminbytelen : HRO; bitpos: [11:5]; default: 1; + /** smem_outminbytelen : R/W; bitpos: [11:5]; default: 1; * It is the minimum output data length in the DDR psram. */ uint32_t smem_outminbytelen:7; - /** smem_tx_ddr_msk_en : HRO; bitpos: [12]; default: 1; + /** smem_tx_ddr_msk_en : R/W; bitpos: [12]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when * accesses to external RAM. */ uint32_t smem_tx_ddr_msk_en:1; - /** smem_rx_ddr_msk_en : HRO; bitpos: [13]; default: 1; + /** smem_rx_ddr_msk_en : R/W; bitpos: [13]; default: 1; * Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when * accesses to external RAM. */ uint32_t smem_rx_ddr_msk_en:1; - /** smem_usr_ddr_dqs_thd : HRO; bitpos: [20:14]; default: 0; + /** smem_usr_ddr_dqs_thd : R/W; bitpos: [20:14]; default: 0; * The delay number of data strobe which from memory based on SPI clock. */ uint32_t smem_usr_ddr_dqs_thd:7; - /** smem_ddr_dqs_loop : HRO; bitpos: [21]; default: 0; + /** smem_ddr_dqs_loop : R/W; bitpos: [21]; default: 0; * 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when - * spi0_slv_st is in spi_mem_c_DIN state. It is used when there is no SPI_DQS signal or + * spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or * SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and * negative edge of SPI_DQS. */ uint32_t smem_ddr_dqs_loop:1; uint32_t reserved_22:2; - /** smem_clk_diff_en : HRO; bitpos: [24]; default: 0; + /** smem_clk_diff_en : R/W; bitpos: [24]; default: 0; * Set this bit to enable the differential SPI_CLK#. */ uint32_t smem_clk_diff_en:1; uint32_t reserved_25:1; - /** smem_dqs_ca_in : HRO; bitpos: [26]; default: 0; + /** smem_dqs_ca_in : R/W; bitpos: [26]; default: 0; * Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR. */ uint32_t smem_dqs_ca_in:1; - /** smem_hyperbus_dummy_2x : HRO; bitpos: [27]; default: 0; + /** smem_hyperbus_dummy_2x : R/W; bitpos: [27]; default: 0; * Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 * accesses flash or SPI1 accesses flash or sram. */ uint32_t smem_hyperbus_dummy_2x:1; - /** smem_clk_diff_inv : HRO; bitpos: [28]; default: 0; + /** smem_clk_diff_inv : R/W; bitpos: [28]; default: 0; * Set this bit to invert SPI_DIFF when accesses to external RAM. . */ uint32_t smem_clk_diff_inv:1; - /** smem_octa_ram_addr : HRO; bitpos: [29]; default: 0; + /** smem_octa_ram_addr : R/W; bitpos: [29]; default: 0; * Set this bit to enable octa_ram address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], * 1'b0}. */ uint32_t smem_octa_ram_addr:1; - /** smem_hyperbus_ca : HRO; bitpos: [30]; default: 0; + /** smem_hyperbus_ca : R/W; bitpos: [30]; default: 0; * Set this bit to enable HyperRAM address out when accesses to external RAM, which * means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}. */ @@ -951,55 +966,55 @@ typedef union { uint32_t reserved_31:1; }; uint32_t val; -} spi_smem_c_ddr_reg_t; +} spi_smem_ddr_reg_t; /** Type of smem_ac register * MSPI external RAM ECC and SPI CS timing control register */ typedef union { struct { - /** smem_cs_setup : HRO; bitpos: [0]; default: 0; + /** smem_cs_setup : R/W; bitpos: [0]; default: 0; * For SPI0 and SPI1, spi cs is enable when spi is in prepare phase. 1: enable 0: * disable. */ uint32_t smem_cs_setup:1; - /** smem_cs_hold : HRO; bitpos: [1]; default: 0; + /** smem_cs_hold : R/W; bitpos: [1]; default: 0; * For SPI0 and SPI1, spi cs keep low when spi is in done phase. 1: enable 0: disable. */ uint32_t smem_cs_hold:1; - /** smem_cs_setup_time : HRO; bitpos: [6:2]; default: 1; + /** smem_cs_setup_time : R/W; bitpos: [6:2]; default: 1; * For spi0, (cycles-1) of prepare phase by spi clock this bits are combined with - * spi_mem_c_cs_setup bit. + * spi_mem_cs_setup bit. */ uint32_t smem_cs_setup_time:5; - /** smem_cs_hold_time : HRO; bitpos: [11:7]; default: 1; + /** smem_cs_hold_time : R/W; bitpos: [11:7]; default: 1; * For SPI0 and SPI1, spi cs signal is delayed to inactive by spi clock this bits are - * combined with spi_mem_c_cs_hold bit. + * combined with spi_mem_cs_hold bit. */ uint32_t smem_cs_hold_time:5; - /** smem_ecc_cs_hold_time : HRO; bitpos: [14:12]; default: 3; - * spi_smem_c_CS_HOLD_TIME + spi_smem_c_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold + /** smem_ecc_cs_hold_time : R/W; bitpos: [14:12]; default: 3; + * SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the SPI0 and SPI1 CS hold * cycles in ECC mode when accessed external RAM. */ uint32_t smem_ecc_cs_hold_time:3; - /** smem_ecc_skip_page_corner : HRO; bitpos: [15]; default: 1; + /** smem_ecc_skip_page_corner : R/W; bitpos: [15]; default: 1; * 1: SPI0 skips page corner when accesses external RAM. 0: Not skip page corner when * accesses external RAM. */ uint32_t smem_ecc_skip_page_corner:1; - /** smem_ecc_16to18_byte_en : HRO; bitpos: [16]; default: 0; + /** smem_ecc_16to18_byte_en : R/W; bitpos: [16]; default: 0; * Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when * accesses external RAM. */ uint32_t smem_ecc_16to18_byte_en:1; uint32_t reserved_17:8; - /** smem_cs_hold_delay : HRO; bitpos: [30:25]; default: 0; + /** smem_cs_hold_delay : R/W; bitpos: [30:25]; default: 0; * These bits are used to set the minimum CS high time tSHSL between SPI burst - * transfer when accesses to external RAM. tSHSL is (spi_smem_c_CS_HOLD_DELAY[5:0] + 1) + * transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) * MSPI core clock cycles. */ uint32_t smem_cs_hold_delay:6; - /** smem_split_trans_en : HRO; bitpos: [31]; default: 0; + /** smem_split_trans_en : R/W; bitpos: [31]; default: 0; * Set this bit to enable SPI0 split one AXI accesses EXT_RAM transfer into two SPI * transfers when one transfer will cross flash/EXT_RAM page corner, valid no matter * whether there is an ECC region or not. @@ -1007,7 +1022,7 @@ typedef union { uint32_t smem_split_trans_en:1; }; uint32_t val; -} spi_smem_c_ac_reg_t; +} spi_smem_ac_reg_t; /** Group: State control register */ @@ -1017,11 +1032,19 @@ typedef union { typedef union { struct { uint32_t reserved_0:7; - /** mem_lock_delay_time : R/W; bitpos: [11:7]; default: 4; + /** mem_lock_delay_time : R/W; bitpos: [18:7]; default: 4; * The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1. */ - uint32_t mem_lock_delay_time:5; - uint32_t reserved_12:20; + uint32_t mem_lock_delay_time:12; + /** mem_flash_lock_en : R/W; bitpos: [19]; default: 0; + * The lock enable for FLASH to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_flash_lock_en:1; + /** mem_sram_lock_en : R/W; bitpos: [20]; default: 0; + * The lock enable for external RAM to lock spi0 trans req.1: Enable. 0: Disable. + */ + uint32_t mem_sram_lock_en:1; + uint32_t reserved_21:11; }; uint32_t val; } spi_mem_c_fsm_reg_t; @@ -1035,34 +1058,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_ena : R/W; bitpos: [3]; default: 0; - * The enable bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The enable bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_ena:1; /** mem_mst_st_end_int_ena : R/W; bitpos: [4]; default: 0; - * The enable bit for spi_mem_c_MST_ST_END_INT interrupt. + * The enable bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_ena:1; - /** mem_ecc_err_int_ena : HRO; bitpos: [5]; default: 0; - * The enable bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_ena : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_ena:1; /** mem_pms_reject_int_ena : R/W; bitpos: [6]; default: 0; - * The enable bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The enable bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_ena:1; /** mem_axi_raddr_err_int_ena : R/W; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_ena:1; - /** mem_axi_wr_flash_err_int_ena : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_ena : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_ena:1; - /** mem_axi_waddr_err_int__ena : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int__ena : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int__ena:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_ena : R/W; bitpos: [28]; default: 0; + * The enable bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_ena:1; + /** mem_dqs1_afifo_ovf_int_ena : R/W; bitpos: [29]; default: 0; + * The enable bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_ena:1; + /** mem_bus_fifo1_udf_int_ena : R/W; bitpos: [30]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_ena:1; + /** mem_bus_fifo0_udf_int_ena : R/W; bitpos: [31]; default: 0; + * The enable bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_ena:1; }; uint32_t val; } spi_mem_c_int_ena_reg_t; @@ -1074,34 +1113,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_clr : WT; bitpos: [3]; default: 0; - * The clear bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The clear bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_clr:1; /** mem_mst_st_end_int_clr : WT; bitpos: [4]; default: 0; - * The clear bit for spi_mem_c_MST_ST_END_INT interrupt. + * The clear bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_clr:1; - /** mem_ecc_err_int_clr : HRO; bitpos: [5]; default: 0; - * The clear bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_clr : WT; bitpos: [5]; default: 0; + * The clear bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_clr:1; /** mem_pms_reject_int_clr : WT; bitpos: [6]; default: 0; - * The clear bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The clear bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_clr:1; /** mem_axi_raddr_err_int_clr : WT; bitpos: [7]; default: 0; - * The clear bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The clear bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_clr:1; - /** mem_axi_wr_flash_err_int_clr : HRO; bitpos: [8]; default: 0; - * The clear bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_clr : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_clr:1; - /** mem_axi_waddr_err_int_clr : HRO; bitpos: [9]; default: 0; - * The clear bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int_clr : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_clr:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_clr : WT; bitpos: [28]; default: 0; + * The clear bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_clr:1; + /** mem_dqs1_afifo_ovf_int_clr : WT; bitpos: [29]; default: 0; + * The clear bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_clr:1; + /** mem_bus_fifo1_udf_int_clr : WT; bitpos: [30]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_clr:1; + /** mem_bus_fifo0_udf_int_clr : WT; bitpos: [31]; default: 0; + * The clear bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_clr:1; }; uint32_t val; } spi_mem_c_int_clr_reg_t; @@ -1113,50 +1168,70 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for spi_mem_c_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is + * The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is * changed from non idle state to idle state. It means that SPI_CS raises high. 0: * Others */ uint32_t mem_slv_st_end_int_raw:1; /** mem_mst_st_end_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for spi_mem_c_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is + * The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is * changed from non idle state to idle state. 0: Others. */ uint32_t mem_mst_st_end_int_raw:1; - /** mem_ecc_err_int_raw : HRO; bitpos: [5]; default: 0; - * The raw bit for spi_mem_c_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set - * and spi_smem_c_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times - * of SPI0/1 ECC read flash are equal or bigger than spi_mem_c_ECC_ERR_INT_NUM. When - * SPI_FMEM_ECC_ERR_INT_EN is cleared and spi_smem_c_ECC_ERR_INT_EN is set, this bit is + /** mem_ecc_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When SPI_FMEM_ECC_ERR_INT_EN is set + * and SPI_SMEM_ECC_ERR_INT_EN is cleared, this bit is triggered when the error times + * of SPI0/1 ECC read flash are equal or bigger than SPI_MEM_ECC_ERR_INT_NUM. When + * SPI_FMEM_ECC_ERR_INT_EN is cleared and SPI_SMEM_ECC_ERR_INT_EN is set, this bit is * triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger - * than spi_mem_c_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and - * spi_smem_c_ECC_ERR_INT_EN are set, this bit is triggered when the total error times + * than SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and + * SPI_SMEM_ECC_ERR_INT_EN are set, this bit is triggered when the total error times * of SPI0/1 ECC read external RAM and flash are equal or bigger than - * spi_mem_c_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and spi_smem_c_ECC_ERR_INT_EN + * SPI_MEM_ECC_ERR_INT_NUM. When SPI_FMEM_ECC_ERR_INT_EN and SPI_SMEM_ECC_ERR_INT_EN * are cleared, this bit will not be triggered. */ uint32_t mem_ecc_err_int_raw:1; /** mem_pms_reject_int_raw : R/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for spi_mem_c_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is + * The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is * rejected. 0: Others. */ uint32_t mem_pms_reject_int_raw:1; /** mem_axi_raddr_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read + * The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_raddr_err_int_raw:1; - /** mem_axi_wr_flash_err_int_raw : HRO; bitpos: [8]; default: 0; - * The raw bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write + /** mem_axi_wr_flash_err_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write * flash request is received. 0: Others. */ uint32_t mem_axi_wr_flash_err_int_raw:1; - /** mem_axi_waddr_err_int_raw : HRO; bitpos: [9]; default: 0; - * The raw bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write + /** mem_axi_waddr_err_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write * address is invalid by compared to MMU configuration. 0: Others. */ uint32_t mem_axi_waddr_err_int_raw:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The raw bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS1 is overflow. + */ + uint32_t mem_dqs0_afifo_ovf_int_raw:1; + /** mem_dqs1_afifo_ovf_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The raw bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. 1: Triggered when the AFIFO + * connected to SPI_DQS is overflow. + */ + uint32_t mem_dqs1_afifo_ovf_int_raw:1; + /** mem_bus_fifo1_udf_int_raw : R/WTC/SS; bitpos: [30]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. 1: Triggered when BUS1 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo1_udf_int_raw:1; + /** mem_bus_fifo0_udf_int_raw : R/WTC/SS; bitpos: [31]; default: 0; + * The raw bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. 1: Triggered when BUS0 FIFO is + * underflow. + */ + uint32_t mem_bus_fifo0_udf_int_raw:1; }; uint32_t val; } spi_mem_c_int_raw_reg_t; @@ -1168,34 +1243,50 @@ typedef union { struct { uint32_t reserved_0:3; /** mem_slv_st_end_int_st : RO; bitpos: [3]; default: 0; - * The status bit for spi_mem_c_SLV_ST_END_INT interrupt. + * The status bit for SPI_MEM_SLV_ST_END_INT interrupt. */ uint32_t mem_slv_st_end_int_st:1; /** mem_mst_st_end_int_st : RO; bitpos: [4]; default: 0; - * The status bit for spi_mem_c_MST_ST_END_INT interrupt. + * The status bit for SPI_MEM_MST_ST_END_INT interrupt. */ uint32_t mem_mst_st_end_int_st:1; - /** mem_ecc_err_int_st : HRO; bitpos: [5]; default: 0; - * The status bit for spi_mem_c_ECC_ERR_INT interrupt. + /** mem_ecc_err_int_st : RO; bitpos: [5]; default: 0; + * The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t mem_ecc_err_int_st:1; /** mem_pms_reject_int_st : RO; bitpos: [6]; default: 0; - * The status bit for spi_mem_c_PMS_REJECT_INT interrupt. + * The status bit for SPI_MEM_PMS_REJECT_INT interrupt. */ uint32_t mem_pms_reject_int_st:1; /** mem_axi_raddr_err_int_st : RO; bitpos: [7]; default: 0; - * The enable bit for spi_mem_c_AXI_RADDR_ERR_INT interrupt. + * The enable bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. */ uint32_t mem_axi_raddr_err_int_st:1; - /** mem_axi_wr_flash_err_int_st : HRO; bitpos: [8]; default: 0; - * The enable bit for spi_mem_c_AXI_WR_FALSH_ERR_INT interrupt. + /** mem_axi_wr_flash_err_int_st : RO; bitpos: [8]; default: 0; + * The enable bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. */ uint32_t mem_axi_wr_flash_err_int_st:1; - /** mem_axi_waddr_err_int_st : HRO; bitpos: [9]; default: 0; - * The enable bit for spi_mem_c_AXI_WADDR_ERR_INT interrupt. + /** mem_axi_waddr_err_int_st : RO; bitpos: [9]; default: 0; + * The enable bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. */ uint32_t mem_axi_waddr_err_int_st:1; - uint32_t reserved_10:22; + uint32_t reserved_10:18; + /** mem_dqs0_afifo_ovf_int_st : RO; bitpos: [28]; default: 0; + * The status bit for SPI_MEM_DQS0_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs0_afifo_ovf_int_st:1; + /** mem_dqs1_afifo_ovf_int_st : RO; bitpos: [29]; default: 0; + * The status bit for SPI_MEM_DQS1_AFIFO_OVF_INT interrupt. + */ + uint32_t mem_dqs1_afifo_ovf_int_st:1; + /** mem_bus_fifo1_udf_int_st : RO; bitpos: [30]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO1_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo1_udf_int_st:1; + /** mem_bus_fifo0_udf_int_st : RO; bitpos: [31]; default: 0; + * The status bit for SPI_MEM_BUS_FIFO0_UDF_INT interrupt. + */ + uint32_t mem_bus_fifo0_udf_int_st:1; }; uint32_t val; } spi_mem_c_int_st_reg_t; @@ -1231,11 +1322,11 @@ typedef union { */ typedef union { struct { - /** fmem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + /** fmem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; * SPI1 flash PMS section n start address value */ - uint32_t fmem_pmsn_addr_s:27; - uint32_t reserved_27:5; + uint32_t fmem_pmsn_addr_s:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_fmem_pmsn_addr_reg_t; @@ -1245,12 +1336,12 @@ typedef union { */ typedef union { struct { - /** fmem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; + /** fmem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; * SPI1 flash PMS section n address region is (SPI_FMEM_PMSn_ADDR_S, * SPI_FMEM_PMSn_ADDR_S + SPI_FMEM_PMSn_SIZE) */ - uint32_t fmem_pmsn_size:15; - uint32_t reserved_15:17; + uint32_t fmem_pmsn_size:17; + uint32_t reserved_17:15; }; uint32_t val; } spi_fmem_pmsn_size_reg_t; @@ -1270,82 +1361,93 @@ typedef union { uint32_t smem_pmsn_wr_attr:1; /** smem_pmsn_ecc : R/W; bitpos: [2]; default: 0; * SPI1 external RAM PMS section n ECC mode, 1: enable ECC mode. 0: Disable it. The - * external RAM PMS section n is configured by registers spi_smem_c_PMSn_ADDR_REG and - * spi_smem_c_PMSn_SIZE_REG. + * external RAM PMS section n is configured by registers SPI_SMEM_PMSn_ADDR_REG and + * SPI_SMEM_PMSn_SIZE_REG. */ uint32_t smem_pmsn_ecc:1; uint32_t reserved_3:29; }; uint32_t val; -} spi_smem_c_pmsn_attr_reg_t; +} spi_smem_pmsn_attr_reg_t; /** Type of smem_pmsn_addr register * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pmsn_addr_s : R/W; bitpos: [26:0]; default: 0; + /** smem_pmsn_addr_s : R/W; bitpos: [28:0]; default: 0; * SPI1 external RAM PMS section n start address value */ - uint32_t smem_pmsn_addr_s:27; - uint32_t reserved_27:5; + uint32_t smem_pmsn_addr_s:29; + uint32_t reserved_29:3; }; uint32_t val; -} spi_smem_c_pmsn_addr_reg_t; +} spi_smem_pmsn_addr_reg_t; /** Type of smem_pmsn_size register * SPI1 external RAM PMS section n start address register */ typedef union { struct { - /** smem_pmsn_size : R/W; bitpos: [14:0]; default: 4096; - * SPI1 external RAM PMS section n address region is (spi_smem_c_PMSn_ADDR_S, - * spi_smem_c_PMSn_ADDR_S + spi_smem_c_PMSn_SIZE) + /** smem_pmsn_size : R/W; bitpos: [16:0]; default: 4096; + * SPI1 external RAM PMS section n address region is (SPI_SMEM_PMSn_ADDR_S, + * SPI_SMEM_PMSn_ADDR_S + SPI_SMEM_PMSn_SIZE) */ - uint32_t smem_pmsn_size:15; - uint32_t reserved_15:17; + uint32_t smem_pmsn_size:17; + uint32_t reserved_17:15; }; uint32_t val; -} spi_smem_c_pmsn_size_reg_t; +} spi_smem_pmsn_size_reg_t; /** Type of mem_pms_reject register * SPI1 access reject register */ typedef union { struct { - /** mem_reject_addr : R/SS/WTC; bitpos: [26:0]; default: 0; - * This bits show the first SPI1 access error address. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. - */ - uint32_t mem_reject_addr:27; + uint32_t reserved_0:27; /** mem_pm_en : R/W; bitpos: [27]; default: 0; * Set this bit to enable SPI0/1 transfer permission control function. */ uint32_t mem_pm_en:1; /** mem_pms_ld : R/SS/WTC; bitpos: [28]; default: 0; * 1: SPI1 write access error. 0: No write access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ld:1; /** mem_pms_st : R/SS/WTC; bitpos: [29]; default: 0; * 1: SPI1 read access error. 0: No read access error. It is cleared by when - * spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_st:1; /** mem_pms_multi_hit : R/SS/WTC; bitpos: [30]; default: 0; * 1: SPI1 access is rejected because of address miss. 0: No address miss error. It is - * cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_multi_hit:1; /** mem_pms_ivd : R/SS/WTC; bitpos: [31]; default: 0; * 1: SPI1 access is rejected because of address multi-hit. 0: No address multi-hit - * error. It is cleared by when spi_mem_c_PMS_REJECT_INT_CLR bit is set. + * error. It is cleared by when SPI_MEM_PMS_REJECT_INT_CLR bit is set. */ uint32_t mem_pms_ivd:1; }; uint32_t val; } spi_mem_c_pms_reject_reg_t; +/** Type of mem_pms_reject_addr register + * SPI1 access reject addr register + */ +typedef union { + struct { + /** mem_reject_addr : R/SS/WTC; bitpos: [28:0]; default: 0; + * This bits show the first SPI1 access error address. It is cleared by when + * SPI_MEM_PMS_REJECT_INT_CLR bit is set. + */ + uint32_t mem_reject_addr:29; + uint32_t reserved_29:3; + }; + uint32_t val; +} spi_mem_c_pms_reject_addr_reg_t; + /** Group: MSPI ECC registers */ /** Type of mem_ecc_ctrl register @@ -1354,16 +1456,16 @@ typedef union { typedef union { struct { uint32_t reserved_0:5; - /** mem_ecc_err_cnt : HRO; bitpos: [10:5]; default: 0; + /** mem_ecc_err_cnt : R/SS/WTC; bitpos: [10:5]; default: 0; * This bits show the error times of MSPI ECC read. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ uint32_t mem_ecc_err_cnt:6; - /** fmem_ecc_err_int_num : HRO; bitpos: [16:11]; default: 10; - * Set the error times of MSPI ECC read to generate MSPI spi_mem_c_ECC_ERR_INT interrupt. + /** fmem_ecc_err_int_num : R/W; bitpos: [16:11]; default: 10; + * Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt. */ uint32_t fmem_ecc_err_int_num:6; - /** fmem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + /** fmem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to flash. */ uint32_t fmem_ecc_err_int_en:1; @@ -1372,24 +1474,25 @@ typedef union { * 1024 bytes. 3: 2048 bytes. */ uint32_t fmem_page_size:2; - /** fmem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + uint32_t reserved_20:1; + /** fmem_ecc_addr_en : R/W; bitpos: [21]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of flash. If there is no ECC region in flash, this bit * should be 0. Otherwise, this bit should be 1. */ uint32_t fmem_ecc_addr_en:1; - /** mem_usr_ecc_addr_en : HRO; bitpos: [21]; default: 0; + /** mem_usr_ecc_addr_en : R/W; bitpos: [22]; default: 0; * Set this bit to enable ECC address convert in SPI0/1 USR_CMD transfer. */ uint32_t mem_usr_ecc_addr_en:1; - uint32_t reserved_22:2; - /** mem_ecc_continue_record_err_en : HRO; bitpos: [24]; default: 1; - * 1: The error information in spi_mem_c_ECC_ERR_BITS and spi_mem_c_ECC_ERR_ADDR is - * updated when there is an ECC error. 0: spi_mem_c_ECC_ERR_BITS and - * spi_mem_c_ECC_ERR_ADDR record the first ECC error information. + uint32_t reserved_23:1; + /** mem_ecc_continue_record_err_en : R/W; bitpos: [24]; default: 1; + * 1: The error information in SPI_MEM_ECC_ERR_BITS and SPI_MEM_ECC_ERR_ADDR is + * updated when there is an ECC error. 0: SPI_MEM_ECC_ERR_BITS and + * SPI_MEM_ECC_ERR_ADDR record the first ECC error information. */ uint32_t mem_ecc_continue_record_err_en:1; - /** mem_ecc_err_bits : HRO; bitpos: [31:25]; default: 0; + /** mem_ecc_err_bits : R/SS/WTC; bitpos: [31:25]; default: 0; * Records the first ECC error bit number in the 16 bytes(From 0~127, corresponding to * byte 0 bit 0 to byte 15 bit 7) */ @@ -1403,12 +1506,12 @@ typedef union { */ typedef union { struct { - /** mem_ecc_err_addr : HRO; bitpos: [26:0]; default: 0; + /** mem_ecc_err_addr : R/SS/WTC; bitpos: [28:0]; default: 0; * This bits show the first MSPI ECC error address. It is cleared by when - * spi_mem_c_ECC_ERR_INT_CLR bit is set. + * SPI_MEM_ECC_ERR_INT_CLR bit is set. */ - uint32_t mem_ecc_err_addr:27; - uint32_t reserved_27:5; + uint32_t mem_ecc_err_addr:29; + uint32_t reserved_29:3; }; uint32_t val; } spi_mem_c_ecc_err_addr_reg_t; @@ -1419,17 +1522,17 @@ typedef union { typedef union { struct { uint32_t reserved_0:17; - /** smem_ecc_err_int_en : HRO; bitpos: [17]; default: 0; + /** smem_ecc_err_int_en : R/W; bitpos: [17]; default: 0; * Set this bit to calculate the error times of MSPI ECC read when accesses to * external RAM. */ uint32_t smem_ecc_err_int_en:1; - /** smem_page_size : HRO; bitpos: [19:18]; default: 2; + /** smem_page_size : R/W; bitpos: [19:18]; default: 2; * Set the page size of the external RAM accessed by MSPI. 0: 256 bytes. 1: 512 bytes. * 2: 1024 bytes. 3: 2048 bytes. */ uint32_t smem_page_size:2; - /** smem_ecc_addr_en : HRO; bitpos: [20]; default: 0; + /** smem_ecc_addr_en : R/W; bitpos: [20]; default: 0; * Set this bit to enable MSPI ECC address conversion, no matter MSPI accesses to the * ECC region or non-ECC region of external RAM. If there is no ECC region in external * RAM, this bit should be 0. Otherwise, this bit should be 1. @@ -1438,7 +1541,7 @@ typedef union { uint32_t reserved_21:11; }; uint32_t val; -} spi_smem_c_ecc_ctrl_reg_t; +} spi_smem_ecc_ctrl_reg_t; /** Group: Status and state control registers */ @@ -1476,38 +1579,38 @@ typedef union { uint32_t all_axi_trans_afifo_empty:1; }; uint32_t val; -} spi_smem_c_axi_addr_ctrl_reg_t; +} spi_smem_axi_addr_ctrl_reg_t; /** Type of mem_axi_err_resp_en register * SPI0 AXI error response enable register */ typedef union { struct { - /** mem_aw_resp_en_mmu_vld : HRO; bitpos: [0]; default: 0; + /** mem_aw_resp_en_mmu_vld : R/W; bitpos: [0]; default: 0; * Set this bit to enable AXI response function for mmu valid err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_vld:1; - /** mem_aw_resp_en_mmu_gid : HRO; bitpos: [1]; default: 0; + /** mem_aw_resp_en_mmu_gid : R/W; bitpos: [1]; default: 0; * Set this bit to enable AXI response function for mmu gid err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_gid:1; - /** mem_aw_resp_en_axi_size : HRO; bitpos: [2]; default: 0; + /** mem_aw_resp_en_axi_size : R/W; bitpos: [2]; default: 0; * Set this bit to enable AXI response function for axi size err in axi write trans. */ uint32_t mem_aw_resp_en_axi_size:1; - /** mem_aw_resp_en_axi_flash : HRO; bitpos: [3]; default: 0; + /** mem_aw_resp_en_axi_flash : R/W; bitpos: [3]; default: 0; * Set this bit to enable AXI response function for axi flash err in axi write trans. */ uint32_t mem_aw_resp_en_axi_flash:1; - /** mem_aw_resp_en_mmu_ecc : HRO; bitpos: [4]; default: 0; + /** mem_aw_resp_en_mmu_ecc : R/W; bitpos: [4]; default: 0; * Set this bit to enable AXI response function for mmu ecc err in axi write trans. */ uint32_t mem_aw_resp_en_mmu_ecc:1; - /** mem_aw_resp_en_mmu_sens : HRO; bitpos: [5]; default: 0; + /** mem_aw_resp_en_mmu_sens : R/W; bitpos: [5]; default: 0; * Set this bit to enable AXI response function for mmu sens in err axi write trans. */ uint32_t mem_aw_resp_en_mmu_sens:1; - /** mem_aw_resp_en_axi_wstrb : HRO; bitpos: [6]; default: 0; + /** mem_aw_resp_en_axi_wstrb : R/W; bitpos: [6]; default: 0; * Set this bit to enable AXI response function for axi wstrb err in axi write trans. */ uint32_t mem_aw_resp_en_axi_wstrb:1; @@ -1556,7 +1659,7 @@ typedef union { * add extra dummy spi clock cycle length for spi clock calibration. */ uint32_t mem_extra_dummy_cyclelen:3; - /** mem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + /** mem_dll_timing_cali : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * flash. */ @@ -1768,91 +1871,102 @@ typedef union { */ typedef union { struct { - /** smem_timing_clk_ena : HRO; bitpos: [0]; default: 1; + /** smem_timing_clk_ena : R/W; bitpos: [0]; default: 1; * For sram, the bit is used to enable timing adjust clock for all reading operations. */ uint32_t smem_timing_clk_ena:1; - /** smem_timing_cali : HRO; bitpos: [1]; default: 0; + /** smem_timing_cali : R/W; bitpos: [1]; default: 0; * For sram, the bit is used to enable timing auto-calibration for all reading * operations. */ uint32_t smem_timing_cali:1; - /** smem_extra_dummy_cyclelen : HRO; bitpos: [4:2]; default: 0; + /** smem_extra_dummy_cyclelen : R/W; bitpos: [4:2]; default: 0; * For sram, add extra dummy spi clock cycle length for spi clock calibration. */ uint32_t smem_extra_dummy_cyclelen:3; - /** smem_dll_timing_cali : HRO; bitpos: [5]; default: 0; + /** smem_dll_timing_cali : R/W; bitpos: [5]; default: 0; * Set this bit to enable DLL for timing calibration in DDR mode when accessed to * EXT_RAM. */ uint32_t smem_dll_timing_cali:1; - uint32_t reserved_6:26; + uint32_t reserved_6:1; + /** smem_dqs0_270_sel : R/W; bitpos: [8:7]; default: 1; + * Set these bits to delay dqs signal & invert delayed signal for DLL timing adjust. + * 2'd0: 0.5ns, 2'd1: 1.0ns, 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_270_sel:2; + /** smem_dqs0_90_sel : R/W; bitpos: [10:9]; default: 1; + * Set these bits to delay dqs signal for DLL timing adjust. 2'd0: 0.5ns, 2'd1: 1.0ns, + * 2'd2: 1.5ns 2'd3: 2.0ns. + */ + uint32_t smem_dqs0_90_sel:2; + uint32_t reserved_11:21; }; uint32_t val; -} spi_smem_c_timing_cali_reg_t; +} spi_smem_timing_cali_reg_t; /** Type of smem_din_mode register * MSPI external RAM input timing delay mode control register */ typedef union { struct { - /** smem_din0_mode : HRO; bitpos: [2:0]; default: 0; + /** smem_din0_mode : R/W; bitpos: [2:0]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din0_mode:3; - /** smem_din1_mode : HRO; bitpos: [5:3]; default: 0; + /** smem_din1_mode : R/W; bitpos: [5:3]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din1_mode:3; - /** smem_din2_mode : HRO; bitpos: [8:6]; default: 0; + /** smem_din2_mode : R/W; bitpos: [8:6]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din2_mode:3; - /** smem_din3_mode : HRO; bitpos: [11:9]; default: 0; + /** smem_din3_mode : R/W; bitpos: [11:9]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din3_mode:3; - /** smem_din4_mode : HRO; bitpos: [14:12]; default: 0; + /** smem_din4_mode : R/W; bitpos: [14:12]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din4_mode:3; - /** smem_din5_mode : HRO; bitpos: [17:15]; default: 0; + /** smem_din5_mode : R/W; bitpos: [17:15]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din5_mode:3; - /** smem_din6_mode : HRO; bitpos: [20:18]; default: 0; + /** smem_din6_mode : R/W; bitpos: [20:18]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din6_mode:3; - /** smem_din7_mode : HRO; bitpos: [23:21]; default: 0; + /** smem_din7_mode : R/W; bitpos: [23:21]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the * spi_clk high edge, 6: input with the spi_clk low edge */ uint32_t smem_din7_mode:3; - /** smem_dins_mode : HRO; bitpos: [26:24]; default: 0; + /** smem_dins_mode : R/W; bitpos: [26:24]; default: 0; * the input signals are delayed by system clock cycles, 0: input without delayed, 1: * input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input * with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the @@ -1862,54 +1976,54 @@ typedef union { uint32_t reserved_27:5; }; uint32_t val; -} spi_smem_c_din_mode_reg_t; +} spi_smem_din_mode_reg_t; /** Type of smem_din_num register * MSPI external RAM input timing delay number control register */ typedef union { struct { - /** smem_din0_num : HRO; bitpos: [1:0]; default: 0; + /** smem_din0_num : R/W; bitpos: [1:0]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din0_num:2; - /** smem_din1_num : HRO; bitpos: [3:2]; default: 0; + /** smem_din1_num : R/W; bitpos: [3:2]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din1_num:2; - /** smem_din2_num : HRO; bitpos: [5:4]; default: 0; + /** smem_din2_num : R/W; bitpos: [5:4]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din2_num:2; - /** smem_din3_num : HRO; bitpos: [7:6]; default: 0; + /** smem_din3_num : R/W; bitpos: [7:6]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din3_num:2; - /** smem_din4_num : HRO; bitpos: [9:8]; default: 0; + /** smem_din4_num : R/W; bitpos: [9:8]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din4_num:2; - /** smem_din5_num : HRO; bitpos: [11:10]; default: 0; + /** smem_din5_num : R/W; bitpos: [11:10]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din5_num:2; - /** smem_din6_num : HRO; bitpos: [13:12]; default: 0; + /** smem_din6_num : R/W; bitpos: [13:12]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din6_num:2; - /** smem_din7_num : HRO; bitpos: [15:14]; default: 0; + /** smem_din7_num : R/W; bitpos: [15:14]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ uint32_t smem_din7_num:2; - /** smem_dins_num : HRO; bitpos: [17:16]; default: 0; + /** smem_dins_num : R/W; bitpos: [17:16]; default: 0; * the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: * delayed by 2 cycles,... */ @@ -1917,70 +2031,70 @@ typedef union { uint32_t reserved_18:14; }; uint32_t val; -} spi_smem_c_din_num_reg_t; +} spi_smem_din_num_reg_t; /** Type of smem_dout_mode register * MSPI external RAM output timing adjustment control register */ typedef union { struct { - /** smem_dout0_mode : HRO; bitpos: [0]; default: 0; + /** smem_dout0_mode : R/W; bitpos: [0]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout0_mode:1; - /** smem_dout1_mode : HRO; bitpos: [1]; default: 0; + /** smem_dout1_mode : R/W; bitpos: [1]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout1_mode:1; - /** smem_dout2_mode : HRO; bitpos: [2]; default: 0; + /** smem_dout2_mode : R/W; bitpos: [2]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout2_mode:1; - /** smem_dout3_mode : HRO; bitpos: [3]; default: 0; + /** smem_dout3_mode : R/W; bitpos: [3]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout3_mode:1; - /** smem_dout4_mode : HRO; bitpos: [4]; default: 0; + /** smem_dout4_mode : R/W; bitpos: [4]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout4_mode:1; - /** smem_dout5_mode : HRO; bitpos: [5]; default: 0; + /** smem_dout5_mode : R/W; bitpos: [5]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout5_mode:1; - /** smem_dout6_mode : HRO; bitpos: [6]; default: 0; + /** smem_dout6_mode : R/W; bitpos: [6]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout6_mode:1; - /** smem_dout7_mode : HRO; bitpos: [7]; default: 0; + /** smem_dout7_mode : R/W; bitpos: [7]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output * with the spi_clk high edge ,6: output with the spi_clk low edge */ uint32_t smem_dout7_mode:1; - /** smem_douts_mode : HRO; bitpos: [8]; default: 0; + /** smem_douts_mode : R/W; bitpos: [8]; default: 0; * the output signals are delayed by system clock cycles, 0: output without delayed, * 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: * output with the posedge of clk_160,4 output with the negedge of clk_160,5: output @@ -1990,8 +2104,7 @@ typedef union { uint32_t reserved_9:23; }; uint32_t val; -} spi_smem_c_dout_mode_reg_t; - +} spi_smem_dout_mode_reg_t; /** Group: Manual Encryption plaintext Memory */ /** Type of mem_xts_plain_base register @@ -2193,11 +2306,11 @@ typedef union { */ uint32_t mmu_page_size:2; uint32_t reserved_5:11; - /** mem_aux_ctrl : HRO; bitpos: [29:16]; default: 4896; + /** mem_aux_ctrl : R/W; bitpos: [29:16]; default: 4896; * MMU PSRAM aux control register */ uint32_t mem_aux_ctrl:14; - /** mem_rdn_ena : HRO; bitpos: [30]; default: 0; + /** mem_rdn_ena : R/W; bitpos: [30]; default: 0; * ECO register enable bit * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2253,16 +2366,20 @@ typedef union { * 2'b11: crypto with pseudo. */ uint32_t mem_mode_pseudo:2; - /** mem_pseudo_base : R/W; bitpos: [5:2]; default: 2; + /** mem_pseudo_rng_cnt : R/W; bitpos: [4:2]; default: 7; + * xts aes peseudo function base round that must be performed. + */ + uint32_t mem_pseudo_rng_cnt:3; + /** mem_pseudo_base : R/W; bitpos: [8:5]; default: 2; * xts aes peseudo function base round that must be performed. */ uint32_t mem_pseudo_base:4; - /** mem_pseudo_inc : R/W; bitpos: [7:6]; default: 2; + /** mem_pseudo_inc : R/W; bitpos: [10:9]; default: 2; * xts aes peseudo function increment round that will be performed randomly between 0 & * 2**(inc+1). */ uint32_t mem_pseudo_inc:2; - uint32_t reserved_8:24; + uint32_t reserved_11:21; }; uint32_t val; } spi_mem_c_xts_pseudo_round_conf_reg_t; @@ -2274,7 +2391,7 @@ typedef union { */ typedef union { struct { - /** mem_registerrnd_eco_high : RO; bitpos: [31:0]; default: 892; + /** mem_registerrnd_eco_high : R/W; bitpos: [31:0]; default: 892; * ECO high register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2288,7 +2405,7 @@ typedef union { */ typedef union { struct { - /** mem_registerrnd_eco_low : RO; bitpos: [31:0]; default: 892; + /** mem_registerrnd_eco_low : R/W; bitpos: [31:0]; default: 892; * ECO low register * This field is only for internal debugging purposes. Do not use it in applications. */ @@ -2304,7 +2421,7 @@ typedef union { */ typedef union { struct { - /** mem_date : R/W; bitpos: [27:0]; default: 36770128; + /** mem_date : R/W; bitpos: [27:0]; default: 37823232; * SPI0 register version. */ uint32_t mem_date:28; @@ -2343,31 +2460,31 @@ typedef struct { volatile spi_mem_c_int_st_reg_t mem_int_st; uint32_t reserved_0d0; volatile spi_mem_c_ddr_reg_t mem_ddr; - volatile spi_smem_c_ddr_reg_t smem_ddr; + volatile spi_smem_ddr_reg_t smem_ddr; uint32_t reserved_0dc[9]; volatile spi_fmem_pmsn_attr_reg_t fmem_pmsn_attr[4]; volatile spi_fmem_pmsn_addr_reg_t fmem_pmsn_addr[4]; volatile spi_fmem_pmsn_size_reg_t fmem_pmsn_size[4]; - volatile spi_smem_c_pmsn_attr_reg_t smem_pmsn_attr[4]; - volatile spi_smem_c_pmsn_addr_reg_t smem_pmsn_addr[4]; - volatile spi_smem_c_pmsn_size_reg_t smem_pmsn_size[4]; - uint32_t reserved_160; + volatile spi_smem_pmsn_attr_reg_t smem_pmsn_attr[4]; + volatile spi_smem_pmsn_addr_reg_t smem_pmsn_addr[4]; + volatile spi_smem_pmsn_size_reg_t smem_pmsn_size[4]; volatile spi_mem_c_pms_reject_reg_t mem_pms_reject; + volatile spi_mem_c_pms_reject_addr_reg_t mem_pms_reject_addr; volatile spi_mem_c_ecc_ctrl_reg_t mem_ecc_ctrl; volatile spi_mem_c_ecc_err_addr_reg_t mem_ecc_err_addr; volatile spi_mem_c_axi_err_addr_reg_t mem_axi_err_addr; - volatile spi_smem_c_ecc_ctrl_reg_t smem_ecc_ctrl; - volatile spi_smem_c_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; + volatile spi_smem_ecc_ctrl_reg_t smem_ecc_ctrl; + volatile spi_smem_axi_addr_ctrl_reg_t smem_axi_addr_ctrl; volatile spi_mem_c_axi_err_resp_en_reg_t mem_axi_err_resp_en; volatile spi_mem_c_timing_cali_reg_t mem_timing_cali; volatile spi_mem_c_din_mode_reg_t mem_din_mode; volatile spi_mem_c_din_num_reg_t mem_din_num; volatile spi_mem_c_dout_mode_reg_t mem_dout_mode; - volatile spi_smem_c_timing_cali_reg_t smem_timing_cali; - volatile spi_smem_c_din_mode_reg_t smem_din_mode; - volatile spi_smem_c_din_num_reg_t smem_din_num; - volatile spi_smem_c_dout_mode_reg_t smem_dout_mode; - volatile spi_smem_c_ac_reg_t smem_ac; + volatile spi_smem_timing_cali_reg_t smem_timing_cali; + volatile spi_smem_din_mode_reg_t smem_din_mode; + volatile spi_smem_din_num_reg_t smem_din_num; + volatile spi_smem_dout_mode_reg_t smem_dout_mode; + volatile spi_smem_ac_reg_t smem_ac; uint32_t reserved_1a4[23]; volatile spi_mem_c_clock_gate_reg_t mem_clock_gate; uint32_t reserved_204[63]; diff --git a/components/soc/esp32c61/register/soc/spi_reg.h b/components/soc/esp32c61/register/soc/spi_reg.h index cce0834349..4ae39b0d7b 100644 --- a/components/soc/esp32c61/register/soc/spi_reg.h +++ b/components/soc/esp32c61/register/soc/spi_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,13 +11,15 @@ extern "C" { #endif +#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C61 + /** SPI_CMD_REG register * Command control register */ #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ #define SPI_CONF_BITLEN 0x0003FFFFU @@ -26,9 +28,9 @@ extern "C" { #define SPI_CONF_BITLEN_S 0 /** SPI_UPDATE : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ #define SPI_UPDATE (BIT(23)) @@ -36,9 +38,9 @@ extern "C" { #define SPI_UPDATE_V 0x00000001U #define SPI_UPDATE_S 23 /** SPI_USR : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -65,9 +67,9 @@ extern "C" { */ #define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8) /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ #define SPI_DUMMY_OUT (BIT(3)) @@ -75,9 +77,9 @@ extern "C" { #define SPI_DUMMY_OUT_V 0x00000001U #define SPI_DUMMY_OUT_S 3 /** SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_DUAL (BIT(5)) @@ -85,9 +87,9 @@ extern "C" { #define SPI_FADDR_DUAL_V 0x00000001U #define SPI_FADDR_DUAL_S 5 /** SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_QUAD (BIT(6)) @@ -95,9 +97,9 @@ extern "C" { #define SPI_FADDR_QUAD_V 0x00000001U #define SPI_FADDR_QUAD_S 6 /** SPI_FADDR_OCT : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FADDR_OCT (BIT(7)) @@ -105,9 +107,9 @@ extern "C" { #define SPI_FADDR_OCT_V 0x00000001U #define SPI_FADDR_OCT_S 7 /** SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_DUAL (BIT(8)) @@ -115,9 +117,9 @@ extern "C" { #define SPI_FCMD_DUAL_V 0x00000001U #define SPI_FCMD_DUAL_S 8 /** SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_QUAD (BIT(9)) @@ -125,9 +127,9 @@ extern "C" { #define SPI_FCMD_QUAD_V 0x00000001U #define SPI_FCMD_QUAD_S 9 /** SPI_FCMD_OCT : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FCMD_OCT (BIT(10)) @@ -136,9 +138,9 @@ extern "C" { #define SPI_FCMD_OCT_S 10 /** SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_DUAL (BIT(14)) @@ -147,9 +149,9 @@ extern "C" { #define SPI_FREAD_DUAL_S 14 /** SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_QUAD (BIT(15)) @@ -158,9 +160,9 @@ extern "C" { #define SPI_FREAD_QUAD_S 15 /** SPI_FREAD_OCT : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FREAD_OCT (BIT(16)) @@ -168,9 +170,9 @@ extern "C" { #define SPI_FREAD_OCT_V 0x00000001U #define SPI_FREAD_OCT_S 16 /** SPI_Q_POL : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_Q_POL (BIT(18)) @@ -178,9 +180,9 @@ extern "C" { #define SPI_Q_POL_V 0x00000001U #define SPI_Q_POL_S 18 /** SPI_D_POL : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_D_POL (BIT(19)) @@ -188,9 +190,9 @@ extern "C" { #define SPI_D_POL_V 0x00000001U #define SPI_D_POL_S 19 /** SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_HOLD_POL (BIT(20)) @@ -198,9 +200,9 @@ extern "C" { #define SPI_HOLD_POL_V 0x00000001U #define SPI_HOLD_POL_S 20 /** SPI_WP_POL : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ #define SPI_WP_POL (BIT(21)) @@ -208,9 +210,9 @@ extern "C" { #define SPI_WP_POL_V 0x00000001U #define SPI_WP_POL_S 21 /** SPI_RD_BIT_ORDER : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_RD_BIT_ORDER 0x00000003U @@ -219,9 +221,9 @@ extern "C" { #define SPI_RD_BIT_ORDER_S 23 /** SPI_WR_BIT_ORDER : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ #define SPI_WR_BIT_ORDER 0x00000003U @@ -245,7 +247,7 @@ extern "C" { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ #define SPI_CLKCNT_H 0x0000003FU @@ -255,7 +257,7 @@ extern "C" { /** SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ #define SPI_CLKCNT_N 0x0000003FU @@ -270,10 +272,21 @@ extern "C" { #define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) #define SPI_CLKDIV_PRE_V 0x0000000FU #define SPI_CLKDIV_PRE_S 18 +/** SPI_CLK_EDGE_SEL : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ +#define SPI_CLK_EDGE_SEL (BIT(30)) +#define SPI_CLK_EDGE_SEL_M (SPI_CLK_EDGE_SEL_V << SPI_CLK_EDGE_SEL_S) +#define SPI_CLK_EDGE_SEL_V 0x00000001U +#define SPI_CLK_EDGE_SEL_S 30 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ #define SPI_CLK_EQU_SYSCLK (BIT(31)) @@ -286,9 +299,9 @@ extern "C" { */ #define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10) /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_DOUTDIN (BIT(0)) @@ -296,9 +309,9 @@ extern "C" { #define SPI_DOUTDIN_V 0x00000001U #define SPI_DOUTDIN_S 0 /** SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -315,18 +328,18 @@ extern "C" { #define SPI_OPI_MODE_V 0x00000001U #define SPI_OPI_MODE_S 4 /** SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ #define SPI_TSCK_I_EDGE (BIT(5)) #define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) #define SPI_TSCK_I_EDGE_V 0x00000001U #define SPI_TSCK_I_EDGE_S 5 /** SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_HOLD (BIT(6)) @@ -334,9 +347,9 @@ extern "C" { #define SPI_CS_HOLD_V 0x00000001U #define SPI_CS_HOLD_S 6 /** SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_CS_SETUP (BIT(7)) @@ -344,9 +357,9 @@ extern "C" { #define SPI_CS_SETUP_V 0x00000001U #define SPI_CS_SETUP_S 7 /** SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ #define SPI_RSCK_I_EDGE (BIT(8)) #define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) @@ -354,8 +367,7 @@ extern "C" { #define SPI_RSCK_I_EDGE_S 8 /** SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ #define SPI_CK_OUT_EDGE (BIT(9)) #define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) @@ -363,9 +375,9 @@ extern "C" { #define SPI_CK_OUT_EDGE_S 9 /** SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_DUAL (BIT(12)) @@ -374,9 +386,9 @@ extern "C" { #define SPI_FWRITE_DUAL_S 12 /** SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ #define SPI_FWRITE_QUAD (BIT(13)) @@ -393,11 +405,11 @@ extern "C" { #define SPI_FWRITE_OCT_S 14 /** SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ #define SPI_USR_CONF_NXT (BIT(15)) @@ -406,9 +418,9 @@ extern "C" { #define SPI_USR_CONF_NXT_S 15 /** SPI_SIO : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_SIO (BIT(17)) @@ -417,9 +429,9 @@ extern "C" { #define SPI_SIO_S 17 /** SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO_HIGHPART (BIT(24)) @@ -428,9 +440,9 @@ extern "C" { #define SPI_USR_MISO_HIGHPART_S 24 /** SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI_HIGHPART (BIT(25)) @@ -438,9 +450,9 @@ extern "C" { #define SPI_USR_MOSI_HIGHPART_V 0x00000001U #define SPI_USR_MOSI_HIGHPART_S 25 /** SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ #define SPI_USR_DUMMY_IDLE (BIT(26)) @@ -448,9 +460,9 @@ extern "C" { #define SPI_USR_DUMMY_IDLE_V 0x00000001U #define SPI_USR_DUMMY_IDLE_S 26 /** SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MOSI (BIT(27)) @@ -458,9 +470,9 @@ extern "C" { #define SPI_USR_MOSI_V 0x00000001U #define SPI_USR_MOSI_S 27 /** SPI_USR_MISO : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_MISO (BIT(28)) @@ -468,9 +480,9 @@ extern "C" { #define SPI_USR_MISO_V 0x00000001U #define SPI_USR_MISO_S 28 /** SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_DUMMY (BIT(29)) @@ -478,9 +490,9 @@ extern "C" { #define SPI_USR_DUMMY_V 0x00000001U #define SPI_USR_DUMMY_S 29 /** SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_ADDR (BIT(30)) @@ -488,9 +500,9 @@ extern "C" { #define SPI_USR_ADDR_V 0x00000001U #define SPI_USR_ADDR_S 30 /** SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_USR_COMMAND (BIT(31)) @@ -504,7 +516,7 @@ extern "C" { #define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14) /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ #define SPI_USR_DUMMY_CYCLELEN 0x000000FFU @@ -513,9 +525,9 @@ extern "C" { #define SPI_USR_DUMMY_CYCLELEN_S 0 /** SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_WFULL_ERR_END_EN (BIT(16)) #define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) @@ -523,7 +535,7 @@ extern "C" { #define SPI_MST_WFULL_ERR_END_EN_S 16 /** SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ @@ -533,7 +545,7 @@ extern "C" { #define SPI_CS_SETUP_TIME_S 17 /** SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ #define SPI_CS_HOLD_TIME 0x0000001FU @@ -563,9 +575,9 @@ extern "C" { #define SPI_USR_COMMAND_VALUE_S 0 /** SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ #define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) #define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) @@ -600,9 +612,9 @@ extern "C" { */ #define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20) /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS0_DIS (BIT(0)) @@ -610,9 +622,9 @@ extern "C" { #define SPI_CS0_DIS_V 0x00000001U #define SPI_CS0_DIS_S 0 /** SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS1_DIS (BIT(1)) @@ -620,9 +632,9 @@ extern "C" { #define SPI_CS1_DIS_V 0x00000001U #define SPI_CS1_DIS_S 1 /** SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS2_DIS (BIT(2)) @@ -630,9 +642,9 @@ extern "C" { #define SPI_CS2_DIS_V 0x00000001U #define SPI_CS2_DIS_S 2 /** SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS3_DIS (BIT(3)) @@ -640,9 +652,9 @@ extern "C" { #define SPI_CS3_DIS_V 0x00000001U #define SPI_CS3_DIS_S 3 /** SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS4_DIS (BIT(4)) @@ -650,9 +662,9 @@ extern "C" { #define SPI_CS4_DIS_V 0x00000001U #define SPI_CS4_DIS_S 4 /** SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ #define SPI_CS5_DIS (BIT(5)) @@ -660,9 +672,9 @@ extern "C" { #define SPI_CS5_DIS_V 0x00000001U #define SPI_CS5_DIS_S 5 /** SPI_CK_DIS : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ #define SPI_CK_DIS (BIT(6)) @@ -670,9 +682,9 @@ extern "C" { #define SPI_CK_DIS_V 0x00000001U #define SPI_CK_DIS_S 6 /** SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ #define SPI_MASTER_CS_POL 0x0000003FU @@ -715,9 +727,9 @@ extern "C" { #define SPI_CMD_DTR_EN_V 0x00000001U #define SPI_CMD_DTR_EN_S 19 /** SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ #define SPI_SLAVE_CS_POL (BIT(23)) @@ -732,9 +744,9 @@ extern "C" { #define SPI_DQS_IDLE_EDGE_V 0x00000001U #define SPI_DQS_IDLE_EDGE_S 24 /** SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ #define SPI_CK_IDLE_EDGE (BIT(29)) @@ -742,9 +754,9 @@ extern "C" { #define SPI_CK_IDLE_EDGE_V 0x00000001U #define SPI_CK_IDLE_EDGE_S 29 /** SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ #define SPI_CS_KEEP_ACTIVE (BIT(30)) @@ -765,13 +777,13 @@ extern "C" { */ #define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24) /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN0_MODE 0x00000003U @@ -779,13 +791,13 @@ extern "C" { #define SPI_DIN0_MODE_V 0x00000003U #define SPI_DIN0_MODE_S 0 /** SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN1_MODE 0x00000003U @@ -793,13 +805,13 @@ extern "C" { #define SPI_DIN1_MODE_V 0x00000003U #define SPI_DIN1_MODE_S 2 /** SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ #define SPI_DIN2_MODE 0x00000003U @@ -807,13 +819,13 @@ extern "C" { #define SPI_DIN2_MODE_V 0x00000003U #define SPI_DIN2_MODE_S 4 /** SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -859,9 +871,9 @@ extern "C" { #define SPI_DIN7_MODE_S 14 /** SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ #define SPI_TIMING_HCLK_ACTIVE (BIT(16)) @@ -874,11 +886,11 @@ extern "C" { */ #define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28) /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN0_NUM 0x00000003U @@ -886,11 +898,11 @@ extern "C" { #define SPI_DIN0_NUM_V 0x00000003U #define SPI_DIN0_NUM_S 0 /** SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN1_NUM 0x00000003U @@ -898,12 +910,11 @@ extern "C" { #define SPI_DIN1_NUM_V 0x00000003U #define SPI_DIN1_NUM_S 2 /** SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN2_NUM 0x00000003U @@ -911,12 +922,11 @@ extern "C" { #define SPI_DIN2_NUM_V 0x00000003U #define SPI_DIN2_NUM_S 4 /** SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ #define SPI_DIN3_NUM 0x00000003U @@ -961,9 +971,9 @@ extern "C" { */ #define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c) /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT0_MODE (BIT(0)) @@ -971,9 +981,9 @@ extern "C" { #define SPI_DOUT0_MODE_V 0x00000001U #define SPI_DOUT0_MODE_S 0 /** SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT1_MODE (BIT(1)) @@ -981,9 +991,9 @@ extern "C" { #define SPI_DOUT1_MODE_V 0x00000001U #define SPI_DOUT1_MODE_S 1 /** SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT2_MODE (BIT(2)) @@ -991,9 +1001,9 @@ extern "C" { #define SPI_DOUT2_MODE_V 0x00000001U #define SPI_DOUT2_MODE_S 2 /** SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ #define SPI_DOUT3_MODE (BIT(3)) @@ -1051,18 +1061,18 @@ extern "C" { */ #define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30) /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_OUTFIFO_EMPTY (BIT(0)) #define SPI_DMA_OUTFIFO_EMPTY_M (SPI_DMA_OUTFIFO_EMPTY_V << SPI_DMA_OUTFIFO_EMPTY_S) #define SPI_DMA_OUTFIFO_EMPTY_V 0x00000001U #define SPI_DMA_OUTFIFO_EMPTY_S 0 /** SPI_DMA_INFIFO_FULL : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ #define SPI_DMA_INFIFO_FULL (BIT(1)) #define SPI_DMA_INFIFO_FULL_M (SPI_DMA_INFIFO_FULL_V << SPI_DMA_INFIFO_FULL_S) @@ -1070,9 +1080,9 @@ extern "C" { #define SPI_DMA_INFIFO_FULL_S 1 /** SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ #define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) #define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) @@ -1080,10 +1090,10 @@ extern "C" { #define SPI_DMA_SLV_SEG_TRANS_EN_S 18 /** SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -1095,12 +1105,11 @@ extern "C" { #define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 /** SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -1120,29 +1129,27 @@ extern "C" { #define SPI_RX_EOF_EN_V 0x00000001U #define SPI_RX_EOF_EN_S 21 /** SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_RX_ENA (BIT(27)) #define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) #define SPI_DMA_RX_ENA_V 0x00000001U #define SPI_DMA_RX_ENA_S 27 /** SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ #define SPI_DMA_TX_ENA (BIT(28)) #define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) #define SPI_DMA_TX_ENA_V 0x00000001U #define SPI_DMA_TX_ENA_S 28 /** SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ #define SPI_RX_AFIFO_RST (BIT(29)) @@ -1150,11 +1157,9 @@ extern "C" { #define SPI_RX_AFIFO_RST_V 0x00000001U #define SPI_RX_AFIFO_RST_S 29 /** SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ #define SPI_BUF_AFIFO_RST (BIT(30)) @@ -1162,11 +1167,9 @@ extern "C" { #define SPI_BUF_AFIFO_RST_V 0x00000001U #define SPI_BUF_AFIFO_RST_S 30 /** SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ #define SPI_DMA_AFIFO_RST (BIT(31)) @@ -2135,11 +2138,11 @@ extern "C" { */ #define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0) /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ #define SPI_CLK_MODE 0x00000003U @@ -2147,20 +2150,18 @@ extern "C" { #define SPI_CLK_MODE_V 0x00000003U #define SPI_CLK_MODE_S 0 /** SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ #define SPI_CLK_MODE_13 (BIT(2)) #define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) #define SPI_CLK_MODE_13_V 0x00000001U #define SPI_CLK_MODE_13_S 2 /** SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ #define SPI_RSCK_DATA_OUT (BIT(3)) #define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) @@ -2168,9 +2169,9 @@ extern "C" { #define SPI_RSCK_DATA_OUT_S 3 /** SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) #define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) @@ -2178,9 +2179,9 @@ extern "C" { #define SPI_SLV_RDDMA_BITLEN_EN_S 8 /** SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) #define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) @@ -2188,9 +2189,9 @@ extern "C" { #define SPI_SLV_WRDMA_BITLEN_EN_S 9 /** SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) #define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) @@ -2198,9 +2199,9 @@ extern "C" { #define SPI_SLV_RDBUF_BITLEN_EN_S 10 /** SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ #define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) #define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) @@ -2223,19 +2224,18 @@ extern "C" { #define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000FU #define SPI_DMA_SEG_MAGIC_VALUE_S 22 /** SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ #define SPI_SLAVE_MODE (BIT(26)) #define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) #define SPI_SLAVE_MODE_V 0x00000001U #define SPI_SLAVE_MODE_S 26 /** SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ #define SPI_SOFT_RESET (BIT(27)) @@ -2244,10 +2244,10 @@ extern "C" { #define SPI_SOFT_RESET_S 27 /** SPI_USR_CONF : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ #define SPI_USR_CONF (BIT(28)) #define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) @@ -2255,9 +2255,9 @@ extern "C" { #define SPI_USR_CONF_S 28 /** SPI_MST_FD_WAIT_DMA_TX_DATA : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ #define SPI_MST_FD_WAIT_DMA_TX_DATA (BIT(29)) #define SPI_MST_FD_WAIT_DMA_TX_DATA_M (SPI_MST_FD_WAIT_DMA_TX_DATA_V << SPI_MST_FD_WAIT_DMA_TX_DATA_S) @@ -2295,9 +2295,9 @@ extern "C" { */ #define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8) /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ #define SPI_CLK_EN (BIT(0)) #define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) @@ -2323,7 +2323,7 @@ extern "C" { * Version control */ #define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0) -/** SPI_DATE : R/W; bitpos: [27:0]; default: 36716931; +/** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ #define SPI_DATE 0x0FFFFFFFU diff --git a/components/soc/esp32c61/register/soc/spi_struct.h b/components/soc/esp32c61/register/soc/spi_struct.h index 88690647ed..5ea6f2956f 100644 --- a/components/soc/esp32c61/register/soc/spi_struct.h +++ b/components/soc/esp32c61/register/soc/spi_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,23 +18,23 @@ typedef union { struct { /** conf_bitlen : R/W; bitpos: [17:0]; default: 0; * Configures the SPI_CLK cycles of SPI CONF state. - * Measurement unit: SPI_CLK clock cycle.\\ + * Measurement unit: SPI_CLK clock cycle. * Can be configured in CONF state. */ uint32_t conf_bitlen:18; uint32_t reserved_18:5; /** update : WT; bitpos: [23]; default: 0; * Configures whether or not to synchronize SPI registers from APB clock domain into - * SPI module clock domain. \\ - * 0: Not synchronize \\ - * 1: Synchronize \\ + * SPI module clock domain. + * 0: Not synchronize + * 1: Synchronize * This bit is only used in SPI master transfer. */ uint32_t update:1; /** usr : R/W/SC; bitpos: [24]; default: 0; - * Configures whether or not to enable user-defined command. \\ - * 0: Not enable \\ - * 1: Enable \\ + * Configures whether or not to enable user-defined command. + * 0: Not enable + * 1: Enable * An SPI operation will be triggered when the bit is set. This bit will be cleared * once the operation is done. Can not be changed by CONF_buf. */ @@ -64,17 +64,17 @@ typedef union { typedef union { struct { /** doutdin : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable full-duplex communication. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable full-duplex communication. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t doutdin:1; uint32_t reserved_1:2; /** qpi_mode : R/W/SS/SC; bitpos: [3]; default: 0; - * Configures whether or not to enable QPI mode. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable QPI mode. + * 0: Disable + * 1: Enable * This configuration is applicable when the SPI controller works as master or slave. * Can be configured in CONF state. */ @@ -85,51 +85,50 @@ typedef union { */ uint32_t opi_mode:1; /** tsck_i_edge : R/W; bitpos: [5]; default: 0; - * Configures whether or not to change the polarity of TSCK in slave transfer. \\ - * 0: TSCK = SPI_CK_I \\ - * 1: TSCK = !SPI_CK_I \\ + * Configures whether or not to change the polarity of TSCK in slave transfer. + * 0: TSCK = SPI_CK_I + * 1: TSCK = !SPI_CK_I */ uint32_t tsck_i_edge:1; /** cs_hold : R/W; bitpos: [6]; default: 1; - * Configures whether or not to keep SPI CS low when SPI is in DONE state. \\ - * 0: Not keep low \\ - * 1: Keep low \\ + * Configures whether or not to keep SPI CS low when SPI is in DONE state. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_hold:1; /** cs_setup : R/W; bitpos: [7]; default: 1; - * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable SPI CS when SPI is in prepare (PREP) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t cs_setup:1; /** rsck_i_edge : R/W; bitpos: [8]; default: 0; - * Configures whether or not to change the polarity of RSCK in slave transfer. \\ - * 0: RSCK = !SPI_CK_I \\ - * 1: RSCK = SPI_CK_I \\ + * Configures whether or not to change the polarity of RSCK in slave transfer. + * 0: RSCK = !SPI_CK_I + * 1: RSCK = SPI_CK_I */ uint32_t rsck_i_edge:1; /** ck_out_edge : R/W; bitpos: [9]; default: 0; * Configures SPI clock mode together with SPI_CK_IDLE_EDGE. - * Can be configured in CONF state. For more information, see Section link. + * Can be configured in CONF state. For more information, see Section . */ uint32_t ck_out_edge:1; uint32_t reserved_10:2; /** fwrite_dual : R/W; bitpos: [12]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data phase in write - * operations.\\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_dual:1; /** fwrite_quad : R/W; bitpos: [13]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data phase in write - * operations. \\ - * 0: Not enable \\ - * 1: Enable \\ + * operations. + * 0: Not enable + * 1: Enable * Can be configured in CONF state. */ uint32_t fwrite_quad:1; @@ -140,79 +139,79 @@ typedef union { uint32_t fwrite_oct:1; /** usr_conf_nxt : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the CONF state for the next transaction - * (segment) in a configurable segmented transfer. \\ + * (segment) in a configurable segmented transfer. * 0: this transfer will end after the current transaction (segment) is finished. Or - * this is not a configurable segmented transfer. \\ + * this is not a configurable segmented transfer. * 1: this configurable segmented transfer will continue its next transaction - * (segment). \\ + * (segment). * Can be configured in CONF state. */ uint32_t usr_conf_nxt:1; uint32_t reserved_16:1; /** sio : R/W; bitpos: [17]; default: 0; * Configures whether or not to enable 3-line half-duplex communication, where MOSI - * and MISO signals share the same pin.\\ - * 0: Disable \\ - * 1: Enable \\ + * and MISO signals share the same pin. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t sio:1; uint32_t reserved_18:6; /** usr_miso_highpart : R/W; bitpos: [24]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in read-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso_highpart:1; /** usr_mosi_highpart : R/W; bitpos: [25]; default: 0; * Configures whether or not to enable high part mode, i.e., only access to high part - * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. \\ - * 0: Disable \\ - * 1: Enable \\ + * of the buffers: SPI_W8_REG ~ SPI_W15_REG in write-data phase. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi_highpart:1; /** usr_dummy_idle : R/W; bitpos: [26]; default: 0; - * Configures whether or not to disable SPI clock in DUMMY state. \\ - * 0: Not disable \\ - * 1: Disable \\ + * Configures whether or not to disable SPI clock in DUMMY state. + * 0: Not disable + * 1: Disable * Can be configured in CONF state. */ uint32_t usr_dummy_idle:1; /** usr_mosi : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable the write-data (DOUT) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the write-data (DOUT) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_mosi:1; /** usr_miso : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable the read-data (DIN) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the read-data (DIN) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_miso:1; /** usr_dummy : R/W; bitpos: [29]; default: 0; - * Configures whether or not to enable the DUMMY state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the DUMMY state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_dummy:1; /** usr_addr : R/W; bitpos: [30]; default: 0; - * Configures whether or not to enable the address (ADDR) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the address (ADDR) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_addr:1; /** usr_command : R/W; bitpos: [31]; default: 1; - * Configures whether or not to enable the command (CMD) state of an operation. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable the command (CMD) state of an operation. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t usr_command:1; @@ -227,28 +226,28 @@ typedef union { struct { /** usr_dummy_cyclelen : R/W; bitpos: [7:0]; default: 7; * Configures the length of DUMMY state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is (the expected cycle number - 1). Can be configured in CONF state. */ uint32_t usr_dummy_cyclelen:8; uint32_t reserved_8:8; /** mst_wfull_err_end_en : R/W; bitpos: [16]; default: 1; * Configures whether or not to end the SPI transfer when SPI RX AFIFO wfull error - * occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_wfull_err_end_en:1; /** cs_setup_time : R/W; bitpos: [21:17]; default: 0; * Configures the length of prepare (PREP) state. - * Measurement unit: SPI_CLK clock cycles.\\ + * Measurement unit: SPI_CLK clock cycles. * This value is equal to the expected cycles - 1. This field is used together with * SPI_CS_SETUP. Can be configured in CONF state. */ uint32_t cs_setup_time:5; /** cs_hold_time : R/W; bitpos: [26:22]; default: 1; * Configures the delay cycles of CS pin. - * Measurement unit: SPI_CLK clock cycles. \\ + * Measurement unit: SPI_CLK clock cycles. * This field is used together with SPI_CS_HOLD. Can be configured in CONF state. */ uint32_t cs_hold_time:5; @@ -274,9 +273,9 @@ typedef union { uint32_t reserved_16:11; /** mst_rempty_err_end_en : R/W; bitpos: [27]; default: 1; * Configures whether or not to end the SPI transfer when SPI TX AFIFO read empty - * error occurs in master full-/half-duplex transfers. \\ - * 0: Not end \\ - * 1: End \\ + * error occurs in master full-/half-duplex transfers. + * 0: Not end + * 1: End */ uint32_t mst_rempty_err_end_en:1; /** usr_command_bitlen : R/W; bitpos: [31:28]; default: 7; @@ -297,122 +296,122 @@ typedef union { struct { uint32_t reserved_0:3; /** dummy_out : R/W; bitpos: [3]; default: 0; - * Configures whether or not to output the FSPI bus signals in DUMMY state. \\ - * 0: Not output \\ - * 1: Output \\ + * Configures whether or not to output the FSPI bus signals in DUMMY state. + * 0: Not output + * 1: Output * Can be configured in CONF state. */ uint32_t dummy_out:1; uint32_t reserved_4:1; /** faddr_dual : R/W; bitpos: [5]; default: 0; - * Configures whether or not to enable 2-bit mode during address (ADDR) state.\\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_dual:1; /** faddr_quad : R/W; bitpos: [6]; default: 0; - * Configures whether or not to enable 4-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_quad:1; /** faddr_oct : HRO; bitpos: [7]; default: 0; - * Configures whether or not to enable 8-bit mode during address (ADDR) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during address (ADDR) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t faddr_oct:1; /** fcmd_dual : R/W; bitpos: [8]; default: 0; - * Configures whether or not to enable 2-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 2-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_dual:1; /** fcmd_quad : R/W; bitpos: [9]; default: 0; - * Configures whether or not to enable 4-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 4-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_quad:1; /** fcmd_oct : HRO; bitpos: [10]; default: 0; - * Configures whether or not to enable 8-bit mode during command (CMD) state. \\ - * 0: Disable \\ - * 1: Enable \\ + * Configures whether or not to enable 8-bit mode during command (CMD) state. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fcmd_oct:1; uint32_t reserved_11:3; /** fread_dual : R/W; bitpos: [14]; default: 0; * Configures whether or not to enable the 2-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_dual:1; /** fread_quad : R/W; bitpos: [15]; default: 0; * Configures whether or not to enable the 4-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_quad:1; /** fread_oct : HRO; bitpos: [16]; default: 0; * Configures whether or not to enable the 8-bit mode of read-data (DIN) state in read - * operations. \\ - * 0: Disable \\ - * 1: Enable \\ + * operations. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t fread_oct:1; uint32_t reserved_17:1; /** q_pol : R/W; bitpos: [18]; default: 1; - * Configures MISO line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MISO line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t q_pol:1; /** d_pol : R/W; bitpos: [19]; default: 1; - * Configures MOSI line polarity. \\ - * 0: Low \\ - * 1: High \\ + * Configures MOSI line polarity. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t d_pol:1; /** hold_pol : R/W; bitpos: [20]; default: 1; - * Configures SPI_HOLD output value when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures SPI_HOLD output value when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t hold_pol:1; /** wp_pol : R/W; bitpos: [21]; default: 1; - * Configures the output value of write-protect signal when SPI is in idle. \\ - * 0: Output low \\ - * 1: Output high \\ + * Configures the output value of write-protect signal when SPI is in idle. + * 0: Output low + * 1: Output high * Can be configured in CONF state. */ uint32_t wp_pol:1; uint32_t reserved_22:1; /** rd_bit_order : R/W; bitpos: [24:23]; default: 0; - * Configures the bit order in read-data (MISO) state. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * Configures the bit order in read-data (MISO) state. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t rd_bit_order:2; /** wr_bit_order : R/W; bitpos: [26:25]; default: 0; * Configures the bit order in command (CMD), address (ADDR), and write-data (MOSI) - * states. \\ - * 0: MSB first \\ - * 1: LSB first \\ + * states. + * 0: MSB first + * 1: LSB first * Can be configured in CONF state. */ uint32_t wr_bit_order:2; @@ -444,58 +443,58 @@ typedef union { typedef union { struct { /** cs0_dis : R/W; bitpos: [0]; default: 0; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs0_dis:1; /** cs1_dis : R/W; bitpos: [1]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs1_dis:1; /** cs2_dis : R/W; bitpos: [2]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs2_dis:1; /** cs3_dis : R/W; bitpos: [3]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs3_dis:1; /** cs4_dis : R/W; bitpos: [4]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs4_dis:1; /** cs5_dis : R/W; bitpos: [5]; default: 1; - * Configures whether or not to disable SPI_CS$n pin.\\ - * 0: SPI_CS$n signal is from/to SPI_CS$n pin.\\ - * 1: Disable SPI_CS$n pin.\\ + * Configures whether or not to disable SPI_CS$n pin. + * 0: SPI_CS$n signal is from/to SPI_CS$n pin. + * 1: Disable SPI_CS$n pin. * Can be configured in CONF state. */ uint32_t cs5_dis:1; /** ck_dis : R/W; bitpos: [6]; default: 0; - * Configures whether or not to disable SPI_CLK output.\\ - * 0: Enable\\ - * 1: Disable\\ + * Configures whether or not to disable SPI_CLK output. + * 0: Enable + * 1: Disable * Can be configured in CONF state. */ uint32_t ck_dis:1; /** master_cs_pol : R/W; bitpos: [12:7]; default: 0; - * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer.\\ - * 0: SPI_CS$n is low active.\\ - * 1: SPI_CS$n is high active.\\ + * Configures the polarity of SPI_CS$n ($n = 0-5) line in master transfer. + * 0: SPI_CS$n is low active. + * 1: SPI_CS$n is high active. * Can be configured in CONF state. */ uint32_t master_cs_pol:6; @@ -525,9 +524,9 @@ typedef union { uint32_t cmd_dtr_en:1; uint32_t reserved_20:3; /** slave_cs_pol : R/W; bitpos: [23]; default: 0; - * Configures whether or not invert SPI slave input CS polarity.\\ - * 0: Not change\\ - * 1: Invert\\ + * Configures whether or not invert SPI slave input CS polarity. + * 0: Not change + * 1: Invert * Can be configured in CONF state. */ uint32_t slave_cs_pol:1; @@ -537,16 +536,16 @@ typedef union { uint32_t dqs_idle_edge:1; uint32_t reserved_25:4; /** ck_idle_edge : R/W; bitpos: [29]; default: 0; - * Configures the level of SPI_CLK line when GP-SPI2 is in idle.\\ - * 0: Low\\ - * 1: High\\ + * Configures the level of SPI_CLK line when GP-SPI2 is in idle. + * 0: Low + * 1: High * Can be configured in CONF state. */ uint32_t ck_idle_edge:1; /** cs_keep_active : R/W; bitpos: [30]; default: 0; - * Configures whether or not to keep the SPI_CS line low.\\ - * 0: Not keep low\\ - * 1: Keep low\\ + * Configures whether or not to keep the SPI_CS line low. + * 0: Not keep low + * 1: Keep low * Can be configured in CONF state. */ uint32_t cs_keep_active:1; @@ -565,31 +564,31 @@ typedef union { typedef union { struct { /** dma_outfifo_empty : RO; bitpos: [0]; default: 1; - * Represents whether or not the DMA TX FIFO is ready for sending data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA TX FIFO is ready for sending data. + * 0: Ready + * 1: Not ready */ uint32_t dma_outfifo_empty:1; /** dma_infifo_full : RO; bitpos: [1]; default: 1; - * Represents whether or not the DMA RX FIFO is ready for receiving data.\\ - * 0: Ready\\ - * 1: Not ready\\ + * Represents whether or not the DMA RX FIFO is ready for receiving data. + * 0: Ready + * 1: Not ready */ uint32_t dma_infifo_full:1; uint32_t reserved_2:16; /** dma_slv_seg_trans_en : R/W; bitpos: [18]; default: 0; * Configures whether or not to enable DMA-controlled segmented transfer in slave - * half-duplex communication.\\ - * 0: Disable\\ - * 1: Enable\\ + * half-duplex communication. + * 0: Disable + * 1: Enable */ uint32_t dma_slv_seg_trans_en:1; /** slv_rx_seg_trans_clr_en : R/W; bitpos: [19]; default: 0; * In slave segmented transfer, if the size of the DMA RX buffer is smaller than the - * size of the received data, \\1: the data in all the following Wr_DMA transactions - * will not be received\\ 0: the data in this Wr_DMA transaction will not be received, - * but in the following transactions,\\ - * + * size of the received data, + * 1: the data in all the following Wr_DMA transactions will not be received + * 0: the data in this Wr_DMA transaction will not be received, but in the following + * transactions, * - if the size of DMA RX buffer is not 0, the data in following Wr_DMA transactions * will be received. * - if the size of DMA RX buffer is 0, the data in following Wr_DMA transactions will @@ -598,12 +597,11 @@ typedef union { uint32_t slv_rx_seg_trans_clr_en:1; /** slv_tx_seg_trans_clr_en : R/W; bitpos: [20]; default: 0; * In slave segmented transfer, if the size of the DMA TX buffer is smaller than the - * size of the transmitted data,\\ + * size of the transmitted data, * 1: the data in the following transactions will not be updated, i.e. the old data is - * transmitted repeatedly.\\ + * transmitted repeatedly. * 0: the data in this transaction will not be updated. But in the following - * transactions,\\ - * + * transactions, * - if new data is filled in DMA TX FIFO, new data will be transmitted. * - if no new data is filled in DMA TX FIFO, no new data will be transmitted. */ @@ -618,41 +616,35 @@ typedef union { uint32_t rx_eof_en:1; uint32_t reserved_22:5; /** dma_rx_ena : R/W; bitpos: [27]; default: 0; - * Configures whether or not to enable DMA-controlled receive data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled receive data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_rx_ena:1; /** dma_tx_ena : R/W; bitpos: [28]; default: 0; - * Configures whether or not to enable DMA-controlled send data transfer.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable DMA-controlled send data transfer. + * 0: Disable + * 1: Enable */ uint32_t dma_tx_ena:1; /** rx_afifo_rst : WT; bitpos: [29]; default: 0; - * Configures whether or not to reset spi_rx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset spi_rx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * spi_rx_afifo is used to receive data in SPI master and slave transfer. */ uint32_t rx_afifo_rst:1; /** buf_afifo_rst : WT; bitpos: [30]; default: 0; - * Configures whether or not to reset buf_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset buf_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * buf_tx_afifo is used to send data out in CPU-controlled master and slave transfer. */ uint32_t buf_afifo_rst:1; /** dma_afifo_rst : WT; bitpos: [31]; default: 0; - * Configures whether or not to reset dma_tx_afifo as shown in Figure link and in Figure link.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether or not to reset dma_tx_afifo as shown in Figure . + * 0: Not reset + * 1: Reset * dma_tx_afifo is used to send data out in DMA-controlled slave transfer. */ uint32_t dma_afifo_rst:1; @@ -666,55 +658,53 @@ typedef union { typedef union { struct { /** clk_mode : R/W; bitpos: [1:0]; default: 0; - * Configures SPI clock mode.\\ - * 0: SPI clock is off when CS becomes inactive.\\ - * 1: SPI clock is delayed one cycle after CS becomes inactive.\\ - * 2: SPI clock is delayed two cycles after CS becomes inactive.\\ - * 3: SPI clock is always on.\\ + * Configures SPI clock mode. + * 0: SPI clock is off when CS becomes inactive. + * 1: SPI clock is delayed one cycle after CS becomes inactive. + * 2: SPI clock is delayed two cycles after CS becomes inactive. + * 3: SPI clock is always on. * Can be configured in CONF state. */ uint32_t clk_mode:2; /** clk_mode_13 : R/W; bitpos: [2]; default: 0; - * Configure clock mode.\\ - * 0: Support SPI clock mode 0 or 2. See Table link.\\ - * 1: Support SPI clock mode 1 or 3. See Table link.\\ + * Configure clock mode. + * 0: Support SPI clock mode 0 or 2. See Table . + * 1: Support SPI clock mode 1 or 3. See Table . */ uint32_t clk_mode_13:1; /** rsck_data_out : R/W; bitpos: [3]; default: 0; - * Configures the edge of output data.\\ - * 0: Output data at TSCK rising edge.\\ - * 1: Output data at RSCK rising edge.\\ + * Configures the edge of output data. + * 0: Output data at TSCK rising edge. + * 1: Output data at RSCK rising edge. */ uint32_t rsck_data_out:1; uint32_t reserved_4:4; /** slv_rddma_bitlen_en : R/W; bitpos: [8]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rddma_bitlen_en:1; /** slv_wrdma_bitlen_en : R/W; bitpos: [9]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_DMA transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_DMA transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrdma_bitlen_en:1; /** slv_rdbuf_bitlen_en : R/W; bitpos: [10]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Rd_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Rd_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_rdbuf_bitlen_en:1; /** slv_wrbuf_bitlen_en : R/W; bitpos: [11]; default: 0; * Configures whether or not to use SPI_SLV_DATA_BITLEN to store the data bit length - * of Wr_BUF transfer.\\ - * 0: Not use\\ - * 1: Use\\ + * of Wr_BUF transfer. + * 0: Not use + * 1: Use */ uint32_t slv_wrbuf_bitlen_en:1; /** slv_last_byte_strb : R/SS; bitpos: [19:12]; default: 0; @@ -729,32 +719,31 @@ typedef union { */ uint32_t dma_seg_magic_value:4; /** slave_mode : R/W; bitpos: [26]; default: 0; - * Configures SPI work mode.\\ - * 0: Master\\ - * 1: Slave\\ + * Configures SPI work mode. + * 0: Master + * 1: Slave */ uint32_t slave_mode:1; /** soft_reset : WT; bitpos: [27]; default: 0; - * Configures whether to reset the SPI clock line, CS line, and data line via - * software.\\ - * 0: Not reset\\ - * 1: Reset\\ + * Configures whether to reset the SPI clock line, CS line, and data line via software. + * 0: Not reset + * 1: Reset * Can be configured in CONF state. */ uint32_t soft_reset:1; /** usr_conf : R/W; bitpos: [28]; default: 0; * Configures whether or not to enable the CONF state of current DMA-controlled - * configurable segmented transfer.\\ + * configurable segmented transfer. * 0: No effect, which means the current transfer is not a configurable segmented - * transfer.\\ - * 1: Enable, which means a configurable segmented transfer is started.\\ + * transfer. + * 1: Enable, which means a configurable segmented transfer is started. */ uint32_t usr_conf:1; /** mst_fd_wait_dma_tx_data : R/W; bitpos: [29]; default: 0; * Configures whether or not to wait DMA TX data gets ready before starting SPI - * transfer in master full-duplex transfer.\\ - * 0: Not wait\\ - * 1: Wait\\ + * transfer in master full-duplex transfer. + * 0: Not wait + * 1: Wait */ uint32_t mst_fd_wait_dma_tx_data:1; uint32_t reserved_30:2; @@ -799,14 +788,14 @@ typedef union { * Configures the duty cycle of SPI_CLK (high level) in master transfer. * It's recommended to configure this value to floor((SPI_CLKCNT_N + 1)/2 - 1). * floor() here is to round a number down, e.g., floor(2.2) = 2. In slave mode, it - * must be 0. \\ + * must be 0. * Can be configured in CONF state. */ uint32_t clkcnt_h:6; /** clkcnt_n : R/W; bitpos: [17:12]; default: 3; * Configures the divider of SPI_CLK in master transfer. * SPI_CLK frequency is $f_{\textrm{apb_clk}}$/(SPI_CLKDIV_PRE + 1)/(SPI_CLKCNT_N + - * 1). \\ + * 1). * Can be configured in CONF state. */ uint32_t clkcnt_n:6; @@ -815,11 +804,19 @@ typedef union { * Can be configured in CONF state. */ uint32_t clkdiv_pre:4; - uint32_t reserved_22:9; + uint32_t reserved_22:8; + /** clk_edge_sel : R/W; bitpos: [30]; default: 0; + * Configures use standard clock sampling edge or delay the sampling edge by half a + * cycle in master transfer. + * 0: clock sampling edge is delayed by half a cycle. + * 1: clock sampling edge is standard. + * Can be configured in CONF state. + */ + uint32_t clk_edge_sel:1; /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1; - * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\ - * 0: SPI_CLK is divided from APB_CLK.\\ - * 1: SPI_CLK is equal to APB_CLK.\\ + * Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer. + * 0: SPI_CLK is divided from APB_CLK. + * 1: SPI_CLK is equal to APB_CLK. * Can be configured in CONF state. */ uint32_t clk_equ_sysclk:1; @@ -833,9 +830,9 @@ typedef union { typedef union { struct { /** clk_en : R/W; bitpos: [0]; default: 0; - * Configures whether or not to enable clock gate.\\ - * 0: Disable\\ - * 1: Enable\\ + * Configures whether or not to enable clock gate. + * 0: Disable + * 1: Enable */ uint32_t clk_en:1; /** mst_clk_active : R/W; bitpos: [1]; default: 0; @@ -860,46 +857,46 @@ typedef union { typedef union { struct { /** din0_mode : R/W; bitpos: [1:0]; default: 0; - * Configures the input mode for FSPID signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPID signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN0_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN0_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din0_mode:2; /** din1_mode : R/W; bitpos: [3:2]; default: 0; - * Configures the input mode for FSPIQ signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIQ signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN1_NUM+1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN1_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din1_mode:2; /** din2_mode : R/W; bitpos: [5:4]; default: 0; - * Configures the input mode for FSPIWP signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIWP signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN2_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN2_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. */ uint32_t din2_mode:2; /** din3_mode : R/W; bitpos: [7:6]; default: 0; - * Configures the input mode for FSPIHD signal.\\ - * 0: Input without delay\\ - * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst\\ + * Configures the input mode for FSPIHD signal. + * 0: Input without delay + * 1: Input at the (SPI_DIN3_NUM + 1)th falling edge of clk_spi_mst * 2: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * rising edge cycle\\ + * rising edge cycle * 3: Input at the (SPI_DIN3_NUM + 1)th rising edge of clk_hclk plus one clk_spi_mst - * falling edge cycle\\ + * falling edge cycle * Can be configured in CONF state. * */ @@ -930,9 +927,9 @@ typedef union { uint32_t din7_mode:2; /** timing_hclk_active : R/W; bitpos: [16]; default: 0; * Configures whether or not to enable HCLK (high-frequency clock) in SPI input timing - * module.\\ - * 0: Disable\\ - * 1: Enable\\ + * module. + * 0: Disable + * 1: Enable * Can be configured in CONF state. */ uint32_t timing_hclk_active:1; @@ -947,40 +944,38 @@ typedef union { typedef union { struct { /** din0_num : R/W; bitpos: [1:0]; default: 0; - * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPID based on the setting of SPI_DIN0_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din0_num:2; /** din1_num : R/W; bitpos: [3:2]; default: 0; - * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIQ based on the setting of SPI_DIN1_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din1_num:2; /** din2_num : R/W; bitpos: [5:4]; default: 0; - * Configures the delays to input signal FSPIWP based on the setting of - * SPI_DIN2_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIWP based on the setting of SPI_DIN2_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din2_num:2; /** din3_num : R/W; bitpos: [7:6]; default: 0; - * Configures the delays to input signal FSPIHD based on the setting of - * SPI_DIN3_MODE.\\ - * 0: Delayed by 1 clock cycle\\ - * 1: Delayed by 2 clock cycles\\ - * 2: Delayed by 3 clock cycles\\ - * 3: Delayed by 4 clock cycles\\ + * Configures the delays to input signal FSPIHD based on the setting of SPI_DIN3_MODE. + * 0: Delayed by 1 clock cycle + * 1: Delayed by 2 clock cycles + * 2: Delayed by 3 clock cycles + * 3: Delayed by 4 clock cycles * Can be configured in CONF state. */ uint32_t din3_num:2; @@ -1015,30 +1010,30 @@ typedef union { typedef union { struct { /** dout0_mode : R/W; bitpos: [0]; default: 0; - * Configures the output mode for FSPID signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPID signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout0_mode:1; /** dout1_mode : R/W; bitpos: [1]; default: 0; - * Configures the output mode for FSPIQ signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIQ signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout1_mode:1; /** dout2_mode : R/W; bitpos: [2]; default: 0; - * Configures the output mode for FSPIWP signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIWP signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout2_mode:1; /** dout3_mode : R/W; bitpos: [3]; default: 0; - * Configures the output mode for FSPIHD signal.\\ - * 0: Output without delay\\ - * 1: Output with a delay of a SPI module clock cycle at its falling edge\\ + * Configures the output mode for FSPIHD signal. + * 0: Output without delay + * 1: Output with a delay of a SPI module clock cycle at its falling edge * Can be configured in CONF state. */ uint32_t dout3_mode:1; @@ -1556,12 +1551,12 @@ typedef union { /** Group: CPU-controlled data buffer */ /** Type of wn register - * SPI CPU-controlled buffer n + * SPI CPU-controlled buffer0 */ typedef union { struct { /** buf : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer + * 32-bit data buffer $n. */ uint32_t buf:32; }; @@ -1575,7 +1570,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [27:0]; default: 36716931; + /** date : R/W; bitpos: [27:0]; default: 37761424; * Version control register. */ uint32_t date:28; diff --git a/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h index 255d08ed4b..0bbfd5c36e 100644 --- a/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h +++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -540,13 +540,6 @@ extern "C" { * PHY hardware configuration. */ #define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) -/** USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; - * Select internal/external PHY - */ -#define USB_SERIAL_JTAG_PHY_SEL (BIT(0)) -#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S) -#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001U -#define USB_SERIAL_JTAG_PHY_SEL_S 0 /** USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0; * Enable software control USB D+ D- exchange */ @@ -640,6 +633,14 @@ extern "C" { #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V << USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S) #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x00000001U #define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 15 +/** USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL (BIT(16)) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_M (USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V << USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S) +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_V 0x00000001U +#define USB_SERIAL_JTAG_USB_PHY_TX_EDGE_SEL_S 16 /** USB_SERIAL_JTAG_TEST_REG register * Registers used for debugging the PHY. @@ -1215,7 +1216,7 @@ extern "C" { * Date register */ #define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) -/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 36770368; +/** USB_SERIAL_JTAG_DATE : R/W; bitpos: [31:0]; default: 37822848; * register version. */ #define USB_SERIAL_JTAG_DATE 0xFFFFFFFFU diff --git a/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h index f53954885d..328eb1375a 100644 --- a/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h +++ b/components/soc/esp32c61/register/soc/usb_serial_jtag_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -23,7 +23,8 @@ typedef union { * can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know * how many data is received, then read data from UART Rx FIFO. */ - uint32_t rdwr_byte:32; + uint32_t rdwr_byte:8; + uint32_t reserved_8:24; }; uint32_t val; } usb_serial_jtag_ep1_reg_t; @@ -59,6 +60,7 @@ typedef union { struct { /** phy_sel : R/W; bitpos: [0]; default: 0; * Select internal/external PHY + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t phy_sel:1; /** exchg_pins_override : R/W; bitpos: [1]; default: 0; @@ -115,7 +117,12 @@ typedef union { * through GPIO Matrix. */ uint32_t usb_jtag_bridge_en:1; - uint32_t reserved_16:16; + /** usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0; + * Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at + * clock negative edge. 1: tx output at clock positive edge. + */ + uint32_t usb_phy_tx_edge_sel:1; + uint32_t reserved_17:15; }; uint32_t val; } usb_serial_jtag_conf0_reg_t; @@ -130,7 +137,7 @@ typedef union { */ uint32_t test_enable:1; /** test_usb_oe : R/W; bitpos: [1]; default: 0; - * USB pad output enable in test + * USB pad oen in test */ uint32_t test_usb_oe:1; /** test_tx_dp : R/W; bitpos: [2]; default: 0; @@ -925,7 +932,7 @@ typedef union { */ typedef union { struct { - /** date : R/W; bitpos: [31:0]; default: 36770368; + /** date : R/W; bitpos: [31:0]; default: 37822848; * register version. */ uint32_t date:32; diff --git a/components/soc/esp32c61/rtc_io_periph.c b/components/soc/esp32c61/rtc_io_periph.c index d997a25da7..3f94474184 100644 --- a/components/soc/esp32c61/rtc_io_periph.c +++ b/components/soc/esp32c61/rtc_io_periph.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -32,4 +32,9 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = { -1,//GPIO22 -1,//GPIO23 -1,//GPIO24 + -1,//GPIO25 + -1,//GPIO26 + -1,//GPIO27 + -1,//GPIO28 + -1,//GPIO29 }; diff --git a/components/soc/esp32h2/include/soc/apm_defs.h b/components/soc/esp32h2/include/soc/apm_defs.h new file mode 100644 index 0000000000..8abbce9bac --- /dev/null +++ b/components/soc/esp32h2/include/soc/apm_defs.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#include "esp_bit_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Number of paths for each supported APM controller */ +#define APM_CTRL_HP_APM_PATH_NUM (4) +#define APM_CTRL_LP_APM_PATH_NUM (1) +/* Number of regions for each supported APM controller */ +#define APM_CTRL_HP_APM_REGION_NUM (16) +#define APM_CTRL_LP_APM_REGION_NUM (2) + +/* Register offset for TEE mode control */ +#define APM_TEE_MODE_CTRL_OFFSET (0x04) +/* Register offset between region bound address registers */ +#define APM_REGION_ADDR_OFFSET (0x0C) +/* Register offset between region pms attribute registers */ +#define APM_REGION_PMS_ATTR_OFFSET (0x0C) +/* Register offset between exception info registers */ +#define APM_EXCP_INFO_OFFSET (0x10) + +/* Bit to clear exception status */ +#define APM_EXCP_STATUS_CLR_BIT (BIT(0)) + +/* APM controller masters mask */ +#define APM_MASTER_MASK_ALL (0x03CD0075U) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index efd4644e31..a101230a2c 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -376,7 +376,7 @@ #define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */ #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */ #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */ -#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission. Only avliable in chip version above 1.2 */ +#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission. Note, 1 data-width loop transmission only avliable in chip version above 1.2 */ #define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */ #define SOC_PARLIO_SUPPORT_SPI_LCD 1 /*!< Support to drive SPI interfaced LCD */ diff --git a/components/soc/esp32h2/register/soc/io_mux_reg.h b/components/soc/esp32h2/register/soc/io_mux_reg.h index 4bbb466906..c19f3de9e0 100644 --- a/components/soc/esp32h2/register/soc/io_mux_reg.h +++ b/components/soc/esp32h2/register/soc/io_mux_reg.h @@ -163,7 +163,6 @@ #define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function #define MAX_PAD_GPIO_NUM 27 #define MAX_GPIO_NUM 31 -#define HIGH_IO_HOLD_BIT_SHIFT 32 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE diff --git a/components/soc/esp32h21/register/soc/io_mux_reg.h b/components/soc/esp32h21/register/soc/io_mux_reg.h index 55266e5e92..909f26160b 100644 --- a/components/soc/esp32h21/register/soc/io_mux_reg.h +++ b/components/soc/esp32h21/register/soc/io_mux_reg.h @@ -150,7 +150,6 @@ extern "C" { #define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function #define MAX_PAD_GPIO_NUM 25 #define MAX_GPIO_NUM 29 -#define HIGH_IO_HOLD_BIT_SHIFT 32 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE diff --git a/components/soc/esp32h4/register/soc/io_mux_reg.h b/components/soc/esp32h4/register/soc/io_mux_reg.h index 2254ec5c4d..9dc982fa4f 100644 --- a/components/soc/esp32h4/register/soc/io_mux_reg.h +++ b/components/soc/esp32h4/register/soc/io_mux_reg.h @@ -157,7 +157,6 @@ extern "C" { #define MAX_RTC_GPIO_NUM 5 #define MAX_PAD_GPIO_NUM 39 #define MAX_GPIO_NUM 43 -#define HIGH_IO_HOLD_BIT_SHIFT 32 #define GPIO_NUM_IN_FORCE_0 0x60 #define GPIO_NUM_IN_FORCE_1 0x40 diff --git a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in index 3e880b3787..ac379a8a95 100644 --- a/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32p4/include/soc/Kconfig.soc_caps.in @@ -1831,6 +1831,10 @@ config SOC_EFUSE_ECDSA_KEY bool default y +config SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT + bool + default y + config SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY bool default y diff --git a/components/soc/esp32p4/include/soc/soc_caps.h b/components/soc/esp32p4/include/soc/soc_caps.h index 86dad09568..2244c625d7 100644 --- a/components/soc/esp32p4/include/soc/soc_caps.h +++ b/components/soc/esp32p4/include/soc/soc_caps.h @@ -671,8 +671,10 @@ #define SOC_EFUSE_ECDSA_KEY 1 /*-------------------------- Key Manager CAPS----------------------------*/ -#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */ -#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */ +#define SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT 1 /*!< Key manager supports key deployment */ +#define SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY 1 /*!< Key manager responsible to deploy ECDSA key */ +#define SOC_KEY_MANAGER_FE_KEY_DEPLOY 1 /*!< Key manager responsible to deploy Flash Encryption key */ + /*-------------------------- Secure Boot CAPS----------------------------*/ #define SOC_SECURE_BOOT_V2_RSA 1 #define SOC_SECURE_BOOT_V2_ECC 1 diff --git a/components/soc/esp32p4/register/soc/io_mux_reg.h b/components/soc/esp32p4/register/soc/io_mux_reg.h index d7eba33c2c..73468f73f5 100644 --- a/components/soc/esp32p4/register/soc/io_mux_reg.h +++ b/components/soc/esp32p4/register/soc/io_mux_reg.h @@ -197,7 +197,6 @@ #define MAX_RTC_GPIO_NUM 15 #define MAX_PAD_GPIO_NUM 54 #define MAX_GPIO_NUM 56 -#define HIGH_IO_HOLD_BIT_SHIFT 32 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE diff --git a/components/soc/esp32p4/register/soc/keymng_reg.h b/components/soc/esp32p4/register/soc/keymng_reg.h index a8f03edc6e..cfb0f9c12b 100644 --- a/components/soc/esp32p4/register/soc/keymng_reg.h +++ b/components/soc/esp32p4/register/soc/keymng_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -239,6 +239,21 @@ extern "C" { #define KEYMNG_KEY_PURPOSE_V 0x0000000FU #define KEYMNG_KEY_PURPOSE_S 3 +#define KEYMNG_KEY_PURPOSE_ECDSA (BIT(0)) +#define KEYMNG_KEY_PURPOSE_ECDSA_M (KEYMNG_KEY_PURPOSE_ECDSA_V << KEYMNG_KEY_PURPOSE_ECDSA_S) +#define KEYMNG_KEY_PURPOSE_ECDSA_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_ECDSA_S 0 + +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1 (BIT(1)) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_1_S 1 + +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2 (BIT(2)) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_M (KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V << KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S) +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_V 0x00000001U +#define KEYMNG_KEY_PURPOSE_XTS_AES_256_2_S 2 + /** KEYMNG_START_REG register * Key Manager control register */ diff --git a/components/spi_flash/Kconfig b/components/spi_flash/Kconfig index 5a3bcefa75..724a5a4819 100644 --- a/components/spi_flash/Kconfig +++ b/components/spi_flash/Kconfig @@ -109,6 +109,18 @@ menu "Main Flash configuration" This config is used for setting Tsus parameter. Tsus means CS# high to next command after suspend. You can refer to the chapter of AC CHARACTERISTICS of flash datasheet. + config SPI_FLASH_SUSPEND_TRS_VAL_US + int "SPI flash tRS value (refer to chapter AC CHARACTERISTICS)" + default 50 + range 20 200 + depends on SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + help + This config is used for setting Trs parameter. Trs means CS Latency Between Resume And Next Suspend. + You can refer to the chapter of AC CHARACTERISTICS of flash datasheet. + For high-performance scenarios, some flash chips allow this set value to be smaller than the + given value in the datasheet without causing errors in the flash state machine. + When you have any related needs, please contact espressif business team. + config SPI_FLASH_FORCE_ENABLE_XMC_C_SUSPEND bool "Enable XMC-C series flash chip suspend feature anyway" default n @@ -374,7 +386,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_ISSI_CHIP bool "ISSI" - default y if SPI_FLASH_VENDOR_ISSI_SUPPORTED + default y if SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED default n help Enable this to support auto detection of ISSI chips if chip vendor not directly @@ -383,7 +395,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_MXIC_CHIP bool "MXIC" - default y if SPI_FLASH_VENDOR_MXIC_SUPPORTED + default y if SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED default n help Enable this to support auto detection of MXIC chips if chip vendor not directly @@ -392,7 +404,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_GD_CHIP bool "GigaDevice" - default y if SPI_FLASH_VENDOR_GD_SUPPORTED + default y if SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED default n help Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not @@ -406,7 +418,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_WINBOND_CHIP bool "Winbond" - default y if SPI_FLASH_VENDOR_WINBOND_SUPPORTED + default y if SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED default n help Enable this to support auto detection of Winbond chips if chip vendor not directly @@ -416,7 +428,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_BOYA_CHIP bool "BOYA" # ESP32 doesn't usually use this chip, default n to save iram. - default y if SPI_FLASH_VENDOR_BOYA_SUPPORTED + default y if SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED default n help Enable this to support auto detection of BOYA chips if chip vendor not directly @@ -426,7 +438,7 @@ menu "SPI Flash driver" config SPI_FLASH_SUPPORT_TH_CHIP bool "TH" # ESP32 doesn't usually use this chip, default n to save iram. - default y if SPI_FLASH_VENDOR_TH_SUPPORTED + default y if SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED default n help Enable this to support auto detection of TH chips if chip vendor not directly diff --git a/components/spi_flash/esp32/Kconfig.soc_caps.in b/components/spi_flash/esp32/Kconfig.soc_caps.in index 530c5d7a59..fed381f618 100644 --- a/components/spi_flash/esp32/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32/Kconfig.soc_caps.in @@ -3,22 +3,22 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_GD_SUPPORTED +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_ISSI_SUPPORTED +config SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_MXIC_SUPPORTED +config SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED +config SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32/flash_vendor_caps.h b/components/spi_flash/esp32/flash_vendor_caps.h index 054b7158c4..c5723a6123 100644 --- a/components/spi_flash/esp32/flash_vendor_caps.h +++ b/components/spi_flash/esp32/flash_vendor_caps.h @@ -1,29 +1,29 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ /** - * This file records the flash vendor that we offically supported. + * This file records the flash vendor that we officially supported. * we have many chip-specific files, like ``spi_flash_chip_gd.c``, * which means that this file is used for GD flash chips. * - * The following definations illustrate what flash vendor is officially + * The following definitions illustrate what flash vendor is officially * supported by ESP chips. If a flash vendor is officially supported, the chip * specific file will be linked by default, vice versa. You can also adjust this * manually in Kconfig options. * * For example: - * Following `SPI_FLASH_VENDOR_ISSI_SUPPORTED` is (1), which means file `spi_flash_chip_issi.c` + * Following `SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED` is (1), which means file `spi_flash_chip_issi.c` * will be linked. * */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32c2/Kconfig.soc_caps.in b/components/spi_flash/esp32c2/Kconfig.soc_caps.in index d1744a6196..5ba748e5aa 100644 --- a/components/spi_flash/esp32c2/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32c2/Kconfig.soc_caps.in @@ -3,30 +3,30 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_GD_SUPPORTED +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_ISSI_SUPPORTED +config SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_MXIC_SUPPORTED +config SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED +config SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_BOYA_SUPPORTED +config SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_TH_SUPPORTED +config SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32c2/flash_vendor_caps.h b/components/spi_flash/esp32c2/flash_vendor_caps.h index 88b64fdba4..65075fc4df 100644 --- a/components/spi_flash/esp32c2/flash_vendor_caps.h +++ b/components/spi_flash/esp32c2/flash_vendor_caps.h @@ -1,14 +1,14 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) -#define SPI_FLASH_VENDOR_BOYA_SUPPORTED (1) -#define SPI_FLASH_VENDOR_TH_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32c3/Kconfig.soc_caps.in b/components/spi_flash/esp32c3/Kconfig.soc_caps.in index d1744a6196..5ba748e5aa 100644 --- a/components/spi_flash/esp32c3/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32c3/Kconfig.soc_caps.in @@ -3,30 +3,30 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_GD_SUPPORTED +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_ISSI_SUPPORTED +config SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_MXIC_SUPPORTED +config SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED +config SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_BOYA_SUPPORTED +config SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_TH_SUPPORTED +config SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32c3/flash_vendor_caps.h b/components/spi_flash/esp32c3/flash_vendor_caps.h index 88b64fdba4..65075fc4df 100644 --- a/components/spi_flash/esp32c3/flash_vendor_caps.h +++ b/components/spi_flash/esp32c3/flash_vendor_caps.h @@ -1,14 +1,14 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) -#define SPI_FLASH_VENDOR_BOYA_SUPPORTED (1) -#define SPI_FLASH_VENDOR_TH_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32c5/Kconfig.soc_caps.in b/components/spi_flash/esp32c5/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32c5/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32c5/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32c5/flash_vendor_caps.h b/components/spi_flash/esp32c5/flash_vendor_caps.h index 6b127dfbd6..24ce9c86b0 100644 --- a/components/spi_flash/esp32c5/flash_vendor_caps.h +++ b/components/spi_flash/esp32c5/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32c6/Kconfig.soc_caps.in b/components/spi_flash/esp32c6/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32c6/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32c6/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32c6/flash_vendor_caps.h b/components/spi_flash/esp32c6/flash_vendor_caps.h index ffa84babf7..b5708c2efe 100644 --- a/components/spi_flash/esp32c6/flash_vendor_caps.h +++ b/components/spi_flash/esp32c6/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32c61/Kconfig.soc_caps.in b/components/spi_flash/esp32c61/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32c61/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32c61/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32c61/flash_vendor_caps.h b/components/spi_flash/esp32c61/flash_vendor_caps.h index 6b127dfbd6..24ce9c86b0 100644 --- a/components/spi_flash/esp32c61/flash_vendor_caps.h +++ b/components/spi_flash/esp32c61/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32h2/Kconfig.soc_caps.in b/components/spi_flash/esp32h2/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32h2/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32h2/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32h2/flash_vendor_caps.h b/components/spi_flash/esp32h2/flash_vendor_caps.h index ffa84babf7..b5708c2efe 100644 --- a/components/spi_flash/esp32h2/flash_vendor_caps.h +++ b/components/spi_flash/esp32h2/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32h21/Kconfig.soc_caps.in b/components/spi_flash/esp32h21/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32h21/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32h21/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32h21/flash_vendor_caps.h b/components/spi_flash/esp32h21/flash_vendor_caps.h index 4c03f22479..2d3759ecf1 100644 --- a/components/spi_flash/esp32h21/flash_vendor_caps.h +++ b/components/spi_flash/esp32h21/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32h4/Kconfig.soc_caps.in b/components/spi_flash/esp32h4/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32h4/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32h4/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32h4/flash_vendor_caps.h b/components/spi_flash/esp32h4/flash_vendor_caps.h index 33d7427d05..07ae467962 100644 --- a/components/spi_flash/esp32h4/flash_vendor_caps.h +++ b/components/spi_flash/esp32h4/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32p4/Kconfig.soc_caps.in b/components/spi_flash/esp32p4/Kconfig.soc_caps.in index 87accd576f..443f776e07 100644 --- a/components/spi_flash/esp32p4/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32p4/Kconfig.soc_caps.in @@ -3,6 +3,10 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED + bool + default y + +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32p4/flash_vendor_caps.h b/components/spi_flash/esp32p4/flash_vendor_caps.h index ffa84babf7..b5708c2efe 100644 --- a/components/spi_flash/esp32p4/flash_vendor_caps.h +++ b/components/spi_flash/esp32p4/flash_vendor_caps.h @@ -5,4 +5,5 @@ */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32s2/Kconfig.soc_caps.in b/components/spi_flash/esp32s2/Kconfig.soc_caps.in index d1744a6196..5ba748e5aa 100644 --- a/components/spi_flash/esp32s2/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32s2/Kconfig.soc_caps.in @@ -3,30 +3,30 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_GD_SUPPORTED +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_ISSI_SUPPORTED +config SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_MXIC_SUPPORTED +config SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED +config SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_BOYA_SUPPORTED +config SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_TH_SUPPORTED +config SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32s2/flash_vendor_caps.h b/components/spi_flash/esp32s2/flash_vendor_caps.h index 88b64fdba4..65075fc4df 100644 --- a/components/spi_flash/esp32s2/flash_vendor_caps.h +++ b/components/spi_flash/esp32s2/flash_vendor_caps.h @@ -1,14 +1,14 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) -#define SPI_FLASH_VENDOR_BOYA_SUPPORTED (1) -#define SPI_FLASH_VENDOR_TH_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp32s3/Kconfig.soc_caps.in b/components/spi_flash/esp32s3/Kconfig.soc_caps.in index d1744a6196..5ba748e5aa 100644 --- a/components/spi_flash/esp32s3/Kconfig.soc_caps.in +++ b/components/spi_flash/esp32s3/Kconfig.soc_caps.in @@ -3,30 +3,30 @@ # using gen_soc_caps_kconfig.py, do not edit manually ##################################################### -config SPI_FLASH_VENDOR_XMC_SUPPORTED +config SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_GD_SUPPORTED +config SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_ISSI_SUPPORTED +config SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_MXIC_SUPPORTED +config SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_WINBOND_SUPPORTED +config SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_BOYA_SUPPORTED +config SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED bool default y -config SPI_FLASH_VENDOR_TH_SUPPORTED +config SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED bool default y diff --git a/components/spi_flash/esp32s3/flash_vendor_caps.h b/components/spi_flash/esp32s3/flash_vendor_caps.h index ba081b1b13..1fdccb3856 100644 --- a/components/spi_flash/esp32s3/flash_vendor_caps.h +++ b/components/spi_flash/esp32s3/flash_vendor_caps.h @@ -1,15 +1,15 @@ /* - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once -#define SPI_FLASH_VENDOR_XMC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_GD_SUPPORTED (1) -#define SPI_FLASH_VENDOR_ISSI_SUPPORTED (1) -#define SPI_FLASH_VENDOR_MXIC_SUPPORTED (1) -#define SPI_FLASH_VENDOR_WINBOND_SUPPORTED (1) -#define SPI_FLASH_VENDOR_BOYA_SUPPORTED (1) -#define SPI_FLASH_VENDOR_TH_SUPPORTED (1) +#define SPI_FLASH_VENDOR_XMC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_GD_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_ISSI_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_MXIC_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_WINBOND_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_BOYA_SUPPORT_ENABLED (1) +#define SPI_FLASH_VENDOR_TH_SUPPORT_ENABLED (1) diff --git a/components/spi_flash/esp_flash_spi_init.c b/components/spi_flash/esp_flash_spi_init.c index e0f30a9d0b..d16506d391 100644 --- a/components/spi_flash/esp_flash_spi_init.c +++ b/components/spi_flash/esp_flash_spi_init.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -34,6 +34,10 @@ __attribute__((unused)) static const char TAG[] = "spi_flash"; #error "CONFIG_SPI_FLASH_PLACE_FUNCTIONS_IN_IRAM cannot be disabled when CONFIG_SPI_FLASH_AUTO_SUSPEND is disabled." #endif +#if CONFIG_SPI_FLASH_ROM_IMPL && (CONFIG_ESPTOOLPY_FLASHSIZE_32MB || CONFIG_ESPTOOLPY_FLASHSIZE_64MB || CONFIG_ESPTOOLPY_FLASHSIZE_128MB) +#error "Flash chip size equal or over 32MB memory cannot use driver in ROM" +#endif + /* This pointer is defined in ROM and extern-ed on targets where CONFIG_SPI_FLASH_ROM_IMPL = y*/ #if !CONFIG_SPI_FLASH_ROM_IMPL esp_flash_t *esp_flash_default_chip = NULL; @@ -125,6 +129,9 @@ esp_flash_t *esp_flash_default_chip = NULL; .cs_setup = 1,\ } #define TSUS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TSUS_VAL_US +#if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR +#define TRS_VAL_SUSPEND CONFIG_SPI_FLASH_SUSPEND_TRS_VAL_US +#endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR #endif //!CONFIG_SPI_FLASH_AUTO_SUSPEND #endif // Other target @@ -392,6 +399,16 @@ esp_err_t esp_flash_init_default_chip(void) return ESP_ERR_INVALID_ARG; } cfg.tsus_val = TSUS_VAL_SUSPEND; + + #if SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + if (TRS_VAL_SUSPEND > 400 || TRS_VAL_SUSPEND < 20) { + // Assume that the TRS value cannot larger than 400 (because the performance might be really bad) + // And value cannot smaller than 20 (never see that small tsus value, might be wrong) + return ESP_ERR_INVALID_ARG; + } + cfg.trs_val = TRS_VAL_SUSPEND; + #endif // SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR + #endif // CONFIG_SPI_FLASH_AUTO_SUSPEND #if CONFIG_SPI_FLASH_AUTO_CHECK_SUSPEND_STATUS diff --git a/components/spi_flash/spi_flash_chip_drivers.c b/components/spi_flash/spi_flash_chip_drivers.c index b513cad6e2..ae5190854a 100644 --- a/components/spi_flash/spi_flash_chip_drivers.c +++ b/components/spi_flash/spi_flash_chip_drivers.c @@ -17,7 +17,9 @@ #include "sdkconfig.h" #include "esp_log.h" -#define TAG "spi_flash" +__attribute__((unused)) static const char *TAG = "spi_flash"; + +#define FORMAT_STR "Detected %s flash chip but using generic driver. For optimal functionality, enable `SPI_FLASH_SUPPORT_%s_CHIP` in menuconfig" #if !CONFIG_SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST /* @@ -65,39 +67,39 @@ void spi_flash_chip_list_check(esp_flash_t *chip, uint32_t device_id) { { case SPI_FLASH_GD: if (&esp_flash_chip_gd == NULL) { - ESP_EARLY_LOGW(TAG, "GigaDevice detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_GD_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "GigaDevice", "GD"); } break; case SPI_FLASH_ISSI: if (&esp_flash_chip_issi == NULL) { - ESP_EARLY_LOGW(TAG, "ISSI detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_ISSI_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "ISSI", "ISSI"); } break; case SPI_FLASH_TH: if (&esp_flash_chip_th == NULL) { - ESP_EARLY_LOGW(TAG, "TH detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_TH_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "TH", "TH"); } break; case SPI_FLASH_WINBOND: if (&esp_flash_chip_winbond == NULL) { - ESP_EARLY_LOGW(TAG, "winbond detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_WINBOND_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "winbond", "WINBOND"); } break; case SPI_FLASH_MXIC: // Need to tell the difference between octal and quad flash. if (chip->read_mode < SPI_FLASH_OPI_FLAG) { if (&esp_flash_chip_mxic == NULL) { - ESP_EARLY_LOGW(TAG, "MXIC detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_MXIC_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "MXIC", "MXIC"); } } else { if (&esp_flash_chip_mxic_opi == NULL) { - ESP_EARLY_LOGW(TAG, "MXIC detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_MXIC_OPI_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "MXIC", "MXIC_OPI"); } } break; case SPI_FLASH_BY: if (&esp_flash_chip_boya == NULL) { - ESP_EARLY_LOGW(TAG, "boya detected but related driver is not linked, please check option `SPI_FLASH_SUPPORT_BOYA_CHIP`"); + ESP_EARLY_LOGW(TAG, FORMAT_STR, "boya", "BOYA"); } break; default: diff --git a/components/spi_flash/spi_flash_chip_generic.c b/components/spi_flash/spi_flash_chip_generic.c index 94efb8215a..019644a8ab 100644 --- a/components/spi_flash/spi_flash_chip_generic.c +++ b/components/spi_flash/spi_flash_chip_generic.c @@ -15,6 +15,9 @@ #include "esp_private/spi_flash_os.h" #include "esp_rom_caps.h" +#define IS_REGION_32BIT(start, len) ((start) + (len) > (1<<24)) +#define IS_ADDR_32BIT(addr) (addr >= (1<<24)) + typedef struct flash_chip_dummy { uint8_t dio_dummy_bitlen; uint8_t qio_dummy_bitlen; @@ -112,6 +115,41 @@ esp_err_t spi_flash_chip_generic_detect_size(esp_flash_t *chip, uint32_t *size) #ifndef CONFIG_SPI_FLASH_ROM_IMPL +static esp_err_t spi_flash_command_generic_program_4B(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length) +{ + spi_flash_trans_t t = { + .command = CMD_PROGRAM_PAGE_4B, + .address_bitlen = 32, + .address = address, + .mosi_len = length, + .mosi_data = buffer, + .flags = SPI_FLASH_TRANS_FLAG_PE_CMD, + }; + return chip->host->driver->common_command(chip->host, &t); +} + +static esp_err_t spi_flash_command_generic_erase_sector_4B(esp_flash_t *chip, uint32_t start_address) +{ + spi_flash_trans_t t = { + .command = CMD_SECTOR_ERASE_4B, + .address_bitlen = 32, + .address = start_address, + .flags = SPI_FLASH_TRANS_FLAG_PE_CMD, + }; + return chip->host->driver->common_command(chip->host, &t); +} + +static esp_err_t spi_flash_command_generic_erase_block_4B(esp_flash_t *chip, uint32_t start_address) +{ + spi_flash_trans_t t = { + .command = CMD_LARGE_BLOCK_ERASE_4B, + .address_bitlen = 32, + .address = start_address, + .flags = SPI_FLASH_TRANS_FLAG_PE_CMD, + }; + return chip->host->driver->common_command(chip->host, &t); +} + esp_err_t spi_flash_chip_generic_probe(esp_flash_t *chip, uint32_t flash_id) { // This is the catch-all probe function, claim the chip always if nothing @@ -173,6 +211,7 @@ esp_err_t spi_flash_chip_generic_erase_chip(esp_flash_t *chip) esp_err_t spi_flash_chip_generic_erase_sector(esp_flash_t *chip, uint32_t start_address) { + bool addr_32b = IS_ADDR_32BIT(start_address); esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false); if (err == ESP_OK) { err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout); @@ -180,7 +219,11 @@ esp_err_t spi_flash_chip_generic_erase_sector(esp_flash_t *chip, uint32_t start_ //The chip didn't accept the previous write command. Ignore this in preparationstage. if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) { SET_FLASH_ERASE_STATUS(chip, SPI_FLASH_OS_IS_ERASING_STATUS_FLAG); - chip->host->driver->erase_sector(chip->host, start_address); + if (addr_32b) { + spi_flash_command_generic_erase_sector_4B(chip, start_address); + } else { + chip->host->driver->erase_sector(chip->host, start_address); + } chip->busy = 1; #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT); @@ -199,6 +242,7 @@ esp_err_t spi_flash_chip_generic_erase_sector(esp_flash_t *chip, uint32_t start_ esp_err_t spi_flash_chip_generic_erase_block(esp_flash_t *chip, uint32_t start_address) { + bool addr_32b = IS_ADDR_32BIT(start_address); esp_err_t err = chip->chip_drv->set_chip_write_protect(chip, false); if (err == ESP_OK) { err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout); @@ -206,7 +250,11 @@ esp_err_t spi_flash_chip_generic_erase_block(esp_flash_t *chip, uint32_t start_a //The chip didn't accept the previous write command. Ignore this in preparationstage. if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) { SET_FLASH_ERASE_STATUS(chip, SPI_FLASH_OS_IS_ERASING_STATUS_FLAG); - chip->host->driver->erase_block(chip->host, start_address); + if (addr_32b) { + spi_flash_command_generic_erase_block_4B(chip, start_address); + } else { + chip->host->driver->erase_block(chip->host, start_address); + } chip->busy = 1; #ifdef CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED err = chip->chip_drv->wait_idle(chip, ESP_FLASH_CHIP_GENERIC_NO_TIMEOUT); @@ -232,6 +280,9 @@ esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t uint32_t config_io_flags = 0; // Configure the host, and return + if (IS_REGION_32BIT(address, length)) { + config_io_flags |= SPI_FLASH_CONFIG_IO_MODE_32B_ADDR; + } err = chip->chip_drv->config_host_io_mode(chip, config_io_flags); if (err == ESP_ERR_NOT_SUPPORTED) { @@ -259,12 +310,16 @@ esp_err_t spi_flash_chip_generic_read(esp_flash_t *chip, void *buffer, uint32_t esp_err_t spi_flash_chip_generic_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length) { esp_err_t err; - + bool addr_32b = IS_ADDR_32BIT(address); err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->idle_timeout); - //The chip didn't accept the previous write command. Ignore this in preparationstage. + //The chip didn't accept the previous write command. Ignore this in preparation stage. if (err == ESP_OK || err == ESP_ERR_NOT_SUPPORTED) { // Perform the actual Page Program command - chip->host->driver->program_page(chip->host, buffer, address, length); + if (addr_32b) { + spi_flash_command_generic_program_4B(chip, buffer, address, length); + } else { + chip->host->driver->program_page(chip->host, buffer, address, length); + } chip->busy = 1; err = chip->chip_drv->wait_idle(chip, chip->chip_drv->timeout->page_program_timeout); @@ -433,48 +488,48 @@ esp_err_t spi_flash_chip_generic_config_host_io_mode(esp_flash_t *chip, uint32_t uint32_t read_command; bool conf_required = false; esp_flash_io_mode_t read_mode = chip->read_mode; - bool addr_32bit = (flags & SPI_FLASH_CONFIG_IO_MODE_32B_ADDR); + bool is_addr_32bit = (flags & SPI_FLASH_CONFIG_IO_MODE_32B_ADDR); switch (read_mode & 0xFFFF) { case SPI_FLASH_QIO: //for QIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that. addr_bitlen = SPI_FLASH_QIO_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->qio_dummy_bitlen : rom_flash_chip_dummy->qio_dummy_bitlen); - read_command = (addr_32bit? CMD_FASTRD_QIO_4B: CMD_FASTRD_QIO); + read_command = (is_addr_32bit? CMD_FASTRD_QIO_4B: CMD_FASTRD_QIO); conf_required = true; break; case SPI_FLASH_QOUT: addr_bitlen = SPI_FLASH_QOUT_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->qout_dummy_bitlen : rom_flash_chip_dummy->qout_dummy_bitlen); - read_command = (addr_32bit? CMD_FASTRD_QUAD_4B: CMD_FASTRD_QUAD); + read_command = (is_addr_32bit? CMD_FASTRD_QUAD_4B: CMD_FASTRD_QUAD); break; case SPI_FLASH_DIO: //for DIO mode, the 4 bit right after the address are used for continuous mode, should be set to 0 to avoid that. addr_bitlen = SPI_FLASH_DIO_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->dio_dummy_bitlen : rom_flash_chip_dummy->dio_dummy_bitlen); - read_command = (addr_32bit? CMD_FASTRD_DIO_4B: CMD_FASTRD_DIO); + read_command = (is_addr_32bit? CMD_FASTRD_DIO_4B: CMD_FASTRD_DIO); conf_required = true; break; case SPI_FLASH_DOUT: addr_bitlen = SPI_FLASH_DOUT_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->dout_dummy_bitlen : rom_flash_chip_dummy->dout_dummy_bitlen); - read_command = (addr_32bit? CMD_FASTRD_DUAL_4B: CMD_FASTRD_DUAL); + read_command = (is_addr_32bit? CMD_FASTRD_DUAL_4B: CMD_FASTRD_DUAL); break; case SPI_FLASH_FASTRD: addr_bitlen = SPI_FLASH_FASTRD_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->fastrd_dummy_bitlen : rom_flash_chip_dummy->fastrd_dummy_bitlen); - read_command = (addr_32bit? CMD_FASTRD_4B: CMD_FASTRD); + read_command = (is_addr_32bit? CMD_FASTRD_4B: CMD_FASTRD); break; case SPI_FLASH_SLOWRD: addr_bitlen = SPI_FLASH_SLOWRD_ADDR_BITLEN; dummy_cyclelen_base = (chip->hpm_dummy_ena ? rom_flash_chip_dummy_hpm->slowrd_dummy_bitlen : rom_flash_chip_dummy->slowrd_dummy_bitlen); - read_command = (addr_32bit? CMD_READ_4B: CMD_READ); + read_command = (is_addr_32bit? CMD_READ_4B: CMD_READ); break; default: return ESP_ERR_FLASH_NOT_INITIALISED; } //For W25Q256 chip, the only difference between 4-Byte address command and 3-Byte version is the command value and the address bit length. - if (addr_32bit) { + if (is_addr_32bit) { addr_bitlen += 8; } @@ -619,6 +674,7 @@ spi_flash_caps_t spi_flash_chip_generic_get_caps(esp_flash_t *chip) // XMC-D support suspend if (chip->chip_id >> 16 == 0x46) { caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND; + caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT; } // XMC-D support suspend (some D series flash chip begin with 0x20, difference checked by SFDP) @@ -637,6 +693,7 @@ spi_flash_caps_t spi_flash_chip_generic_get_caps(esp_flash_t *chip) chip->host->driver->common_command(chip->host, &t); if((data & 0x8) == 0x8) { caps_flags |= SPI_FLASH_CHIP_CAP_SUSPEND; + caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT; } } diff --git a/docs/en/api-guides/bootloader.rst b/docs/en/api-guides/bootloader.rst index e0ef23c2ac..135dbec9ea 100644 --- a/docs/en/api-guides/bootloader.rst +++ b/docs/en/api-guides/bootloader.rst @@ -189,3 +189,67 @@ In the bootloader space, you cannot use the drivers and functions from other com * :example:`storage/nvs/nvs_bootloader` If the bootloader grows too large then it can collide with the partition table, which is flashed at offset 0x8000 by default. Increase the :ref:`partition table offset ` value to place the partition table later in the flash. This increases the space available for the bootloader. + +.. only:: SOC_RECOVERY_BOOTLOADER_SUPPORTED + + Recovery Bootloader + ------------------- + + The {IDF_TARGET_NAME} introduces Recovery Bootloader and Anti-rollback Bootloader features, implemented in the ROM bootloader to enhance device security and reliability during OTA updates. + + The recovery bootloader feature enables safe OTA updates of the bootloader itself. When the eFuse field ``ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR`` is set, it specifies the flash address (in sectors) of the recovery bootloader. If the primary bootloader at {IDF_TARGET_CONFIG_BOOTLOADER_OFFSET_IN_FLASH} fails to load, the ROM bootloader attempts to load the recovery bootloader from this address. + + - The eFuse can be programmed using ``espefuse.py`` or via the user application using :cpp:func:`esp_efuse_set_recovery_bootloader_offset()`. + - The address can be set via the ``CONFIG_BOOTLOADER_RECOVERY_OFFSET``, it must be a multiple of the flash sector size (0x1000 bytes). This Kconfig option helps ensure the recovery bootloader does not overlap with existing partitions. + - Note that the eFuse field stores the offset in sectors. Setting it to the maximum value ``0xFFF`` disables the feature. + - The recovery bootloader image at the ``CONFIG_BOOTLOADER_RECOVERY_OFFSET`` is not flashed by default. It can be written as part of the OTA update process. + + The example below shows the bootloader log when the primary bootloader fails to load and the recovery bootloader is loaded instead. + + .. code-block:: none + + ESP-ROM:esp32c5-eco2-20250121 + Build:Jan 21 2025 + rst:0x1 (POWERON),boot:0x18 (SPI_FAST_FLASH_BOOT) + invalid header: 0xffffffff + invalid header: 0xffffffff + invalid header: 0xffffffff + PRIMARY - FAIL + Loading RECOVERY Bootloader... + SPI mode:DIO, clock div:1 + load:0x408556b0,len:0x17cc + load:0x4084bba0,len:0xdac + load:0x4084e5a0,len:0x3140 + entry 0x4084bbaa + + I (46) boot: ESP-IDF v6.0-dev-172-g12c5d730097-dirty 2nd stage bootloader + I (46) boot: compile time May 22 2025 12:41:59 + I (47) boot: chip revision: v1.0 + I (48) boot: efuse block revision: v0.1 + I (52) boot.esp32c5: SPI Speed : 80MHz + I (55) boot.esp32c5: SPI Mode : DIO + I (59) boot.esp32c5: SPI Flash Size : 4MB + I (63) boot: Enabling RNG early entropy source... + I (67) boot: Partition Table: + ... + + Anti-Rollback Feature + ^^^^^^^^^^^^^^^^^^^^^ + + The anti-rollback feature prevents downgrading to an older, potentially vulnerable bootloader version. The bootloader header includes a security version, defined by ``CONFIG_BOOTLOADER_SECURE_VERSION``. When ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN`` is set, the ROM bootloader checks this version against the value stored in ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION``. Only bootloaders with a version greater than or equal to the eFuse value are allowed to boot. + + - The ROM bootloader can update the secure version in eFuse if ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_UPDATE_IN_ROM`` is set. + - The secure version value is incremented as new bootloader versions are deployed, and cannot be decreased. + - If the secure version in eFuse is not updated in the ROM bootloader, then the application can update it using the :cpp:func:`esp_efuse_write_field_blob` function. + + Relevant eFuses + ^^^^^^^^^^^^^^^ + + - ``EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR`` (12 bits): Flash sector address for the recovery bootloader. Default value is 0 (disabled), set any other value to enable, 0xFFF to permanently disable. + - ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN`` (1 bit): Enables anti-rollback check in the ROM bootloader. + - ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION`` (4 bits): Secure version for anti-rollback protection. The value increases as bits are set - 0x0, 0x1, 0x3, 0x7, 0xF. + - ``EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_UPDATE_IN_ROM`` (1 bit): Allows the ROM bootloader to update the secure version in eFuse. + + .. note:: + + Use these features to improve device security and reliability during OTA updates. Carefully plan eFuse programming, as these settings are permanent and may affect future update strategies. diff --git a/docs/en/api-reference/peripherals/gpio/esp32c61.inc b/docs/en/api-reference/peripherals/gpio/esp32c61.inc index c040f34bac..5cb75418a0 100644 --- a/docs/en/api-reference/peripherals/gpio/esp32c61.inc +++ b/docs/en/api-reference/peripherals/gpio/esp32c61.inc @@ -9,7 +9,7 @@ .. gpio-summary -The {IDF_TARGET_NAME} chip features 25 physical GPIO pins (GPIO0 ~ GPIO24). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. +The {IDF_TARGET_NAME} chip features 30 physical GPIO pins (GPIO0 ~ GPIO29). Each pin can be used as a general-purpose I/O, or to be connected to an internal peripheral signal. Through GPIO matrix and IO MUX, peripheral input signals can be from any IO pins, and peripheral output signals can be routed to any IO pins. Together these modules provide highly configurable I/O. For more details, see *{IDF_TARGET_NAME} Technical Reference Manual* > *IO MUX and GPIO Matrix (GPIO, IO_MUX)* [`PDF <{IDF_TARGET_TRM_EN_URL}#iomuxgpio>`__]. The table below provides more information on pin usage, and please note the comments in the table for GPIOs with restrictions. @@ -147,6 +147,31 @@ The table below provides more information on pin usage, and please note the comm - - + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - + - + - + + * - GPIO29 + - + - + - + .. note:: - Some pins are used as strapping pins, which can be used to select in which boot mode to load the chip, etc.. The details can be found in `datasheet <{IDF_TARGET_DATASHEET_EN_URL}>`_ > ``Strapping Pins``. diff --git a/docs/en/api-reference/peripherals/parlio/parlio_tx.rst b/docs/en/api-reference/peripherals/parlio/parlio_tx.rst index 5d469be742..716dad3b4b 100644 --- a/docs/en/api-reference/peripherals/parlio/parlio_tx.rst +++ b/docs/en/api-reference/peripherals/parlio/parlio_tx.rst @@ -174,6 +174,7 @@ When the TX unit generates events such as transmission done, it will notify the For the event callbacks supported by the TX unit, refer to :cpp:type:`parlio_tx_event_callbacks_t`: - :cpp:member:`parlio_tx_event_callbacks_t::on_trans_done` Sets the callback function for the "transmission complete" event, with the function prototype declared as :cpp:type:`parlio_tx_done_callback_t`. +- :cpp:member:`parlio_tx_event_callbacks_t::on_buffer_switched` Sets the callback function for the "buffer switch" event, with the function prototype declared as :cpp:type:`parlio_tx_buffer_switched_callback_t`. Resource Recycling ^^^^^^^^^^^^^^^^^^ @@ -307,7 +308,7 @@ The waveform of the external clock input is shown below: .. note:: - If you need to modify the transmission payload after enabling infinite loop transmission, you can configure :cpp:member:`parlio_transmit_config_t::flags::loop_transmission` and call :cpp:func:`parlio_tx_unit_transmit` again with a new payload buffer. The driver will switch to the new buffer after the old buffer is completely transmitted. Therefore, users need to maintain two buffers to avoid data inconsistency caused by premature modification or recycling of the old buffer. + If you need to modify the transmission payload after enabling infinite loop transmission, you can configure :cpp:member:`parlio_transmit_config_t::flags::loop_transmission` and call :cpp:func:`parlio_tx_unit_transmit` again with a new payload buffer. The driver will switch to the new buffer after the old buffer is completely transmitted. You can register :cpp:member:`parlio_tx_event_callbacks_t::on_buffer_switched` to set the callback function for the "buffer switch" event, and need to maintain two buffers to avoid data inconsistency caused by premature modification or recycling of the old buffer. .. only:: SOC_BITSCRAMBLER_SUPPORTED @@ -320,6 +321,12 @@ The waveform of the external clock input is shown below: After writing the BitScrambler program, we can enable it by calling :cpp:func:`parlio_tx_unit_decorate_bitscrambler`. And configure the :cpp:member:`parlio_transmit_config_t::bitscrambler_program` to point to the binary file of the BitScrambler program. Different transmission transactions can use different BitScrambler programs. The binary file must conform to the BitScrambler assembly language specification, and will be loaded into the BitScrambler's instruction memory at runtime. For details on how to write and compile the BitScrambler program, please refer to :doc:`BitScrambler Programming Guide `. + .. only:: not SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + + .. note:: + + Due to hardware limitations, the bitstream generated by the BitScrambler cannot change the length compared to the original bitstream, otherwise transmission blocking or data loss may occur. + :cpp:func:`parlio_tx_unit_decorate_bitscrambler` and :cpp:func:`parlio_tx_unit_undecorate_bitscrambler` need to be used in pairs. When deleting the TX unit, you need to call :cpp:func:`parlio_tx_unit_undecorate_bitscrambler` first to remove the BitScrambler. Power Management diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst index 9a7b58e802..a3c500a49f 100644 --- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst +++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst @@ -15,7 +15,7 @@ Feature Supported by ESP-IDF but Not in Chip-ROM .. list:: - Octal flash chip support. See :ref:`oct-flash-doc` for details. - - 32-bit-address support for GD25Q256. Note that this feature is an optional feature, please do read :ref:`32-bit-flash-doc` for details. + - 32-bit-address support on flash chips. Note that this feature is an optional feature, please do read :ref:`32-bit-flash-doc` for details. - TH flash chip support. - Kconfig option :ref:`CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED`. - :ref:`CONFIG_SPI_FLASH_VERIFY_WRITE`, enabling this option helps you detect bad writing. diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst index 8b99de0c0a..15eedf7f29 100644 --- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst +++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst @@ -155,6 +155,7 @@ List of Flash chips that support this feature: 1. W25Q256 2. GD25Q256 +3. XM25QH256D Restrictions ^^^^^^^^^^^^ diff --git a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc index 41f213f3ae..fb45d9a6eb 100644 --- a/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc +++ b/docs/zh_CN/api-reference/peripherals/gpio/esp32c61.inc @@ -9,7 +9,7 @@ .. gpio-summary -{IDF_TARGET_NAME} 芯片具有 25 个物理 GPIO 管脚（GPIO0 ~ GPIO24）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 +{IDF_TARGET_NAME} 芯片具有 30 个物理 GPIO 管脚（GPIO0 ~ GPIO29）。每个管脚都可用作一个通用 IO，或连接一个内部的外设 信号。通过 GPIO 交换矩阵和 IO MUX，可配置外设模块的输入信号来源于任何的 IO 管脚，并且外设模块的输 出信号也可连接到任意 IO 管脚。这些模块共同组成了芯片的 IO 控制。更多详细信息，请参阅 *{IDF_TARGET_NAME} 技术参考手册* > *IO MUX 和 GPIO 矩阵（GPIO、IO_MUX）* [`PDF <{IDF_TARGET_TRM_CN_URL}#iomuxgpio>`__]。 下表提供了各管脚的详细信息，部分 GPIO 具有特殊的使用限制，具体可参考表中的注释列。 @@ -147,6 +147,31 @@ - - + * - GPIO25 + - + - + - + + * - GPIO26 + - + - + - + + * - GPIO27 + - + - + - + + * - GPIO28 + - + - + - + + * - GPIO29 + - + - + - + .. note:: - 其中一些管脚被用作 Strapping 管脚，可用于选择加载芯片的启动模式等。详细信息请见 `ESP32-C61 技术规格书 <{IDF_TARGET_DATASHEET_CN_URL}>`_ > ``Strapping 管脚``。 diff --git a/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst b/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst index ad0fd0ee58..f7bae42759 100644 --- a/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst +++ b/docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst @@ -174,6 +174,7 @@ TX 单元以比特为单位进行传输，且传输的比特长度必须配置 有关 TX 单元支持的事件回调，请参阅 :cpp:type:`parlio_tx_event_callbacks_t`： - :cpp:member:`parlio_tx_event_callbacks_t::on_trans_done` 为“发送完成”的事件设置回调函数，函数原型声明为 :cpp:type:`parlio_tx_done_callback_t`。 +- :cpp:member:`parlio_tx_event_callbacks_t::on_buffer_switched` 为“缓冲区切换”的事件设置回调函数，函数原型声明为 :cpp:type:`parlio_tx_buffer_switched_callback_t`。 资源回收 ^^^^^^^^ @@ -307,7 +308,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特 .. note:: - 如果启用无限循环发送后需要修改发送内容，可以配置 :cpp:member:`parlio_transmit_config_t::flags::loop_transmission` 并再次调用 :cpp:func:`parlio_tx_unit_transmit` 传入新的 payload buffer，驱动会在旧 buffer 完整发送后，切换到新传入的 buffer。因此需要用户自行维护好两块buffer，避免旧 buffer 被提早修改或者回收导致产生数据不连贯的现象。 + 如果启用无限循环发送后需要修改发送内容，可以配置 :cpp:member:`parlio_transmit_config_t::flags::loop_transmission` 并再次调用 :cpp:func:`parlio_tx_unit_transmit` 传入新的 payload buffer，驱动会在旧 buffer 完整发送后，切换到新传入的 buffer。可以通过注册 :cpp:member:`parlio_tx_event_callbacks_t::on_buffer_switched` 为“缓冲区切换”的事件设置回调函数，用户需要自行维护好两块buffer，避免旧 buffer 被提早修改或者回收导致产生数据不连贯的现象。 .. only:: SOC_BITSCRAMBLER_SUPPORTED @@ -320,6 +321,12 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特 编写好比特调节器程序后，通过调用 :cpp:func:`parlio_tx_unit_decorate_bitscrambler` 启用比特调节器。并在 :cpp:member:`parlio_transmit_config_t::bitscrambler_program` 配置本次传输使用比特调节器程序的二进制文件。不同的传输事务可以使用不同的比特调节器程序。该二进制文件必须符合比特调节器的汇编语言规范，并且在运行时会被加载到比特调节器的指令存储器中。如何编写并编译比特调节器程序请参考 :doc:`比特调节器编程指南 `。 + .. only:: not SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA + + .. note:: + + 由于硬件限制，使用比特调节器生成的比特流与原本比特流相比，长度不能发生变化，否则可能会发生传输阻塞或数据丢失。 + :cpp:func:`parlio_tx_unit_decorate_bitscrambler` 和 :cpp:func:`parlio_tx_unit_undecorate_bitscrambler` 需要成对使用。在删除 TX 单元时，需要先调用 :cpp:func:`parlio_tx_unit_undecorate_bitscrambler` 移除比特调节器。 电源管理 diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst index cc2ed38203..276f780054 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst @@ -15,7 +15,7 @@ ESP-IDF 支持但不包含在芯片 ROM 中的功能 .. list:: - 八线 flash 芯片。详情请参阅 :ref:`oct-flash-doc`。 - - GD25Q256 32 位地址。请注意，此功能为可选功能，详情请参阅 :ref:`32-bit-flash-doc`。 + - Flash 的 32 位地址。请注意，此功能为可选功能，详情请参阅 :ref:`32-bit-flash-doc`。 - TH flash 芯片。 - Kconfig 选项 :ref:`CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED`。 - :ref:`CONFIG_SPI_FLASH_VERIFY_WRITE`，启用此选项可检测错误写入。 diff --git a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst index 4123c8ea88..a97693efea 100644 --- a/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst +++ b/docs/zh_CN/api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst @@ -155,6 +155,7 @@ QSPI flash 芯片的 32 位地址支持 1. W25Q256 2. GD25Q256 +3. XM25QH256D 限制 ^^^^ diff --git a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md index f89104c4cb..6d3570be59 100644 --- a/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md +++ b/examples/bluetooth/esp_ble_mesh/aligenie_demo/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh AliGenie Example ============================= diff --git a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md index 52ec6f3fa5..7cdc334e5f 100644 --- a/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md +++ b/examples/bluetooth/esp_ble_mesh/directed_forwarding/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Directed Forwarding diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md index d498835b81..58ca4371fd 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Fast Provisioning Client example ======================== diff --git a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md index 4cbcfb1820..bd9ed0a7bc 100644 --- a/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/fast_provisioning/fast_prov_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Fast Provisioning Server example ======================== diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md index f1f7ea462b..267c62c596 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Client Model Demo ======================== diff --git a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md index e412f506aa..3a0fdc8612 100644 --- a/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/onoff_models/onoff_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Node demo ========================== diff --git a/examples/bluetooth/esp_ble_mesh/provisioner/README.md b/examples/bluetooth/esp_ble_mesh/provisioner/README.md index 40d4540b11..c5fa5c6572 100644 --- a/examples/bluetooth/esp_ble_mesh/provisioner/README.md +++ b/examples/bluetooth/esp_ble_mesh/provisioner/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Provisioner demo ================================ diff --git a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md index 46fcbf9681..53842d0f25 100644 --- a/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md +++ b/examples/bluetooth/esp_ble_mesh/remote_provisioning/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | # Remote Provisioning (See the README.md file in the upper level 'examples' directory for more information about examples.) diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md index f76b47d8e2..d711ea9f7e 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Sensor Client Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md index 3ea258109f..ef25333faf 100644 --- a/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/sensor_models/sensor_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Sensor Server Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md index a236ac08bf..085aef23cd 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_client/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Vendor Client Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md index 4aa875a23d..b9db144804 100644 --- a/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md +++ b/examples/bluetooth/esp_ble_mesh/vendor_models/vendor_server/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | ESP BLE Mesh Vendor Server Example ================================== diff --git a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md index 567f4901c4..2d672fa0be 100644 --- a/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md +++ b/examples/bluetooth/esp_ble_mesh/wifi_coexist/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-C61 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | --------- | -------- | +| Supported Targets | ESP32 | ESP32-C3 | ESP32-C6 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | ESP-BLE-MESH and Wi-Fi Coexistence Example ============================================= diff --git a/examples/common_components/env_caps/esp32c61/Kconfig.env_caps b/examples/common_components/env_caps/esp32c61/Kconfig.env_caps index db601e0962..cb3bd34ea8 100644 --- a/examples/common_components/env_caps/esp32c61/Kconfig.env_caps +++ b/examples/common_components/env_caps/esp32c61/Kconfig.env_caps @@ -4,7 +4,7 @@ config ENV_GPIO_RANGE_MIN config ENV_GPIO_RANGE_MAX int - default 24 + default 29 config ENV_GPIO_IN_RANGE_MAX int diff --git a/examples/common_components/env_caps/esp32p4/Kconfig.env_caps b/examples/common_components/env_caps/esp32p4/Kconfig.env_caps index d736f9c179..fae0fac8be 100644 --- a/examples/common_components/env_caps/esp32p4/Kconfig.env_caps +++ b/examples/common_components/env_caps/esp32p4/Kconfig.env_caps @@ -4,7 +4,7 @@ config ENV_GPIO_RANGE_MIN config ENV_GPIO_RANGE_MAX int - default 56 + default 54 config ENV_GPIO_IN_RANGE_MAX int diff --git a/examples/peripherals/lcd/parlio_simulate/main/parlio_simulate_example_main.c b/examples/peripherals/lcd/parlio_simulate/main/parlio_simulate_example_main.c index cb4f3f90c1..53e3763248 100644 --- a/examples/peripherals/lcd/parlio_simulate/main/parlio_simulate_example_main.c +++ b/examples/peripherals/lcd/parlio_simulate/main/parlio_simulate_example_main.c @@ -126,7 +126,7 @@ void example_init_parlio_panel(esp_lcd_panel_io_handle_t *io_handle) #endif }, .data_width = CONFIG_EXAMPLE_LCD_PARLIO_DATA_WIDTH, - .max_transfer_bytes = EXAMPLE_LCD_H_RES * 100 * sizeof(uint16_t), + .max_transfer_bytes = EXAMPLE_LCD_H_RES * EXAMPLE_LVGL_DRAW_BUF_LINES * sizeof(uint16_t), .dma_burst_size = EXAMPLE_DMA_BURST_SIZE, .cs_gpio_num = EXAMPLE_PIN_NUM_CS, .pclk_hz = EXAMPLE_LCD_PIXEL_CLOCK_HZ, diff --git a/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c b/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c index c28a4d6626..c4dca2bab5 100644 --- a/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c +++ b/examples/peripherals/parlio/parlio_tx/advanced_rgb_led_matrix/main/advanced_rgb_led_matrix_example_main.c @@ -85,6 +85,13 @@ static void merge_two_pixels(lv_color16_t *upper_half, lv_color16_t *lower_half, extern void example_lvgl_demo_ui(lv_display_t *disp); +static IRAM_ATTR bool example_notify_lvgl_flush_ready(parlio_tx_unit_handle_t tx_unit, const parlio_tx_buffer_switched_event_data_t *edata, void *user_ctx) +{ + lv_display_t *display = (lv_display_t *)user_ctx; + lv_display_flush_ready(display); + return false; +} + static void example_lvgl_flush_cb(lv_display_t *display, const lv_area_t *area, uint8_t *color_map) { static uint8_t buffer_idx = 0; @@ -114,7 +121,6 @@ static void example_lvgl_flush_cb(lv_display_t *display, const lv_area_t *area, parlio_tx_unit_transmit(tx_unit, s_frame_buffer[buffer_idx], (EXAMPLE_LED_MATRIX_V_RES / 2 * (EXAMPLE_LED_MATRIX_H_RES + EXAMPLE_GAP_CYCLE_PER_LINE)) * sizeof(uint16_t) * 8, &transmit_config); // switch to the next frame buffer buffer_idx ^= 0x01; - lv_display_flush_ready(display); } static IRAM_ATTR void timer_alarm_cb_lvgl_tick(void* arg) @@ -187,6 +193,12 @@ void app_main(void) }; lv_display_set_user_data(display, &user_ctx); + // register the callback to notify LVGL that the buffer is switched + parlio_tx_event_callbacks_t callbacks = { + .on_buffer_switched = example_notify_lvgl_flush_ready, + }; + parlio_tx_unit_register_event_callbacks(tx_unit, &callbacks, display); + ESP_LOGI(TAG, "Install LVGL tick timer"); // increase the LVGL tick in the esp_timer alarm callback const esp_timer_create_args_t timer_args = { @@ -201,6 +213,9 @@ void app_main(void) ESP_ERROR_CHECK(esp_timer_start_periodic(lvgl_tick_timer, EXAMPLE_LVGL_TICK_PERIOD_MS * 1000)); + // fake transmit, to trigger the buffer switchd event in the flush callback + parlio_tx_unit_transmit(tx_unit, s_frame_buffer[0], (EXAMPLE_LED_MATRIX_V_RES / 2 * (EXAMPLE_LED_MATRIX_H_RES + EXAMPLE_GAP_CYCLE_PER_LINE)) * sizeof(uint16_t) * 8, &transmit_config); + uint32_t time_till_next_ms = 0; while (1) { if (time_till_next_ms > 500) { diff --git a/examples/system/.build-test-rules.yml b/examples/system/.build-test-rules.yml index e76b552a0c..01df0af08b 100644 --- a/examples/system/.build-test-rules.yml +++ b/examples/system/.build-test-rules.yml @@ -9,7 +9,7 @@ examples/system/app_trace_basic: temporary: true reason: not supported yet #TODO: OCD-1137 disable_test: - - if: IDF_TARGET == "esp32p4" + - if: IDF_TARGET in ["esp32p4", "esp32c61"] temporary: true reason: lack of runners. @@ -100,7 +100,7 @@ examples/system/gcov: temporary: true reason: not supported yet #TODO: OCD-1138 disable_test: - - if: IDF_TARGET == "esp32p4" + - if: IDF_TARGET in ["esp32p4", "esp32c61"] temporary: true reason: lack of runners - if: IDF_TARGET == "esp32s3" @@ -194,10 +194,16 @@ examples/system/ota/partitions_ota: - if: IDF_TARGET in ["esp32h2", "esp32h21", "esp32h4"] temporary: true reason: not supported yet + - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED != 1 + temporary: true + reason: disabled for targets that do not support recovery bootloader disable_test: - if: IDF_TARGET not in ["esp32", "esp32c3", "esp32s3"] temporary: true reason: lack of runners + - if: CONFIG_NAME == "recovery_bootloader" and SOC_RECOVERY_BOOTLOADER_SUPPORTED == 1 + temporary: true + reason: lack of runners with recovery_bootloader lablel depends_components: - app_update - esp_https_ota diff --git a/examples/system/ota/partitions_ota/README.md b/examples/system/ota/partitions_ota/README.md index fa93835fe6..5e13b44073 100644 --- a/examples/system/ota/partitions_ota/README.md +++ b/examples/system/ota/partitions_ota/README.md @@ -22,7 +22,42 @@ Application OTA updates use one active and one passive partition. The new image ### Bootloader -Bootloader OTA updates are not inherently safe because the ROM bootloader does not support fallback to a recovery bootloader partition. Only the primary bootloader partition can be loaded by the ROM bootloader. Updating the bootloader is rarely necessary, and it is generally not recommended. However, if required, it can be done using the following approaches: +Updating the bootloader is rarely necessary, and it is generally not recommended. However, if required, it can be done using the following approaches, depending on chip support: + +- **Safe OTA Update (with Recovery Bootloader):** On chips that support the recovery bootloader feature in the ROM, a backup of the original bootloader is created in a dedicated recovery partition before updating. If the update fails or power is lost, the device can boot from this recovery bootloader, reducing the risk of bricking. The recovery bootloader partition and its offset must be configured in the partition table and eFuse. + +- Enable `CONFIG_BOOTLOADER_RECOVERY_ENABLE` and set the reocevery bootloader offset in `CONFIG_BOOTLOADER_RECOVERY_OFFSET`. +- Ensure that both the primary and recovery bootloader partitions are defined in the partition table (see `test/partitions_efuse_emul_2.csv`). If these entries are missing, the application can register them automatically, so manual addition is optional. +- Backup the primary bootloader to the recovery bootloader. +- Download directly into the primary bootloader partition or into a passive app partition. + +#### Example: ROM Bootloader Fallback to Recovery Bootloader + +Below is a sample log output demonstrating the ROM bootloader behavior when the primary bootloader is corrupted or fails to load, and the device successfully falls back to the recovery bootloader partition. This mechanism helps prevent device bricking in the event of a failed bootloader update. + +``` +ESP-ROM:esp32c5-eco2-20250121 +Build:Jan 21 2025 +rst:0x1 (POWERON),boot:0x18 (SPI_FAST_FLASH_BOOT) +invalid header: 0xffffffff +invalid header: 0xffffffff +invalid header: 0xffffffff +PRIMARY - FAIL +Loading RECOVERY Bootloader... +SPI mode:DIO, clock div:1 +load:0x408556b0,len:0x17cc +load:0x4084bba0,len:0xdac +load:0x4084e5a0,len:0x3140 +entry 0x4084bbaa +I (46) boot: ESP-IDF v6.0-dev-172-g12c5d730097-dirty 2nd stage bootloader +I (46) boot: compile time May 22 2025 12:41:59 +I (47) boot: chip revision: v1.0 +I (48) boot: efuse block revision: v0.1 +I (52) boot.esp32c5: SPI Speed : 80MHz +... +``` + +- **Unsafe OTA Update (ROM bootloader does not support the Recovery Bootloader):** Bootloader OTA updates are not inherently safe because the ROM bootloader does not support fallback to a recovery bootloader partition. Only the primary bootloader partition can be loaded by the ROM bootloader. On chips without recovery bootloader support, the new bootloader is downloaded to a staging partition and then copied to the primary bootloader partition. If power is lost during the final copy, the device may become unbootable. - Register the primary bootloader partition in the partition table, if not already present (see `test/partitions_efuse_emul_2.csv`). - Decide where to download the new bootloader image: @@ -32,9 +67,11 @@ Bootloader OTA updates are not inherently safe because the ROM bootloader does n After verification, if `finalize_with_copy` is set to `true`, the tool will automatically copy the new image to the primary bootloader partition. Set `finalize_with_copy` to `false` if you wish to control the final copy step manually. -Limitations for Bootloader OTA updates: +**Limitations:** - Secure Boot V1-enabled devices do not support bootloader updates. -- There is always a risk of device bricking when updating the bootloader. +- There is always a risk of device bricking when updating the bootloader, especially if power is lost during the final copy step to the primary bootloader. + +On chips that support a recovery bootloader feature, a backup of the original bootloader can be created in a dedicated recovery partition before updating. If the update fails or power is lost, the device is able to boot from this recovery bootloader, reducing the risk of bricking. The recovery bootloader partition and its offset must be configured in the partition table and eFuse. ### Partition Table diff --git a/examples/system/ota/partitions_ota/main/app_main.c b/examples/system/ota/partitions_ota/main/app_main.c index b77d85b0c0..02aa425365 100644 --- a/examples/system/ota/partitions_ota/main/app_main.c +++ b/examples/system/ota/partitions_ota/main/app_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Unlicense OR CC0-1.0 */ @@ -14,6 +14,7 @@ #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_system.h" +#include "esp_check.h" #include "esp_event.h" #include "esp_log.h" #include "esp_ota_ops.h" @@ -27,7 +28,10 @@ #include "esp_flash.h" #include "esp_flash_partitions.h" #include "esp_partition.h" - +#include "soc/soc_caps.h" +#if SOC_RECOVERY_BOOTLOADER_SUPPORTED +#include "esp_efuse.h" +#endif #include "nvs.h" #include "nvs_flash.h" #include "protocol_examples_common.h" @@ -99,6 +103,67 @@ static esp_err_t register_partition(size_t offset, size_t size, const char *labe return ESP_OK; } +#if CONFIG_BOOTLOADER_RECOVERY_ENABLE +static esp_err_t safe_bootloader_ota_update(esp_https_ota_config_t *ota_config) +{ + const esp_partition_t *primary_bootloader; + const esp_partition_t *recovery_bootloader; + ESP_ERROR_CHECK(register_partition(ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader)); + ESP_ERROR_CHECK(register_partition(CONFIG_BOOTLOADER_RECOVERY_OFFSET, ESP_BOOTLOADER_SIZE, "RecoveryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_RECOVERY, &recovery_bootloader)); + ESP_RETURN_ON_FALSE(recovery_bootloader->address == CONFIG_BOOTLOADER_RECOVERY_OFFSET, ESP_FAIL, TAG, + "The partition table contains <%s> (0x%08" PRIx32 "), which does not match the efuse recovery address (0x%08" PRIx32 ")", recovery_bootloader->label, recovery_bootloader->address, CONFIG_BOOTLOADER_RECOVERY_OFFSET); + // Since the recovery boot partition is registered successfully, we are sure that the flash memory size is enough to store it. + ESP_ERROR_CHECK(esp_efuse_set_recovery_bootloader_offset(CONFIG_BOOTLOADER_RECOVERY_OFFSET)); + + ESP_LOGI(TAG, "Backup, copy <%s> -> <%s>", primary_bootloader->label, recovery_bootloader->label); + ESP_ERROR_CHECK(esp_partition_copy(recovery_bootloader, 0, primary_bootloader, 0, primary_bootloader->size)); + + ota_config->partition.staging = primary_bootloader; + esp_err_t ret = esp_https_ota(ota_config); + if (ret == ESP_OK) { + // If the recovery_bootloader or primary_bootloader already exists in the partition table on flash, it will not be deregistered, and the function will return an error. + esp_partition_deregister_external(recovery_bootloader); + esp_partition_deregister_external(primary_bootloader); + } + return ret; +} +#else // !CONFIG_BOOTLOADER_RECOVERY_ENABLE + +static esp_err_t unsafe_bootloader_ota_update(esp_https_ota_config_t *ota_config) +{ + const esp_partition_t *primary_bootloader; + ESP_ERROR_CHECK(register_partition(ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader)); + const esp_partition_t *ota_partition = esp_ota_get_next_update_partition(NULL); // free app ota partition will be used for downloading a new image +#if CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE + // Check if the passive OTA app partition is not needed for rollback before using it for other partitions. + // The same can be done for partition table and storage updates. + esp_ota_img_states_t ota_state; + ESP_ERROR_CHECK(esp_ota_get_state_partition(ota_partition, &ota_state)); + if (ota_state == ESP_OTA_IMG_VALID) { + ESP_LOGW(TAG, "Passive OTA app partition <%s> contains a valid app image eligible for rollback.", ota_partition->label); + uint32_t ota_bootloader_offset; + ESP_ERROR_CHECK(partition_utils_find_unallocated(NULL, ESP_BOOTLOADER_SIZE, ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_SIZE, &ota_bootloader_offset, NULL)); + ESP_ERROR_CHECK(register_partition(ota_bootloader_offset, ESP_BOOTLOADER_SIZE, "OtaBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA, &ota_partition)); + ESP_LOGW(TAG, "To avoid overwriting the passive app partition, using the unallocated space on the flash to create a temporary OTA bootloader partition <%s>", ota_partition->label); + } +#endif + ota_config->partition.staging = ota_partition; + ota_config->partition.final = primary_bootloader; + esp_err_t ret = esp_https_ota(ota_config); + if (ret == ESP_OK) { + ESP_LOGW(TAG, "Ensure stable power supply! Loss of power at this stage leads to a chip bricking"); + ESP_LOGI(TAG, "Copy from <%s> staging partition to <%s>...", ota_partition->label, primary_bootloader->label); + ret = esp_partition_copy(primary_bootloader, 0, ota_partition, 0, primary_bootloader->size); + if (ret != ESP_OK) { + ESP_LOGE(TAG, "Failed to copy partition to Primary bootloader (err=0x%x). Bootloader likely corrupted. Device will not be able to boot again!", ret); + } + // If the primary_bootloader already exists in the partition table on flash, it will not be deregistered, and the function will return an error. + esp_partition_deregister_external(primary_bootloader); + } + return ret; +} +#endif // !CONFIG_BOOTLOADER_RECOVERY_ENABLE + static esp_err_t ota_update_partitions(esp_https_ota_config_t *ota_config) { esp_err_t ret = ESP_ERR_NOT_SUPPORTED; @@ -106,35 +171,16 @@ static esp_err_t ota_update_partitions(esp_https_ota_config_t *ota_config) ret = esp_https_ota(ota_config); } else if (strstr(ota_config->http_config->url, "bootloader.bin") != NULL) { - const esp_partition_t *primary_bootloader; - ESP_ERROR_CHECK(register_partition(ESP_PRIMARY_BOOTLOADER_OFFSET, ESP_BOOTLOADER_SIZE, "PrimaryBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_PRIMARY, &primary_bootloader)); - const esp_partition_t *ota_partition = esp_ota_get_next_update_partition(NULL); // free app ota partition will be used for downloading a new image -#if CONFIG_BOOTLOADER_APP_ROLLBACK_ENABLE - // Check if the passive OTA app partition is not needed for rollback before using it for other partitions. - // The same can be done for partition table and storage updates. - esp_ota_img_states_t ota_state; - ESP_ERROR_CHECK(esp_ota_get_state_partition(ota_partition, &ota_state)); - if (ota_state == ESP_OTA_IMG_VALID) { - ESP_LOGW(TAG, "Passive OTA app partition <%s> contains a valid app image eligible for rollback.", ota_partition->label); - uint32_t ota_bootloader_offset; - ESP_ERROR_CHECK(partition_utils_find_unallocated(NULL, ESP_BOOTLOADER_SIZE, ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_SIZE, &ota_bootloader_offset, NULL)); - ESP_ERROR_CHECK(register_partition(ota_bootloader_offset, ESP_BOOTLOADER_SIZE, "OtaBTLDR", ESP_PARTITION_TYPE_BOOTLOADER, ESP_PARTITION_SUBTYPE_BOOTLOADER_OTA, &ota_partition)); - ESP_LOGW(TAG, "To avoid overwriting the passive app partition, using the unallocated space on the flash to create a temporary OTA bootloader partition <%s>", ota_partition->label); - } +#if CONFIG_BOOTLOADER_RECOVERY_ENABLE + ESP_LOGI(TAG, "Safe OTA bootloader update: This chip version supports the recovery bootloader feature."); + ESP_LOGI(TAG, "If a failure or power loss occurs during the update, the recovery bootloader will be used."); + ESP_LOGI(TAG, "The recovery bootloader contains a backup of the original bootloader created before the OTA update."); + ret = safe_bootloader_ota_update(ota_config); +#else + ESP_LOGW(TAG, "Unsafe OTA bootloader update: This chip version does not support the recovery bootloader feature."); + ESP_LOGW(TAG, "If a failure or power loss occurs during the final copy, the chip may become unbootable."); + ret = unsafe_bootloader_ota_update(ota_config); #endif - ota_config->partition.staging = ota_partition; - ota_config->partition.final = primary_bootloader; - ret = esp_https_ota(ota_config); - if (ret == ESP_OK) { - ESP_LOGW(TAG, "Ensure stable power supply! Loss of power at this stage leads to a chip bricking"); - ESP_LOGI(TAG, "Copy from <%s> staging partition to <%s>...", ota_partition->label, primary_bootloader->label); - ret = esp_partition_copy(primary_bootloader, 0, ota_partition, 0, primary_bootloader->size); - if (ret != ESP_OK) { - ESP_LOGE(TAG, "Failed to copy partition to Primary bootloader (err=0x%x). Bootloader likely corrupted. Device will not be able to boot again!", ret); - } - // If the primary_bootloader already exists in the partition table on flash, it will not be deregistered, and the function will return an error. - esp_partition_deregister_external(primary_bootloader); - } } else if (strstr(ota_config->http_config->url, "partition-table.bin") != NULL) { const esp_partition_t *primary_partition_table; diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader b/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader new file mode 100644 index 0000000000..077a4903b9 --- /dev/null +++ b/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader @@ -0,0 +1,5 @@ +CONFIG_BOOTLOADER_RECOVERY_ENABLE=y +CONFIG_BOOTLOADER_RECOVERY_OFFSET=0x3F0000 + +CONFIG_PARTITION_TABLE_CUSTOM=y +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="test/partitions_efuse_emul_3.csv" diff --git a/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader.esp32c5 b/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader.esp32c5 new file mode 100644 index 0000000000..1e9b4e16a8 --- /dev/null +++ b/examples/system/ota/partitions_ota/sdkconfig.ci.recovery_bootloader.esp32c5 @@ -0,0 +1,2 @@ +# ESP32C5 supports the Recovery bootloader feature in ROM starting from v1.0 (ECO2) +CONFIG_IDF_TARGET="esp32c5" diff --git a/examples/system/ota/partitions_ota/test/partitions_efuse_emul_3.csv b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_3.csv new file mode 100644 index 0000000000..4f0cf7d252 --- /dev/null +++ b/examples/system/ota/partitions_ota/test/partitions_efuse_emul_3.csv @@ -0,0 +1,12 @@ +# Name, Type, SubType, Offset, Size, Flags +PrimaryBTLDR, bootloader, primary, N/A, N/A, +PrimaryPrtTable, partition_table, primary, N/A, N/A, +nvs, data, nvs, , 0x6000, +nvs_key, data, nvs_keys, , 4K, +storage, data, , , 0x1000, encrypted +otadata, data, ota, , 0x2000, +phy_init, data, phy, , 0x1000, +emul_efuse, data, efuse, , 0x2000, +ota_0, app, ota_0, , 0x1B0000, +ota_1, app, ota_1, , 0x1B0000, +RecoveryBTLDR, bootloader, recovery, N/A, N/A, diff --git a/examples/wifi/wifi_nvs_config/README.md b/examples/wifi/wifi_nvs_config/README.md new file mode 100644 index 0000000000..ccab6ce2cd --- /dev/null +++ b/examples/wifi/wifi_nvs_config/README.md @@ -0,0 +1,217 @@ +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | + +# WiFi NVS Config Example + +(See the `README.md` file in the upper-level 'examples' directory for more information about examples.) + +This example demonstrates how to configure Wi-Fi settings in NVS directly using a CSV file and utilize the Wi-Fi functionality of the ESP Wi-Fi driver. + +## How to Use the Example + +### 1) Configuration + +Open the CSV file `nvs_station_data.csv` or `nvs_ap_data.csv`. + +- Set the Wi-Fi configuration keys as explained below. These values are written into the NVS partition and read by the Wi-Fi driver during `esp_wifi_init()`. +- If needed, adjust or set other options as per your requirements. The AP and station keys along with their encoding types are listed [here](#key-configuration). + +**Note 1:** To set the device in SoftAP mode, enable the `CONFIG_ESP_WIFI_SOFTAP_SUPPORT` flag in `menuconfig`. + +**Note 2:** Setting these values is optional. Defaults are applied when `esp_wifi_init()` is called. + +### 2) Generate the Binary File Using the NVS Partition Generator Utility + +- Check the size of the NVS partition in the `partition_example.csv` file provided in this example. +- Generate a `.bin` file of the specified size using the following command: + +**Usage:** + +```bash +python nvs_partition_gen.py generate [-h] [--version {1,2}] [--outdir OUTDIR] input output size +``` + +- Sample command: + +```bash +python nvs_partition_gen.py generate nvs_station_data.csv sample_nvs.bin 0x6000 +``` + +- Please update the NVS Partition Generator to the latest version to avoid encoding type errors. +- For more information, see the [NVS Partition Generator Utility Documentation](https://docs.espressif.com/projects/esp-idf/en/stable/esp32/api-reference/storage/nvs_partition_gen.html). + +### 3) Flash the NVS Binary File to the ESP Device + +- Check the offset of the NVS partition in the `partition_example.csv` file. +- After flashing the build, flash the `sample_nvs.bin` file to the ESP device at the specified offset using `esptool.py`. +- Refer to the [Esptool Documentation](https://docs.espressif.com/projects/esptool/en/latest/esp32/esptool/index.html) for detailed usage. + +### 4) Build and Flash + +Build the project and flash it to the board, then run the monitor tool to view the serial output. + +Run `idf.py -p PORT flash monitor` to build, flash and monitor the project. + +(To exit the serial monitor, type ``Ctrl-]``.) + +### 5) Monitor the Output + +- Use `idf.py monitor` to view the console output of the example. + +See the Getting Started Guide for all the steps to configure and use the ESP-IDF to build projects. + +* [ESP-IDF Getting Started Guide on ESP32](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) + +## Key Configuration + +### Station Keys + + + | Key Name | Encoding Type | Mandatory/Optional | Description / Meaning | + |--------------------------|---------------|---------------------|----------------------------------------------------| + | sta.ssid | blob_sz_fill | Mandatory | SSID (Service Set Identifier) for station. (Refer parameter `uint8_t ssid[32]` from `struct wifi_sta_config_t`) | + | sta.pswd | blob_fill | Mandatory | Password for connecting to the Wi-Fi network. (Refer parameter `uint8_t password[64]` from `struct wifi_sta_config_t`) | + | bssid.set | u8 | Optional | Whether the BSSID is set or not. (Refer parameter `bool bssid_set` from `struct wifi_sta_config_t`) | + | sta.bssid | blob | Optional | BSSID (Basic Service Set Identifier) of the network. (Refer parameter `uint8_t bssid[6]` from `struct wifi_sta_config_t`) | + | sta.lis_intval | u16 | Optional | Listen interval (Refer parameter `uint16_t listen_interval` from `struct wifi_sta_config_t`) | + | sta.phym | u8 | Optional | Physical mode e.g., 802.11a/b/g/n/ac/ax. (Refer `esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap)`) | + | sta.phybw | u8 | Optional | Physical bandwidth (e.g., 20MHz, 40MHz) (Refer `esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidths_t* bw)`) | + | sta.sort_method | u8 | Optional | Sorting method for APs e.g. enum wifi_sort_method_t (Refer parameter `wifi_sort_method_t sort_method` from `struct wifi_sta_config_t`)| + | sta.minrssi | i8 | Optional | Minimum RSSI for the station to connect. (Refer `esp_err_t esp_wifi_set_rssi_threshold()` OR `int8_t rssi` from `wifi_scan_threshold_t threshold`) | + | sta.minauth | u8 | Optional | Minimum authentication level required for APs. (Refer `wifi_auth_mode_t authmode` from `wifi_scan_threshold_t threshold`) | + | sta.pmf_r | u8 | Optional | Whether PMF is required. (Refer `wifi_pmf_config_t pmf_cfg` parameter from `struct wifi_sta_config_t`) | + | sta.btm_e | u8 | Optional | Whether BTM is enabled. (Refer parameter `uint32_t btm_enabled` from `struct wifi_sta_config_t`) | + | sta.rrm_e | u8 | Optional | Whether RRM is enabled. (Refer parameter `uint32_t rm_enabled` from `struct wifi_sta_config_t`) | + | sta.mbo_e | u8 | Optional | Whether MBO (Multi-band Operation) is enabled. (Refer parameter `uint32_t mbo_enabled` from `struct wifi_sta_config_t`) | + | sta.phym5g | u8 | Optional | 5 GHz physical mode. (Only for chips supporting 5GHz bandwidth. (Refer `esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap)`) | + | sta.phybw5g | u8 | Optional | 5 GHz bandwidth setting.(Only for chips supporting 5GHz bandwidth. (Refer `esp_err_t esp_wifi_set_bandwidths(wifi_interface_t ifx, wifi_bandwidths_t* bw)` | + | sta.ft | u8 | Optional | Whether fast transition is enabled. (Refer parameter `uint32_t ft_enabled` from `struct wifi_sta_config_t`) | + | sta.owe | u8 | Optional | Whether OWE (Opportunistic Wireless Encryption) is enabled. (Refer parameter `uint32_t owe_enabled` from `struct wifi_sta_config_t`) | + | sta.trans_d | u8 | Optional | Transition disabled setting. (Refer parameter `uint32_t transition_disable` from `struct wifi_sta_config_t`) | + | sta.sae_h2e | u8 | Optional | SAE PWE method (e.g. enum wifi_sae_pwe_method_t). (Refer parameter `wifi_sae_pwe_method_t sae_pwe_h2e` from `struct wifi_sta_config_t`) | + | sta.sae_pk_mode | u8 | Optional | SAE-pk mode setting (e.g. enum wifi_sae_pk_mode_t) (Refer parameter `wifi_sae_pk_mode_t sae_pk_mode` from `struct wifi_sta_config_t`) | + | sta.bss_retry | u8 | Optional | BSS retry counter. (Refer parameter `uint8_t failure_retry_cnt` from `struct wifi_sta_config_t`) | + | sta.sae_h2e_id | blob | Optional | Password identifier for H2E. This must be a null-terminated string (Refer parameter `uint8_t sae_h2e_identifier[SAE_H2E_IDENTIFIER_LEN]` from `struct wifi_sta_config_t`) | + | sta.rssi_5g_adj | u8 | Optional | RSSI adjustment for 5 GHz. (Refer `uint8_t rssi_5g_adjustment` from `wifi_scan_threshold_t threshold`) | + + +### AP Keys + + | Key Name | Encoding Type | Mandatory/Optional | Description / Meaning | + |--------------------------|---------------|---------------------|----------------------------------------------------| + | ap.ssid | blob_sz_fill | Mandatory | SSID (Service Set Identifier) for the AP prefixed with the length of the SSID. (Refer parameter `uint8_t ssid[32]` from `struct wifi_ap_config_t`) | + | ap.passwd | blob_fill | Mandatory | Password for the AP's Wi-Fi network. (Refer parameter `uint8_t password[64]` from `struct wifi_ap_config_t`) | + | ap.chan | u8 | Mandatory | Channel number on which the AP is broadcasting. (Refer parameter `uint8_t channel` from `struct wifi_ap_config_t`) | + | ap.authmode | u8 | Mandatory | Authentication mode for the AP e.g. enum wifi_auth_mode_t. (Refer parameter `wifi_auth_mode_t authmode` from `struct wifi_ap_config_t`) | + | ap.hidden | u8 | Optional | Whether the AP is hidden (1 for hidden, 0 for visible). (Refer parameter `uint8_t ssid_hidden` from `struct wifi_ap_config_t`) | + | ap.max.conn | u8 | Optional | Maximum number of connections the AP supports. It is different for different chips.(Please refer parameter `uint8_t max_connection` from `struct wifi_ap_config_t` and [AP Basic Configurations](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/wifi.html#ap-basic-configuration) for more details). | + | bcn.interval | u8 | Optional | Beacon interval time for the AP. (Refer parameter `uint16_t beacon_interval` from `struct wifi_ap_config_t`)) | + | ap.pmf_r | u8 | Optional | Whether PMF is required on the AP. (Refer parameter `wifi_pmf_config_t pmf_cfg` from `struct wifi_ap_config_t`)) | + | ap.p_cipher | u8 | Optional | Pairwise Cipher suite used by the AP e.g. enum wifi_cipher_type_t (Refer parameter `wifi_cipher_type_t pairwise_cipher` from `struct wifi_ap_config_t`) | + | ap.ftm_r | u8 | Optional | Whether FTM (Fine Timing Measurement) responder is enabled. (Refer parameter `bool ftm_responder` from `struct wifi_ap_config_t`) | + | ap.sae_h2e | u8 | Optional | Config method for SAE e.g. enum `wifi_sae_pwe_method_t` (Refer parameter `wifi_sae_pwe_method_t sae_pwe_h2e` from `struct wifi_ap_config_t`) | + | ap.csa_count | u8 | Optional | Channel Switch Announcement count for the AP. (Refer parameter `uint8_t csa_count` from `struct wifi_ap_config_t`) | + | ap.dtim_period | u8 | Optional | DTIM period for the AP. (Refer parameter `uint8_t dtim_period` from `struct wifi_ap_config_t`) | + | ap.phym5g | u8 | Optional | 5 GHz physical mode. (Refer `esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap)`) | + | ap.phybw5g | u8 | Optional | 5 GHz bandwidth setting. (Refer `esp_err_t esp_wifi_set_bandwidths(wifi_interface_t ifx, wifi_bandwidth_t bw)`) | + +### Generic Keys + + | Key Name | Encoding Type | Mandatory/Optional | Description / Meaning | + |--------------------------|---------------|---------------------|----------------------------------------------------| + | opmode | u8 | Mandatory | Operating mode (e.g. enum `wifi_mode_t` OR refer `esp_err_t esp_wifi_set_mode(wifi_mode_t mode)`) | + | country | blob | Optional | Operating country (e.g. enum `wifi_country_t` OR refer `esp_err_t esp_wifi_set_country_code(const char *country, bool ieee80211d_enabled)`) | + | band_mode | u8 | Optional | Operating band (e.g. enum `wifi_band_t` or refer [esp_err_t esp_wifi_set_band_mode(wifi_band_mode_t band_mode)](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/network/esp_wifi.html#_CPPv422esp_wifi_set_band_mode16wifi_band_mode_t)) | + +These keys can be configured by setting the desired values in `nvs_station_data.csv` or `nvs_ap_data.csv`. + +For more details on station and AP configurations, refer to the following: + +- [Station Basic Configuration](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/wifi.html#station-basic-configuration) +- [AP Basic Configuration](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/wifi.html#ap-basic-configuration) + +Also review the limitations for values of each key in the [ESP-IDF API Reference Guide](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-reference/network/esp_wifi.html). + + +## Example Output +Note that the output, in particular the order of the output, may vary depending on the environment. + +Console output if station connects to AP successfully: +``` +I (599) wifi: wifi driver task: 3ffc08b4, prio:23, stack:3584, core=0 +I (599) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE +I (599) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE +I (629) wifi: wifi firmware version: 2d94f02 +I (629) wifi: config NVS flash: enabled +I (629) wifi: config nano formatting: disabled +I (629) wifi: Init dynamic tx buffer num: 32 +I (629) wifi: Init data frame dynamic rx buffer num: 32 +I (639) wifi: Init management frame dynamic rx buffer num: 32 +I (639) wifi: Init management short buffer num: 32 +I (649) wifi: Init static rx buffer size: 1600 +I (649) wifi: Init static rx buffer num: 10 +I (659) wifi: Init dynamic rx buffer num: 32 +I (759) phy: phy_version: 4180, cb3948e, Sep 12 2019, 16:39:13, 0, 0 +I (769) wifi: mode : sta (30:ae:a4:d9:bc:c4) +I (769) wifi station: wifi_init_sta finished. +I (889) wifi: new:<6,0>, old:<1,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (889) wifi: state: init -> auth (b0) +I (899) wifi: state: auth -> assoc (0) +I (909) wifi: state: assoc -> run (10) +I (939) wifi: connected with #!/bin/test, aid = 1, channel 6, BW20, bssid = ac:9e:17:7e:31:40 +I (939) wifi: security type: 3, phy: bgn, rssi: -68 +I (949) wifi: pm start, type: 1 + +I (1029) wifi: AP's beacon interval = 102400 us, DTIM period = 3 +I (2089) esp_netif_handlers: sta ip: 192.168.77.89, mask: 255.255.255.0, gw: 192.168.77.1 +I (2089) wifi station: got ip:192.168.77.89 +I (2089) wifi station: connected to ap SSID:myssid password:mypassword +``` + +Console output if the station failed to connect to AP: +``` +I (599) wifi: wifi driver task: 3ffc08b4, prio:23, stack:3584, core=0 +I (599) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE +I (599) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE +I (629) wifi: wifi firmware version: 2d94f02 +I (629) wifi: config NVS flash: enabled +I (629) wifi: config nano formatting: disabled +I (629) wifi: Init dynamic tx buffer num: 32 +I (629) wifi: Init data frame dynamic rx buffer num: 32 +I (639) wifi: Init management frame dynamic rx buffer num: 32 +I (639) wifi: Init management short buffer num: 32 +I (649) wifi: Init static rx buffer size: 1600 +I (649) wifi: Init static rx buffer num: 10 +I (659) wifi: Init dynamic rx buffer num: 32 +I (759) phy: phy_version: 4180, cb3948e, Sep 12 2019, 16:39:13, 0, 0 +I (759) wifi: mode : sta (30:ae:a4:d9:bc:c4) +I (769) wifi station: wifi_init_sta finished. +I (889) wifi: new:<6,0>, old:<1,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (889) wifi: state: init -> auth (b0) +I (1889) wifi: state: auth -> init (200) +I (1889) wifi: new:<6,0>, old:<6,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (1889) wifi station: retry to connect to the AP +I (1899) wifi station: connect to the AP fail +I (3949) wifi station: retry to connect to the AP +I (3949) wifi station: connect to the AP fail +I (4069) wifi: new:<6,0>, old:<6,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (4069) wifi: state: init -> auth (b0) +I (5069) wifi: state: auth -> init (200) +I (5069) wifi: new:<6,0>, old:<6,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (5069) wifi station: retry to connect to the AP +I (5069) wifi station: connect to the AP fail +I (7129) wifi station: retry to connect to the AP +I (7129) wifi station: connect to the AP fail +I (7249) wifi: new:<6,0>, old:<6,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (7249) wifi: state: init -> auth (b0) +I (8249) wifi: state: auth -> init (200) +I (8249) wifi: new:<6,0>, old:<6,0>, ap:<255,255>, sta:<6,0>, prof:1 +I (8249) wifi station: retry to connect to the AP +I (8249) wifi station: connect to the AP fail +I (10299) wifi station: connect to the AP fail +I (10299) wifi station: Failed to connect to SSID:myssid, password:mypassword +``` + +## Troubleshooting + +For any technical queries, please open an [issue](https://github.com/espressif/esp-idf/issues) on GitHub. We will get back to you soon. diff --git a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml index e23c477367..d723dc9ae1 100644 --- a/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml +++ b/tools/ci/dynamic_pipelines/templates/known_generate_test_child_pipeline_warnings.yml @@ -17,12 +17,8 @@ no_runner_tags: - esp32c5,jtag - esp32c5_2,generic_multi_device - esp32c6,jtag - - esp32c61,generic - esp32c61,jtag - esp32c61,usb_serial_jtag - - esp32c61,wifi_ap - - esp32c61,wifi_router - - esp32c61_2,wifi_two_dut - esp32h2,jtag - esp32p4,jtag - esp32s2,usb_host_flash_disk diff --git a/tools/ci/idf_pytest/constants.py b/tools/ci/idf_pytest/constants.py index 35399bec0d..d816f5bbcd 100644 --- a/tools/ci/idf_pytest/constants.py +++ b/tools/ci/idf_pytest/constants.py @@ -147,6 +147,7 @@ ENV_MARKERS = { 'ram_app': 'ram_app runners', 'esp32c3eco7': 'esp32c3 major version(v1.1) chips', 'esp32c2eco4': 'esp32c2 major version(v2.0) chips', + 'recovery_bootloader': 'Runner with recovery bootloader offset set in eFuse', } # by default the timeout is 1h, for some special cases we need to extend it