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feat(all): Use PRIx macro in all logs

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This commit is contained in:
Konstantin Kondrashov
2024-03-07 17:43:45 +02:00
parent 08d1460f15
commit 3f89072af1
57 changed files with 194 additions and 194 deletions
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components/esp_mm/esp_cache.c
+2 -2
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@@ -32,7 +32,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
uint32_t addr_end = 0;
bool ovf = __builtin_add_overflow((uint32_t)addr, size, &addr_end);
ESP_EARLY_LOGV(TAG, "addr_end: 0x%x\n", addr_end);
ESP_EARLY_LOGV(TAG, "addr_end: 0x%" PRIx32, addr_end);
ESP_RETURN_ON_FALSE_ISR(!ovf, ESP_ERR_INVALID_ARG, TAG, "wrong size, total size overflow");
bool both_dir = (flags & ESP_CACHE_MSYNC_FLAG_DIR_C2M) && (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C);
@@ -53,7 +53,7 @@ esp_err_t esp_cache_msync(void *addr, size_t size, int flags)
uint32_t cache_line_size = cache_hal_get_cache_line_size(cache_level, cache_type);
if ((flags & ESP_CACHE_MSYNC_FLAG_UNALIGNED) == 0) {
bool aligned_addr = (((uint32_t)addr % cache_line_size) == 0) && ((size % cache_line_size) == 0);
ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address: 0x%x, or the size: 0x%x is(are) not aligned with cache line size (0x%x)B", (uint32_t)addr, size, cache_line_size);
ESP_RETURN_ON_FALSE_ISR(aligned_addr, ESP_ERR_INVALID_ARG, TAG, "start address: 0x%" PRIx32 ", or the size: 0x%" PRIx32 " is(are) not aligned with cache line size (0x%" PRIx32 ")B", (uint32_t)addr, (uint32_t)size, cache_line_size);
}
if (flags & ESP_CACHE_MSYNC_FLAG_DIR_M2C) {