diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
index a8bc0d5b18..97f6eefb0b 100644
--- a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+++ b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c
@@ -19,11 +19,13 @@
 #include "soc/lp_clkrst_reg.h"
 #include "soc/lp_system_reg.h"
 #include "soc/pmu_reg.h"
+#include "soc/chip_revision.h"
 #include "esp_hw_log.h"
 #include "sdkconfig.h"
 #include "esp_rom_uart.h"
 #include "esp_private/esp_pmu.h"
 #include "hal/clk_tree_ll.h"
+#include "hal/efuse_hal.h"
 
 static const char *TAG = "rtc_clk_init";
 
@@ -71,6 +73,10 @@ void rtc_clk_init(rtc_clk_config_t cfg)
     pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
     SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
     esp_rom_delay_us(1000);
+    unsigned chip_version = efuse_hal_chip_revision();
+    if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
+        REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
+    }
     pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, false);
 
     soc_xtal_freq_t xtal_freq = cfg.xtal_freq;
diff --git a/components/soc/esp32p4/register/hw_ver1/soc/lp_system_reg.h b/components/soc/esp32p4/register/hw_ver1/soc/lp_system_reg.h
index 910c591aaa..a0485fa38d 100644
--- a/components/soc/esp32p4/register/hw_ver1/soc/lp_system_reg.h
+++ b/components/soc/esp32p4/register/hw_ver1/soc/lp_system_reg.h
@@ -88,6 +88,14 @@ extern "C" {
 #define LP_SYSTEM_REG_ANA_FIB_M  (LP_SYSTEM_REG_ANA_FIB_V << LP_SYSTEM_REG_ANA_FIB_S)
 #define LP_SYSTEM_REG_ANA_FIB_V  0x0000007FU
 #define LP_SYSTEM_REG_ANA_FIB_S  14
+/** LP_SYSTEM_REG_LP_FIB_SEL : R/W; bitpos: [28:21]; default: 255;
+ *  This is for compatibility with hw_ver3 chips
+ *  This field does not exist on hw_ver1 chips
+ */
+#define LP_SYSTEM_REG_LP_FIB_SEL    0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_M  (LP_SYSTEM_REG_LP_FIB_SEL_V << LP_SYSTEM_REG_LP_FIB_SEL_S)
+#define LP_SYSTEM_REG_LP_FIB_SEL_V  0x000000FFU
+#define LP_SYSTEM_REG_LP_FIB_SEL_S  21
 /** LP_SYSTEM_REG_LP_FIB_BOD_RESET : R/W; bitpos: [22]; default: 1;
  *  need_des
  */