feat(cache): added cache msync doc
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@@ -153,10 +153,7 @@ SPI Flash can be accessed by SPI1 (ESP-IDF ``esp_flash`` driver APIs), or by poi
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PSRAM can also be accessed by EDMA. Data desynchronisation may happen because hardware does not guarantee the data consistency under such condition. You should call :cpp:func:`esp_cache_msync` to synchronise the Cache and the PSRAM.
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:cpp:func:`esp_cache_msync` has two synchronization directions,
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* :c:macro:`ESP_CACHE_MSYNC_FLAG_DIR_C2M`: from cache to memory. By default (if you do not specify a direction), the synchronization is in this direction. Content in the address you specified is written back to the memory.
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* :c:macro:`ESP_CACHE_MSYNC_FLAG_DIR_M2C`: from memory to cache. By default, content in the address you specified is invalidated from the cache.
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See :doc:`Memory Synchronization </api-reference/system/mm_sync>` for more details.
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Thread Safety
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@@ -174,9 +171,3 @@ API Reference - ESP MMAP Driver
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-------------------------------
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.. include-build-file:: inc/esp_mmu_map.inc
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API Reference - ESP MSYNC Driver
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--------------------------------
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.. include-build-file:: inc/esp_cache.inc
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