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esp_rom: extract common efuse apis into esp_rom_efuse.h

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This commit is contained in:
morris
2020-07-13 21:57:24 +08:00
parent 24e49cc21d
commit 458b14a8ea
24 changed files with 124 additions and 68 deletions
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components/bootloader_support/src/bootloader_flash_config_esp32.c
+3 -3
View File
@@ -18,8 +18,8 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/efuse.h"
#include "soc/gpio_periph.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
@@ -91,8 +91,8 @@ void IRAM_ATTR bootloader_flash_gpio_config(const esp_image_header_t* pfhdr)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
} else {
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_CS, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(SPI_IOMUX_PIN_NUM_MISO, SPIQ_IN_IDX, 0);
components/bootloader_support/src/bootloader_flash_config_esp32s2.c
-1
View File
@@ -18,7 +18,6 @@
#include "esp_err.h"
#include "esp_log.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/efuse.h"
#include "soc/efuse_reg.h"
#include "soc/spi_reg.h"
#include "soc/spi_mem_reg.h"
components/bootloader_support/src/bootloader_utility.c
-2
View File
@@ -21,7 +21,6 @@
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/cache.h"
#include "esp32/rom/efuse.h"
#include "esp32/rom/ets_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
@@ -29,7 +28,6 @@
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/efuse.h"
#include "esp32s2/rom/ets_sys.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/rtc.h"
components/bootloader_support/src/esp32/bootloader_esp32.c
+5 -5
View File
@@ -35,9 +35,9 @@
#include "soc/spi_periph.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/efuse.h"
#include "esp32/rom/ets_sys.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/uart.h"
@@ -72,8 +72,8 @@ void bootloader_configure_spi_pins(int drv)
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
} else {
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) {
esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
@@ -260,8 +260,8 @@ static esp_err_t bootloader_init_spi_flash(void)
{
bootloader_init_flash_configure();
#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
return ESP_FAIL;
}
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
+5 -5
View File
@@ -18,8 +18,8 @@
#include "soc/gpio_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "esp32s2/rom/efuse.h"
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp32s2/rom/spi_flash.h"
#include "bootloader_init.h"
@@ -48,8 +48,8 @@
static const char *TAG = "boot.esp32s2";
void bootloader_configure_spi_pins(int drv)
{
const uint32_t spiconfig = ets_efuse_get_spiconfig();
uint8_t wp_pin = ets_efuse_get_wp_pad();
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio();
uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
uint8_t q_gpio_num = SPI_Q_GPIO_NUM;
uint8_t d_gpio_num = SPI_D_GPIO_NUM;
@@ -199,8 +199,8 @@ static esp_err_t bootloader_init_spi_flash(void)
{
bootloader_init_flash_configure();
#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
const uint32_t spiconfig = ets_efuse_get_spiconfig();
if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
return ESP_FAIL;
}
components/bootloader_support/src/esp32s2/secure_boot.c
+2 -2
View File
@@ -21,7 +21,7 @@ esp_err_t esp_secure_boot_permanently_enable(void)
{
uint8_t hash[32];
if (ets_efuse_secure_boot_enabled())
if (esp_rom_efuse_is_secure_boot_enabled())
{
ESP_LOGI(TAG, "secure boot is already enabled, continuing..");
return ESP_OK;
@@ -45,7 +45,7 @@ esp_err_t esp_secure_boot_permanently_enable(void)
esp_err_t err = esp_efuse_batch_write_commit();
if (err == ESP_OK) {
assert(ets_efuse_secure_boot_enabled());
assert(esp_rom_efuse_is_secure_boot_enabled());
ESP_LOGI(TAG, "Secure boot permanently enabled");
}
components/bootloader_support/src/flash_qio_mode.c
+5 -6
View File
@@ -16,12 +16,11 @@
#include "flash_qio_mode.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_rom_efuse.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/efuse.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/efuse.h"
#include "soc/spi_mem_struct.h"
#endif
#include "soc/spi_struct.h"
@@ -222,10 +221,10 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
uint8_t status_qio_bit)
{
uint32_t status;
const uint32_t spiconfig = ets_efuse_get_spiconfig();
const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
#if CONFIG_IDF_TARGET_ESP32
if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
// spiconfig specifies a custom efuse pin configuration. This config defines all pins -except- WP,
// which is compiled into the bootloader instead.
//
@@ -278,8 +277,8 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
#if CONFIG_IDF_TARGET_ESP32
esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
#elif CONFIG_IDF_TARGET_ESP32S2
if (ets_efuse_get_wp_pad() <= MAX_PAD_GPIO_NUM) {
esp_rom_spiflash_select_qio_pins(ets_efuse_get_wp_pad(), spiconfig);
if (esp_rom_efuse_get_flash_wp_gpio() <= MAX_PAD_GPIO_NUM) {
esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), spiconfig);
} else {
esp_rom_spiflash_select_qio_pins(CONFIG_BOOTLOADER_SPI_WP_PIN, spiconfig);
}