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ESP32H2: Introduce new chip target esp32h2, hello_world example supported

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This commit is contained in:
Cao Sen Miao
2022-12-29 11:01:13 +08:00
parent 4e67332b74
commit 4713a9a7f2
98 changed files with 3911 additions and 99 deletions
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components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+1 -9
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@@ -3,10 +3,6 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_IEEE802154_SUPPORTED
bool
default y
config SOC_IEEE802154_BLE_ONLY
bool
default y
@@ -69,7 +65,7 @@ config SOC_ADC_MONITOR_SUPPORTED
config SOC_ADC_PERIPH_NUM
int
default 2
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
@@ -539,10 +535,6 @@ config SOC_SPI_SUPPORT_CONTINUOUS_TRANS
bool
default y
config SOC_SPI_SUPPORT_SLAVE_HD_VER2
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
components/soc/esp32h2/include/soc/aes_struct.h
+2 -2
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@@ -377,7 +377,7 @@ typedef union {
/** continue : WT; bitpos: [0]; default: 0;
* Set this bit to continue GCM operation.
*/
uint32_t continue:1;
uint32_t conti:1;
uint32_t reserved_1:31;
};
uint32_t val;
@@ -478,7 +478,7 @@ typedef struct {
volatile aes_inc_sel_reg_t inc_sel;
volatile aes_aad_block_num_reg_t aad_block_num;
volatile aes_remainder_bit_num_reg_t remainder_bit_num;
volatile aes_continue_reg_t continue;
volatile aes_continue_reg_t conti;
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
components/soc/esp32h2/include/soc/apb_saradc_struct.h
+2 -2
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@@ -744,12 +744,12 @@ typedef struct {
volatile apb_tsens_sample_reg_t tsens_sample;
uint32_t reserved_06c[228];
volatile apb_saradc_ctrl_date_reg_t saradc_ctrl_date;
} apb_dev_t;
} apb_saradc_dev_t;
extern apb_saradc_dev_t APB_SARADC;
#ifndef __cplusplus
_Static_assert(sizeof(apb_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
_Static_assert(sizeof(apb_saradc_dev_t) == 0x400, "Invalid size of apb_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32h2/include/soc/ext_mem_defs.h
+1
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@@ -7,6 +7,7 @@
#define _CACHE_MEMORY_H_
#include "esp_bit_defs.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
components/soc/esp32h2/include/soc/interrupt_matrix_struct.h
+3 -3
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@@ -989,7 +989,7 @@ typedef union {
} intmtx_core0_interrupt_reg_date_reg_t;
typedef struct {
typedef struct interrupt_matrix_dev_t {
volatile intmtx_core0_pmu_intr_map_reg_t pmu_intr_map;
volatile intmtx_core0_efuse_intr_map_reg_t efuse_intr_map;
volatile intmtx_core0_lp_rtc_timer_intr_map_reg_t lp_rtc_timer_intr_map;
@@ -1061,12 +1061,12 @@ typedef struct {
volatile intmtx_core0_clock_gate_reg_t clock_gate;
uint32_t reserved_114[442];
volatile intmtx_core0_interrupt_reg_date_reg_t interrupt_reg_date;
} intmtx_core0_dev_t;
} interrupt_matrix_dev_t;
extern interrupt_matrix_dev_t INTMTX;
#ifndef __cplusplus
_Static_assert(sizeof(intmtx_core0_dev_t) == 0x800, "Invalid size of intmtx_core0_dev_t structure");
_Static_assert(sizeof(interrupt_matrix_dev_t) == 0x800, "Invalid size of interrupt_matrix_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32h2/include/soc/pmu_icg_mapping.h
-1
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@@ -64,4 +64,3 @@
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_HPBUS 15
#endif /* _SOC_ICG_MAP_H_ */
components/soc/esp32h2/include/soc/sha_struct.h
+2 -2
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@@ -89,7 +89,7 @@ typedef union {
/** continue : RO; bitpos: [31:1]; default: 0;
* Reserved.
*/
uint32_t continue:31;
uint32_t conti:31;
};
uint32_t val;
} sha_continue_reg_t;
@@ -193,7 +193,7 @@ typedef struct {
volatile sha_t_length_reg_t t_length;
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_continue_reg_t conti;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
components/soc/esp32h2/include/soc/soc.h
+4 -4
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@@ -163,10 +163,10 @@
#define SOC_IROM_LOW 0x42000000
#define SOC_IROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<7))
#define SOC_DROM_LOW SOC_IROM_HIGH
#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8))
#define SOC_DROM_HIGH (SOC_IROM_LOW + (CONFIG_MMU_PAGE_SIZE<<8)) // ESP32H2 MMU-TODO: IDF-6251
#define SOC_IROM_MASK_LOW 0x40000000
#define SOC_IROM_MASK_HIGH 0x4004A000
#define SOC_DROM_MASK_LOW 0x4004A000
#define SOC_IROM_MASK_HIGH 0x4001C400
#define SOC_DROM_MASK_LOW 0x4001C400
#define SOC_DROM_MASK_HIGH 0x40020000
#define SOC_IRAM_LOW 0x40800000
#define SOC_IRAM_HIGH 0x40850000
@@ -212,7 +212,7 @@
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4087c770
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
//There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.
components/soc/esp32h2/include/soc/soc_caps.h
+4 -3
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@@ -32,7 +32,7 @@
// #define SOC_MCPWM_SUPPORTED 1 // TODO: IDF-6237
// #define SOC_TWAI_SUPPORTED 1 // TODO: IDF-6217
// #define SOC_BT_SUPPORTED 1 // TODO: IDF-6416
#define SOC_IEEE802154_SUPPORTED 1
// #define SOC_IEEE802154_SUPPORTED 1 // TODO: IDF-6577
#define SOC_IEEE802154_BLE_ONLY 1
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: IDF-6238
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: IDF-6239
@@ -46,6 +46,7 @@
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-6219
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-6224
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-6220
// #define SOC_GPSPI_SUPPORTED 1 // TODO: IDF-6264
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: IDF-6416
// #define SOC_AES_SUPPORTED 1 // TODO: IDF-6280
@@ -76,7 +77,7 @@
#define SOC_ADC_ARBITER_SUPPORTED 1
#define SOC_ADC_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
#define SOC_ADC_MAX_CHANNEL_NUM (5)
#define SOC_ADC_ATTEN_NUM (4)
@@ -307,7 +308,7 @@
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1
//#define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 //TODO: IDF-6247
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,