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clk_tree: Update clock tree programming guide for esp32c6

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Song Ruo Jing
2022-12-28 19:33:22 +08:00
parent c7c2462d39
commit 4bd36e6576
3 changed files with 15 additions and 12 deletions
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docs/en/api-reference/peripherals/clk_tree.rst
+12 -8
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@@ -1,11 +1,11 @@
Clock Tree
==========
{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8"}
{IDF_TARGET_RC_FAST_VAGUE_FREQ: default="8", esp32="8", esp32s2="8", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8"}
{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32h4="8.5"}
{IDF_TARGET_RC_FAST_ADJUSTED_FREQ: default="8.5", esp32="8.5", esp32s2="8.5", esp32c3="17.5", esp32s3="17.5", esp32c2="17.5", esp32c6="17.5", esp32h4="8.5"}
{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32s2="40", esp32c3="40", esp32s3="40", esp32c2="40", esp32h4="32"}
{IDF_TARGET_XTAL_FREQ: default="40", esp32="2~40", esp32c2="40/26", esp32h4="32"}
{IDF_TARGET_RC_SLOW_VAGUE_FREQ: default="136", esp32="150", esp32s2="90"}
@@ -31,13 +31,17 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
This RC oscillator generates a ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz clock signal output as the RC_FAST_CLK.
.. only:: not esp32h4
.. only:: SOC_CLK_RC_FAST_D256_SUPPORTED
The ~{IDF_TARGET_RC_FAST_ADJUSTED_FREQ}MHz signal output is also passed into a configurable divider, which by default divides the input clock frequency by 256, to generate a RC_FAST_D256_CLK.
The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
.. only:: not SOC_CLK_RC_FAST_D256_SUPPORTED and SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
.. only:: esp32h4
The exact frequency of RC_FAST_CLK can be computed in runtime through calibration.
.. only:: not SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration, but it is still possible to get its frequency through an oscillscope or a logic analyzer by routing the clock signal to a GPIO pin.
@@ -47,7 +51,7 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
This RC oscillator generates a ~{IDF_TARGET_RC_SLOW_VAGUE_FREQ}kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock can be computed in runtime through calibration.
.. only:: not esp32c2
.. only:: SOC_CLK_XTAL32K_SUPPORTED
- External 32kHz Crystal - optional (XTAL32K)
@@ -61,13 +65,13 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
XTAL32K_CLK can also be calibrated to get its exact frequency.
.. only:: esp32c2
.. only:: SOC_CLK_OSC_SLOW_SUPPORTED
- External Slow Clock - optional (OSC_SLOW)
A clock signal generated by an external circuit can be connected to pin0 to be the clock source for the RTC_SLOW_CLK. This clock can also be calibrated to get its exact frequency.
.. only:: esp32h4
.. only:: SOC_CLK_RC32K_SUPPORTED
- Internal 32kHz RC Oscillator (RC32K)