esp32s3: Remove APB frequency RTC register

Usage of this register changed between ESP32-S3 beta2 and the
final chip.

components/esp_system/fpga_overrides.c

@@ -22,6 +22,13 @@
 
 static const char *TAG = "fpga";
 
+#ifdef CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/rtc.h"
+#endif
+#ifdef CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/rtc.h"
+#endif
+
 extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
 
 static void s_warn(void)
@@ -41,7 +48,9 @@ void bootloader_clock_configure(void)
     uint32_t apb_freq_hz = 40000000;
 #endif // CONFIG_IDF_TARGET_ESP32S2
     ets_update_cpu_frequency(apb_freq_hz / 1000000);
-    REG_WRITE(RTC_CNTL_STORE5_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
+#ifdef RTC_APB_FREQ_REG
+    REG_WRITE(RTC_APB_FREQ_REG, (apb_freq_hz >> 12) | ((apb_freq_hz >> 12) << 16));
+#endif
     REG_WRITE(RTC_CNTL_STORE4_REG, (xtal_freq_mhz) | ((xtal_freq_mhz) << 16));
 }
 

components/esp_system/port/soc/esp32s3/reset_reason.c

@@ -84,10 +84,8 @@ esp_reset_reason_t esp_reset_reason(void)
  * is only used for deep sleep reset, and in this case the reason provided by
  * rtc_get_reset_reason is unambiguous.
  *
- * Same layout is used as for RTC_APB_FREQ_REG (a.k.a. RTC_CNTL_STORE5_REG):
- * the value is replicated in low and high half-words. In addition to that,
- * MSB is set to 1, which doesn't happen when RTC_CNTL_STORE6_REG contains
- * deep sleep wake stub address.
+ * In addition to that, MSB is set to 1, which doesn't happen when
+ * RTC_CNTL_STORE6_REG contains deep sleep wake stub address.
  */
 
 #define RST_REASON_BIT  0x80000000