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Merge branch 'feature/optimize_chips_active_power' into 'master'

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feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798
This commit is contained in:
Wu Zheng Hui
2024-03-14 12:08:33 +08:00
parent 79d8057a8c 0fc97f0e84
commit 5a682c3bbb
45 changed files with 617 additions and 227 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/Kconfig
+9
View File
@@ -269,6 +269,7 @@ menu "ESP System Settings"
# Internal option, indicates that console USB SERIAL JTAG is used
bool
default y if ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG
select USJ_ENABLE_USB_SERIAL_JTAG
config ESP_CONSOLE_UART
# Internal option, indicates that console UART is used (and not USB, for example)
@@ -586,6 +587,14 @@ menu "ESP System Settings"
which may increase about the boot-up time by about 200 us. Disable this when your bootloader is built with
ESP-IDF version v5.2 and above.
config ESP_SYSTEM_HW_PC_RECORD
bool "Hardware PC recording"
depends on SOC_ASSIST_DEBUG_SUPPORTED
default y
help
This option will enable the PC recording function of assist_debug module. The PC value of the CPU will be
recorded to PC record register in assist_debug module in real time. When an exception occurs and the CPU
is reset, this register will be kept, then we can use the recorded PC to debug the causes of the reset.
endmenu # ESP System Settings
menu "IPC (Inter-Processor Call)"
components/esp_system/port/soc/esp32c2/clk.c
+7
View File
@@ -228,6 +228,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_I2C_EXT0_CLK_EN;
common_perip_clk1 = 0;
#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
/* Disable ASSIST Debug module clock if PC recoreding function is not used,
* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
SET_PERI_REG_MASK(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
#endif
/* Disable some peripheral clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
components/esp_system/port/soc/esp32c3/clk.c
+15
View File
@@ -21,6 +21,8 @@
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/wdt_hal.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "soc/syscon_reg.h"
@@ -241,6 +243,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_WIFI_CLK_BT_EN_M |
SYSTEM_WIFI_CLK_I2C_CLK_EN |
SYSTEM_WIFI_CLK_UNUSED_BIT12;
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
_usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
@@ -271,6 +279,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
// REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
// REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
/* Disable ASSIST Debug module clock if PC recoreding function is not used,
* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
CLEAR_PERI_REG_MASK(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
SET_PERI_REG_MASK(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
#endif
/* Disable some peripheral clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
components/esp_system/port/soc/esp32c6/clk.c
+98 -90
View File
@@ -18,8 +18,29 @@
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "esp_cpu.h"
#include "hal/wdt_hal.h"
#include "hal/uart_ll.h"
#include "hal/i2c_ll.h"
#include "hal/rmt_ll.h"
#include "hal/ledc_ll.h"
#include "hal/lp_clkrst_ll.h"
#include "hal/timer_ll.h"
#include "hal/twai_ll.h"
#include "hal/i2s_ll.h"
#include "hal/pcnt_ll.h"
#include "hal/etm_ll.h"
#include "hal/mcpwm_ll.h"
#include "hal/parlio_ll.h"
#include "hal/gdma_ll.h"
#include "hal/spi_ll.h"
#include "hal/clk_gate_ll.h"
#include "hal/lp_core_ll.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/esp_modem_clock.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
@@ -193,102 +214,89 @@ __attribute__((weak)) void esp_perip_clk_init(void)
: SOC_RTC_SLOW_CLK_SRC_RC_SLOW);
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: IDF-5658
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
} else {
common_perip_clk = SYSTEM_WDG_CLK_EN |
SYSTEM_I2S0_CLK_EN |
if (rst_reason != RESET_REASON_CPU0_MWDT0 && rst_reason != RESET_REASON_CPU0_MWDT1 \
&& rst_reason != RESET_REASON_CPU0_SW && rst_reason != RESET_REASON_CPU0_RTC_WDT \
&& RESET_REASON_CPU0_JTAG) {
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
uart_ll_enable_bus_clock(UART_NUM_0, false);
#elif CONFIG_ESP_CONSOLE_UART_NUM != 1
uart_ll_enable_bus_clock(UART_NUM_1, false);
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
i2c_ll_enable_bus_clock(0, false);
i2c_ll_enable_controller_clock(&I2C0, false);
rmt_ll_enable_bus_clock(0, false);
rmt_ll_enable_group_clock(0, false);
ledc_ll_enable_clock(&LEDC, false);
ledc_ll_enable_bus_clock(false);
timer_ll_enable_clock(&TIMERG0, 0, false);
timer_ll_enable_clock(&TIMERG1, 0, false);
_timer_ll_enable_bus_clock(0, false);
_timer_ll_enable_bus_clock(1, false);
twai_ll_enable_clock(0, false);
twai_ll_enable_bus_clock(0, false);
twai_ll_enable_clock(1, false);
twai_ll_enable_bus_clock(1, false);
i2s_ll_enable_bus_clock(0, false);
i2s_ll_tx_disable_clock(&I2S0);
i2s_ll_rx_disable_clock(&I2S0);
pcnt_ll_enable_bus_clock(0, false);
etm_ll_enable_bus_clock(0, false);
mcpwm_ll_enable_bus_clock(0, false);
mcpwm_ll_group_enable_clock(0, false);
parlio_ll_rx_enable_clock(&PARL_IO, false);
parlio_ll_tx_enable_clock(&PARL_IO, false);
parlio_ll_enable_bus_clock(0, false);
gdma_ll_force_enable_reg_clock(&GDMA, false);
gdma_ll_enable_bus_clock(0, false);
#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
spi_ll_enable_bus_clock(SPI1_HOST, false);
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_LEDC_CLK_EN |
SYSTEM_TIMERGROUP1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_TWAI_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
spi_ll_enable_bus_clock(SPI2_HOST, false);
temperature_sensor_ll_bus_clk_enable(false);
common_perip_clk1 = 0;
hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
SYSTEM_CRYPTO_SHA_CLK_EN |
SYSTEM_CRYPTO_RSA_CLK_EN;
wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
SYSTEM_WIFI_CLK_BT_EN_M |
SYSTEM_WIFI_CLK_UNUSED_BIT5 |
SYSTEM_WIFI_CLK_UNUSED_BIT12;
periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_SDIO_SLAVE_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_REGDMA_MODULE);
#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
/* Disable ASSIST Debug module clock if PC recoreding function is not used,
* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE);
#endif
periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
// TODO: Replace with hal implementation
REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
REG_CLR_BIT(PCR_RETENTION_CONF_REG, PCR_RETENTION_CLK_EN);
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
common_perip_clk |= SYSTEM_I2S0_CLK_EN |
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_UHCI1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_I2C_EXT1_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
_lp_i2c_ll_enable_bus_clock(0, false);
_lp_uart_ll_enable_bus_clock(0, false);
lp_core_ll_enable_bus_clock(false);
_lp_clkrst_ll_enable_rng_clock(false);
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
* the current is not reduced when disable I2S clock.
*/
// TOCK(check replacement)
// REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
// REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
/* Disable some peripheral clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
/* Disable hardware crypto clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
/* Disable WiFi/BT/SDIO clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
#endif
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
}
}
components/esp_system/port/soc/esp32h2/clk.c
+93 -92
View File
@@ -16,11 +16,32 @@
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/uart.h"
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "soc/lpperi_reg.h"
#include "soc/lp_clkrst_reg.h"
#include "soc/pcr_reg.h"
#include "hal/wdt_hal.h"
#include "hal/uart_ll.h"
#include "hal/i2c_ll.h"
#include "hal/rmt_ll.h"
#include "hal/ledc_ll.h"
#include "hal/lp_clkrst_ll.h"
#include "hal/timer_ll.h"
#include "hal/twai_ll.h"
#include "hal/i2s_ll.h"
#include "hal/pcnt_ll.h"
#include "hal/etm_ll.h"
#include "hal/mcpwm_ll.h"
#include "hal/parlio_ll.h"
#include "hal/gdma_ll.h"
#include "hal/spi_ll.h"
#include "hal/clk_gate_ll.h"
#include "hal/temperature_sensor_ll.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_pmu.h"
@@ -186,103 +207,83 @@ __attribute__((weak)) void esp_perip_clk_init(void)
: ESP_PD_DOMAIN_MAX);
esp_sleep_pd_config(pu_domain, ESP_PD_OPTION_ON);
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
// ESP32H2-TODO: IDF-5658
#if 0
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
uint32_t common_perip_clk1 = 0;
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
/* For reason that only reset CPU, do not disable the clocks
* that have been enabled before reset.
*/
if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
} else {
common_perip_clk = SYSTEM_WDG_CLK_EN |
SYSTEM_I2S0_CLK_EN |
if (rst_reason != RESET_REASON_CPU0_MWDT0 && rst_reason != RESET_REASON_CPU0_MWDT1 \
&& rst_reason != RESET_REASON_CPU0_SW && rst_reason != RESET_REASON_CPU0_RTC_WDT) {
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
uart_ll_enable_bus_clock(UART_NUM_0, false);
#elif CONFIG_ESP_CONSOLE_UART_NUM != 1
uart_ll_enable_bus_clock(UART_NUM_1, false);
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
i2c_ll_enable_bus_clock(0, false);
i2c_ll_enable_bus_clock(1, false);
i2c_ll_enable_controller_clock(&I2C0, false);
i2c_ll_enable_controller_clock(&I2C1, false);
rmt_ll_enable_bus_clock(0, false);
rmt_ll_enable_group_clock(0, false);
ledc_ll_enable_clock(&LEDC, false);
ledc_ll_enable_bus_clock(false);
timer_ll_enable_clock(&TIMERG0, 0, false);
timer_ll_enable_clock(&TIMERG1, 0, false);
_timer_ll_enable_bus_clock(0, false);
_timer_ll_enable_bus_clock(1, false);
twai_ll_enable_clock(0, false);
twai_ll_enable_bus_clock(0, false);
i2s_ll_enable_bus_clock(0, false);
i2s_ll_tx_disable_clock(&I2S0);
i2s_ll_rx_disable_clock(&I2S0);
pcnt_ll_enable_bus_clock(0, false);
etm_ll_enable_bus_clock(0, false);
mcpwm_ll_enable_bus_clock(0, false);
mcpwm_ll_group_enable_clock(0, false);
parlio_ll_rx_enable_clock(&PARL_IO, false);
parlio_ll_tx_enable_clock(&PARL_IO, false);
parlio_ll_enable_bus_clock(0, false);
gdma_ll_force_enable_reg_clock(&GDMA, false);
gdma_ll_enable_bus_clock(0, false);
#if CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
spi_ll_enable_bus_clock(SPI1_HOST, false);
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_LEDC_CLK_EN |
SYSTEM_TIMERGROUP1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_TWAI_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
spi_ll_enable_bus_clock(SPI2_HOST, false);
temperature_sensor_ll_bus_clk_enable(false);
common_perip_clk1 = 0;
hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
SYSTEM_CRYPTO_SHA_CLK_EN |
SYSTEM_CRYPTO_RSA_CLK_EN;
wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
SYSTEM_WIFI_CLK_BT_EN_M |
SYSTEM_WIFI_CLK_UNUSED_BIT5 |
SYSTEM_WIFI_CLK_UNUSED_BIT12;
periph_ll_disable_clk_set_rst(PERIPH_UHCI0_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_SARADC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_REGDMA_MODULE);
#if !CONFIG_ESP_SYSTEM_HW_PC_RECORD
/* Disable ASSIST Debug module clock if PC recoreding function is not used,
* if stack guard function needs it, it will be re-enabled at esp_hw_stack_guard_init */
periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE);
#endif
periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);
periph_ll_disable_clk_set_rst(PERIPH_ECDSA_MODULE);
// TODO: Replace with hal implementation
REG_CLR_BIT(PCR_CTRL_TICK_CONF_REG, PCR_TICK_ENABLE);
REG_CLR_BIT(PCR_TRACE_CONF_REG, PCR_TRACE_CLK_EN);
REG_CLR_BIT(PCR_MEM_MONITOR_CONF_REG, PCR_MEM_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
REG_CLR_BIT(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
WRITE_PERI_REG(PCR_CTRL_CLK_OUT_EN_REG, 0);
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
common_perip_clk |= SYSTEM_I2S0_CLK_EN |
#if CONFIG_ESP_CONSOLE_UART_NUM != 0
SYSTEM_UART_CLK_EN |
#endif
#if CONFIG_ESP_CONSOLE_UART_NUM != 1
SYSTEM_UART1_CLK_EN |
#endif
SYSTEM_SPI2_CLK_EN |
SYSTEM_I2C_EXT0_CLK_EN |
SYSTEM_UHCI0_CLK_EN |
SYSTEM_RMT_CLK_EN |
SYSTEM_UHCI1_CLK_EN |
SYSTEM_SPI3_CLK_EN |
SYSTEM_SPI4_CLK_EN |
SYSTEM_I2C_EXT1_CLK_EN |
SYSTEM_I2S1_CLK_EN |
SYSTEM_SPI2_DMA_CLK_EN |
SYSTEM_SPI3_DMA_CLK_EN;
common_perip_clk1 = 0;
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
* the current is not reduced when disable I2S clock.
*/
// TOCK(check replacement)
// REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
// REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
/* Disable some peripheral clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
/* Disable hardware crypto clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
/* Disable WiFi/BT/SDIO clocks. */
CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
/* Set WiFi light sleep clock source to RTC slow clock */
REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL32K | SYSTEM_LPCLK_SEL_XTAL | SYSTEM_LPCLK_SEL_8M | SYSTEM_LPCLK_SEL_RTC_SLOW);
SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
#endif
if (rst_reason == RESET_REASON_CHIP_POWER_ON || rst_reason == RESET_REASON_CHIP_BROWN_OUT \
|| rst_reason == RESET_REASON_SYS_RTC_WDT || rst_reason == RESET_REASON_SYS_SUPER_WDT) {
_lp_clkrst_ll_enable_rng_clock(false);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_OTP_DBG_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_ANA_I2C_CK_EN);
CLEAR_PERI_REG_MASK(LPPERI_CLK_EN_REG, LPPERI_LP_IO_CK_EN);
WRITE_PERI_REG(LP_CLKRST_LP_CLK_PO_EN_REG, 0);
}
}
components/esp_system/port/soc/esp32s3/clk.c
+8
View File
@@ -21,6 +21,8 @@
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "hal/wdt_hal.h"
#include "hal/usb_serial_jtag_ll.h"
#include "hal/usb_fsls_phy_ll.h"
#include "esp_private/periph_ctrl.h"
#include "esp_private/esp_clk.h"
#include "bootloader_clock.h"
@@ -260,6 +262,12 @@ __attribute__((weak)) void esp_perip_clk_init(void)
SYSTEM_WIFI_CLK_I2C_CLK_EN |
SYSTEM_WIFI_CLK_UNUSED_BIT12 |
SYSTEM_WIFI_CLK_SDIO_HOST_EN;
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
// Disable USB-Serial-JTAG clock and it's pad if not used
usb_fsls_phy_ll_int_jtag_disable(&USB_SERIAL_JTAG);
usb_serial_jtag_ll_enable_bus_clock(false);
#endif
}
//Reset the communication peripherals like I2C, SPI, UART, I2S and bring them to known state.
components/esp_system/system_init_fn.txt
+3
View File
@@ -67,6 +67,9 @@ SECONDARY: 100: esp_timer_init_os in components/esp_timer/src/esp_timer.c on ESP
# HW stack guard via assist-debug module.
SECONDARY: 101: esp_hw_stack_guard_init in components/esp_system/hw_stack_guard.c on ESP_SYSTEM_INIT_ALL_CORES
# RNG module clock was disabled in `esp_perip_clk_init`, if hw_random is used, need to re-ebnabled it in startup
SECONDARY: 102: init_rng_clock in components/esp_hw_support/hw_random.c on BIT(0)
# esp_sleep doesn't have init dependencies
SECONDARY: 105: esp_sleep_startup_init in components/esp_hw_support/sleep_gpio.c on BIT(0)
SECONDARY: 106: sleep_clock_startup_init in components/esp_hw_support/sleep_clock.c on BIT(0)