Merge branch 'feature/optimize_chips_active_power' into 'master'

feat(system): Optimize the power consumption of esp32h2 and esp32c6 in the active state

Closes IDF-5658

See merge request espressif/esp-idf!27798

components/hal/esp32h2/include/hal/clk_tree_ll.h

@@ -749,6 +749,16 @@ static inline void clk_ll_rc_fast_tick_conf(void)
     PCR.ctrl_tick_conf.fosc_tick_num = REG_FOSC_TICK_NUM;
 }
 
+/*
+ * Enable/Disable the clock gate for clock output signal source
+*/
+static inline void clk_ll_enable_clkout_source(soc_clkout_sig_id_t clk_src, bool en)
+{
+    if (clk_src == CLKOUT_SIG_XTAL) {
+        PCR.ctrl_clk_out_en.clk_xtal_oen = en;
+    }
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/lp_clkrst_ll.h

@@ -1,10 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-// The LL layer for ESP32-H2 LP CLKRST register operations
+// The LL layer for ESP32-H2 LP CLKRST & LP PERI register operations
 
 #pragma once
 
@@ -12,6 +12,7 @@
 #include <stdlib.h>
 #include "soc/soc.h"
 #include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -59,6 +60,15 @@ static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *h
     hw->lpperi.lp_bletimer_32k_sel = src;
 }
 
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32h2/include/hal/rtc_io_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,7 +12,10 @@
 
 #pragma once
 
+#include <stdbool.h>
+#include "soc/soc_caps.h"
 #include "soc/lp_aon_struct.h"
+#include "soc/lpperi_struct.h"
 #include "soc/pmu_struct.h"
 #include "hal/misc.h"
 
@@ -27,6 +30,19 @@ typedef enum {
     RTCIO_LL_FUNC_DIGITAL = 0x1,     /*!< The pin controlled by DIGITAL module. */
 } rtcio_ll_func_t;
 
+
+/**
+ * @brief Enable/Disable LP_IO peripheral clock.
+ *
+ * @param enable true to enable the clock / false to enable the clock
+ */
+static inline void _rtcio_ll_enable_io_clock(bool enable)
+{
+    LPPERI.clk_en.lp_io_ck_en = enable;
+}
+
+#define rtcio_ll_enable_io_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _rtcio_ll_enable_io_clock(__VA_ARGS__)
+
 /**
  * @brief Select the rtcio function.
  *
@@ -40,6 +56,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
     if (func == RTCIO_LL_FUNC_RTC) {
         // 0: GPIO connected to digital GPIO module. 1: GPIO connected to analog RTC module.
         uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
+        if ((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
+            _rtcio_ll_enable_io_clock(true);
+        }
         sel_mask |= BIT(rtcio_num);
         HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
     } else if (func == RTCIO_LL_FUNC_DIGITAL) {
@@ -47,6 +66,9 @@ static inline void rtcio_ll_function_select(int rtcio_num, rtcio_ll_func_t func)
         uint32_t sel_mask = HAL_FORCE_READ_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel);
         sel_mask &= ~BIT(rtcio_num);
         HAL_FORCE_MODIFY_U32_REG_FIELD(LP_AON.gpio_mux, gpio_mux_sel, sel_mask);
+        if((sel_mask & SOC_RTCIO_VALID_RTCIO_MASK) == 0) {
+            _rtcio_ll_enable_io_clock(false);
+        }
     }
 }
 

components/hal/esp32h2/include/hal/timer_ll.h

@@ -57,7 +57,7 @@ extern "C" {
  * @param group_id Group ID
  * @param enable true to enable, false to disable
  */
-static inline void timer_ll_enable_bus_clock(int group_id, bool enable)
+static inline void _timer_ll_enable_bus_clock(int group_id, bool enable)
 {
     if (group_id == 0) {
         PCR.timergroup0_conf.tg0_clk_en = enable;
@@ -68,7 +68,7 @@ static inline void timer_ll_enable_bus_clock(int group_id, bool enable)
 
 /// use a macro to wrap the function, force the caller to use it in a critical section
 /// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
-#define timer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; timer_ll_enable_bus_clock(__VA_ARGS__)
+#define timer_ll_enable_bus_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _timer_ll_enable_bus_clock(__VA_ARGS__)
 
 /**
  * @brief Reset the timer group module

components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h

@@ -29,6 +29,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
     hw->conf0.usb_pad_enable = 1;
 }
 
+/**
+ * @brief Disable the internal PHY for USB_Serial_JTAG
+ *
+ * @param hw Start address of the USB Serial_JTAG registers
+ */
+static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
+{
+    // Disable USB D+ pullup
+    hw->conf0.dp_pullup = 0;
+    // Disable USB pad function
+    hw->conf0.usb_pad_enable = 0;
+}
+
 #ifdef __cplusplus
 }
 #endif