Merge branch 'feature/support_bss_on_psram' into 'master'

psram: support .bss on psram on esp32s3

Closes IDF-4814, IDF-4396, IDFGH-7148, and IDFGH-7153

See merge request espressif/esp-idf!17557

components/esp_system/ld/esp32/sections.ld.in

@@ -223,7 +223,7 @@ SECTIONS
     _noinit_end = ABSOLUTE(.);
   } > dram0_0_seg
 
-   /* external memory bss, from any global variable with EXT_RAM_ATTR attribute*/
+   /* external memory bss, from any global variable with EXT_RAM_BSS_ATTR attribute*/
   .ext_ram.bss (NOLOAD) :
   {
     _ext_ram_bss_start = ABSOLUTE(.);

components/esp_system/ld/esp32s2/sections.ld.in

@@ -233,7 +233,7 @@ SECTIONS
     _noinit_end = ABSOLUTE(.);
   } > dram0_0_seg
 
-   /* external memory bss, from any global variable with EXT_RAM_ATTR attribute*/
+   /* external memory bss, from any global variable with EXT_RAM_BSS_ATTR attribute*/
   .ext_ram.bss (NOLOAD) :
   {
     _ext_ram_bss_start = ABSOLUTE(.);
@@ -249,7 +249,6 @@ SECTIONS
   {
     . = ALIGN (8);
     _bss_start = ABSOLUTE(.);
-    *(.ext_ram.bss*)
 
     mapping[dram0_bss]
 

components/esp_system/ld/esp32s3/memory.ld.in

@@ -90,7 +90,7 @@ MEMORY
 
 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
   /* Flash mapped constant data */
-  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x800000-0x20
+  drom0_0_seg (R) :                  org = 0x3C000020, len = 0x2000000-0x20
 
   /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
 #endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
@@ -115,6 +115,11 @@ MEMORY
 #else
   rtc_slow_seg(RW)  :                org = 0x50000000 , len = 0x2000
 #endif // CONFIG_ULP_COPROC_ENABLED
+  /**
+   * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region.
+   * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
+   */
+  extern_ram_seg(RWX) :              org = 0x3c000020 , len = 0x2000000-0x20
 }
 
 #if CONFIG_ESP32S3_USE_FIXED_STATIC_RAM_SIZE

components/esp_system/ld/esp32s3/sections.ld.in

@@ -231,7 +231,6 @@ SECTIONS
   {
     . = ALIGN (8);
     _bss_start = ABSOLUTE(.);
-    *(.ext_ram.bss*)
 
     mapping[dram0_bss]
 
@@ -292,7 +291,7 @@ SECTIONS
    */
   .flash_rodata_dummy (NOLOAD):
   {
-    _flash_rodata_dummy_start = .;
+    _flash_rodata_dummy_start = ABSOLUTE(.);
     /* Start at the same alignment constraint than .flash.text */
     . = ALIGN(ALIGNOF(.flash.text));
     /* Create an empty gap as big as .flash.text section */
@@ -381,6 +380,25 @@ SECTIONS
     mapping[rodata_noload]
   } > default_rodata_seg
 
+  /**
+   * This section is required to skip flash rodata sections, because `extern_ram_seg`
+   * and `drom0_0_seg` are on the same bus
+   */
+  .ext_ram.dummy (NOLOAD):
+  {
+    . = ORIGIN(extern_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
+    . = ALIGN (0x10000);
+  } > extern_ram_seg
+
+  /* This section holds .ext_ram.bss data, and will be put in PSRAM */
+  .ext_ram.bss (NOLOAD) :
+  {
+    _ext_ram_bss_start = ABSOLUTE(.);
+    mapping[extern_ram]
+    . = ALIGN(4);
+    _ext_ram_bss_end = ABSOLUTE(.);
+  } > extern_ram_seg
+
   /* Marks the end of IRAM code segment */
   .iram0.text_end (NOLOAD) :
   {

components/esp_system/port/cpu_start.c

@@ -389,12 +389,10 @@ void IRAM_ATTR call_start_cpu0(void)
     bootloader_init_mem();
 #if CONFIG_SPIRAM_BOOT_INIT
     if (esp_spiram_init() != ESP_OK) {
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
 #if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
         ESP_EARLY_LOGE(TAG, "Failed to init external RAM, needed for external .bss segment");
         abort();
 #endif
-#endif
 
 #if CONFIG_SPIRAM_IGNORE_NOTFOUND
         ESP_EARLY_LOGI(TAG, "Failed to init external RAM; continuing without it.");
@@ -405,11 +403,11 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif
     }
     //TODO: IDF-4382
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32
     if (g_spiram_ok) {
         esp_spiram_init_cache();
     }
-#endif  //#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3, //TODO: IDF-4382
+#endif  //#if CONFIG_IDF_TARGET_ESP32, //TODO: IDF-4382
 #endif
 
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
@@ -439,7 +437,7 @@ void IRAM_ATTR call_start_cpu0(void)
 
 #if CONFIG_SPIRAM_MEMTEST
     //TODO: IDF-4382
-#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
+#if CONFIG_IDF_TARGET_ESP32
     if (g_spiram_ok) {
         bool ext_ram_ok = esp_spiram_test();
         if (!ext_ram_ok) {
@@ -447,7 +445,7 @@ void IRAM_ATTR call_start_cpu0(void)
             abort();
         }
     }
-#endif  //CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3, //TODO: IDF-4382
+#endif  //CONFIG_IDF_TARGET_ESP32, //TODO: IDF-4382
 #endif  //CONFIG_SPIRAM_MEMTEST
 
     //TODO: IDF-4382