G0: RISC-V targets have now an independent G0 layer

G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-04-27 11:37:08 +08:00
parent 4e4d0a5011
commit 5bcd9b2db8
24 changed files with 366 additions and 269 deletions
@@ -15,6 +15,8 @@
 #pragma once

 #include <esp_err.h>
+#include "sdkconfig.h"
+
 #if !CONFIG_IDF_TARGET_ESP32C3 && !CONFIG_IDF_TARGET_ESP32H2 && !CONFIG_IDF_TARGET_ESP32C2
 #include "soc/soc_caps.h"
 #include "hal/rtc_io_ll.h"