ci(i2s): fixed occationally failure on P4
read write case can sometimes failed due to the low frequency of the default I2S clock source on P4.
This commit is contained in:
committed by
Kevin (Lao Kaiyao)
parent
4483e2628d
commit
5dc3eda4ad
@@ -742,7 +742,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]")
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TEST_ESP_OK(i2s_del_channel(rx_handle));
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}
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#if SOC_I2S_NUM > 1
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#if SOC_I2S_NUM > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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TEST_CASE("I2S_master_write_slave_read_test", "[i2s]")
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{
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i2s_chan_handle_t tx_handle;
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@@ -908,8 +908,8 @@ TEST_CASE("I2S_default_PLL_clock_test", "[i2s]")
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TEST_ESP_OK(i2s_new_channel(&chan_cfg, NULL, &rx_handle));
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TEST_ESP_OK(i2s_channel_init_std_mode(rx_handle, &std_cfg));
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#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP_REV_MIN_FULL >= 300
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std_cfg.clk_cfg.clk_src = I2S_CLK_SRC_PLL_160M;
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#ifdef I2S_LL_DEFAULT_CLK_SRC
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std_cfg.clk_cfg.clk_src = I2S_LL_DEFAULT_CLK_SRC;
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#endif
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i2s_test_common_sample_rate(rx_handle, &std_cfg.clk_cfg);
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#if SOC_I2S_SUPPORTS_XTAL
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