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refactor(mspi): refactor mspi clock src settings

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This commit is contained in:
Armando
2024-12-03 12:13:00 +08:00
parent 56696866ba
commit 6528ab5971
25 changed files with 196 additions and 161 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
+1 -1
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@@ -53,7 +53,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+1 -1
View File
@@ -51,7 +51,7 @@ void IRAM_ATTR bootloader_init_mspi_clock(void)
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
mspi_ll_fast_set_hs_divider(6);
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
+3 -3
View File
@@ -19,7 +19,7 @@
#include "bootloader_init.h"
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/spimem_flash_ll.h"
#include "hal/mspi_timing_tuning_ll.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "esp_private/bootloader_flash_internal.h"
@@ -44,8 +44,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
_spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
_spimem_ctrlr_ll_set_core_clock(0, 6);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_SPLL);
_mspi_timing_ll_set_flash_core_clock(0, 80);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)