system/sleep: further fix spi flash/ram current leakage

components/esp_rom/CMakeLists.txt

@@ -11,6 +11,7 @@ if(target STREQUAL "linux")
                         "${target}/esp_rom_crc.c"
                         "${target}/esp_rom_md5.c"
                         "${target}/esp_rom_efuse.c")
+    list(APPEND include_dirs "${IDF_PATH}/tools/mocks/soc/include")
 else()
     list(APPEND include_dirs "${target}")
     list(APPEND sources "patches/esp_rom_crc.c"
@@ -18,7 +19,8 @@ else()
                         "patches/esp_rom_uart.c"
                         "patches/esp_rom_spiflash.c"
                         "patches/esp_rom_tjpgd.c"
-                        "patches/esp_rom_regi2c.c")
+                        "patches/esp_rom_regi2c.c"
+                        "patches/esp_rom_efuse.c")
     list(APPEND private_required_comp soc hal)
 endif()
 

components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld

@@ -16,6 +16,7 @@ PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
 PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
 PROVIDE ( esp_rom_efuse_get_flash_gpio_info    = ets_efuse_get_spiconfig );
 PROVIDE ( esp_rom_efuse_get_flash_wp_gpio      = ets_efuse_get_wp_pad );
+PROVIDE ( esp_rom_efuse_get_opiconfig          = ets_efuse_get_opiconfig );
 PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
 
 PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );

components/esp_rom/include/esp_rom_efuse.h

@@ -1,16 +1,8 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -20,6 +12,7 @@ extern "C" {
 
 #include <stdint.h>
 #include <stdbool.h>
+#include "soc/soc_caps.h"
 
 #define ESP_ROM_EFUSE_FLASH_DEFAULT_SPI  (0)
 #define ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI (1)
@@ -56,6 +49,18 @@ uint32_t esp_rom_efuse_get_flash_gpio_info(void);
  */
 uint32_t esp_rom_efuse_get_flash_wp_gpio(void);
 
+#if SOC_SPI_MEM_SUPPORT_OPI_MODE
+/**
+ * @brief Read opi flash pads configuration from Efuse
+ *
+ * @return
+ * - 0 for default SPI pins.
+ * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
+ *   DQS, D4, D5, D6, D7 accordingly.
+ */
+uint32_t esp_rom_efuse_get_opiconfig(void);
+#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
+
 /**
  * @brief Read eFuse to check whether secure boot has been enabled or not
  *

components/esp_rom/linux/esp_rom_efuse.c

@@ -1,16 +1,8 @@
-// Copyright 2021 Espressif Systems (Shanghai) CO LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include "esp_rom_efuse.h"
 
@@ -49,6 +41,13 @@ uint32_t esp_rom_efuse_get_flash_wp_gpio(void)
     return 0;
 }
 
+#if SOC_SPI_MEM_SUPPORT_OPI_MODE
+uint32_t esp_rom_efuse_get_opiconfig(void)
+{
+    return 0;
+}
+#endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
+
 bool esp_rom_efuse_is_secure_boot_enabled(void)
 {
     return false;

components/esp_rom/patches/esp_rom_efuse.c

@@ -0,0 +1,31 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc.h"
+#include "soc/efuse_reg.h"
+
+#if CONFIG_IDF_TARGET_ESP32S3
+/**
+ * Since rom of esp32s3 does not export function ets_efuse_get_opiconfig,
+ * patch this function here.
+ */
+uint32_t esp_rom_efuse_get_opiconfig(void)
+{
+    uint64_t spiconfig1 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_2_REG, EFUSE_SPI_PAD_CONF_1);
+    uint64_t spiconfig2 = REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_SPI_PAD_CONF_2);
+    uint64_t opiconfig = (spiconfig2 << 12) | (spiconfig1 >> 20);
+    if (opiconfig == 0 || opiconfig == 0x3fffffffllu) {
+        return 0;
+    }
+    // （MSB）EFUSE_SPI_PAD_CONF_2(18bit) + EFUSE_SPI_PAD_CONF_1(32bit) + EFUSE_SPI_PAD_CONF_0(16bit) (LSB)
+    // [36:41] -- DQS
+    // [42:47] -- D4
+    // [48:53] -- D5
+    // [54:59] -- D6
+    // [60:65] -- D7
+    return opiconfig & 0x3fffffff;
+}
+#endif