pioduino/esp-idf
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

feat(gptimer): use RCC atomic block to enable/reset peripheral

Browse Source
This commit is contained in:
morris
2023-08-18 13:26:46 +08:00
parent a9c813ca3e
commit 71cf16ec01
27 changed files with 488 additions and 113 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_system/fpga_overrides.c
-8
View File
@@ -77,14 +77,6 @@ void esp_clk_init(void)
void esp_perip_clk_init(void)
{
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
/**
components/esp_system/int_wdt.c
+11 -1
View File
@@ -11,6 +11,7 @@
#include "soc/soc_caps.h"
#include "hal/wdt_hal.h"
#include "hal/mwdt_ll.h"
#include "hal/timer_ll.h"
#include "freertos/FreeRTOS.h"
#include "esp_cpu.h"
#include "esp_err.h"
@@ -30,6 +31,8 @@
#define IWDT_TICKS_PER_US 500
#define IWDT_INSTANCE WDT_MWDT1
#define IWDT_INITIAL_TIMEOUT_S 5
#define IWDT_PERIPH PERIPH_TIMG1_MODULE
#define IWDT_TIMER_GROUP 1
#else
@@ -38,6 +41,8 @@
#define IWDT_TICKS_PER_US 500
#define IWDT_INSTANCE WDT_MWDT0
#define IWDT_INITIAL_TIMEOUT_S 5
#define IWDT_PERIPH PERIPH_TIMG0_MODULE
#define IWDT_TIMER_GROUP 0
#endif // SOC_TIMER_GROUPS > 1
@@ -99,7 +104,12 @@ static void IRAM_ATTR tick_hook(void)
void esp_int_wdt_init(void)
{
periph_module_enable(PERIPH_TIMG1_MODULE);
PERIPH_RCC_ACQUIRE_ATOMIC(IWDT_PERIPH, ref_count) {
if (ref_count == 0) {
timer_ll_enable_bus_clock(IWDT_TIMER_GROUP, true);
timer_ll_reset_register(IWDT_TIMER_GROUP);
}
}
/*
* Initialize the WDT timeout stages. Note that the initial timeout is set to 5 seconds as variable startup times of
* each CPU can lead to a timeout. The tick hooks will set the WDT timers to the actual timeout.
components/esp_system/port/soc/esp32/clk.c
+1 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -300,15 +300,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
void rtc_clk_select_rtc_slow_clk(void)
components/esp_system/port/soc/esp32c2/clk.c
+1 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -251,13 +251,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/port/soc/esp32c3/clk.c
+1 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -294,13 +294,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/port/soc/esp32c6/clk.c
-9
View File
@@ -294,13 +294,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
#endif
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/port/soc/esp32h2/clk.c
-9
View File
@@ -286,13 +286,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
#endif
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/port/soc/esp32s2/clk.c
+1 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -312,13 +312,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/port/soc/esp32s3/clk.c
+1 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -314,13 +314,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
/* Enable RNG clock. */
periph_module_enable(PERIPH_RNG_MODULE);
/* Enable TimerGroup 0 clock to ensure its reference counter will never
* be decremented to 0 during normal operation and preventing it from
* being disabled.
* If the TimerGroup 0 clock is disabled and then reenabled, the watchdog
* registers (Flashboot protection included) will be reenabled, and some
* seconds later, will trigger an unintended reset.
*/
periph_module_enable(PERIPH_TIMG0_MODULE);
}
components/esp_system/task_wdt/task_wdt_impl_timergroup.c
+14 -2
View File
@@ -10,6 +10,7 @@
#include "sdkconfig.h"
#include "hal/wdt_hal.h"
#include "hal/mwdt_ll.h"
#include "hal/timer_ll.h"
#include "esp_err.h"
#include "esp_attr.h"
#include "esp_intr_alloc.h"
@@ -21,6 +22,7 @@
#define TWDT_TICKS_PER_US 500
#define TWDT_PRESCALER MWDT_LL_DEFAULT_CLK_PRESCALER // Tick period of 500us if WDT source clock is 80MHz
#define TWDT_PERIPH_MODULE PERIPH_TIMG0_MODULE
#define TWDT_TIMER_GROUP 0
#define TWDT_INTR_SOURCE ETS_TG0_WDT_LEVEL_INTR_SOURCE
/**
@@ -55,7 +57,13 @@ esp_err_t esp_task_wdt_impl_timer_allocate(const esp_task_wdt_config_t *config,
}
if (ret == ESP_OK) {
periph_module_enable(TWDT_PERIPH_MODULE);
// enable bus clock for the timer group registers
PERIPH_RCC_ACQUIRE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) {
if (ref_count == 0) {
timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, true);
timer_ll_reset_register(TWDT_TIMER_GROUP);
}
}
wdt_hal_init(&ctx->hal, TWDT_INSTANCE, TWDT_PRESCALER, true);
wdt_hal_write_protect_disable(&ctx->hal);
@@ -106,7 +114,11 @@ void esp_task_wdt_impl_timer_free(twdt_ctx_t obj)
ESP_ERROR_CHECK(esp_intr_disable(ctx->intr_handle));
/* Disable the Timer Group module */
periph_module_disable(TWDT_PERIPH_MODULE);
PERIPH_RCC_RELEASE_ATOMIC(TWDT_PERIPH_MODULE, ref_count) {
if (ref_count == 0) {
timer_ll_enable_bus_clock(TWDT_TIMER_GROUP, false);
}
}
/* Deregister interrupt */
ESP_ERROR_CHECK(esp_intr_free(ctx->intr_handle));