Merge branch 'feat/c6lite_c61_soc_part3_build' into 'master'

feat(esp32c61): add & modify soc header files to pass build (stage 2/8 part 3/3) See merge request espressif/esp-idf!29482
2024-03-13 14:03:43 +08:00
parent aa6e49e60f 616c72b96c
commit 794eec3483
51 changed files with 10383 additions and 10045 deletions
@@ -4,3 +4,7 @@ components/bootloader_support/test_apps/rtc_custom_section:
  enable:
    - if: SOC_RTC_MEM_SUPPORTED == 1
      reason: this feature is supported on chips that have RTC memory
+  disable:
+    - if: IDF_TARGET == "esp32c61"
+      temporary: true
+      reason: IDF-9260