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Merge branch 'docs/update_out-of-sync_files_in_api-reference' into 'master'

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docs: Update CN translation for out-of-sync api-reference files

Closes DOC-4268

See merge request espressif/esp-idf!21566
This commit is contained in:
Shang Zhou
2022-12-19 10:48:47 +08:00
parent a3dd334081 172aca432a
commit 798a6d6d9b
6 changed files with 205 additions and 134 deletions
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docs/en/api-reference/peripherals/gpio.rst
+4 -6
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@@ -21,7 +21,6 @@ GPIO Summary
:SOC_ULP_SUPPORTED: - The :doc:`Ultra Low Power co-processor <../../api-reference/system/ulp>` is running
- Analog functions such as ADC/DAC/etc are in use.
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
GPIO Glitch Filter
@@ -31,7 +30,7 @@ GPIO Summary
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
Each GPIO can be configured with a glitch filter, which can be used to filter out pulses shorter than **two** sample clock cycles. The duration of the filter is not configurable. The sample clock is the clock source of the IO-MUX. In the driver, we call this kind of filter as "pin glitch filter". You can create the filter handle by calling :cpp:func:`gpio_new_pin_glitch_filter`. All the configurations for a pin glitch filter are listed in the :cpp:type:`gpio_pin_glitch_filter_config_t` structure.
Each GPIO can be configured with a glitch filter, which can be used to filter out pulses shorter than **two** sample clock cycles. The duration of the filter is not configurable. The sample clock is the clock source of the IO_MUX. In the driver, we call this kind of filter as ``pin glitch filter``. You can create the filter handle by calling :cpp:func:`gpio_new_pin_glitch_filter`. All the configurations for a pin glitch filter are listed in the :cpp:type:`gpio_pin_glitch_filter_config_t` structure.
- :cpp:member:`gpio_pin_glitch_filter_config_t::gpio_num` sets the GPIO number to enable the glitch filter.
@@ -39,14 +38,14 @@ GPIO Summary
{IDF_TARGET_FLEX_GLITCH_FILTER_NUM:default="8"}
{IDF_TARGET_NAME} provides {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} flexible glitch filters, whose duration is configurable. We refer to this kind of filter as "flex flitch filter". Each of them can be applied to any input GPIO. However, applying multiple filters to the same GPIO doesn't make difference from one. You can create the filter handle by calling :cpp:func:`gpio_new_flex_glitch_filter`. All the configurations for a flexible glitch filter are listed in the :cpp:type:`gpio_flex_glitch_filter_config_t` structure.
{IDF_TARGET_NAME} provides {IDF_TARGET_FLEX_GLITCH_FILTER_NUM} flexible glitch filters, whose duration is configurable. We refer to this kind of filter as ``flex flitch filter``. Each of them can be applied to any input GPIO. However, applying multiple filters to the same GPIO doesn't make difference from one. You can create the filter handle by calling :cpp:func:`gpio_new_flex_glitch_filter`. All the configurations for a flexible glitch filter are listed in the :cpp:type:`gpio_flex_glitch_filter_config_t` structure.
- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` sets the GPIO that will be applied the flex glitch filter.
- :cpp:member:`gpio_flex_glitch_filter_config_t::gpio_num` sets the GPIO that will be applied to the flex glitch filter.
- :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns` and :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` are the key parameters of the glitch filter. During :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`, any pulse whose width is shorter than :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` will be discarded. Please note that, you can't set :cpp:member:`gpio_flex_glitch_filter_config_t::window_thres_ns` bigger than :cpp:member:`gpio_flex_glitch_filter_config_t::window_width_ns`.
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER and SOC_GPIO_FLEX_GLITCH_FILTER_NUM
Please note, the "pin glitch filter" and "flex glitch filter" are independent. You can enable both of them for the same GPIO.
Please note, the ``pin glitch filter`` and ``flex glitch filter`` are independent. You can enable both of them for the same GPIO.
The glitch filter is disabled by default, and can be enabled by calling :cpp:func:`gpio_glitch_filter_enable`. To recycle the filter, you can call :cpp:func:`gpio_del_glitch_filter`. Please note, before deleting the filter, you should disable it first by calling :cpp:func:`gpio_glitch_filter_disable`.
@@ -71,7 +70,6 @@ API Reference - Normal GPIO
.. include-build-file:: inc/rtc_io.inc
.. include-build-file:: inc/rtc_io_types.inc
.. only:: SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER or SOC_GPIO_FLEX_GLITCH_FILTER_NUM
API Reference - GPIO Glitch Filter
docs/en/api-reference/peripherals/gptimer.rst
+1
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@@ -43,6 +43,7 @@ A GPTimer instance is represented by :cpp:type:`gptimer_handle_t`. The driver be
To install a timer instance, there is a configuration structure that needs to be given in advance: :cpp:type:`gptimer_config_t`:
- :cpp:member:`gptimer_config_t::clk_src` selects the source clock for the timer. The available clocks are listed in :cpp:type:`gptimer_clock_source_t`, you can only pick one of them. For the effect on power consumption of different clock source, please refer to Section :ref:`gptimer-power-management`.
- :cpp:member:`gptimer_config_t::direction` sets the counting direction of the timer, supported directions are listed in :cpp:type:`gptimer_count_direction_t`, you can only pick one of them.
- :cpp:member:`gptimer_config_t::resolution_hz` sets the resolution of the internal counter. Each count step is equivalent to **1 / resolution_hz** seconds.
docs/en/api-reference/peripherals/spi_slave.rst
+82 -71
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@@ -7,13 +7,13 @@ SPI Slave driver is a program that controls {IDF_TARGET_NAME}'s SPI peripherals
Overview of {IDF_TARGET_NAME}'s SPI peripherals
-----------------------------------------------
On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has independent signal bus with the same name.
On {IDF_TARGET_NAME}, {SOC_SPI_PERIPH_NUM} SPI controllers are available for general purpose usage. A certain SPI controller has an independent signal bus with the same name.
.. only:: esp32
.. note::
On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
On ESP32, HSPI refers to SPI2, VSPI refers to SPI3.
Terminology
-----------
@@ -120,91 +120,102 @@ GPIO Matrix and IO_MUX
The IO_MUX pins for SPI buses are given below.
+----------+------+------+
| Pin Name | SPI2 | SPI3 |
+ +------+------+
| | GPIO Number |
+==========+======+======+
| CS0* | 15 | 5 |
+----------+------+------+
| SCLK | 14 | 18 |
+----------+------+------+
| MISO | 12 | 19 |
+----------+------+------+
| MOSI | 13 | 23 |
+----------+------+------+
| QUADWP | 2 | 22 |
+----------+------+------+
| QUADHD | 4 | 21 |
+----------+------+------+
.. list-table::
:widths: 40 30 30
:header-rows: 1
* - Pin Name
- GPIO Number (SPI2)
- GPIO Number (SPI3)
* - CS0*
- 15
- 5
* - SCLK
- 14
- 18
* - MISO
- 12
- 19
* - MOSI
- 13
- 23
* - QUADWP
- 2
- 22
* - QUADHD
- 4
- 21
.. only:: not esp32
Most of chip's peripheral signals have direct connection to their dedicated IO_MUX pins. However, the signals can also be routed to any other available pins using the less direct GPIO matrix. If at least one signal is routed through the GPIO matrix, then all signals will be routed through it.
When an SPI Host is set to 80MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same comparing to routing them via IOMUX.
When an SPI Host is set to 80 MHz or lower frequencies, routing SPI pins via GPIO matrix will behave the same compared to routing them via IO_MUX.
The IO_MUX pins for SPI buses are given below.
.. only:: esp32s2 or esp32s3
+----------+------+------+
| Pin Name | SPI2 | SPI3 |
+ +------+------+
| | GPIO Number |
+==========+======+======+
| CS0* | 10 | N/A |
+----------+------+------+
| SCLK | 12 | N/A |
+----------+------+------+
| MISO | 13 | N/A |
+----------+------+------+
| MOSI | 11 | N/A |
+----------+------+------+
| QUADWP | 14 | N/A |
+----------+------+------+
| QUADHD | 9 | N/A |
+----------+------+------+
.. list-table::
:widths: 40 30
:header-rows: 1
* - Pin Name
- GPIO Number (SPI2)
* - CS0*
- 10
* - SCLK
- 12
* - MISO
- 13
* - MOSI
- 11
* - QUADWP
- 14
* - QUADHD
- 9
.. only:: esp32c2 or esp32c3
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
| | GPIO Number |
+==========+=============+
| CS0* | 10 |
+----------+-------------+
| SCLK | 6 |
+----------+-------------+
| MISO | 2 |
+----------+-------------+
| MOSI | 7 |
+----------+-------------+
| QUADWP | 5 |
+----------+-------------+
| QUADHD | 4 |
+----------+-------------+
.. list-table::
:widths: 40 30
:header-rows: 1
* - Pin Name
- GPIO Number (SPI2)
* - CS0*
- 10
* - SCLK
- 6
* - MISO
- 2
* - MOSI
- 7
* - QUADWP
- 5
* - QUADHD
- 4
.. only:: esp32c6
+----------+-------------+
| Pin Name | SPI2 |
+ +-------------+
| | GPIO Number |
+==========+=============+
| CS0* | 16 |
+----------+-------------+
| SCLK | 6 |
+----------+-------------+
| MISO | 2 |
+----------+-------------+
| MOSI | 7 |
+----------+-------------+
| QUADWP | 5 |
+----------+-------------+
| QUADHD | 4 |
+----------+-------------+
.. list-table::
:widths: 40 30
:header-rows: 1
* - Pin Name
- GPIO Number (SPI2)
* - CS0*
- 16
* - SCLK
- 6
* - MISO
- 2
* - MOSI
- 7
* - QUADWP
- 5
* - QUADHD
- 4
* Only the first Device attached to the bus can use the CS0 pin.