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feat(esp_system): Support IPC_ISR for ESP32P4

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This commit is contained in:
KonstantinKondrashov
2023-09-06 19:33:39 +08:00
parent addfc0d870
commit 7a878bdc50
37 changed files with 591 additions and 133 deletions
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components/esp_system/test_apps/esp_system_unity_tests/main/CMakeLists.txt
+6 -1
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@@ -16,7 +16,12 @@ set(SRC "test_app_main.c"
"test_task_wdt.c")
if(CONFIG_ESP_IPC_ISR_ENABLE)
list(APPEND SRC "test_ipc_isr.c" "test_ipc_isr.S")
list(APPEND SRC "test_ipc_isr.c")
if(CONFIG_IDF_TARGET_ARCH_XTENSA)
list(APPEND SRC "port/arch/xtensa/test_ipc_isr.S")
elseif(CONFIG_IDF_TARGET_ARCH_RISCV)
list(APPEND SRC "port/arch/riscv/test_ipc_isr.c")
endif()
endif()
idf_component_register(SRCS ${SRC}
components/esp_system/test_apps/esp_system_unity_tests/main/port/arch/riscv/test_ipc_isr.c
+29
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "sdkconfig.h"
#if CONFIG_ESP_IPC_ISR_ENABLE
void esp_test_ipc_isr_callback(void *arg) {
uint32_t value = 0xa5a5;
*(volatile uint32_t*)arg = value;
}
void esp_test_ipc_isr_get_other_core_id(void *arg) {
uint32_t core_id;
__asm volatile("csrr %0, mhartid" : "=r"(core_id));
*(volatile uint32_t*)arg = core_id;
}
void esp_test_ipc_isr_get_cycle_count_other_cpu(void *arg) {
uint32_t cycle_count;
__asm volatile("rdcycle %0;" : "=r"(cycle_count));
*(volatile uint32_t*)arg = cycle_count;
}
#endif // CONFIG_ESP_IPC_ISR_ENABLE
components/esp_system/test_apps/esp_system_unity_tests/main/test_ipc_isr.S → components/esp_system/test_apps/esp_system_unity_tests/main/port/arch/xtensa/test_ipc_isr.S
+5 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,18 +13,18 @@
#include <xtensa/config/system.h>
#include <xtensa/hal.h>
/* esp_test_ipc_isr_asm(void *arg)
/* esp_test_ipc_isr_callback(void *arg)
*
* It should be called by the CALLX0 command from the handler of High-priority interrupt.
* Only these registers [a2, a3, a4] can be used here.
*/
.section .iram1, "ax"
.align 4
.global esp_test_ipc_isr_asm
.type esp_test_ipc_isr_asm, @function
.global esp_test_ipc_isr_callback
.type esp_test_ipc_isr_callback, @function
// Args:
// a2 - void* arg
esp_test_ipc_isr_asm:
esp_test_ipc_isr_callback:
movi a3, 0xa5a5
s32i a3, a2, 0
ret
components/esp_system/test_apps/esp_system_unity_tests/main/test_ipc_isr.c
+17 -11
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,12 +17,18 @@
#ifdef CONFIG_ESP_IPC_ISR_ENABLE
void esp_test_ipc_isr_asm(void* arg);
#if CONFIG_IDF_TARGET_ARCH_RISCV
#define STORE_ERROR "Store access fault"
#else
#define STORE_ERROR "StoreProhibited"
#endif
void esp_test_ipc_isr_callback(void* arg);
TEST_CASE("Test ipc_isr blocking IPC function calls a ASM function", "[ipc]")
{
int val = 0x5a5a;
esp_ipc_isr_asm_call_blocking(esp_test_ipc_isr_asm, &val);
esp_ipc_isr_call_blocking(esp_test_ipc_isr_callback, &val);
TEST_ASSERT_EQUAL_HEX(val, 0xa5a5);
}
@@ -32,13 +38,13 @@ void esp_test_ipc_isr_get_other_core_id(void* arg);
TEST_CASE("Test ipc_isr blocking IPC function calls get_other_core_id", "[ipc]")
{
int val = 0x5a5a;
esp_ipc_isr_asm_call_blocking(esp_test_ipc_isr_get_other_core_id, &val);
esp_ipc_isr_call_blocking(esp_test_ipc_isr_get_other_core_id, &val);
TEST_ASSERT_EQUAL_HEX(val, 1);
}
static void do_esp_ipc_isr_asm_call_blocking(void)
static void do_esp_ipc_isr_call_blocking(void)
{
esp_ipc_isr_asm_call_blocking(esp_test_ipc_isr_asm, NULL);
esp_ipc_isr_call_blocking(esp_test_ipc_isr_callback, NULL);
}
static void check_reset_reason_panic(void)
@@ -46,8 +52,8 @@ static void check_reset_reason_panic(void)
TEST_ASSERT_EQUAL(ESP_RST_PANIC, esp_reset_reason());
}
TEST_CASE_MULTIPLE_STAGES("Test ipc_isr exception in asm func leads to StoreProhibited not to Unhandled debug exception", "[ipc][reset=StoreProhibited,SW_CPU_RESET]",
do_esp_ipc_isr_asm_call_blocking,
TEST_CASE_MULTIPLE_STAGES("Test ipc_isr exception in asm func leads to StoreProhibited not to Unhandled debug exception", "[ipc][reset="STORE_ERROR",SW_CPU_RESET]",
do_esp_ipc_isr_call_blocking,
check_reset_reason_panic)
void esp_test_ipc_isr_get_cycle_count_other_cpu(void* arg);
@@ -55,7 +61,7 @@ void esp_test_ipc_isr_get_cycle_count_other_cpu(void* arg);
TEST_CASE("Test ipc_isr blocking IPC function calls get_cycle_count_other_cpu", "[ipc]")
{
int val = 0x5a5a;
esp_ipc_isr_asm_call_blocking(esp_test_ipc_isr_get_cycle_count_other_cpu, &val);
esp_ipc_isr_call_blocking(esp_test_ipc_isr_get_cycle_count_other_cpu, &val);
esp_rom_printf("CCOUNT CPU0 = %d\n", esp_cpu_get_cycle_count());
esp_rom_printf("CCOUNT CPU1 = %d\n", val);
}
@@ -70,12 +76,12 @@ static void task_asm(void *arg)
printf("task_asm\n");
while (s_stop == false) {
val = 0x5a5a;
esp_ipc_isr_asm_call_blocking(esp_test_ipc_isr_asm, &val);
esp_ipc_isr_call_blocking(esp_test_ipc_isr_callback, &val);
TEST_ASSERT_EQUAL_HEX(val, 0xa5a5);
++counter;
}
printf("task_asm counter = %d\n", counter);
TEST_ASSERT_GREATER_THAN(10000, counter);
TEST_ASSERT_GREATER_THAN(1000, counter);
xSemaphoreGive(*sema);
vTaskDelete(NULL);
}