From 7eca03a2acd4119e45fcb780170949877035cc0a Mon Sep 17 00:00:00 2001 From: armando Date: Thu, 15 Jan 2026 11:04:33 +0800 Subject: [PATCH] feat(p4): added rev3_1 macro --- components/esp_hw_support/port/esp32p4/Kconfig.hw_support | 4 ++++ components/esp_hw_support/port/esp32p4/rtc_clk_init.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support index 7699334a4a..779fb19e95 100644 --- a/components/esp_hw_support/port/esp32p4/Kconfig.hw_support +++ b/components/esp_hw_support/port/esp32p4/Kconfig.hw_support @@ -34,6 +34,9 @@ choice ESP32P4_REV_MIN config ESP32P4_REV_MIN_300 bool "Rev v3.0" depends on !ESP32P4_SELECTS_REV_LESS_V3 + config ESP32P4_REV_MIN_301 + bool "Rev v3.1" + depends on !ESP32P4_SELECTS_REV_LESS_V3 endchoice config ESP32P4_REV_MIN_FULL @@ -42,6 +45,7 @@ config ESP32P4_REV_MIN_FULL default 1 if ESP32P4_REV_MIN_1 default 100 if ESP32P4_REV_MIN_100 default 300 if ESP32P4_REV_MIN_300 + default 301 if ESP32P4_REV_MIN_301 config ESP_REV_MIN_FULL int diff --git a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c index 00c3298f8e..a49598ff2f 100644 --- a/components/esp_hw_support/port/esp32p4/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32p4/rtc_clk_init.c @@ -68,20 +68,24 @@ void rtc_clk_init(rtc_clk_config_t cfg) hp_dcmvset = pvt_hp_dcmvset; } // Switch to DCDC +#if CONFIG_ESP32P4_REV_MIN_301 unsigned chip_version = efuse_hal_chip_revision(); if (ESP_CHIP_REV_ABOVE(chip_version, 301)) { SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD); } +#endif pmu_ll_set_dcdc_en(&PMU, true); pmu_ll_set_dcdc_switch_force_power_down(&PMU, false); pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset); SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu esp_rom_delay_us(1000); +#if CONFIG_ESP32P4_REV_MIN_301 if (ESP_CHIP_REV_ABOVE(chip_version, 301)) { REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD); esp_rom_delay_us(10); } +#endif pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, false); soc_xtal_freq_t xtal_freq = cfg.xtal_freq;