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Merge branch 'feat/pwr_glitch_bringup_c5_c61' into 'master'

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feat(pwr_glitch): Add power glitch reset support on esp32c5, esp32c61

See merge request espressif/esp-idf!33032
This commit is contained in:
Jiang Jiang Jian
2024-10-15 14:15:49 +08:00
parent 2c71890bf8 858d0647e8
commit 88317cff24
11 changed files with 123 additions and 51 deletions
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components/bootloader_support/src/esp32c5/bootloader_esp32c5.c
+5 -3
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@@ -92,11 +92,13 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
// TODO: [ESP32C5] IDF-8650
//Enable super WDT reset.
// bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset (mode1)
brownout_ll_ana_reset_enable(true);
if (efuse_hal_chip_revision() == 0) {
// decrease power glitch reset voltage to avoid start the glitch reset
uint8_t power_glitch_dref = 0;
bootloader_power_glitch_reset_config(true, power_glitch_dref);
}
}
esp_err_t bootloader_init(void)
components/bootloader_support/src/esp32c5/bootloader_soc.c
+20 -9
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@@ -7,18 +7,29 @@
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
// TODO: [ESP32C5] IDF-8667 remove esp_log.h
#include "esp_log.h"
void bootloader_ana_super_wdt_reset_config(bool enable)
{
// TODO: [ESP32C5] IDF-8667
ESP_EARLY_LOGW("bootloader", "bootloader_ana_super_wdt_reset_config() has not been implemented on C5 yet");
}
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
// TODO: [ESP32C5] IDF-8667, PM-207
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_XTAL, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_CK_GLITCH_CNTL_REG, LP_ANA_PWR_GLITCH_RESET_ENA, 0);
}
}
components/bootloader_support/src/esp32c61/bootloader_esp32c61.c
+3 -3
View File
@@ -93,17 +93,17 @@ static inline void bootloader_hardware_init(void)
static inline void bootloader_ana_reset_config(void)
{
//Enable super WDT reset.
bootloader_ana_super_wdt_reset_config(true);
//Enable BOD reset (mode1)
brownout_ll_ana_reset_enable(true);
uint8_t power_glitch_dref = 0;
bootloader_power_glitch_reset_config(true, power_glitch_dref);
}
esp_err_t bootloader_init(void)
{
esp_err_t ret = ESP_OK;
bootloader_hardware_init();
// bootloader_ana_reset_config(); //TODO: [ESP32C61] IDF-9260
bootloader_ana_reset_config();
bootloader_super_wdt_auto_feed();
// In RAM_APP, memory will be initialized in `call_start_cpu0`
components/bootloader_support/src/esp32c61/bootloader_soc.c
+20 -10
View File
@@ -7,19 +7,29 @@
#include <assert.h>
#include "soc/soc.h"
#include "soc/lp_analog_peri_reg.h"
//TODO: [ESP32C61] IDF-9260, commented in verify code, check
void bootloader_ana_super_wdt_reset_config(bool enable)
{
//C61 doesn't support bypass super WDT reset
assert(enable);
// lp_analog_peri_reg.h updated, now following registers
// REG_CLR_BIT(LP_ANALOG_PERI_LP_ANA_FIB_ENABLE_REG, LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST);
}
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_saradc.h"
//Not supported but common bootloader calls the function. Do nothing
void bootloader_ana_clock_glitch_reset_config(bool enable)
{
(void)enable;
}
void bootloader_power_glitch_reset_config(bool enable, uint8_t dref)
{
assert(dref < 8);
REG_SET_FIELD(LP_ANA_FIB_ENABLE_REG, LP_ANA_ANA_FIB_PWR_GLITCH_ENA, 0);
if (enable) {
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PERIF, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_VDDPST, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLLBB, dref);
REGI2C_WRITE_MASK(I2C_SAR_ADC, POWER_GLITCH_DREF_VDET_PLL, dref);
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0xf);
} else {
REG_SET_FIELD(LP_ANA_POWER_GLITCH_CNTL_REG, LP_ANA_POWER_GLITCH_RESET_ENA, 0);
}
}