ulp-riscv: add more wakeup test cases
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@@ -42,13 +42,28 @@ void handle_commands(riscv_test_commands_t cmd)
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ulp_riscv_wakeup_main_processor();
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break;
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case RISCV_DEEP_SLEEP_WAKEUP_TEST:
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case RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST:
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/* Echo the command ID back to the main CPU */
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command_resp = RISCV_DEEP_SLEEP_WAKEUP_TEST;
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command_resp = RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST;
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/* Set the command reply status */
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main_cpu_reply = RISCV_COMMAND_OK;
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ulp_riscv_delay_cycles(1000 * ULP_RISCV_CYCLES_PER_MS);
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/* Wakeup the main CPU */
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ulp_riscv_wakeup_main_processor();
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break;
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case RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST:
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/* Echo the command ID back to the main CPU */
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command_resp = RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST;
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/* Set the command reply status */
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main_cpu_reply = RISCV_COMMAND_OK;
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ulp_riscv_delay_cycles(10000 * ULP_RISCV_CYCLES_PER_MS);
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/* Wakeup the main CPU */
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ulp_riscv_wakeup_main_processor();
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break;
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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@@ -10,7 +10,8 @@
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typedef enum{
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RISCV_READ_WRITE_TEST = 1,
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RISCV_DEEP_SLEEP_WAKEUP_TEST,
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RISCV_DEEP_SLEEP_WAKEUP_SHORT_DELAY_TEST,
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RISCV_DEEP_SLEEP_WAKEUP_LONG_DELAY_TEST,
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RISCV_LIGHT_SLEEP_WAKEUP_TEST,
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RISCV_STOP_TEST,
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RISCV_MUTEX_TEST,
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