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fix(esp32p4): Fixed interrupt handling to use the CLIC controller

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This commit is contained in:
Omar Chebib
2023-08-14 15:44:24 +08:00
parent eb8883cc20
commit 8ca191e4c1
27 changed files with 822 additions and 510 deletions
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components/freertos/FreeRTOS-Kernel/portable/riscv/port.c
+8 -1
View File
@@ -92,6 +92,10 @@ volatile UBaseType_t xPortSwitchFlag[portNUM_PROCESSORS] = {0};
__attribute__((aligned(16))) StackType_t xIsrStack[portNUM_PROCESSORS][configISR_STACK_SIZE];
StackType_t *xIsrStackTop[portNUM_PROCESSORS] = {0};
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
StackType_t *xIsrStackBottom[portNUM_PROCESSORS] = {0};
#endif
/* ------------------------------------------------ FreeRTOS Portable --------------------------------------------------
* - Provides implementation for functions required by FreeRTOS
* - Declared in portable.h
@@ -107,9 +111,12 @@ BaseType_t xPortStartScheduler(void)
port_uxCriticalNesting[coreID] = 0;
port_xSchedulerRunning[coreID] = 0;
/* Initialize ISR Stack top */
/* Initialize ISR Stack(s) */
for (int i = 0; i < portNUM_PROCESSORS; i++) {
xIsrStackTop[i] = &xIsrStack[i][0] + (configISR_STACK_SIZE & (~((portPOINTER_SIZE_TYPE)portBYTE_ALIGNMENT_MASK)));
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
xIsrStackBottom[i] = &xIsrStack[i][0];
#endif
}
/* Setup the hardware to generate the tick. */
components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S
+98 -107
View File
@@ -19,7 +19,7 @@
.global vTaskSwitchContext
.global xPortSwitchFlag
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
.global xIsrStack
.global xIsrStackBottom
.global port_offset_pxStack
.global port_offset_pxEndOfStack
.global esp_hw_stack_guard_monitor_stop
@@ -34,75 +34,73 @@
* current task stack pointer and places it into the pxCurrentTCB.
* It then loads the ISR stack into sp.
* TODO: ISR nesting code improvements ?
* In the routines below, let's use a0-a5 registers to let the compiler generate
* 16-bit instructions.
*/
.global rtos_int_enter
.type rtos_int_enter, @function
rtos_int_enter:
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7861
/* preserve the return address */
mv t1, ra
mv t2, a0
#endif
/* If the scheduler is not enabled, jump directly to the ISR handler */
#if ( configNUM_CORES > 1 )
csrr t6, mhartid /* t6 = coreID */
slli t6, t6, 2 /* t6 = coreID * 4 */
la t0, port_xSchedulerRunning /* t0 = &port_xSchedulerRunning */
add t0, t0, t6 /* t0 = &port_xSchedulerRunning[coreID] */
lw t0, (t0) /* t0 = port_xSchedulerRunning[coreID] */
csrr a5, mhartid /* a5 = coreID */
slli a5, a5, 2 /* a5 = coreID * 4 */
la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
add a0, a0, a5 /* a0 = &port_xSchedulerRunning[coreID] */
lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
#else
lw t0, port_xSchedulerRunning /* t0 = port_xSchedulerRunning */
#endif /* (configNUM_CORES > 1) */
beq t0, zero, rtos_int_enter_end /* if (port_xSchedulerRunning[coreID] == 0) jump to rtos_int_enter_end */
lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
#endif /* ( configNUM_CORES > 1 ) */
beqz a0, rtos_int_enter_end /* if (port_xSchedulerRunning[coreID] == 0) jump to rtos_int_enter_end */
/* Increment the ISR nesting count */
la t3, port_uxInterruptNesting /* t3 = &port_usInterruptNesting */
la a0, port_uxInterruptNesting /* a0 = &port_uxInterruptNesting */
#if ( configNUM_CORES > 1 )
add t3, t3, t6 /* t3 = &port_uxInterruptNesting[coreID] // t6 already contains coreID * 4 */
add a0, a0, a5 /* a0 = &port_uxInterruptNesting[coreID] // a5 already contains coreID * 4 */
#endif /* ( configNUM_CORES > 1 ) */
lw t4, 0x0(t3) /* t4 = port_uxInterruptNesting[coreID] */
addi t5, t4, 1 /* t5 = t4 + 1 */
sw t5, 0x0(t3) /* port_uxInterruptNesting[coreID] = t5 */
lw a1, 0(a0) /* a1 = port_uxInterruptNesting[coreID] */
addi a2, a1, 1 /* a2 = a1 + 1 */
sw a2, 0(a0) /* port_uxInterruptNesting[coreID] = a2 */
/* If we reached here from another low-prio ISR, i.e, port_uxInterruptNesting[coreID] > 0, then skip stack pushing to TCB */
bne t4, zero, rtos_int_enter_end /* if (port_uxInterruptNesting[coreID] > 0) jump to rtos_int_enter_end */
/* If we reached here from another low-priority ISR, i.e, port_uxInterruptNesting[coreID] > 0, then skip stack pushing to TCB */
bnez a1, rtos_int_enter_end /* if (port_uxInterruptNesting[coreID] > 0) jump to rtos_int_enter_end */
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_monitor_stop(); */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
/* Save the current sp in pxCurrentTCB[coreID] and load the ISR stack on to sp */
#if ( configNUM_CORES > 1 )
la t0, pxCurrentTCB /* t0 = &pxCurrentTCB */
add t0, t0, t6 /* t0 = &pxCurrentTCB[coreID] // t6 already contains coreID * 4 */
lw t0, (t0) /* t0 = pxCurrentTCB[coreID] */
sw sp, 0x0(t0) /* pxCurrentTCB[coreID] = sp */
la t0, xIsrStackTop /* t0 = &xIsrStackTop */
add t0, t0, t6 /* t0 = &xIsrStackTop[coreID] // t6 already contains coreID * 4 */
lw sp, 0x0(t0) /* sp = xIsrStackTop[coreID] */
la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
add a0, a0, a5 /* a0 = &pxCurrentTCB[coreID] // a5 already contains coreID * 4 */
lw a0, (a0) /* a0 = pxCurrentTCB[coreID] */
sw sp, 0(a0) /* pxCurrentTCB[coreID] = sp */
la a0, xIsrStackTop /* a0 = &xIsrStackTop */
add a0, a0, a5 /* a0 = &xIsrStackTop[coreID] // a5 already contains coreID * 4 */
lw sp, (a0) /* sp = xIsrStackTop[coreID] */
#else
lw t0, pxCurrentTCB /* t0 = pxCurrentTCB */
sw sp, 0x0(t0) /* pxCurrentTCB = sp */
lw a0, pxCurrentTCB /* a0 = pxCurrentTCB */
sw sp, 0(a0) /* pxCurrentTCB[0] = sp */
lw sp, xIsrStackTop /* sp = xIsrStackTop */
#endif /* ( configNUM_CORES > 1 ) */
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_set_bounds(xIsrStack, xIsrStackTop); */
la a0, xIsrStack
/* Prepare the parameters for esp_hw_stack_guard_set_bounds(xIsrStackBottom, xIsrStackTop); */
#if ( configNUM_CORES > 1 )
/* Load the xIsrStack for the current core and set the new bounds */
la a0, xIsrStackBottom
add a0, a0, a5 /* a0 = &xIsrStackBottom[coreID] */
lw a0, (a0) /* a0 = xIsrStackBottom[coreID] */
#else
lw a0, xIsrStackBottom
#endif /* ( configNUM_CORES > 1 ) */
mv a1, sp
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
ESP_HW_STACK_GUARD_MONITOR_START_CPU0
/* esp_hw_stack_guard_set_bounds(xIsrStackBottom[coreID], xIsrStackTop[coreID]);
*/
ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
rtos_int_enter_end:
#if CONFIG_IDF_TARGET_ESP32P4
//TODO: IDF-7861
mv ra, t1
#endif
ret
/**
@@ -111,98 +109,91 @@ rtos_int_enter_end:
.global rtos_int_exit
.type rtos_int_exit, @function
rtos_int_exit:
/* Skip if the scheduler was not started */
#if ( configNUM_CORES > 1 )
csrr t1, mhartid /* t1 = coreID */
slli t1, t1, 2 /* t1 = t1 * 4 */
la t0, port_xSchedulerRunning /* t0 = &port_xSchedulerRunning */
add t0, t0, t1 /* t0 = &port_xSchedulerRunning[coreID] */
lw t0, (t0) /* t0 = port_xSchedulerRunning[coreID] */
csrr a1, mhartid /* a1 = coreID */
slli a1, a1, 2 /* a1 = a1 * 4 */
la a0, port_xSchedulerRunning /* a0 = &port_xSchedulerRunning */
add a0, a0, a1 /* a0 = &port_xSchedulerRunning[coreID] */
lw a0, (a0) /* a0 = port_xSchedulerRunning[coreID] */
#else
lw t0, port_xSchedulerRunning /* t0 = port_xSchedulerRunning */
lw a0, port_xSchedulerRunning /* a0 = port_xSchedulerRunning */
#endif /* ( configNUM_CORES > 1 ) */
beq t0, zero, rtos_int_exit_end /* if (port_uxSchewdulerRunning == 0) jump to rtos_int_exit_end */
beqz a0, rtos_int_exit_end /* if (port_uxSchewdulerRunning == 0) jump to rtos_int_exit_end */
/* Decrement interrupt nesting counter */
la t2, port_uxInterruptNesting /* t2 = &port_uxInterruptNesting */
/* Update nesting interrupts counter */
la a0, port_uxInterruptNesting /* a0 = &port_uxInterruptNesting */
#if ( configNUM_CORES > 1 )
add t2, t2, t1 /* t2 = &port_uxInterruptNesting[coreID] // t1 already contains coreID * 4 */
#endif
lw t3, 0x0(t2) /* t3 = port_uxInterruptNesting[coreID] */
add a0, a0, a1 /* a0 = &port_uxInterruptNesting[coreID] // a1 already contains coreID * 4 */
#endif /* ( configNUM_CORES > 1 ) */
lw a2, 0(a0) /* a2 = port_uxInterruptNesting[coreID] */
/* If the interrupt nesting counter is already zero, then protect against underflow */
beq t3, zero, isr_skip_decrement /* if (port_uxInterruptNesting[coreID] == 0) jump to isr_skip_decrement */
addi t3, t3, -1 /* t3 = t3 - 1 */
sw t3, 0x0(t2) /* port_uxInterruptNesting[coreID] = t3 */
/* Already zero, protect against underflow */
beqz a2, isr_skip_decrement /* if (port_uxInterruptNesting[coreID] == 0) jump to isr_skip_decrement */
addi a2, a2, -1 /* a2 = a2 - 1 */
sw a2, 0(a0) /* port_uxInterruptNesting[coreID] = a2 */
/* May still have interrupts pending, skip section below and exit */
bnez a2, rtos_int_exit_end
isr_skip_decrement:
/* If the CPU reached this label, a2 (uxInterruptNesting) is 0 for sure */
/* We may still have interrupts pending. Skip the section below and exit */
bne t3, zero, rtos_int_exit_end /* (if port_uxInterruptNesting[coreID] > 0) jump to rtos_int_exit_end */
/* Schedule the next task if an yield is pending */
la t0, xPortSwitchFlag /* t0 = &xPortSwitchFlag */
/* Schedule the next task if a yield is pending */
la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
#if ( configNUM_CORES > 1 )
add t0, t0, t1 /* t0 = &xPortSwitchFlag[coreID] // t1 already contains coreID * 4 */
add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID] // a1 already contains coreID * 4 */
#endif /* ( configNUM_CORES > 1 ) */
lw t2, 0x0(t0) /* t2 = xPortSwitchFlag[coreID] */
beq t2, zero, no_switch /* if (xPortSwitchFlag[coreID] == 0) jump to no_switch */
lw a2, 0(a0) /* a2 = xPortSwitchFlag[coreID] */
beqz a2, no_switch /* if (xPortSwitchFlag[coreID] == 0) jump to no_switch */
/* Save the return address on the stack and create space on the stack for the c-routine call to schedule
* the next task. Stack pointer for RISC-V should always be 16 byte aligned. After the switch, restore
* the return address and sp.
*/
addi sp, sp, -16 /* sp = sp - 16 */
sw ra, 0(sp) /* sp = ra */
call vTaskSwitchContext /* vTaskSwitchContext() */
lw ra, 0(sp) /* ra = sp */
addi sp, sp, 16 /* sp = sp + 16 */
/* Preserve return address and schedule next task. To speed up the process, instead of allocating stack
* space, let's use a callee-saved register: s0. Since the caller is not using it, let's use it. */
mv s0, ra
call vTaskSwitchContext
mv ra, s0
/* Clear the switch pending flag */
la t0, xPortSwitchFlag /* t0 = &xPortSwitchFlag */
/* Clears the switch pending flag */
la a0, xPortSwitchFlag /* a0 = &xPortSwitchFlag */
#if ( configNUM_CORES > 1 )
/* c routine vTaskSwitchContext may change the temp registers, so we read again */
csrr t3, mhartid /* t3 = coreID */
slli t3, t3, 2 /* t3 = t3 * 4 */
add t0, t0, t3 /* t0 = &xPortSwitchFlag[coreID] */
/* C routine vTaskSwitchContext may change the temp registers, so we read again */
csrr a1, mhartid /* a1 = coreID */
slli a1, a1, 2 /* a1 = a1 * 4 */
add a0, a0, a1 /* a0 = &xPortSwitchFlag[coreID]; */
#endif /* ( configNUM_CORES > 1 ) */
mv t2, zero /* t2 = 0 */
sw t2, 0x0(t0) /* xPortSwitchFlag[coreID] = t2 */
sw zero, 0(a0) /* xPortSwitchFlag[coreID] = 0; */
no_switch:
#if SOC_INT_CLIC_SUPPORTED
/* Recover the stack of next task and prepare to exit */
la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
#if ( configNUM_CORES > 1 )
csrr t3, mhartid /* t3 = coreID */
slli t3, t3, 2 /* t3 = t3 * 4 */
add a0, a0, t3 /* a0 = &pxCurrentTCB[coreID] */
#endif /* ( configNUM_CORES > 1 ) */
lw a0, (a0) /* a0 = pxCurrentTCB[coreID] */
lw a0, 0x0(a0) /* a0 = previous sp */
#else
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_monitor_stop(); */
ESP_HW_STACK_GUARD_MONITOR_STOP_CPU0
/* esp_hw_stack_guard_monitor_stop(); pass the scratch registers */
ESP_HW_STACK_GUARD_MONITOR_STOP_CUR_CORE a0 a1
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
#if ( configNUM_CORES > 1 )
/* Recover the stack of next task and prepare to exit */
csrr a1, mhartid
slli a1, a1, 2
la a0, pxCurrentTCB /* a0 = &pxCurrentTCB */
add a0, a0, a1 /* a0 = &pxCurrentTCB[coreID] */
lw a0, 0(a0) /* a0 = pxCurrentTCB[coreID] */
lw sp, 0(a0) /* sp = previous sp */
#else
/* Recover the stack of next task */
lw t0, pxCurrentTCB
lw sp, 0x0(t0)
lw a0, pxCurrentTCB
lw sp, 0(a0)
#endif /* ( configNUM_CORES > 1 ) */
#if CONFIG_ESP_SYSTEM_HW_STACK_GUARD
/* esp_hw_stack_guard_set_bounds(pxCurrentTCB[0]->pxStack,
* pxCurrentTCB[0]->pxEndOfStack);
*/
lw a0, PORT_OFFSET_PX_STACK(t0)
lw a1, PORT_OFFSET_PX_END_OF_STACK(t0)
ESP_HW_STACK_GUARD_SET_BOUNDS_CPU0
lw a1, PORT_OFFSET_PX_END_OF_STACK(a0)
lw a0, PORT_OFFSET_PX_STACK(a0)
ESP_HW_STACK_GUARD_SET_BOUNDS_CUR_CORE a2
/* esp_hw_stack_guard_monitor_start(); */
ESP_HW_STACK_GUARD_MONITOR_START_CPU0
ESP_HW_STACK_GUARD_MONITOR_START_CUR_CORE a0 a1
#endif /* CONFIG_ESP_SYSTEM_HW_STACK_GUARD */
#endif /* SOC_INT_CLIC_SUPPORTED */
rtos_int_exit_end:
ret