change(esp_hw_support): pmu reset and isolate contorl signal waiting time configuration
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@@ -28,6 +28,10 @@ void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t
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uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
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void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
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void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
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@@ -637,6 +637,26 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *
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return hw->power.wait_timer1.powerup_timer;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
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{
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hw->power.wait_timer2.lp_iso_wait_timer = isolate_wait_cycle;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
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{
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hw->power.wait_timer2.lp_rst_wait_timer = reset_wait_cycle;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
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{
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hw->power.wait_timer2.hp_iso_wait_timer = isolate_wait_cycle;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
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{
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hw->power.wait_timer2.hp_rst_wait_timer = reset_wait_cycle;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
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