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Merge branch 'feature/ledc_sleep_retention_support' into 'master'

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feat(ledc): support ledc sleep mode selection

Closes IDFGH-12713, IDF-9740, IDF-9769, IDF-9909, IDF-10372, IDF-10394, IDF-8472, and IDFCI-2450

See merge request espressif/esp-idf!34097
This commit is contained in:
Song Ruo Jing
2024-10-24 11:43:11 +08:00
parent 5dda8a3211 7a516554a6
commit 92d335548f
64 changed files with 1463 additions and 177 deletions
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docs/en/api-reference/peripherals/ledc.rst
+19 -7
View File
@@ -88,7 +88,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
* - RC_FAST_CLK
- ~ 8 MHz
- Low
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
.. only:: esp32s2
@@ -107,7 +107,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- Dynamic Frequency Scaling compatible
* - RC_FAST_CLK
- ~ 8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 40 MHz
- Dynamic Frequency Scaling compatible
@@ -126,7 +126,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- /
* - RC_FAST_CLK
- ~ 20 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 40 MHz
- Dynamic Frequency Scaling compatible
@@ -145,7 +145,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- /
* - RC_FAST_CLK
- ~ 20 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 40/26 MHz
- Dynamic Frequency Scaling compatible
@@ -164,7 +164,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- /
* - RC_FAST_CLK
- ~ 17.5 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 48 MHz
- Dynamic Frequency Scaling compatible
@@ -183,7 +183,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- /
* - RC_FAST_CLK
- ~ 17.5 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 40 MHz
- Dynamic Frequency Scaling compatible
@@ -202,7 +202,7 @@ The source clock can also limit the PWM frequency. The higher the source clock f
- /
* - RC_FAST_CLK
- ~ 8 MHz
- Dynamic Frequency Scaling compatible, Light sleep compatible
- Dynamic Frequency Scaling compatible, Light-sleep compatible
* - XTAL_CLK
- 32 MHz
- Dynamic Frequency Scaling compatible
@@ -337,6 +337,18 @@ When configuring an LEDC channel, one of the parameters selected within :cpp:typ
For registration of a handler to address this interrupt, call :cpp:func:`ledc_isr_register`.
Power Management
----------------
LEDC driver does not utilize power management lock to prevent the system from going into Light-sleep. Instead, the LEDC peripheral power domain state and the PWM signal output behavior during sleep can be chosen by configuring :cpp:member:`ledc_channel_config_t::sleep_mode`. The default mode is :cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_NO_PD`, which stands for no signal output and LEDC power domain will not be powered down during sleep.
If signal output needs to be maintained in Light-sleep, then select :cpp:enumerator:`LEDC_SLEEP_MODE_KEEP_ALIVE`. As long as the binded LEDC timer clock source is Light-sleep compatible, the PWM signal can continue its output even the system enters Light-sleep. The cost is a higher power consumption in sleep, since the clock source and the power domain where LEDC belongs to cannot be powered down. Note that, if there is an unfinished fade before entering sleep, the fade can also continue during sleep, but the target duty might not be reached exactly. It will adjust to the target duty after wake-up.
.. only:: SOC_LEDC_SUPPORT_SLEEP_RETENTION
There is another sleep mode, :cpp:enumerator:`LEDC_SLEEP_MODE_NO_ALIVE_ALLOW_PD`, can save some power consumption in sleep, but at the expense of more memory being consumed. The system retains LEDC register context before entering Light-sleep and restores them after waking up, so that the LEDC power domain can be powered down during sleep. Any unfinished fade will not resume upon waking up from sleep, instead, it will output a PWM signal with a fixed duty cycle that matches the duty cycle just before entering sleep.
.. only:: esp32
.. _ledc-api-high_low_speed_mode: