mspi: mspi timing tuning ll
This commit is contained in:
Armando
committed by
Armando (Dou Yiwen)
Armando (Dou Yiwen)
parent
9c1897028a
commit
99882ac2d1
@@ -0,0 +1,317 @@
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <sys/param.h>
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#include "esp_bit_defs.h"
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#include "hal/assert.h"
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#include "soc/soc.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/io_mux_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define ARRAY_SIZE(arr) (sizeof((arr))/sizeof(*(arr)))
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#define MSPI_TIMING_LL_FLASH_OCT_MASK (SPI_MEM_FCMD_OCT | SPI_MEM_FADDR_OCT | SPI_MEM_FDIN_OCT | SPI_MEM_FDOUT_OCT)
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#define MSPI_TIMING_LL_FLASH_QUAD_MASK (SPI_MEM_FASTRD_MODE | SPI_MEM_FREAD_DUAL | SPI_MEM_FREAD_DIO | SPI_MEM_FREAD_QUAD | SPI_MEM_FREAD_QIO)
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#define MSPI_TIMING_LL_FLASH_QIO_MODE_MASK (SPI_MEM_FREAD_QIO | SPI_MEM_FASTRD_MODE)
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#define MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK (SPI_MEM_FREAD_QUAD | SPI_MEM_FASTRD_MODE)
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#define MSPI_TIMING_LL_FLASH_DIO_MODE_MASK (SPI_MEM_FREAD_DIO | SPI_MEM_FASTRD_MODE)
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#define MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK (SPI_MEM_FREAD_DUAL | SPI_MEM_FASTRD_MODE)
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#define MSPI_TIMING_LL_FLASH_FAST_MODE_MASK (SPI_MEM_FASTRD_MODE)
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#define MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK 0
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typedef enum {
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MSPI_TIMING_LL_FLASH_OPI_MODE = BIT(0),
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MSPI_TIMING_LL_FLASH_QIO_MODE = BIT(1),
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MSPI_TIMING_LL_FLASH_QUAD_MODE = BIT(2),
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MSPI_TIMING_LL_FLASH_DIO_MODE = BIT(3),
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MSPI_TIMING_LL_FLASH_DUAL_MODE = BIT(4),
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MSPI_TIMING_LL_FLASH_FAST_MODE = BIT(5),
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MSPI_TIMING_LL_FLASH_SLOW_MODE = BIT(6),
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} mspi_timing_ll_flash_mode_t;
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/**
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* Set all MSPI pin drive strength
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*
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* @param spi_num SPI0 / SPI1
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* @param val Pin drive strength
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_all_pin_drive(uint8_t spi_num, uint32_t val)
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{
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SET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
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REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
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REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
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uint32_t regs[] = {IO_MUX_GPIO27_REG, IO_MUX_GPIO28_REG,
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IO_MUX_GPIO31_REG, IO_MUX_GPIO32_REG,
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IO_MUX_GPIO33_REG, IO_MUX_GPIO34_REG,
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IO_MUX_GPIO35_REG, IO_MUX_GPIO36_REG,
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IO_MUX_GPIO37_REG};
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for (int i = 0; i < ARRAY_SIZE(regs); i++) {
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PIN_SET_DRV(regs[i], val);
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}
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}
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/**
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* Set all MSPI Flash clock pin drive strength
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*
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* @param spi_num SPI0 / SPI1
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* @param val Pin drive strength
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_clock_pin_drive(uint8_t spi_num, uint32_t val)
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{
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bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
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//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
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HAL_ASSERT(clk_pin_drive_control);
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REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV, val);
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}
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/**
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* Set all MSPI PSRAM clock pin drive strength
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*
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* @param spi_num SPI0 / SPI1
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* @param val Pin drive strength
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_clock_pin_drive(uint8_t spi_num, uint32_t val)
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{
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bool clk_pin_drive_control = GET_PERI_REG_MASK(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPICLK_PAD_DRV_CTL_EN);
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//You should never call this function, while `mspi_timing_ll_set_all_pin_drive()` isn't called
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HAL_ASSERT(clk_pin_drive_control);
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REG_SET_FIELD(SPI_MEM_DATE_REG(spi_num), SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV, val);
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}
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/**
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* Enable Flash HCLK
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*
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* @param spi_num SPI0 / SPI1
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*/
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__attribute__((always_inline))
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static inline void mspi_timinng_ll_enable_flash_hclk(uint8_t spi_num)
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{
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REG_SET_BIT(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CLK_ENA);
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}
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/**
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* Enable PSRAM HCLK
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*
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* @param spi_num SPI0 / SPI1
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*/
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__attribute__((always_inline))
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static inline void mspi_timinng_ll_enable_psram_hclk(uint8_t spi_num)
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{
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REG_SET_BIT(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CLK_ENA);
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}
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/**
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* Enable/Disable Flash variable dummy
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*
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* @param spi_num SPI0 / SPI1
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* @param enable Enable / Disable
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_enable_flash_variable_dummy(uint8_t spi_num, bool enable)
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{
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REG_SET_FIELD(SPI_MEM_DDR_REG(1), SPI_MEM_SPI_FMEM_VAR_DUMMY, enable);
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}
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/**
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* Set MSPI core clock divider
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*
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* @param spi_num SPI0 / SPI1
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* @param val Divider value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_core_clock_divider(uint8_t spi_num, uint32_t val)
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{
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REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, val);
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}
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/**
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* Set MSPI Flash clock
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*
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* @param spi_num SPI0 / SPI1
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* @param freqdiv Divider value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), SPI_MEM_CLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv - 1) << SPI_MEM_CLKCNT_N_S)) | (((freqdiv / 2 - 1) << SPI_MEM_CLKCNT_H_S)) | ((freqdiv - 1) << SPI_MEM_CLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_CLOCK_REG(spi_num), freqbits);
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}
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}
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/**
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* Set MSPI PSRAM clock
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*
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* @param spi_num SPI0 / SPI1
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* @param freqdiv Divider value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_clock(uint8_t spi_num, uint32_t freqdiv)
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{
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if (freqdiv == 1) {
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), SPI_MEM_SCLK_EQU_SYSCLK);
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} else {
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uint32_t freqbits = (((freqdiv-1)<<SPI_MEM_SCLKCNT_N_S)) | (((freqdiv/2-1)<<SPI_MEM_SCLKCNT_H_S)) | ((freqdiv-1)<<SPI_MEM_SCLKCNT_L_S);
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WRITE_PERI_REG(SPI_MEM_SRAM_CLK_REG(spi_num), freqbits);
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}
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}
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/**
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* Set MSPI Flash din mode
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*
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* @param spi_num SPI0 / SPI1
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* @param din_mode Din mode value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_din_mode(uint8_t spi_num, uint8_t din_mode)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_DIN0_MODE_M | SPI_MEM_DIN1_MODE_M | SPI_MEM_DIN2_MODE_M | SPI_MEM_DIN3_MODE_M | SPI_MEM_DIN4_MODE_M | SPI_MEM_DIN5_MODE_M | SPI_MEM_DIN6_MODE_M | SPI_MEM_DIN7_MODE_M | SPI_MEM_DINS_MODE_M)))
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| (din_mode << SPI_MEM_DIN0_MODE_S) | (din_mode << SPI_MEM_DIN1_MODE_S) | (din_mode << SPI_MEM_DIN2_MODE_S) | (din_mode << SPI_MEM_DIN3_MODE_S)
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| (din_mode << SPI_MEM_DIN4_MODE_S) | (din_mode << SPI_MEM_DIN5_MODE_S) | (din_mode << SPI_MEM_DIN6_MODE_S) | (din_mode << SPI_MEM_DIN7_MODE_S) | (din_mode << SPI_MEM_DINS_MODE_S);
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REG_WRITE(SPI_MEM_DIN_MODE_REG(spi_num), reg_val);
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}
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/**
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* Set MSPI Flash din num
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*
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* @param spi_num SPI0 / SPI1
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* @param din_num Din num value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_flash_din_num(uint8_t spi_num, uint8_t din_num)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_DIN0_NUM_M | SPI_MEM_DIN1_NUM_M | SPI_MEM_DIN2_NUM_M | SPI_MEM_DIN3_NUM_M | SPI_MEM_DIN4_NUM_M | SPI_MEM_DIN5_NUM_M | SPI_MEM_DIN6_NUM_M | SPI_MEM_DIN7_NUM_M | SPI_MEM_DINS_NUM_M)))
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| (din_num << SPI_MEM_DIN0_NUM_S) | (din_num << SPI_MEM_DIN1_NUM_S) | (din_num << SPI_MEM_DIN2_NUM_S) | (din_num << SPI_MEM_DIN3_NUM_S)
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| (din_num << SPI_MEM_DIN4_NUM_S) | (din_num << SPI_MEM_DIN5_NUM_S) | (din_num << SPI_MEM_DIN6_NUM_S) | (din_num << SPI_MEM_DIN7_NUM_S) | (din_num << SPI_MEM_DINS_NUM_S);
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REG_WRITE(SPI_MEM_DIN_NUM_REG(spi_num), reg_val);
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}
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/**
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* Get MSPI Flash mode
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*
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* @param spi_num SPI0 / SPI1
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*
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* @return Flash mode
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*/
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__attribute__((always_inline))
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static inline mspi_timing_ll_flash_mode_t mspi_timing_ll_get_flash_mode(uint8_t spi_num)
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{
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uint32_t ctrl_reg = READ_PERI_REG(SPI_MEM_CTRL_REG(0));
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if (ctrl_reg & MSPI_TIMING_LL_FLASH_OCT_MASK) {
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return MSPI_TIMING_LL_FLASH_OPI_MODE;
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}
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switch (ctrl_reg & MSPI_TIMING_LL_FLASH_QUAD_MASK) {
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case MSPI_TIMING_LL_FLASH_QIO_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_QIO_MODE;
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case MSPI_TIMING_LL_FLASH_QUAD_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_QUAD_MODE;
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case MSPI_TIMING_LL_FLASH_DIO_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_DIO_MODE;
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case MSPI_TIMING_LL_FLASH_DUAL_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_DUAL_MODE;
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case MSPI_TIMING_LL_FLASH_FAST_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_FAST_MODE;
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case MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK:
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return MSPI_TIMING_LL_FLASH_SLOW_MODE;
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default:
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HAL_ASSERT(false);
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}
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}
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/**
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* Set MSPI Octal Flash extra dummy
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*
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* @param spi_num SPI0 / SPI1
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* @param extra_dummy Extra dummy
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_octal_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_TIMING_CALI_REG(spi_num), SPI_MEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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}
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/**
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* Set MSPI PSRAM din mode
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*
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* @param spi_num SPI0 / SPI1
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* @param din_mode Din mode value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_din_mode(uint8_t spi_num, uint8_t din_mode)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_MODE_M | SPI_MEM_SPI_SMEM_DIN1_MODE_M | SPI_MEM_SPI_SMEM_DIN2_MODE_M | SPI_MEM_SPI_SMEM_DIN3_MODE_M | SPI_MEM_SPI_SMEM_DIN4_MODE_M | SPI_MEM_SPI_SMEM_DIN5_MODE_M | SPI_MEM_SPI_SMEM_DIN6_MODE_M | SPI_MEM_SPI_SMEM_DIN7_MODE_M | SPI_MEM_SPI_SMEM_DINS_MODE_M)))
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| (din_mode << SPI_MEM_SPI_SMEM_DIN0_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN1_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN2_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN3_MODE_S)
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| (din_mode << SPI_MEM_SPI_SMEM_DIN4_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN5_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN6_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DIN7_MODE_S) | (din_mode << SPI_MEM_SPI_SMEM_DINS_MODE_S);
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REG_WRITE(SPI_MEM_SPI_SMEM_DIN_MODE_REG(spi_num), reg_val);
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}
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/**
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* Set MSPI PSRAM din num
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*
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* @param spi_num SPI0 / SPI1
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* @param din_num Din num value
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_psram_din_num(uint8_t spi_num, uint8_t din_num)
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{
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uint32_t reg_val = (REG_READ(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num)) & (~(SPI_MEM_SPI_SMEM_DIN0_NUM_M | SPI_MEM_SPI_SMEM_DIN1_NUM_M | SPI_MEM_SPI_SMEM_DIN2_NUM_M | SPI_MEM_SPI_SMEM_DIN3_NUM_M | SPI_MEM_SPI_SMEM_DIN4_NUM_M | SPI_MEM_SPI_SMEM_DIN5_NUM_M | SPI_MEM_SPI_SMEM_DIN6_NUM_M | SPI_MEM_SPI_SMEM_DIN7_NUM_M | SPI_MEM_SPI_SMEM_DINS_NUM_M)))
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| (din_num << SPI_MEM_SPI_SMEM_DIN0_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN1_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN2_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN3_NUM_S)
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| (din_num << SPI_MEM_SPI_SMEM_DIN4_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN5_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN6_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DIN7_NUM_S) | (din_num << SPI_MEM_SPI_SMEM_DINS_NUM_S);
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REG_WRITE(SPI_MEM_SPI_SMEM_DIN_NUM_REG(spi_num), reg_val);
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}
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/**
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* Set MSPI Octal PSRAM extra dummy
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*
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* @param spi_num SPI0 / SPI1
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* @param extra_dummy Extra dummy
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*/
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__attribute__((always_inline))
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static inline void mspi_timing_ll_set_octal_psram_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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if (extra_dummy > 0) {
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SET_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, extra_dummy,
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SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_TIMING_CALI_M);
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SET_PERI_REG_BITS(SPI_MEM_SPI_SMEM_TIMING_CALI_REG(spi_num), SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V, 0,
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SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S);
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}
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}
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#ifdef __cplusplus
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}
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#endif
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