fix(panic): fixed cache error being reported as illegal instruction

On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.

components/esp_system/include/esp_private/panic_internal.h

@@ -75,6 +75,8 @@ void panic_arch_fill_info(void *frame, panic_info_t *info);
 
 void panic_soc_fill_info(void *frame, panic_info_t *info);
 
+bool panic_soc_check_pseudo_cause(void *f, panic_info_t *info);
+
 void panic_print_registers(const void *frame, int core);
 
 void panic_print_backtrace(const void *frame, int core);