fix(panic): fixed cache error being reported as illegal instruction

On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.

components/esp_system/port/include/private/esp_private/cache_err_int.h

@@ -1,15 +1,18 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include <stdbool.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+
 /**
  * @brief initialize cache invalid access interrupt
  *
@@ -32,6 +35,22 @@ void esp_cache_err_int_init(void);
  */
 int esp_cache_err_get_cpuid(void);
 
+
+/**
+ * @brief Returns a pointer to the cache error message
+ *
+ * @return const char* Pointer to the error message
+ */
+const char *esp_cache_err_panic_string(void);
+
+/**
+ * @brief Checks if any cache errors are active
+ *
+ * @return true
+ * @return false
+ */
+bool esp_cache_err_has_active_err(void);
+
 #ifdef __cplusplus
 }
 #endif