fix(panic): fixed cache error being reported as illegal instruction

On riscv chips accessing cache mapped memory regions over the ibus would
result in an illegal instructions exception triggering faster than the cache
error interrupt/exception.

Added a cache error check in the panic handler, if any cache errors are active
the panic handler will now report a cache error, even if the trigger exception
was a illegal instructions.

components/riscv/include/esp_private/panic_reason.h

@@ -18,3 +18,5 @@
 #endif
 
 #define PANIC_RSN_CACHEERR    3
+
+#define MCAUSE_ILLEGAL_INSTRUCTION  2