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fix(mspi): fixed mspi clock wrong on ram loadable app on c61, enable tests on c5 c61

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This commit is contained in:
Armando
2024-09-08 10:06:07 +08:00
parent 17fc026c48
commit 9c81fe6114
7 changed files with 19 additions and 20 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
+12 -7
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@@ -46,8 +46,19 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -198,13 +209,7 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
bootloader_init_mspi_clock();
bootloader_init_flash_configure();
bootloader_spi_flash_resume();
bootloader_flash_unlock();