feat(i2s): add bclk_div config for std mode

2025-03-28 15:41:08 +08:00
parent 7dd1f9eb41
commit 9d33cd4947
2 changed files with 9 additions and 2 deletions
@@ -204,6 +204,7 @@ extern "C" {
    .sample_rate_hz = rate, \
    .clk_src = I2S_CLK_SRC_DEFAULT, \
    .mclk_multiple = I2S_MCLK_MULTIPLE_256, \
+    .bclk_div = 8, \
 }
 #else
 /**
@@ -217,6 +218,7 @@ extern "C" {
    .clk_src = I2S_CLK_SRC_DEFAULT, \
    .ext_clk_freq_hz = 0, \
    .mclk_multiple = I2S_MCLK_MULTIPLE_256, \
+    .bclk_div = 8, \
 }
 #endif

@@ -265,6 +267,7 @@ typedef struct {
                                                 *   but please set this field a multiple of `3` (like 384) when using 24-bit data width,
                                                 *   otherwise the sample rate might be inaccurate
                                                 */
+    uint32_t                bclk_div;           /*!< The division from MCLK to BCLK, only take effect for slave role, it shouldn't be smaller than 8. Increase this field when data sent by slave lag behind */
 } i2s_std_clk_config_t;

 /**